./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.15.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 47ea0209 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7c7b99f6-3a9c-466e-933d-861f23542dc7/bin/uautomizer-AkOaLMaTGY/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7c7b99f6-3a9c-466e-933d-861f23542dc7/bin/uautomizer-AkOaLMaTGY/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7c7b99f6-3a9c-466e-933d-861f23542dc7/bin/uautomizer-AkOaLMaTGY/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7c7b99f6-3a9c-466e-933d-861f23542dc7/bin/uautomizer-AkOaLMaTGY/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.15.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7c7b99f6-3a9c-466e-933d-861f23542dc7/bin/uautomizer-AkOaLMaTGY/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7c7b99f6-3a9c-466e-933d-861f23542dc7/bin/uautomizer-AkOaLMaTGY --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d827a13f264a8106bf76fcdb72d7bd8ed8c070aef2487e4bd9a858009359b9d5 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-47ea020 [2021-11-07 07:29:42,908 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-07 07:29:42,912 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-07 07:29:42,978 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-07 07:29:42,979 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-07 07:29:42,986 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-07 07:29:42,991 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-07 07:29:42,994 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-07 07:29:42,996 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-07 07:29:42,997 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-07 07:29:42,999 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-07 07:29:43,001 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-07 07:29:43,003 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-07 07:29:43,013 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-07 07:29:43,016 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-07 07:29:43,023 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-07 07:29:43,025 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-07 07:29:43,026 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-07 07:29:43,028 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-07 07:29:43,031 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-07 07:29:43,038 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-07 07:29:43,040 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-07 07:29:43,045 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-07 07:29:43,046 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-07 07:29:43,062 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-07 07:29:43,062 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-07 07:29:43,063 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-07 07:29:43,065 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-07 07:29:43,066 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-07 07:29:43,068 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-07 07:29:43,068 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-07 07:29:43,070 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-07 07:29:43,072 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-07 07:29:43,073 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-07 07:29:43,075 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-07 07:29:43,075 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-07 07:29:43,076 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-07 07:29:43,077 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-07 07:29:43,077 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-07 07:29:43,078 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-07 07:29:43,079 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-07 07:29:43,080 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7c7b99f6-3a9c-466e-933d-861f23542dc7/bin/uautomizer-AkOaLMaTGY/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-07 07:29:43,148 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-07 07:29:43,151 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-07 07:29:43,152 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-07 07:29:43,152 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-07 07:29:43,154 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-07 07:29:43,155 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-07 07:29:43,155 INFO L138 SettingsManager]: * Use SBE=true [2021-11-07 07:29:43,155 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-07 07:29:43,156 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-07 07:29:43,156 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-07 07:29:43,157 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-07 07:29:43,158 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-07 07:29:43,158 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-07 07:29:43,158 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-07 07:29:43,159 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-07 07:29:43,159 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-07 07:29:43,159 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-07 07:29:43,160 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-07 07:29:43,160 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-07 07:29:43,160 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-07 07:29:43,160 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-07 07:29:43,161 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-07 07:29:43,161 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-07 07:29:43,161 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-07 07:29:43,162 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-07 07:29:43,162 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-07 07:29:43,164 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-07 07:29:43,164 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-07 07:29:43,165 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-07 07:29:43,165 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-07 07:29:43,165 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-07 07:29:43,166 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-07 07:29:43,167 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-07 07:29:43,167 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7c7b99f6-3a9c-466e-933d-861f23542dc7/bin/uautomizer-AkOaLMaTGY/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7c7b99f6-3a9c-466e-933d-861f23542dc7/bin/uautomizer-AkOaLMaTGY Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d827a13f264a8106bf76fcdb72d7bd8ed8c070aef2487e4bd9a858009359b9d5 [2021-11-07 07:29:43,502 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-07 07:29:43,530 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-07 07:29:43,534 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-07 07:29:43,535 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-07 07:29:43,537 INFO L275 PluginConnector]: CDTParser initialized [2021-11-07 07:29:43,538 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7c7b99f6-3a9c-466e-933d-861f23542dc7/bin/uautomizer-AkOaLMaTGY/../../sv-benchmarks/c/systemc/token_ring.15.cil.c [2021-11-07 07:29:43,645 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7c7b99f6-3a9c-466e-933d-861f23542dc7/bin/uautomizer-AkOaLMaTGY/data/e638f0491/30a25a12fa9444f7b56d691e599c8ec7/FLAG00644adf8 [2021-11-07 07:29:44,306 INFO L306 CDTParser]: Found 1 translation units. [2021-11-07 07:29:44,309 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7c7b99f6-3a9c-466e-933d-861f23542dc7/sv-benchmarks/c/systemc/token_ring.15.cil.c [2021-11-07 07:29:44,336 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7c7b99f6-3a9c-466e-933d-861f23542dc7/bin/uautomizer-AkOaLMaTGY/data/e638f0491/30a25a12fa9444f7b56d691e599c8ec7/FLAG00644adf8 [2021-11-07 07:29:44,559 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7c7b99f6-3a9c-466e-933d-861f23542dc7/bin/uautomizer-AkOaLMaTGY/data/e638f0491/30a25a12fa9444f7b56d691e599c8ec7 [2021-11-07 07:29:44,563 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-07 07:29:44,565 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-07 07:29:44,567 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-07 07:29:44,567 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-07 07:29:44,572 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-07 07:29:44,572 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.11 07:29:44" (1/1) ... [2021-11-07 07:29:44,574 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@538ea97e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:29:44, skipping insertion in model container [2021-11-07 07:29:44,574 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.11 07:29:44" (1/1) ... [2021-11-07 07:29:44,584 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-07 07:29:44,643 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-07 07:29:44,859 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7c7b99f6-3a9c-466e-933d-861f23542dc7/sv-benchmarks/c/systemc/token_ring.15.cil.c[669,682] [2021-11-07 07:29:45,049 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-07 07:29:45,065 INFO L203 MainTranslator]: Completed pre-run [2021-11-07 07:29:45,084 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7c7b99f6-3a9c-466e-933d-861f23542dc7/sv-benchmarks/c/systemc/token_ring.15.cil.c[669,682] [2021-11-07 07:29:45,232 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-07 07:29:45,260 INFO L208 MainTranslator]: Completed translation [2021-11-07 07:29:45,261 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:29:45 WrapperNode [2021-11-07 07:29:45,261 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-07 07:29:45,263 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-07 07:29:45,263 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-07 07:29:45,263 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-07 07:29:45,286 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:29:45" (1/1) ... [2021-11-07 07:29:45,306 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:29:45" (1/1) ... [2021-11-07 07:29:45,497 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-07 07:29:45,498 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-07 07:29:45,498 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-07 07:29:45,498 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-07 07:29:45,509 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:29:45" (1/1) ... [2021-11-07 07:29:45,510 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:29:45" (1/1) ... [2021-11-07 07:29:45,523 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:29:45" (1/1) ... [2021-11-07 07:29:45,523 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:29:45" (1/1) ... [2021-11-07 07:29:45,602 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:29:45" (1/1) ... [2021-11-07 07:29:45,660 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:29:45" (1/1) ... [2021-11-07 07:29:45,668 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:29:45" (1/1) ... [2021-11-07 07:29:45,683 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-07 07:29:45,685 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-07 07:29:45,685 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-07 07:29:45,685 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-07 07:29:45,691 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:29:45" (1/1) ... [2021-11-07 07:29:45,700 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 07:29:45,715 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7c7b99f6-3a9c-466e-933d-861f23542dc7/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:29:45,737 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7c7b99f6-3a9c-466e-933d-861f23542dc7/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 07:29:45,759 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_7c7b99f6-3a9c-466e-933d-861f23542dc7/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-07 07:29:45,797 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-07 07:29:45,798 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-07 07:29:45,798 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-07 07:29:45,798 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-07 07:29:49,027 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-07 07:29:49,028 INFO L299 CfgBuilder]: Removed 622 assume(true) statements. [2021-11-07 07:29:49,033 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.11 07:29:49 BoogieIcfgContainer [2021-11-07 07:29:49,034 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-07 07:29:49,035 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-07 07:29:49,035 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-07 07:29:49,040 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-07 07:29:49,041 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-07 07:29:49,041 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 07.11 07:29:44" (1/3) ... [2021-11-07 07:29:49,043 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@480b5eb6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.11 07:29:49, skipping insertion in model container [2021-11-07 07:29:49,043 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-07 07:29:49,043 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:29:45" (2/3) ... [2021-11-07 07:29:49,044 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@480b5eb6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.11 07:29:49, skipping insertion in model container [2021-11-07 07:29:49,044 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-07 07:29:49,044 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.11 07:29:49" (3/3) ... [2021-11-07 07:29:49,046 INFO L389 chiAutomizerObserver]: Analyzing ICFG token_ring.15.cil.c [2021-11-07 07:29:49,104 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-07 07:29:49,104 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-07 07:29:49,105 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-07 07:29:49,105 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-07 07:29:49,105 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-07 07:29:49,105 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-07 07:29:49,105 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-07 07:29:49,106 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-07 07:29:49,171 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1992 states, 1991 states have (on average 1.505273731793069) internal successors, (2997), 1991 states have internal predecessors, (2997), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:49,307 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2021-11-07 07:29:49,307 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:29:49,307 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:29:49,332 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:49,333 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:49,333 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-07 07:29:49,340 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1992 states, 1991 states have (on average 1.505273731793069) internal successors, (2997), 1991 states have internal predecessors, (2997), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:49,372 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1817 [2021-11-07 07:29:49,373 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:29:49,373 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:29:49,380 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:49,380 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:49,392 INFO L791 eck$LassoCheckResult]: Stem: 459#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1920#L-1true havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 302#L1898true havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1843#L902true assume !(1 == ~m_i~0);~m_st~0 := 2; 273#L909-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 409#L914-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 434#L919-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1216#L924-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1088#L929-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1832#L934-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1254#L939-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1653#L944-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 305#L949-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1306#L954-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1929#L959-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 624#L964-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 1158#L969-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 1741#L974-1true assume !(0 == ~M_E~0); 862#L1286-1true assume !(0 == ~T1_E~0); 256#L1291-1true assume !(0 == ~T2_E~0); 1821#L1296-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 684#L1301-1true assume !(0 == ~T4_E~0); 1203#L1306-1true assume !(0 == ~T5_E~0); 1171#L1311-1true assume !(0 == ~T6_E~0); 234#L1316-1true assume !(0 == ~T7_E~0); 1660#L1321-1true assume !(0 == ~T8_E~0); 699#L1326-1true assume !(0 == ~T9_E~0); 141#L1331-1true assume !(0 == ~T10_E~0); 5#L1336-1true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1053#L1341-1true assume !(0 == ~T12_E~0); 29#L1346-1true assume !(0 == ~T13_E~0); 1472#L1351-1true assume !(0 == ~E_M~0); 204#L1356-1true assume !(0 == ~E_1~0); 1937#L1361-1true assume !(0 == ~E_2~0); 1629#L1366-1true assume !(0 == ~E_3~0); 229#L1371-1true assume !(0 == ~E_4~0); 1436#L1376-1true assume 0 == ~E_5~0;~E_5~0 := 1; 735#L1381-1true assume !(0 == ~E_6~0); 1716#L1386-1true assume !(0 == ~E_7~0); 1853#L1391-1true assume !(0 == ~E_8~0); 1771#L1396-1true assume !(0 == ~E_9~0); 647#L1401-1true assume !(0 == ~E_10~0); 1266#L1406-1true assume !(0 == ~E_11~0); 891#L1411-1true assume !(0 == ~E_12~0); 1683#L1416-1true assume 0 == ~E_13~0;~E_13~0 := 1; 600#L1421-1true havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 493#L635true assume 1 == ~m_pc~0; 1464#L636true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 200#L646true is_master_triggered_#res := is_master_triggered_~__retres1~0; 578#L647true activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1290#L1598true assume !(0 != activate_threads_~tmp~1); 121#L1598-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 563#L654true assume !(1 == ~t1_pc~0); 1309#L654-2true is_transmit1_triggered_~__retres1~1 := 0; 1706#L665true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1894#L666true activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 562#L1606true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 808#L1606-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 143#L673true assume 1 == ~t2_pc~0; 1762#L674true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 860#L684true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1831#L685true activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1856#L1614true assume !(0 != activate_threads_~tmp___1~0); 1949#L1614-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 615#L692true assume !(1 == ~t3_pc~0); 494#L692-2true is_transmit3_triggered_~__retres1~3 := 0; 1755#L703true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 411#L704true activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 390#L1622true assume !(0 != activate_threads_~tmp___2~0); 1688#L1622-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 154#L711true assume 1 == ~t4_pc~0; 420#L712true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1301#L722true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 715#L723true activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 16#L1630true assume !(0 != activate_threads_~tmp___3~0); 1807#L1630-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1805#L730true assume !(1 == ~t5_pc~0); 1933#L730-2true is_transmit5_triggered_~__retres1~5 := 0; 101#L741true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 276#L742true activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 158#L1638true assume !(0 != activate_threads_~tmp___4~0); 342#L1638-2true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 858#L749true assume 1 == ~t6_pc~0; 217#L750true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 410#L760true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 325#L761true activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1432#L1646true assume !(0 != activate_threads_~tmp___5~0); 455#L1646-2true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 7#L768true assume 1 == ~t7_pc~0; 756#L769true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 1367#L779true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 118#L780true activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1343#L1654true assume !(0 != activate_threads_~tmp___6~0); 771#L1654-2true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 235#L787true assume !(1 == ~t8_pc~0); 1457#L787-2true is_transmit8_triggered_~__retres1~8 := 0; 1669#L798true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1356#L799true activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1871#L1662true assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 28#L1662-2true havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1172#L806true assume 1 == ~t9_pc~0; 1117#L807true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 45#L817true is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 796#L818true activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 159#L1670true assume !(0 != activate_threads_~tmp___8~0); 1574#L1670-2true havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1096#L825true assume !(1 == ~t10_pc~0); 1361#L825-2true is_transmit10_triggered_~__retres1~10 := 0; 728#L836true is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 835#L837true activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 201#L1678true assume !(0 != activate_threads_~tmp___9~0); 1980#L1678-2true havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 535#L844true assume 1 == ~t11_pc~0; 353#L845true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 1245#L855true is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 582#L856true activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 1154#L1686true assume !(0 != activate_threads_~tmp___10~0); 1084#L1686-2true havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1383#L863true assume !(1 == ~t12_pc~0); 1444#L863-2true is_transmit12_triggered_~__retres1~12 := 0; 194#L874true is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1510#L875true activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 1210#L1694true assume !(0 != activate_threads_~tmp___11~0); 1598#L1694-2true havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 623#L882true assume 1 == ~t13_pc~0; 890#L883true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 1827#L893true is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 1531#L894true activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 1161#L1702true assume !(0 != activate_threads_~tmp___12~0); 832#L1702-2true assume !(1 == ~M_E~0); 1401#L1434-1true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1825#L1439-1true assume !(1 == ~T2_E~0); 151#L1444-1true assume !(1 == ~T3_E~0); 895#L1449-1true assume !(1 == ~T4_E~0); 388#L1454-1true assume !(1 == ~T5_E~0); 1467#L1459-1true assume !(1 == ~T6_E~0); 772#L1464-1true assume !(1 == ~T7_E~0); 841#L1469-1true assume !(1 == ~T8_E~0); 1703#L1474-1true assume 1 == ~T9_E~0;~T9_E~0 := 2; 601#L1479-1true assume !(1 == ~T10_E~0); 779#L1484-1true assume !(1 == ~T11_E~0); 1234#L1489-1true assume !(1 == ~T12_E~0); 514#L1494-1true assume !(1 == ~T13_E~0); 1812#L1499-1true assume !(1 == ~E_M~0); 638#L1504-1true assume !(1 == ~E_1~0); 1517#L1509-1true assume !(1 == ~E_2~0); 1233#L1514-1true assume 1 == ~E_3~0;~E_3~0 := 2; 871#L1519-1true assume !(1 == ~E_4~0); 1921#L1524-1true assume !(1 == ~E_5~0); 1671#L1529-1true assume !(1 == ~E_6~0); 1745#L1534-1true assume !(1 == ~E_7~0); 53#L1539-1true assume !(1 == ~E_8~0); 266#L1544-1true assume !(1 == ~E_9~0); 1590#L1549-1true assume !(1 == ~E_10~0); 1614#L1554-1true assume 1 == ~E_11~0;~E_11~0 := 2; 1587#L1559-1true assume !(1 == ~E_12~0); 1291#L1564-1true assume !(1 == ~E_13~0); 361#L1935-1true [2021-11-07 07:29:49,397 INFO L793 eck$LassoCheckResult]: Loop: 361#L1935-1true assume !false; 57#L1936true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 1700#L1261true assume false; 804#L1276true start_simulation_~kernel_st~0 := 2; 1247#L902-1true start_simulation_~kernel_st~0 := 3; 1429#L1286-2true assume 0 == ~M_E~0;~M_E~0 := 1; 432#L1286-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 954#L1291-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1835#L1296-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1750#L1301-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1613#L1306-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 573#L1311-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 165#L1316-3true assume !(0 == ~T7_E~0); 221#L1321-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 660#L1326-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1578#L1331-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 874#L1336-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1503#L1341-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 384#L1346-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 377#L1351-3true assume 0 == ~E_M~0;~E_M~0 := 1; 348#L1356-3true assume !(0 == ~E_1~0); 720#L1361-3true assume 0 == ~E_2~0;~E_2~0 := 1; 749#L1366-3true assume 0 == ~E_3~0;~E_3~0 := 1; 23#L1371-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1262#L1376-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1546#L1381-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1056#L1386-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1675#L1391-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1310#L1396-3true assume !(0 == ~E_9~0); 1943#L1401-3true assume 0 == ~E_10~0;~E_10~0 := 1; 199#L1406-3true assume 0 == ~E_11~0;~E_11~0 := 1; 122#L1411-3true assume 0 == ~E_12~0;~E_12~0 := 1; 1749#L1416-3true assume 0 == ~E_13~0;~E_13~0 := 1; 463#L1421-3true havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 66#L635-45true assume 1 == ~m_pc~0; 488#L636-15true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 833#L646-15true is_master_triggered_#res := is_master_triggered_~__retres1~0; 1389#L647-15true activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1083#L1598-45true assume !(0 != activate_threads_~tmp~1); 210#L1598-47true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 712#L654-45true assume 1 == ~t1_pc~0; 1728#L655-15true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1026#L665-15true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 48#L666-15true activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 59#L1606-45true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1430#L1606-47true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 499#L673-45true assume !(1 == ~t2_pc~0); 1327#L673-47true is_transmit2_triggered_~__retres1~2 := 0; 724#L684-15true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1544#L685-15true activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1480#L1614-45true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1157#L1614-47true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 282#L692-45true assume !(1 == ~t3_pc~0); 139#L692-47true is_transmit3_triggered_~__retres1~3 := 0; 1187#L703-15true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 776#L704-15true activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 309#L1622-45true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 492#L1622-47true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1976#L711-45true assume 1 == ~t4_pc~0; 577#L712-15true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1938#L722-15true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 479#L723-15true activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1674#L1630-45true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 757#L1630-47true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 223#L730-45true assume 1 == ~t5_pc~0; 144#L731-15true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1994#L741-15true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 359#L742-15true activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 879#L1638-45true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 980#L1638-47true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 132#L749-45true assume 1 == ~t6_pc~0; 1098#L750-15true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 1191#L760-15true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 855#L761-15true activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1396#L1646-45true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1002#L1646-47true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 295#L768-45true assume 1 == ~t7_pc~0; 369#L769-15true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 1159#L779-15true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 944#L780-15true activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1817#L1654-45true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 982#L1654-47true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1869#L787-45true assume 1 == ~t8_pc~0; 1193#L788-15true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 374#L798-15true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1662#L799-15true activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 637#L1662-45true assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 878#L1662-47true havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1743#L806-45true assume !(1 == ~t9_pc~0); 74#L806-47true is_transmit9_triggered_~__retres1~9 := 0; 515#L817-15true is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1122#L818-15true activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 417#L1670-45true assume !(0 != activate_threads_~tmp___8~0); 362#L1670-47true havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1794#L825-45true assume !(1 == ~t10_pc~0); 695#L825-47true is_transmit10_triggered_~__retres1~10 := 0; 1813#L836-15true is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 783#L837-15true activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 912#L1678-45true assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 1003#L1678-47true havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 171#L844-45true assume 1 == ~t11_pc~0; 1482#L845-15true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 464#L855-15true is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 472#L856-15true activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 754#L1686-45true assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 1315#L1686-47true havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 189#L863-45true assume 1 == ~t12_pc~0; 1116#L864-15true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 4#L874-15true is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1407#L875-15true activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 254#L1694-45true assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 761#L1694-47true havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 1093#L882-45true assume !(1 == ~t13_pc~0); 444#L882-47true is_transmit13_triggered_~__retres1~13 := 0; 12#L893-15true is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 316#L894-15true activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 1300#L1702-45true assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 1352#L1702-47true assume 1 == ~M_E~0;~M_E~0 := 2; 845#L1434-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1024#L1439-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 149#L1444-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 230#L1449-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1612#L1454-3true assume !(1 == ~T5_E~0); 838#L1459-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1972#L1464-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1390#L1469-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1265#L1474-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1620#L1479-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1398#L1484-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 576#L1489-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 1153#L1494-3true assume !(1 == ~T13_E~0); 1768#L1499-3true assume 1 == ~E_M~0;~E_M~0 := 2; 785#L1504-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1279#L1509-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1341#L1514-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1863#L1519-3true assume 1 == ~E_4~0;~E_4~0 := 2; 516#L1524-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1454#L1529-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1670#L1534-3true assume !(1 == ~E_7~0); 727#L1539-3true assume 1 == ~E_8~0;~E_8~0 := 2; 370#L1544-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1406#L1549-3true assume 1 == ~E_10~0;~E_10~0 := 2; 700#L1554-3true assume 1 == ~E_11~0;~E_11~0 := 2; 173#L1559-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1178#L1564-3true assume 1 == ~E_13~0;~E_13~0 := 2; 923#L1569-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1097#L987-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 426#L1059-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1086#L1060-1true start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 904#L1954true assume !(0 == start_simulation_~tmp~3); 867#L1954-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1180#L987-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 979#L1059-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1364#L1060-2true stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 1136#L1909true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1274#L1916true stop_simulation_#res := stop_simulation_~__retres2~0; 1381#L1917true start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 1770#L1967true assume !(0 != start_simulation_~tmp___0~1); 361#L1935-1true [2021-11-07 07:29:49,405 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:49,405 INFO L85 PathProgramCache]: Analyzing trace with hash -1425010847, now seen corresponding path program 1 times [2021-11-07 07:29:49,417 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:49,417 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [195649316] [2021-11-07 07:29:49,418 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:49,419 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:49,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:49,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:49,741 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:49,741 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [195649316] [2021-11-07 07:29:49,743 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [195649316] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:49,743 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:49,744 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:49,747 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1788154083] [2021-11-07 07:29:49,756 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:29:49,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:49,760 INFO L85 PathProgramCache]: Analyzing trace with hash -1212143188, now seen corresponding path program 1 times [2021-11-07 07:29:49,761 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:49,761 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1215033274] [2021-11-07 07:29:49,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:49,762 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:49,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:49,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:49,877 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:49,877 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1215033274] [2021-11-07 07:29:49,877 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1215033274] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:49,878 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:49,878 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 07:29:49,878 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1095323351] [2021-11-07 07:29:49,883 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:29:49,884 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:29:49,911 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:29:49,912 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:29:49,921 INFO L87 Difference]: Start difference. First operand has 1992 states, 1991 states have (on average 1.505273731793069) internal successors, (2997), 1991 states have internal predecessors, (2997), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:50,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:29:50,099 INFO L93 Difference]: Finished difference Result 1992 states and 2962 transitions. [2021-11-07 07:29:50,100 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:29:50,102 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1992 states and 2962 transitions. [2021-11-07 07:29:50,125 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:50,150 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1992 states to 1986 states and 2956 transitions. [2021-11-07 07:29:50,152 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-07 07:29:50,155 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-07 07:29:50,156 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2956 transitions. [2021-11-07 07:29:50,170 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:29:50,170 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2956 transitions. [2021-11-07 07:29:50,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2956 transitions. [2021-11-07 07:29:50,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-07 07:29:50,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.4884189325276937) internal successors, (2956), 1985 states have internal predecessors, (2956), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:50,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2956 transitions. [2021-11-07 07:29:50,329 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2956 transitions. [2021-11-07 07:29:50,330 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2956 transitions. [2021-11-07 07:29:50,330 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-07 07:29:50,330 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2956 transitions. [2021-11-07 07:29:50,353 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:50,355 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:29:50,355 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:29:50,367 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:50,368 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:50,370 INFO L791 eck$LassoCheckResult]: Stem: 4864#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 4865#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 4601#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4602#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 4543#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4544#L914-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4787#L919-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4823#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5637#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5638#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5748#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5749#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4607#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4608#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5785#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5120#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5121#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 5691#L974-1 assume !(0 == ~M_E~0); 5424#L1286-1 assume !(0 == ~T1_E~0); 4514#L1291-1 assume !(0 == ~T2_E~0); 4515#L1296-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5209#L1301-1 assume !(0 == ~T4_E~0); 5210#L1306-1 assume !(0 == ~T5_E~0); 5700#L1311-1 assume !(0 == ~T6_E~0); 4474#L1316-1 assume !(0 == ~T7_E~0); 4475#L1321-1 assume !(0 == ~T8_E~0); 5229#L1326-1 assume !(0 == ~T9_E~0); 4291#L1331-1 assume !(0 == ~T10_E~0); 3997#L1336-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3998#L1341-1 assume !(0 == ~T12_E~0); 4049#L1346-1 assume !(0 == ~T13_E~0); 4050#L1351-1 assume !(0 == ~E_M~0); 4421#L1356-1 assume !(0 == ~E_1~0); 4422#L1361-1 assume !(0 == ~E_2~0); 5914#L1366-1 assume !(0 == ~E_3~0); 4467#L1371-1 assume !(0 == ~E_4~0); 4468#L1376-1 assume 0 == ~E_5~0;~E_5~0 := 1; 5269#L1381-1 assume !(0 == ~E_6~0); 5270#L1386-1 assume !(0 == ~E_7~0); 5941#L1391-1 assume !(0 == ~E_8~0); 5954#L1396-1 assume !(0 == ~E_9~0); 5153#L1401-1 assume !(0 == ~E_10~0); 5154#L1406-1 assume !(0 == ~E_11~0); 5452#L1411-1 assume !(0 == ~E_12~0); 5453#L1416-1 assume 0 == ~E_13~0;~E_13~0 := 1; 5080#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4918#L635 assume 1 == ~m_pc~0; 4919#L636 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4068#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4416#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 5044#L1598 assume !(0 != activate_threads_~tmp~1); 4246#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4247#L654 assume !(1 == ~t1_pc~0); 4944#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 4943#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5938#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 5024#L1606 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5025#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4294#L673 assume 1 == ~t2_pc~0; 4295#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5422#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5423#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 5965#L1614 assume !(0 != activate_threads_~tmp___1~0); 5972#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5103#L692 assume !(1 == ~t3_pc~0); 4920#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 4921#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4788#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 4758#L1622 assume !(0 != activate_threads_~tmp___2~0); 4759#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4319#L711 assume 1 == ~t4_pc~0; 4320#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4801#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5246#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 4022#L1630 assume !(0 != activate_threads_~tmp___3~0); 4023#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5961#L730 assume !(1 == ~t5_pc~0); 5356#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 4201#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4202#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 4329#L1638 assume !(0 != activate_threads_~tmp___4~0); 4330#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4672#L749 assume 1 == ~t6_pc~0; 4444#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 4206#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4638#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 4639#L1646 assume !(0 != activate_threads_~tmp___5~0); 4856#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4002#L768 assume 1 == ~t7_pc~0; 4003#L769 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 5293#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4239#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 4240#L1654 assume !(0 != activate_threads_~tmp___6~0); 5310#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4476#L787 assume !(1 == ~t8_pc~0); 4477#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 5651#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5811#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 5812#L1662 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 4047#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 4048#L806 assume 1 == ~t9_pc~0; 5662#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 4082#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 4083#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 4331#L1670 assume !(0 != activate_threads_~tmp___8~0); 4332#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 5645#L825 assume !(1 == ~t10_pc~0); 5646#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 5260#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 5261#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 4417#L1678 assume !(0 != activate_threads_~tmp___9~0); 4418#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 4993#L844 assume 1 == ~t11_pc~0; 4693#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 4694#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 5050#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 5051#L1686 assume !(0 != activate_threads_~tmp___10~0); 5634#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 5635#L863 assume !(1 == ~t12_pc~0); 4181#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 4182#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 4407#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 5724#L1694 assume !(0 != activate_threads_~tmp___11~0); 5725#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 5117#L882 assume 1 == ~t13_pc~0; 5118#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 5395#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 5885#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 5693#L1702 assume !(0 != activate_threads_~tmp___12~0); 5382#L1702-2 assume !(1 == ~M_E~0); 5383#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5831#L1439-1 assume !(1 == ~T2_E~0); 4312#L1444-1 assume !(1 == ~T3_E~0); 4313#L1449-1 assume !(1 == ~T4_E~0); 4755#L1454-1 assume !(1 == ~T5_E~0); 4756#L1459-1 assume !(1 == ~T6_E~0); 5311#L1464-1 assume !(1 == ~T7_E~0); 5312#L1469-1 assume !(1 == ~T8_E~0); 5396#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5081#L1479-1 assume !(1 == ~T10_E~0); 5082#L1484-1 assume !(1 == ~T11_E~0); 5318#L1489-1 assume !(1 == ~T12_E~0); 4959#L1494-1 assume !(1 == ~T13_E~0); 4960#L1499-1 assume !(1 == ~E_M~0); 5138#L1504-1 assume !(1 == ~E_1~0); 5139#L1509-1 assume !(1 == ~E_2~0); 5740#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5434#L1519-1 assume !(1 == ~E_4~0); 5435#L1524-1 assume !(1 == ~E_5~0); 5925#L1529-1 assume !(1 == ~E_6~0); 5926#L1534-1 assume !(1 == ~E_7~0); 4102#L1539-1 assume !(1 == ~E_8~0); 4103#L1544-1 assume !(1 == ~E_9~0); 4531#L1549-1 assume !(1 == ~E_10~0); 5904#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 5902#L1559-1 assume !(1 == ~E_12~0); 5769#L1564-1 assume !(1 == ~E_13~0); 4711#L1935-1 [2021-11-07 07:29:50,373 INFO L793 eck$LassoCheckResult]: Loop: 4711#L1935-1 assume !false; 4111#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 4112#L1261 assume !false; 5322#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 5323#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 4242#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 4410#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 4411#L1074 assume !(0 != eval_~tmp~0); 4770#L1276 start_simulation_~kernel_st~0 := 2; 5351#L902-1 start_simulation_~kernel_st~0 := 3; 5744#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4819#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4820#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5525#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5951#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5910#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5037#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4346#L1316-3 assume !(0 == ~T7_E~0); 4347#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4450#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5175#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5437#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5438#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4748#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4740#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4683#L1356-3 assume !(0 == ~E_1~0); 4684#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5250#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4037#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4038#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5755#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5607#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5608#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5786#L1396-3 assume !(0 == ~E_9~0); 5787#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4415#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4248#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 4249#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 4871#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4126#L635-45 assume 1 == ~m_pc~0; 4128#L636-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4911#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5384#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 5633#L1598-45 assume !(0 != activate_threads_~tmp~1); 4433#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4434#L654-45 assume 1 == ~t1_pc~0; 5242#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5582#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4089#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 4090#L1606-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4115#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4932#L673-45 assume !(1 == ~t2_pc~0); 4933#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 5253#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5254#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 5866#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5690#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4560#L692-45 assume 1 == ~t3_pc~0; 4561#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4287#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5314#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 4614#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4615#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4917#L711-45 assume 1 == ~t4_pc~0; 5041#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5043#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4896#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 4897#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5294#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4457#L730-45 assume 1 == ~t5_pc~0; 4297#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4298#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4707#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 4708#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5443#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4270#L749-45 assume 1 == ~t6_pc~0; 4272#L750-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 5648#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5417#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 5418#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 5565#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4586#L768-45 assume 1 == ~t7_pc~0; 4587#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 4727#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5512#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 5513#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 5550#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 5551#L787-45 assume 1 == ~t8_pc~0; 5715#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 4733#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 4734#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 5136#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 5137#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 5442#L806-45 assume !(1 == ~t9_pc~0); 4145#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 4146#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 4961#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 4797#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 4712#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 4713#L825-45 assume !(1 == ~t10_pc~0); 5222#L825-47 is_transmit10_triggered_~__retres1~10 := 0; 5223#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 5324#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 5325#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 5475#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 4354#L844-45 assume !(1 == ~t11_pc~0); 4355#L844-47 is_transmit11_triggered_~__retres1~11 := 0; 4872#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 4873#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 4886#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 5291#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 4394#L863-45 assume 1 == ~t12_pc~0; 4395#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 3995#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 3996#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 4509#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 4510#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 5297#L882-45 assume !(1 == ~t13_pc~0); 4837#L882-47 is_transmit13_triggered_~__retres1~13 := 0; 4014#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 4015#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 4623#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 5777#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 5401#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5402#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4308#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4309#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4469#L1454-3 assume !(1 == ~T5_E~0); 5391#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5392#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5828#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5757#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5758#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5830#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5039#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5040#L1494-3 assume !(1 == ~T13_E~0); 5687#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5328#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5329#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5766#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5804#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4962#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4963#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5850#L1534-3 assume !(1 == ~E_7~0); 5259#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4728#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4729#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5230#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4359#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4360#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 5490#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 5491#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 4244#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 4807#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 5463#L1954 assume !(0 == start_simulation_~tmp~3); 5429#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 5430#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 4525#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 5548#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 5675#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5676#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 5764#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 5824#L1967 assume !(0 != start_simulation_~tmp___0~1); 4711#L1935-1 [2021-11-07 07:29:50,375 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:50,375 INFO L85 PathProgramCache]: Analyzing trace with hash -813741789, now seen corresponding path program 1 times [2021-11-07 07:29:50,376 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:50,376 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [676743751] [2021-11-07 07:29:50,377 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:50,378 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:50,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:50,568 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:50,569 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:50,569 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [676743751] [2021-11-07 07:29:50,569 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [676743751] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:50,570 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:50,570 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:50,570 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [708707618] [2021-11-07 07:29:50,571 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:29:50,572 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:50,572 INFO L85 PathProgramCache]: Analyzing trace with hash 128246747, now seen corresponding path program 1 times [2021-11-07 07:29:50,572 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:50,573 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1679590469] [2021-11-07 07:29:50,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:50,573 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:50,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:50,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:50,785 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:50,791 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1679590469] [2021-11-07 07:29:50,792 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1679590469] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:50,792 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:50,793 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:50,793 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1166972003] [2021-11-07 07:29:50,795 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:29:50,795 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:29:50,797 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:29:50,799 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:29:50,801 INFO L87 Difference]: Start difference. First operand 1986 states and 2956 transitions. cyclomatic complexity: 971 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:50,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:29:50,850 INFO L93 Difference]: Finished difference Result 1986 states and 2955 transitions. [2021-11-07 07:29:50,851 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:29:50,854 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2955 transitions. [2021-11-07 07:29:50,936 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:50,960 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2955 transitions. [2021-11-07 07:29:50,960 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-07 07:29:50,963 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-07 07:29:50,964 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2955 transitions. [2021-11-07 07:29:50,969 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:29:50,969 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2955 transitions. [2021-11-07 07:29:50,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2955 transitions. [2021-11-07 07:29:51,026 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-07 07:29:51,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.487915407854985) internal successors, (2955), 1985 states have internal predecessors, (2955), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:51,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2955 transitions. [2021-11-07 07:29:51,045 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2955 transitions. [2021-11-07 07:29:51,045 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2955 transitions. [2021-11-07 07:29:51,045 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-07 07:29:51,046 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2955 transitions. [2021-11-07 07:29:51,071 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:51,071 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:29:51,071 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:29:51,082 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:51,083 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:51,084 INFO L791 eck$LassoCheckResult]: Stem: 8843#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 8844#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 8580#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8581#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 8522#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8523#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8766#L919-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8802#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9616#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9617#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9727#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9728#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8586#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8587#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9764#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9099#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9100#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 9670#L974-1 assume !(0 == ~M_E~0); 9403#L1286-1 assume !(0 == ~T1_E~0); 8493#L1291-1 assume !(0 == ~T2_E~0); 8494#L1296-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9188#L1301-1 assume !(0 == ~T4_E~0); 9189#L1306-1 assume !(0 == ~T5_E~0); 9679#L1311-1 assume !(0 == ~T6_E~0); 8453#L1316-1 assume !(0 == ~T7_E~0); 8454#L1321-1 assume !(0 == ~T8_E~0); 9208#L1326-1 assume !(0 == ~T9_E~0); 8270#L1331-1 assume !(0 == ~T10_E~0); 7976#L1336-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 7977#L1341-1 assume !(0 == ~T12_E~0); 8028#L1346-1 assume !(0 == ~T13_E~0); 8029#L1351-1 assume !(0 == ~E_M~0); 8400#L1356-1 assume !(0 == ~E_1~0); 8401#L1361-1 assume !(0 == ~E_2~0); 9893#L1366-1 assume !(0 == ~E_3~0); 8446#L1371-1 assume !(0 == ~E_4~0); 8447#L1376-1 assume 0 == ~E_5~0;~E_5~0 := 1; 9248#L1381-1 assume !(0 == ~E_6~0); 9249#L1386-1 assume !(0 == ~E_7~0); 9920#L1391-1 assume !(0 == ~E_8~0); 9933#L1396-1 assume !(0 == ~E_9~0); 9132#L1401-1 assume !(0 == ~E_10~0); 9133#L1406-1 assume !(0 == ~E_11~0); 9431#L1411-1 assume !(0 == ~E_12~0); 9432#L1416-1 assume 0 == ~E_13~0;~E_13~0 := 1; 9059#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8897#L635 assume 1 == ~m_pc~0; 8898#L636 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 8047#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8395#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 9023#L1598 assume !(0 != activate_threads_~tmp~1); 8225#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8226#L654 assume !(1 == ~t1_pc~0); 8923#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 8922#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9917#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 9003#L1606 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9004#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8273#L673 assume 1 == ~t2_pc~0; 8274#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9401#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9402#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 9944#L1614 assume !(0 != activate_threads_~tmp___1~0); 9951#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9082#L692 assume !(1 == ~t3_pc~0); 8899#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 8900#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8767#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 8737#L1622 assume !(0 != activate_threads_~tmp___2~0); 8738#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8298#L711 assume 1 == ~t4_pc~0; 8299#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8780#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9225#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 8001#L1630 assume !(0 != activate_threads_~tmp___3~0); 8002#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9940#L730 assume !(1 == ~t5_pc~0); 9335#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 8180#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8181#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 8308#L1638 assume !(0 != activate_threads_~tmp___4~0); 8309#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8651#L749 assume 1 == ~t6_pc~0; 8423#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 8185#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8617#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 8618#L1646 assume !(0 != activate_threads_~tmp___5~0); 8835#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 7981#L768 assume 1 == ~t7_pc~0; 7982#L769 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 9272#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8218#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 8219#L1654 assume !(0 != activate_threads_~tmp___6~0); 9289#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 8455#L787 assume !(1 == ~t8_pc~0); 8456#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 9630#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 9790#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 9791#L1662 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 8026#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 8027#L806 assume 1 == ~t9_pc~0; 9641#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 8061#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 8062#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 8310#L1670 assume !(0 != activate_threads_~tmp___8~0); 8311#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 9624#L825 assume !(1 == ~t10_pc~0); 9625#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 9239#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 9240#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 8396#L1678 assume !(0 != activate_threads_~tmp___9~0); 8397#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 8972#L844 assume 1 == ~t11_pc~0; 8672#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 8673#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 9029#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 9030#L1686 assume !(0 != activate_threads_~tmp___10~0); 9613#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 9614#L863 assume !(1 == ~t12_pc~0); 8160#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 8161#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 8386#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 9703#L1694 assume !(0 != activate_threads_~tmp___11~0); 9704#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 9096#L882 assume 1 == ~t13_pc~0; 9097#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 9374#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 9864#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 9672#L1702 assume !(0 != activate_threads_~tmp___12~0); 9361#L1702-2 assume !(1 == ~M_E~0); 9362#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9810#L1439-1 assume !(1 == ~T2_E~0); 8291#L1444-1 assume !(1 == ~T3_E~0); 8292#L1449-1 assume !(1 == ~T4_E~0); 8734#L1454-1 assume !(1 == ~T5_E~0); 8735#L1459-1 assume !(1 == ~T6_E~0); 9290#L1464-1 assume !(1 == ~T7_E~0); 9291#L1469-1 assume !(1 == ~T8_E~0); 9375#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9060#L1479-1 assume !(1 == ~T10_E~0); 9061#L1484-1 assume !(1 == ~T11_E~0); 9297#L1489-1 assume !(1 == ~T12_E~0); 8938#L1494-1 assume !(1 == ~T13_E~0); 8939#L1499-1 assume !(1 == ~E_M~0); 9117#L1504-1 assume !(1 == ~E_1~0); 9118#L1509-1 assume !(1 == ~E_2~0); 9719#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 9413#L1519-1 assume !(1 == ~E_4~0); 9414#L1524-1 assume !(1 == ~E_5~0); 9904#L1529-1 assume !(1 == ~E_6~0); 9905#L1534-1 assume !(1 == ~E_7~0); 8081#L1539-1 assume !(1 == ~E_8~0); 8082#L1544-1 assume !(1 == ~E_9~0); 8510#L1549-1 assume !(1 == ~E_10~0); 9883#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 9881#L1559-1 assume !(1 == ~E_12~0); 9748#L1564-1 assume !(1 == ~E_13~0); 8690#L1935-1 [2021-11-07 07:29:51,085 INFO L793 eck$LassoCheckResult]: Loop: 8690#L1935-1 assume !false; 8090#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 8091#L1261 assume !false; 9301#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 9302#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 8221#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 8389#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 8390#L1074 assume !(0 != eval_~tmp~0); 8749#L1276 start_simulation_~kernel_st~0 := 2; 9330#L902-1 start_simulation_~kernel_st~0 := 3; 9723#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 8798#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8799#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9504#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9930#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9889#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9016#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8325#L1316-3 assume !(0 == ~T7_E~0); 8326#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8429#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9154#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9416#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9417#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8727#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 8719#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8662#L1356-3 assume !(0 == ~E_1~0); 8663#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9229#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8016#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8017#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9734#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9586#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9587#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9765#L1396-3 assume !(0 == ~E_9~0); 9766#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8394#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 8227#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 8228#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 8850#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8105#L635-45 assume !(1 == ~m_pc~0); 8106#L635-47 is_master_triggered_~__retres1~0 := 0; 8890#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9363#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 9612#L1598-45 assume !(0 != activate_threads_~tmp~1); 8412#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8413#L654-45 assume 1 == ~t1_pc~0; 9221#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9561#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8068#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 8069#L1606-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8094#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8911#L673-45 assume !(1 == ~t2_pc~0); 8912#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 9232#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9233#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 9845#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9669#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8539#L692-45 assume !(1 == ~t3_pc~0); 8265#L692-47 is_transmit3_triggered_~__retres1~3 := 0; 8266#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9293#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 8593#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8594#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8896#L711-45 assume 1 == ~t4_pc~0; 9020#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9022#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8875#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 8876#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 9273#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8436#L730-45 assume 1 == ~t5_pc~0; 8276#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8277#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8686#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 8687#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 9422#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8249#L749-45 assume !(1 == ~t6_pc~0); 8250#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 9627#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9396#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 9397#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 9544#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8565#L768-45 assume 1 == ~t7_pc~0; 8566#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 8706#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 9491#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 9492#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 9529#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 9530#L787-45 assume 1 == ~t8_pc~0; 9694#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 8712#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 8713#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 9115#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 9116#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 9421#L806-45 assume !(1 == ~t9_pc~0); 8124#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 8125#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 8940#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 8776#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 8691#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 8692#L825-45 assume !(1 == ~t10_pc~0); 9201#L825-47 is_transmit10_triggered_~__retres1~10 := 0; 9202#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 9303#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 9304#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 9454#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 8333#L844-45 assume !(1 == ~t11_pc~0); 8334#L844-47 is_transmit11_triggered_~__retres1~11 := 0; 8851#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 8852#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 8865#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 9270#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 8373#L863-45 assume 1 == ~t12_pc~0; 8374#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 7974#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 7975#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 8488#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 8489#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 9276#L882-45 assume !(1 == ~t13_pc~0); 8816#L882-47 is_transmit13_triggered_~__retres1~13 := 0; 7993#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 7994#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 8602#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 9756#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 9380#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9381#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8287#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8288#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8448#L1454-3 assume !(1 == ~T5_E~0); 9370#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9371#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9807#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9736#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9737#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9809#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9018#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 9019#L1494-3 assume !(1 == ~T13_E~0); 9666#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9307#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9308#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9745#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9783#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8941#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8942#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9829#L1534-3 assume !(1 == ~E_7~0); 9238#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8707#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 8708#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9209#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8338#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8339#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 9469#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 9470#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 8223#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 8786#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 9442#L1954 assume !(0 == start_simulation_~tmp~3); 9408#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 9409#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 8504#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 9527#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 9654#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9655#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 9743#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 9803#L1967 assume !(0 != start_simulation_~tmp___0~1); 8690#L1935-1 [2021-11-07 07:29:51,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:51,086 INFO L85 PathProgramCache]: Analyzing trace with hash 1586891621, now seen corresponding path program 1 times [2021-11-07 07:29:51,087 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:51,087 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1044231488] [2021-11-07 07:29:51,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:51,088 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:51,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:51,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:51,207 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:51,207 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1044231488] [2021-11-07 07:29:51,208 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1044231488] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:51,208 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:51,209 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:51,209 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [796041860] [2021-11-07 07:29:51,210 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:29:51,210 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:51,211 INFO L85 PathProgramCache]: Analyzing trace with hash -1038037640, now seen corresponding path program 1 times [2021-11-07 07:29:51,212 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:51,212 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [433420338] [2021-11-07 07:29:51,213 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:51,214 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:51,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:51,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:51,302 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:51,303 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [433420338] [2021-11-07 07:29:51,303 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [433420338] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:51,303 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:51,303 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:51,304 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [811973322] [2021-11-07 07:29:51,304 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:29:51,305 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:29:51,305 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:29:51,306 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:29:51,306 INFO L87 Difference]: Start difference. First operand 1986 states and 2955 transitions. cyclomatic complexity: 970 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:51,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:29:51,362 INFO L93 Difference]: Finished difference Result 1986 states and 2954 transitions. [2021-11-07 07:29:51,362 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:29:51,362 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2954 transitions. [2021-11-07 07:29:51,387 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:51,412 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2954 transitions. [2021-11-07 07:29:51,412 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-07 07:29:51,415 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-07 07:29:51,416 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2954 transitions. [2021-11-07 07:29:51,421 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:29:51,421 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2954 transitions. [2021-11-07 07:29:51,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2954 transitions. [2021-11-07 07:29:51,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-07 07:29:51,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.487411883182276) internal successors, (2954), 1985 states have internal predecessors, (2954), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:51,489 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2954 transitions. [2021-11-07 07:29:51,489 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2954 transitions. [2021-11-07 07:29:51,490 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2954 transitions. [2021-11-07 07:29:51,490 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-07 07:29:51,490 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2954 transitions. [2021-11-07 07:29:51,509 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:51,509 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:29:51,509 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:29:51,513 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:51,514 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:51,514 INFO L791 eck$LassoCheckResult]: Stem: 12822#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 12823#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 12559#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12560#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 12501#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12502#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12745#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12781#L924-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13595#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13596#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13706#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13707#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12565#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12566#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13743#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13078#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13079#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 13649#L974-1 assume !(0 == ~M_E~0); 13382#L1286-1 assume !(0 == ~T1_E~0); 12472#L1291-1 assume !(0 == ~T2_E~0); 12473#L1296-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13167#L1301-1 assume !(0 == ~T4_E~0); 13168#L1306-1 assume !(0 == ~T5_E~0); 13658#L1311-1 assume !(0 == ~T6_E~0); 12432#L1316-1 assume !(0 == ~T7_E~0); 12433#L1321-1 assume !(0 == ~T8_E~0); 13187#L1326-1 assume !(0 == ~T9_E~0); 12249#L1331-1 assume !(0 == ~T10_E~0); 11955#L1336-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 11956#L1341-1 assume !(0 == ~T12_E~0); 12007#L1346-1 assume !(0 == ~T13_E~0); 12008#L1351-1 assume !(0 == ~E_M~0); 12379#L1356-1 assume !(0 == ~E_1~0); 12380#L1361-1 assume !(0 == ~E_2~0); 13872#L1366-1 assume !(0 == ~E_3~0); 12425#L1371-1 assume !(0 == ~E_4~0); 12426#L1376-1 assume 0 == ~E_5~0;~E_5~0 := 1; 13227#L1381-1 assume !(0 == ~E_6~0); 13228#L1386-1 assume !(0 == ~E_7~0); 13899#L1391-1 assume !(0 == ~E_8~0); 13912#L1396-1 assume !(0 == ~E_9~0); 13111#L1401-1 assume !(0 == ~E_10~0); 13112#L1406-1 assume !(0 == ~E_11~0); 13410#L1411-1 assume !(0 == ~E_12~0); 13411#L1416-1 assume 0 == ~E_13~0;~E_13~0 := 1; 13038#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12876#L635 assume 1 == ~m_pc~0; 12877#L636 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 12026#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12374#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 13002#L1598 assume !(0 != activate_threads_~tmp~1); 12204#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12205#L654 assume !(1 == ~t1_pc~0); 12902#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 12901#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13896#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 12982#L1606 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12983#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12252#L673 assume 1 == ~t2_pc~0; 12253#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 13380#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13381#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 13923#L1614 assume !(0 != activate_threads_~tmp___1~0); 13930#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13061#L692 assume !(1 == ~t3_pc~0); 12878#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 12879#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12746#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 12716#L1622 assume !(0 != activate_threads_~tmp___2~0); 12717#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12277#L711 assume 1 == ~t4_pc~0; 12278#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12759#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13204#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 11980#L1630 assume !(0 != activate_threads_~tmp___3~0); 11981#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13919#L730 assume !(1 == ~t5_pc~0); 13314#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 12159#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12160#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 12287#L1638 assume !(0 != activate_threads_~tmp___4~0); 12288#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12630#L749 assume 1 == ~t6_pc~0; 12402#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 12164#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12596#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 12597#L1646 assume !(0 != activate_threads_~tmp___5~0); 12814#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11960#L768 assume 1 == ~t7_pc~0; 11961#L769 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 13251#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12197#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 12198#L1654 assume !(0 != activate_threads_~tmp___6~0); 13268#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 12434#L787 assume !(1 == ~t8_pc~0); 12435#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 13609#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 13769#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 13770#L1662 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 12005#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 12006#L806 assume 1 == ~t9_pc~0; 13620#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 12040#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 12041#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 12289#L1670 assume !(0 != activate_threads_~tmp___8~0); 12290#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 13603#L825 assume !(1 == ~t10_pc~0); 13604#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 13218#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 13219#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 12375#L1678 assume !(0 != activate_threads_~tmp___9~0); 12376#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 12951#L844 assume 1 == ~t11_pc~0; 12651#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 12652#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 13008#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 13009#L1686 assume !(0 != activate_threads_~tmp___10~0); 13592#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 13593#L863 assume !(1 == ~t12_pc~0); 12139#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 12140#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 12365#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 13682#L1694 assume !(0 != activate_threads_~tmp___11~0); 13683#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 13075#L882 assume 1 == ~t13_pc~0; 13076#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 13353#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 13843#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 13651#L1702 assume !(0 != activate_threads_~tmp___12~0); 13340#L1702-2 assume !(1 == ~M_E~0); 13341#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13789#L1439-1 assume !(1 == ~T2_E~0); 12270#L1444-1 assume !(1 == ~T3_E~0); 12271#L1449-1 assume !(1 == ~T4_E~0); 12713#L1454-1 assume !(1 == ~T5_E~0); 12714#L1459-1 assume !(1 == ~T6_E~0); 13269#L1464-1 assume !(1 == ~T7_E~0); 13270#L1469-1 assume !(1 == ~T8_E~0); 13354#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13039#L1479-1 assume !(1 == ~T10_E~0); 13040#L1484-1 assume !(1 == ~T11_E~0); 13276#L1489-1 assume !(1 == ~T12_E~0); 12917#L1494-1 assume !(1 == ~T13_E~0); 12918#L1499-1 assume !(1 == ~E_M~0); 13096#L1504-1 assume !(1 == ~E_1~0); 13097#L1509-1 assume !(1 == ~E_2~0); 13698#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 13392#L1519-1 assume !(1 == ~E_4~0); 13393#L1524-1 assume !(1 == ~E_5~0); 13883#L1529-1 assume !(1 == ~E_6~0); 13884#L1534-1 assume !(1 == ~E_7~0); 12060#L1539-1 assume !(1 == ~E_8~0); 12061#L1544-1 assume !(1 == ~E_9~0); 12489#L1549-1 assume !(1 == ~E_10~0); 13862#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 13860#L1559-1 assume !(1 == ~E_12~0); 13727#L1564-1 assume !(1 == ~E_13~0); 12669#L1935-1 [2021-11-07 07:29:51,515 INFO L793 eck$LassoCheckResult]: Loop: 12669#L1935-1 assume !false; 12069#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 12070#L1261 assume !false; 13280#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 13281#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 12200#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 12368#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 12369#L1074 assume !(0 != eval_~tmp~0); 12728#L1276 start_simulation_~kernel_st~0 := 2; 13309#L902-1 start_simulation_~kernel_st~0 := 3; 13702#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12777#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12778#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13483#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13909#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13868#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12995#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12304#L1316-3 assume !(0 == ~T7_E~0); 12305#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12408#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13133#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13395#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 13396#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12706#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 12698#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12641#L1356-3 assume !(0 == ~E_1~0); 12642#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13208#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11995#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11996#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13713#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13565#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13566#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13744#L1396-3 assume !(0 == ~E_9~0); 13745#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12373#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12206#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 12207#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 12829#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12084#L635-45 assume !(1 == ~m_pc~0); 12085#L635-47 is_master_triggered_~__retres1~0 := 0; 12869#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13342#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 13591#L1598-45 assume !(0 != activate_threads_~tmp~1); 12391#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12392#L654-45 assume 1 == ~t1_pc~0; 13200#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 13540#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12047#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 12048#L1606-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12073#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12890#L673-45 assume !(1 == ~t2_pc~0); 12891#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 13211#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13212#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 13824#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13648#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12518#L692-45 assume !(1 == ~t3_pc~0); 12244#L692-47 is_transmit3_triggered_~__retres1~3 := 0; 12245#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13272#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 12572#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12573#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12875#L711-45 assume 1 == ~t4_pc~0; 12999#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 13001#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12854#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 12855#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 13252#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12415#L730-45 assume !(1 == ~t5_pc~0); 12257#L730-47 is_transmit5_triggered_~__retres1~5 := 0; 12256#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12665#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 12666#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 13401#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12228#L749-45 assume !(1 == ~t6_pc~0); 12229#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 13606#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 13375#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 13376#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 13523#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 12544#L768-45 assume 1 == ~t7_pc~0; 12545#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 12685#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 13470#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 13471#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 13508#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 13509#L787-45 assume 1 == ~t8_pc~0; 13673#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 12691#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 12692#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 13094#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 13095#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 13400#L806-45 assume !(1 == ~t9_pc~0); 12103#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 12104#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 12919#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 12755#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 12670#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 12671#L825-45 assume 1 == ~t10_pc~0; 13266#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 13181#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 13282#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 13283#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 13433#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 12312#L844-45 assume !(1 == ~t11_pc~0); 12313#L844-47 is_transmit11_triggered_~__retres1~11 := 0; 12830#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 12831#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 12844#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 13249#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 12352#L863-45 assume 1 == ~t12_pc~0; 12353#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 11953#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 11954#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 12467#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 12468#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 13255#L882-45 assume 1 == ~t13_pc~0; 13600#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 11972#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 11973#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 12581#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 13735#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 13359#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13360#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12266#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12267#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12427#L1454-3 assume !(1 == ~T5_E~0); 13349#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13350#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13786#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13715#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13716#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13788#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12997#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12998#L1494-3 assume !(1 == ~T13_E~0); 13645#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13286#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13287#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13724#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13762#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12920#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12921#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13808#L1534-3 assume !(1 == ~E_7~0); 13217#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12686#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12687#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13188#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12317#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12318#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 13448#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 13449#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 12202#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 12765#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 13421#L1954 assume !(0 == start_simulation_~tmp~3); 13387#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 13388#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 12483#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 13506#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 13633#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 13634#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 13722#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 13782#L1967 assume !(0 != start_simulation_~tmp___0~1); 12669#L1935-1 [2021-11-07 07:29:51,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:51,516 INFO L85 PathProgramCache]: Analyzing trace with hash 140310755, now seen corresponding path program 1 times [2021-11-07 07:29:51,516 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:51,517 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [895027758] [2021-11-07 07:29:51,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:51,517 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:51,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:51,571 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:51,571 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:51,571 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [895027758] [2021-11-07 07:29:51,572 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [895027758] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:51,572 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:51,572 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:51,572 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [940585673] [2021-11-07 07:29:51,573 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:29:51,574 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:51,574 INFO L85 PathProgramCache]: Analyzing trace with hash -161956135, now seen corresponding path program 1 times [2021-11-07 07:29:51,574 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:51,575 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1599993779] [2021-11-07 07:29:51,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:51,575 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:51,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:51,708 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:51,712 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:51,713 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1599993779] [2021-11-07 07:29:51,714 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1599993779] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:51,714 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:51,714 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:51,715 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [262279137] [2021-11-07 07:29:51,716 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:29:51,716 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:29:51,718 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:29:51,719 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:29:51,720 INFO L87 Difference]: Start difference. First operand 1986 states and 2954 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:51,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:29:51,770 INFO L93 Difference]: Finished difference Result 1986 states and 2953 transitions. [2021-11-07 07:29:51,770 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:29:51,770 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2953 transitions. [2021-11-07 07:29:51,793 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:51,815 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2953 transitions. [2021-11-07 07:29:51,816 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-07 07:29:51,819 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-07 07:29:51,819 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2953 transitions. [2021-11-07 07:29:51,824 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:29:51,824 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2953 transitions. [2021-11-07 07:29:51,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2953 transitions. [2021-11-07 07:29:51,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-07 07:29:51,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.486908358509567) internal successors, (2953), 1985 states have internal predecessors, (2953), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:51,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2953 transitions. [2021-11-07 07:29:51,885 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2953 transitions. [2021-11-07 07:29:51,885 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2953 transitions. [2021-11-07 07:29:51,885 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-07 07:29:51,885 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2953 transitions. [2021-11-07 07:29:51,902 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:51,902 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:29:51,902 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:29:51,906 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:51,907 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:51,907 INFO L791 eck$LassoCheckResult]: Stem: 16801#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 16802#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 16538#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 16539#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 16480#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16481#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16724#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16760#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17574#L929-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17575#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17685#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17686#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16544#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16545#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17722#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17057#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 17058#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 17628#L974-1 assume !(0 == ~M_E~0); 17361#L1286-1 assume !(0 == ~T1_E~0); 16451#L1291-1 assume !(0 == ~T2_E~0); 16452#L1296-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17146#L1301-1 assume !(0 == ~T4_E~0); 17147#L1306-1 assume !(0 == ~T5_E~0); 17637#L1311-1 assume !(0 == ~T6_E~0); 16411#L1316-1 assume !(0 == ~T7_E~0); 16412#L1321-1 assume !(0 == ~T8_E~0); 17166#L1326-1 assume !(0 == ~T9_E~0); 16228#L1331-1 assume !(0 == ~T10_E~0); 15934#L1336-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 15935#L1341-1 assume !(0 == ~T12_E~0); 15986#L1346-1 assume !(0 == ~T13_E~0); 15987#L1351-1 assume !(0 == ~E_M~0); 16358#L1356-1 assume !(0 == ~E_1~0); 16359#L1361-1 assume !(0 == ~E_2~0); 17851#L1366-1 assume !(0 == ~E_3~0); 16404#L1371-1 assume !(0 == ~E_4~0); 16405#L1376-1 assume 0 == ~E_5~0;~E_5~0 := 1; 17206#L1381-1 assume !(0 == ~E_6~0); 17207#L1386-1 assume !(0 == ~E_7~0); 17878#L1391-1 assume !(0 == ~E_8~0); 17891#L1396-1 assume !(0 == ~E_9~0); 17090#L1401-1 assume !(0 == ~E_10~0); 17091#L1406-1 assume !(0 == ~E_11~0); 17389#L1411-1 assume !(0 == ~E_12~0); 17390#L1416-1 assume 0 == ~E_13~0;~E_13~0 := 1; 17017#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16855#L635 assume 1 == ~m_pc~0; 16856#L636 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 16005#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16353#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 16981#L1598 assume !(0 != activate_threads_~tmp~1); 16183#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16184#L654 assume !(1 == ~t1_pc~0); 16881#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 16880#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17875#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 16961#L1606 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16962#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16231#L673 assume 1 == ~t2_pc~0; 16232#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 17359#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17360#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 17902#L1614 assume !(0 != activate_threads_~tmp___1~0); 17909#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17040#L692 assume !(1 == ~t3_pc~0); 16857#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 16858#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16725#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 16695#L1622 assume !(0 != activate_threads_~tmp___2~0); 16696#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16256#L711 assume 1 == ~t4_pc~0; 16257#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 16738#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17183#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 15959#L1630 assume !(0 != activate_threads_~tmp___3~0); 15960#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 17898#L730 assume !(1 == ~t5_pc~0); 17293#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 16138#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16139#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 16266#L1638 assume !(0 != activate_threads_~tmp___4~0); 16267#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 16609#L749 assume 1 == ~t6_pc~0; 16381#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 16143#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16575#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 16576#L1646 assume !(0 != activate_threads_~tmp___5~0); 16793#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 15939#L768 assume 1 == ~t7_pc~0; 15940#L769 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 17230#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 16176#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 16177#L1654 assume !(0 != activate_threads_~tmp___6~0); 17247#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 16413#L787 assume !(1 == ~t8_pc~0); 16414#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 17588#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 17748#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 17749#L1662 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 15984#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 15985#L806 assume 1 == ~t9_pc~0; 17599#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 16019#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 16020#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 16268#L1670 assume !(0 != activate_threads_~tmp___8~0); 16269#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 17582#L825 assume !(1 == ~t10_pc~0); 17583#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 17197#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 17198#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 16354#L1678 assume !(0 != activate_threads_~tmp___9~0); 16355#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 16930#L844 assume 1 == ~t11_pc~0; 16630#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 16631#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 16987#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 16988#L1686 assume !(0 != activate_threads_~tmp___10~0); 17571#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 17572#L863 assume !(1 == ~t12_pc~0); 16118#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 16119#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 16344#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 17661#L1694 assume !(0 != activate_threads_~tmp___11~0); 17662#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 17054#L882 assume 1 == ~t13_pc~0; 17055#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 17332#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 17822#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 17630#L1702 assume !(0 != activate_threads_~tmp___12~0); 17319#L1702-2 assume !(1 == ~M_E~0); 17320#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17768#L1439-1 assume !(1 == ~T2_E~0); 16249#L1444-1 assume !(1 == ~T3_E~0); 16250#L1449-1 assume !(1 == ~T4_E~0); 16692#L1454-1 assume !(1 == ~T5_E~0); 16693#L1459-1 assume !(1 == ~T6_E~0); 17248#L1464-1 assume !(1 == ~T7_E~0); 17249#L1469-1 assume !(1 == ~T8_E~0); 17333#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17018#L1479-1 assume !(1 == ~T10_E~0); 17019#L1484-1 assume !(1 == ~T11_E~0); 17255#L1489-1 assume !(1 == ~T12_E~0); 16896#L1494-1 assume !(1 == ~T13_E~0); 16897#L1499-1 assume !(1 == ~E_M~0); 17075#L1504-1 assume !(1 == ~E_1~0); 17076#L1509-1 assume !(1 == ~E_2~0); 17677#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 17371#L1519-1 assume !(1 == ~E_4~0); 17372#L1524-1 assume !(1 == ~E_5~0); 17862#L1529-1 assume !(1 == ~E_6~0); 17863#L1534-1 assume !(1 == ~E_7~0); 16039#L1539-1 assume !(1 == ~E_8~0); 16040#L1544-1 assume !(1 == ~E_9~0); 16468#L1549-1 assume !(1 == ~E_10~0); 17841#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 17839#L1559-1 assume !(1 == ~E_12~0); 17706#L1564-1 assume !(1 == ~E_13~0); 16648#L1935-1 [2021-11-07 07:29:51,908 INFO L793 eck$LassoCheckResult]: Loop: 16648#L1935-1 assume !false; 16048#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 16049#L1261 assume !false; 17259#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 17260#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 16179#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 16347#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 16348#L1074 assume !(0 != eval_~tmp~0); 16707#L1276 start_simulation_~kernel_st~0 := 2; 17288#L902-1 start_simulation_~kernel_st~0 := 3; 17681#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 16756#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16757#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17462#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17888#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17847#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16974#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16283#L1316-3 assume !(0 == ~T7_E~0); 16284#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16387#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 17112#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 17374#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17375#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 16685#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 16677#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16620#L1356-3 assume !(0 == ~E_1~0); 16621#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17187#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15974#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15975#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17692#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17544#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17545#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17723#L1396-3 assume !(0 == ~E_9~0); 17724#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16352#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16185#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 16186#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 16808#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16063#L635-45 assume !(1 == ~m_pc~0); 16064#L635-47 is_master_triggered_~__retres1~0 := 0; 16848#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17321#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 17570#L1598-45 assume !(0 != activate_threads_~tmp~1); 16370#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16371#L654-45 assume 1 == ~t1_pc~0; 17179#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 17519#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16026#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 16027#L1606-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16052#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16869#L673-45 assume !(1 == ~t2_pc~0); 16870#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 17190#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17191#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 17803#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 17627#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16497#L692-45 assume 1 == ~t3_pc~0; 16498#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 16224#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17251#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 16551#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 16552#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16854#L711-45 assume 1 == ~t4_pc~0; 16978#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 16980#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16833#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 16834#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 17231#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16394#L730-45 assume 1 == ~t5_pc~0; 16234#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 16235#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16644#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 16645#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 17380#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 16207#L749-45 assume !(1 == ~t6_pc~0); 16208#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 17585#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 17354#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 17355#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 17502#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 16523#L768-45 assume 1 == ~t7_pc~0; 16524#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 16664#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 17449#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 17450#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 17487#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 17488#L787-45 assume 1 == ~t8_pc~0; 17652#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 16670#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 16671#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 17073#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 17074#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 17379#L806-45 assume !(1 == ~t9_pc~0); 16082#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 16083#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 16898#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 16734#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 16649#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 16650#L825-45 assume !(1 == ~t10_pc~0); 17159#L825-47 is_transmit10_triggered_~__retres1~10 := 0; 17160#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 17261#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 17262#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 17412#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 16291#L844-45 assume !(1 == ~t11_pc~0); 16292#L844-47 is_transmit11_triggered_~__retres1~11 := 0; 16809#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 16810#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 16823#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 17228#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 16331#L863-45 assume 1 == ~t12_pc~0; 16332#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 15932#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 15933#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 16446#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 16447#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 17234#L882-45 assume !(1 == ~t13_pc~0); 16774#L882-47 is_transmit13_triggered_~__retres1~13 := 0; 15951#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 15952#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 16560#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 17714#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 17338#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17339#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16245#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16246#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16406#L1454-3 assume !(1 == ~T5_E~0); 17328#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17329#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17765#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17694#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17695#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17767#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16976#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16977#L1494-3 assume !(1 == ~T13_E~0); 17624#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17265#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17266#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17703#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17741#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16899#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16900#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17787#L1534-3 assume !(1 == ~E_7~0); 17196#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16665#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 16666#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 17167#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16296#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16297#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 17427#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 17428#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 16181#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 16744#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 17400#L1954 assume !(0 == start_simulation_~tmp~3); 17366#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 17367#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 16462#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 17485#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 17612#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 17613#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 17701#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 17761#L1967 assume !(0 != start_simulation_~tmp___0~1); 16648#L1935-1 [2021-11-07 07:29:51,909 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:51,909 INFO L85 PathProgramCache]: Analyzing trace with hash 1063478181, now seen corresponding path program 1 times [2021-11-07 07:29:51,910 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:51,910 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [571451107] [2021-11-07 07:29:51,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:51,910 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:51,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:51,968 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:51,968 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:51,969 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [571451107] [2021-11-07 07:29:51,969 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [571451107] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:51,969 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:51,970 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:51,970 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1458603824] [2021-11-07 07:29:51,971 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:29:51,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:51,971 INFO L85 PathProgramCache]: Analyzing trace with hash -1359360103, now seen corresponding path program 1 times [2021-11-07 07:29:51,972 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:51,972 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [799354350] [2021-11-07 07:29:51,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:51,972 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:51,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:52,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:52,042 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:52,043 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [799354350] [2021-11-07 07:29:52,043 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [799354350] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:52,043 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:52,043 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:52,044 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [539362729] [2021-11-07 07:29:52,044 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:29:52,045 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:29:52,046 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:29:52,046 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:29:52,047 INFO L87 Difference]: Start difference. First operand 1986 states and 2953 transitions. cyclomatic complexity: 968 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:52,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:29:52,096 INFO L93 Difference]: Finished difference Result 1986 states and 2952 transitions. [2021-11-07 07:29:52,098 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:29:52,098 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2952 transitions. [2021-11-07 07:29:52,120 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:52,142 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2952 transitions. [2021-11-07 07:29:52,143 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-07 07:29:52,146 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-07 07:29:52,146 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2952 transitions. [2021-11-07 07:29:52,151 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:29:52,151 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2952 transitions. [2021-11-07 07:29:52,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2952 transitions. [2021-11-07 07:29:52,196 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-07 07:29:52,202 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.486404833836858) internal successors, (2952), 1985 states have internal predecessors, (2952), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:52,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2952 transitions. [2021-11-07 07:29:52,213 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2952 transitions. [2021-11-07 07:29:52,213 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2952 transitions. [2021-11-07 07:29:52,213 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-07 07:29:52,213 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2952 transitions. [2021-11-07 07:29:52,225 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:52,225 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:29:52,225 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:29:52,229 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:52,230 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:52,230 INFO L791 eck$LassoCheckResult]: Stem: 20780#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 20781#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 20517#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 20518#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 20459#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20460#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20703#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20739#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21553#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21554#L934-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 21664#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 21665#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20523#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20524#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21701#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21036#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21037#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 21607#L974-1 assume !(0 == ~M_E~0); 21340#L1286-1 assume !(0 == ~T1_E~0); 20430#L1291-1 assume !(0 == ~T2_E~0); 20431#L1296-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21125#L1301-1 assume !(0 == ~T4_E~0); 21126#L1306-1 assume !(0 == ~T5_E~0); 21616#L1311-1 assume !(0 == ~T6_E~0); 20390#L1316-1 assume !(0 == ~T7_E~0); 20391#L1321-1 assume !(0 == ~T8_E~0); 21145#L1326-1 assume !(0 == ~T9_E~0); 20207#L1331-1 assume !(0 == ~T10_E~0); 19913#L1336-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 19914#L1341-1 assume !(0 == ~T12_E~0); 19965#L1346-1 assume !(0 == ~T13_E~0); 19966#L1351-1 assume !(0 == ~E_M~0); 20337#L1356-1 assume !(0 == ~E_1~0); 20338#L1361-1 assume !(0 == ~E_2~0); 21830#L1366-1 assume !(0 == ~E_3~0); 20383#L1371-1 assume !(0 == ~E_4~0); 20384#L1376-1 assume 0 == ~E_5~0;~E_5~0 := 1; 21185#L1381-1 assume !(0 == ~E_6~0); 21186#L1386-1 assume !(0 == ~E_7~0); 21857#L1391-1 assume !(0 == ~E_8~0); 21870#L1396-1 assume !(0 == ~E_9~0); 21069#L1401-1 assume !(0 == ~E_10~0); 21070#L1406-1 assume !(0 == ~E_11~0); 21368#L1411-1 assume !(0 == ~E_12~0); 21369#L1416-1 assume 0 == ~E_13~0;~E_13~0 := 1; 20996#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20834#L635 assume 1 == ~m_pc~0; 20835#L636 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 19984#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20332#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 20960#L1598 assume !(0 != activate_threads_~tmp~1); 20162#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20163#L654 assume !(1 == ~t1_pc~0); 20860#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 20859#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21854#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 20940#L1606 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 20941#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20210#L673 assume 1 == ~t2_pc~0; 20211#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 21338#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21339#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 21881#L1614 assume !(0 != activate_threads_~tmp___1~0); 21888#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21019#L692 assume !(1 == ~t3_pc~0); 20836#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 20837#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20704#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 20674#L1622 assume !(0 != activate_threads_~tmp___2~0); 20675#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20235#L711 assume 1 == ~t4_pc~0; 20236#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 20717#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21162#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 19938#L1630 assume !(0 != activate_threads_~tmp___3~0); 19939#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 21877#L730 assume !(1 == ~t5_pc~0); 21272#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 20117#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 20118#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 20245#L1638 assume !(0 != activate_threads_~tmp___4~0); 20246#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 20588#L749 assume 1 == ~t6_pc~0; 20360#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 20122#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 20554#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 20555#L1646 assume !(0 != activate_threads_~tmp___5~0); 20772#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 19918#L768 assume 1 == ~t7_pc~0; 19919#L769 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 21209#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 20155#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 20156#L1654 assume !(0 != activate_threads_~tmp___6~0); 21226#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 20392#L787 assume !(1 == ~t8_pc~0); 20393#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 21567#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 21727#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 21728#L1662 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 19963#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 19964#L806 assume 1 == ~t9_pc~0; 21578#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 19998#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 19999#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 20247#L1670 assume !(0 != activate_threads_~tmp___8~0); 20248#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 21561#L825 assume !(1 == ~t10_pc~0); 21562#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 21176#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 21177#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 20333#L1678 assume !(0 != activate_threads_~tmp___9~0); 20334#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 20909#L844 assume 1 == ~t11_pc~0; 20609#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 20610#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 20966#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 20967#L1686 assume !(0 != activate_threads_~tmp___10~0); 21550#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 21551#L863 assume !(1 == ~t12_pc~0); 20097#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 20098#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 20323#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 21640#L1694 assume !(0 != activate_threads_~tmp___11~0); 21641#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 21033#L882 assume 1 == ~t13_pc~0; 21034#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 21311#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 21801#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 21609#L1702 assume !(0 != activate_threads_~tmp___12~0); 21298#L1702-2 assume !(1 == ~M_E~0); 21299#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21747#L1439-1 assume !(1 == ~T2_E~0); 20228#L1444-1 assume !(1 == ~T3_E~0); 20229#L1449-1 assume !(1 == ~T4_E~0); 20671#L1454-1 assume !(1 == ~T5_E~0); 20672#L1459-1 assume !(1 == ~T6_E~0); 21227#L1464-1 assume !(1 == ~T7_E~0); 21228#L1469-1 assume !(1 == ~T8_E~0); 21312#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 20997#L1479-1 assume !(1 == ~T10_E~0); 20998#L1484-1 assume !(1 == ~T11_E~0); 21234#L1489-1 assume !(1 == ~T12_E~0); 20875#L1494-1 assume !(1 == ~T13_E~0); 20876#L1499-1 assume !(1 == ~E_M~0); 21054#L1504-1 assume !(1 == ~E_1~0); 21055#L1509-1 assume !(1 == ~E_2~0); 21656#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 21350#L1519-1 assume !(1 == ~E_4~0); 21351#L1524-1 assume !(1 == ~E_5~0); 21841#L1529-1 assume !(1 == ~E_6~0); 21842#L1534-1 assume !(1 == ~E_7~0); 20018#L1539-1 assume !(1 == ~E_8~0); 20019#L1544-1 assume !(1 == ~E_9~0); 20447#L1549-1 assume !(1 == ~E_10~0); 21820#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 21818#L1559-1 assume !(1 == ~E_12~0); 21685#L1564-1 assume !(1 == ~E_13~0); 20627#L1935-1 [2021-11-07 07:29:52,231 INFO L793 eck$LassoCheckResult]: Loop: 20627#L1935-1 assume !false; 20027#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 20028#L1261 assume !false; 21238#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 21239#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 20158#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 20326#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 20327#L1074 assume !(0 != eval_~tmp~0); 20686#L1276 start_simulation_~kernel_st~0 := 2; 21267#L902-1 start_simulation_~kernel_st~0 := 3; 21660#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 20735#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20736#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21441#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21867#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21826#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20953#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20262#L1316-3 assume !(0 == ~T7_E~0); 20263#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20366#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21091#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21353#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 21354#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 20664#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 20656#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20599#L1356-3 assume !(0 == ~E_1~0); 20600#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21166#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19953#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19954#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21671#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21523#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21524#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 21702#L1396-3 assume !(0 == ~E_9~0); 21703#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 20331#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20164#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 20165#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 20787#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20042#L635-45 assume !(1 == ~m_pc~0); 20043#L635-47 is_master_triggered_~__retres1~0 := 0; 20827#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21300#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 21549#L1598-45 assume !(0 != activate_threads_~tmp~1); 20349#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20350#L654-45 assume 1 == ~t1_pc~0; 21158#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 21498#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20005#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 20006#L1606-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 20031#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20848#L673-45 assume !(1 == ~t2_pc~0); 20849#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 21169#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21170#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 21782#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 21606#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20476#L692-45 assume !(1 == ~t3_pc~0); 20202#L692-47 is_transmit3_triggered_~__retres1~3 := 0; 20203#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21230#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 20530#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 20531#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20833#L711-45 assume 1 == ~t4_pc~0; 20957#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 20959#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20812#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 20813#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 21210#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 20373#L730-45 assume 1 == ~t5_pc~0; 20213#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 20214#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 20623#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 20624#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 21359#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 20186#L749-45 assume !(1 == ~t6_pc~0); 20187#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 21564#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 21333#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 21334#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 21481#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 20502#L768-45 assume 1 == ~t7_pc~0; 20503#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 20643#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 21428#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 21429#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 21466#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 21467#L787-45 assume !(1 == ~t8_pc~0); 21632#L787-47 is_transmit8_triggered_~__retres1~8 := 0; 20649#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 20650#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 21052#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 21053#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 21358#L806-45 assume !(1 == ~t9_pc~0); 20061#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 20062#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 20877#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 20713#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 20628#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 20629#L825-45 assume !(1 == ~t10_pc~0); 21138#L825-47 is_transmit10_triggered_~__retres1~10 := 0; 21139#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 21240#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 21241#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 21391#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 20270#L844-45 assume 1 == ~t11_pc~0; 20272#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 20788#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 20789#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 20802#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 21207#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 20310#L863-45 assume 1 == ~t12_pc~0; 20311#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 19911#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 19912#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 20425#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 20426#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 21213#L882-45 assume !(1 == ~t13_pc~0); 20753#L882-47 is_transmit13_triggered_~__retres1~13 := 0; 19930#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 19931#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 20539#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 21693#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 21317#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21318#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20224#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20225#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20385#L1454-3 assume !(1 == ~T5_E~0); 21307#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21308#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21744#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21673#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21674#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21746#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20955#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20956#L1494-3 assume !(1 == ~T13_E~0); 21603#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21244#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21245#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21682#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21720#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20878#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20879#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21766#L1534-3 assume !(1 == ~E_7~0); 21175#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20644#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20645#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 21146#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20275#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 20276#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 21406#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 21407#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 20160#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 20723#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 21379#L1954 assume !(0 == start_simulation_~tmp~3); 21345#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 21346#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 20441#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 21464#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 21591#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 21592#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 21680#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 21740#L1967 assume !(0 != start_simulation_~tmp___0~1); 20627#L1935-1 [2021-11-07 07:29:52,232 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:52,232 INFO L85 PathProgramCache]: Analyzing trace with hash 677615779, now seen corresponding path program 1 times [2021-11-07 07:29:52,233 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:52,234 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [52577808] [2021-11-07 07:29:52,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:52,235 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:52,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:52,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:52,297 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:52,297 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [52577808] [2021-11-07 07:29:52,297 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [52577808] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:52,298 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:52,298 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:52,298 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [803197443] [2021-11-07 07:29:52,299 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:29:52,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:52,300 INFO L85 PathProgramCache]: Analyzing trace with hash 182727608, now seen corresponding path program 1 times [2021-11-07 07:29:52,300 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:52,301 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1323687632] [2021-11-07 07:29:52,301 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:52,301 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:52,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:52,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:52,364 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:52,369 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1323687632] [2021-11-07 07:29:52,370 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1323687632] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:52,372 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:52,372 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:52,372 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1856012842] [2021-11-07 07:29:52,374 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:29:52,377 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:29:52,378 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:29:52,378 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:29:52,379 INFO L87 Difference]: Start difference. First operand 1986 states and 2952 transitions. cyclomatic complexity: 967 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:52,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:29:52,427 INFO L93 Difference]: Finished difference Result 1986 states and 2951 transitions. [2021-11-07 07:29:52,427 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:29:52,427 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2951 transitions. [2021-11-07 07:29:52,446 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:52,469 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2951 transitions. [2021-11-07 07:29:52,471 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-07 07:29:52,474 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-07 07:29:52,474 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2951 transitions. [2021-11-07 07:29:52,479 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:29:52,479 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2951 transitions. [2021-11-07 07:29:52,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2951 transitions. [2021-11-07 07:29:52,524 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-07 07:29:52,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.485901309164149) internal successors, (2951), 1985 states have internal predecessors, (2951), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:52,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2951 transitions. [2021-11-07 07:29:52,541 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2951 transitions. [2021-11-07 07:29:52,542 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2951 transitions. [2021-11-07 07:29:52,542 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-07 07:29:52,542 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2951 transitions. [2021-11-07 07:29:52,556 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:52,556 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:29:52,556 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:29:52,560 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:52,561 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:52,561 INFO L791 eck$LassoCheckResult]: Stem: 24759#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 24760#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 24496#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 24497#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 24438#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24439#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24682#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24718#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25532#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25533#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25643#L939-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25644#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 24502#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24503#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25680#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25015#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25016#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 25586#L974-1 assume !(0 == ~M_E~0); 25319#L1286-1 assume !(0 == ~T1_E~0); 24409#L1291-1 assume !(0 == ~T2_E~0); 24410#L1296-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25104#L1301-1 assume !(0 == ~T4_E~0); 25105#L1306-1 assume !(0 == ~T5_E~0); 25595#L1311-1 assume !(0 == ~T6_E~0); 24369#L1316-1 assume !(0 == ~T7_E~0); 24370#L1321-1 assume !(0 == ~T8_E~0); 25124#L1326-1 assume !(0 == ~T9_E~0); 24186#L1331-1 assume !(0 == ~T10_E~0); 23892#L1336-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 23893#L1341-1 assume !(0 == ~T12_E~0); 23944#L1346-1 assume !(0 == ~T13_E~0); 23945#L1351-1 assume !(0 == ~E_M~0); 24316#L1356-1 assume !(0 == ~E_1~0); 24317#L1361-1 assume !(0 == ~E_2~0); 25809#L1366-1 assume !(0 == ~E_3~0); 24362#L1371-1 assume !(0 == ~E_4~0); 24363#L1376-1 assume 0 == ~E_5~0;~E_5~0 := 1; 25164#L1381-1 assume !(0 == ~E_6~0); 25165#L1386-1 assume !(0 == ~E_7~0); 25836#L1391-1 assume !(0 == ~E_8~0); 25849#L1396-1 assume !(0 == ~E_9~0); 25048#L1401-1 assume !(0 == ~E_10~0); 25049#L1406-1 assume !(0 == ~E_11~0); 25347#L1411-1 assume !(0 == ~E_12~0); 25348#L1416-1 assume 0 == ~E_13~0;~E_13~0 := 1; 24975#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 24813#L635 assume 1 == ~m_pc~0; 24814#L636 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 23963#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 24311#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 24939#L1598 assume !(0 != activate_threads_~tmp~1); 24141#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 24142#L654 assume !(1 == ~t1_pc~0); 24839#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 24838#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25833#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 24919#L1606 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 24920#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 24189#L673 assume 1 == ~t2_pc~0; 24190#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 25317#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25318#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 25860#L1614 assume !(0 != activate_threads_~tmp___1~0); 25867#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 24998#L692 assume !(1 == ~t3_pc~0); 24815#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 24816#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 24683#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 24653#L1622 assume !(0 != activate_threads_~tmp___2~0); 24654#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 24214#L711 assume 1 == ~t4_pc~0; 24215#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 24696#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 25141#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 23917#L1630 assume !(0 != activate_threads_~tmp___3~0); 23918#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 25856#L730 assume !(1 == ~t5_pc~0); 25251#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 24096#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 24097#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 24224#L1638 assume !(0 != activate_threads_~tmp___4~0); 24225#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 24567#L749 assume 1 == ~t6_pc~0; 24339#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 24101#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 24533#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 24534#L1646 assume !(0 != activate_threads_~tmp___5~0); 24751#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 23897#L768 assume 1 == ~t7_pc~0; 23898#L769 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 25188#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 24134#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 24135#L1654 assume !(0 != activate_threads_~tmp___6~0); 25205#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 24371#L787 assume !(1 == ~t8_pc~0); 24372#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 25546#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 25706#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 25707#L1662 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 23942#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 23943#L806 assume 1 == ~t9_pc~0; 25557#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 23977#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 23978#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 24226#L1670 assume !(0 != activate_threads_~tmp___8~0); 24227#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 25540#L825 assume !(1 == ~t10_pc~0); 25541#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 25155#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 25156#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 24312#L1678 assume !(0 != activate_threads_~tmp___9~0); 24313#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 24888#L844 assume 1 == ~t11_pc~0; 24588#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 24589#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 24945#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 24946#L1686 assume !(0 != activate_threads_~tmp___10~0); 25529#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 25530#L863 assume !(1 == ~t12_pc~0); 24076#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 24077#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 24302#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 25619#L1694 assume !(0 != activate_threads_~tmp___11~0); 25620#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 25012#L882 assume 1 == ~t13_pc~0; 25013#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 25290#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 25780#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 25588#L1702 assume !(0 != activate_threads_~tmp___12~0); 25277#L1702-2 assume !(1 == ~M_E~0); 25278#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25726#L1439-1 assume !(1 == ~T2_E~0); 24207#L1444-1 assume !(1 == ~T3_E~0); 24208#L1449-1 assume !(1 == ~T4_E~0); 24650#L1454-1 assume !(1 == ~T5_E~0); 24651#L1459-1 assume !(1 == ~T6_E~0); 25206#L1464-1 assume !(1 == ~T7_E~0); 25207#L1469-1 assume !(1 == ~T8_E~0); 25291#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24976#L1479-1 assume !(1 == ~T10_E~0); 24977#L1484-1 assume !(1 == ~T11_E~0); 25213#L1489-1 assume !(1 == ~T12_E~0); 24854#L1494-1 assume !(1 == ~T13_E~0); 24855#L1499-1 assume !(1 == ~E_M~0); 25033#L1504-1 assume !(1 == ~E_1~0); 25034#L1509-1 assume !(1 == ~E_2~0); 25635#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 25329#L1519-1 assume !(1 == ~E_4~0); 25330#L1524-1 assume !(1 == ~E_5~0); 25820#L1529-1 assume !(1 == ~E_6~0); 25821#L1534-1 assume !(1 == ~E_7~0); 23997#L1539-1 assume !(1 == ~E_8~0); 23998#L1544-1 assume !(1 == ~E_9~0); 24426#L1549-1 assume !(1 == ~E_10~0); 25799#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 25797#L1559-1 assume !(1 == ~E_12~0); 25664#L1564-1 assume !(1 == ~E_13~0); 24606#L1935-1 [2021-11-07 07:29:52,562 INFO L793 eck$LassoCheckResult]: Loop: 24606#L1935-1 assume !false; 24006#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 24007#L1261 assume !false; 25217#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 25218#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 24137#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 24305#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 24306#L1074 assume !(0 != eval_~tmp~0); 24665#L1276 start_simulation_~kernel_st~0 := 2; 25246#L902-1 start_simulation_~kernel_st~0 := 3; 25639#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 24714#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24715#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25420#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25846#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25805#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24932#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24241#L1316-3 assume !(0 == ~T7_E~0); 24242#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24345#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25070#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25332#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 25333#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 24643#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 24635#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 24578#L1356-3 assume !(0 == ~E_1~0); 24579#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25145#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23932#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23933#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25650#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25502#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 25503#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25681#L1396-3 assume !(0 == ~E_9~0); 25682#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24310#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24143#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 24144#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 24766#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 24021#L635-45 assume !(1 == ~m_pc~0); 24022#L635-47 is_master_triggered_~__retres1~0 := 0; 24806#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25279#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 25528#L1598-45 assume !(0 != activate_threads_~tmp~1); 24328#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 24329#L654-45 assume 1 == ~t1_pc~0; 25137#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 25477#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23984#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 23985#L1606-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 24010#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 24827#L673-45 assume !(1 == ~t2_pc~0); 24828#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 25148#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25149#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 25761#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 25585#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 24455#L692-45 assume !(1 == ~t3_pc~0); 24181#L692-47 is_transmit3_triggered_~__retres1~3 := 0; 24182#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25209#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 24509#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 24510#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 24812#L711-45 assume 1 == ~t4_pc~0; 24936#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 24938#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 24791#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 24792#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 25189#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 24352#L730-45 assume 1 == ~t5_pc~0; 24192#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 24193#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 24602#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 24603#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 25338#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 24165#L749-45 assume !(1 == ~t6_pc~0); 24166#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 25543#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 25312#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 25313#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 25460#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 24481#L768-45 assume 1 == ~t7_pc~0; 24482#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 24622#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 25407#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 25408#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 25445#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 25446#L787-45 assume 1 == ~t8_pc~0; 25610#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 24628#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 24629#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 25031#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 25032#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 25337#L806-45 assume !(1 == ~t9_pc~0); 24040#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 24041#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 24856#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 24692#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 24607#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 24608#L825-45 assume 1 == ~t10_pc~0; 25203#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 25118#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 25219#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 25220#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 25370#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 24249#L844-45 assume !(1 == ~t11_pc~0); 24250#L844-47 is_transmit11_triggered_~__retres1~11 := 0; 24767#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 24768#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 24781#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 25186#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 24289#L863-45 assume 1 == ~t12_pc~0; 24290#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 23890#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 23891#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 24404#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 24405#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 25192#L882-45 assume 1 == ~t13_pc~0; 25537#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 23909#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 23910#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 24518#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 25672#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 25296#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25297#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24203#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 24204#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 24364#L1454-3 assume !(1 == ~T5_E~0); 25286#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25287#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 25723#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25652#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25653#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25725#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24934#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 24935#L1494-3 assume !(1 == ~T13_E~0); 25582#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25223#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25224#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25661#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25699#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 24857#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24858#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25745#L1534-3 assume !(1 == ~E_7~0); 25154#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24623#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24624#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25125#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 24254#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 24255#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 25385#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 25386#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 24139#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 24702#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 25358#L1954 assume !(0 == start_simulation_~tmp~3); 25324#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 25325#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 24420#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 25443#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 25570#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 25571#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 25659#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 25719#L1967 assume !(0 != start_simulation_~tmp___0~1); 24606#L1935-1 [2021-11-07 07:29:52,563 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:52,563 INFO L85 PathProgramCache]: Analyzing trace with hash 942263269, now seen corresponding path program 1 times [2021-11-07 07:29:52,564 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:52,564 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2089672331] [2021-11-07 07:29:52,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:52,565 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:52,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:52,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:52,628 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:52,628 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2089672331] [2021-11-07 07:29:52,628 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2089672331] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:52,628 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:52,629 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:52,629 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [581939884] [2021-11-07 07:29:52,629 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:29:52,630 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:52,630 INFO L85 PathProgramCache]: Analyzing trace with hash -434951558, now seen corresponding path program 1 times [2021-11-07 07:29:52,630 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:52,631 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1178746618] [2021-11-07 07:29:52,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:52,631 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:52,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:52,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:52,698 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:52,699 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1178746618] [2021-11-07 07:29:52,699 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1178746618] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:52,699 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:52,700 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:52,700 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [758828172] [2021-11-07 07:29:52,700 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:29:52,701 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:29:52,701 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:29:52,702 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:29:52,702 INFO L87 Difference]: Start difference. First operand 1986 states and 2951 transitions. cyclomatic complexity: 966 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:52,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:29:52,751 INFO L93 Difference]: Finished difference Result 1986 states and 2950 transitions. [2021-11-07 07:29:52,752 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:29:52,752 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2950 transitions. [2021-11-07 07:29:52,772 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:52,795 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2950 transitions. [2021-11-07 07:29:52,795 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-07 07:29:52,798 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-07 07:29:52,798 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2950 transitions. [2021-11-07 07:29:52,803 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:29:52,803 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2950 transitions. [2021-11-07 07:29:52,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2950 transitions. [2021-11-07 07:29:52,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-07 07:29:52,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.48539778449144) internal successors, (2950), 1985 states have internal predecessors, (2950), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:52,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2950 transitions. [2021-11-07 07:29:52,863 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2950 transitions. [2021-11-07 07:29:52,864 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2950 transitions. [2021-11-07 07:29:52,864 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-07 07:29:52,864 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2950 transitions. [2021-11-07 07:29:52,876 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:52,877 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:29:52,877 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:29:52,880 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:52,881 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:52,881 INFO L791 eck$LassoCheckResult]: Stem: 28738#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 28739#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 28475#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 28476#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 28417#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28418#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28661#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28697#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29511#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29512#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29622#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29623#L944-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 28481#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28482#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29659#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28994#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 28995#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 29565#L974-1 assume !(0 == ~M_E~0); 29298#L1286-1 assume !(0 == ~T1_E~0); 28388#L1291-1 assume !(0 == ~T2_E~0); 28389#L1296-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29083#L1301-1 assume !(0 == ~T4_E~0); 29084#L1306-1 assume !(0 == ~T5_E~0); 29574#L1311-1 assume !(0 == ~T6_E~0); 28348#L1316-1 assume !(0 == ~T7_E~0); 28349#L1321-1 assume !(0 == ~T8_E~0); 29103#L1326-1 assume !(0 == ~T9_E~0); 28165#L1331-1 assume !(0 == ~T10_E~0); 27871#L1336-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 27872#L1341-1 assume !(0 == ~T12_E~0); 27923#L1346-1 assume !(0 == ~T13_E~0); 27924#L1351-1 assume !(0 == ~E_M~0); 28295#L1356-1 assume !(0 == ~E_1~0); 28296#L1361-1 assume !(0 == ~E_2~0); 29788#L1366-1 assume !(0 == ~E_3~0); 28341#L1371-1 assume !(0 == ~E_4~0); 28342#L1376-1 assume 0 == ~E_5~0;~E_5~0 := 1; 29143#L1381-1 assume !(0 == ~E_6~0); 29144#L1386-1 assume !(0 == ~E_7~0); 29815#L1391-1 assume !(0 == ~E_8~0); 29828#L1396-1 assume !(0 == ~E_9~0); 29027#L1401-1 assume !(0 == ~E_10~0); 29028#L1406-1 assume !(0 == ~E_11~0); 29326#L1411-1 assume !(0 == ~E_12~0); 29327#L1416-1 assume 0 == ~E_13~0;~E_13~0 := 1; 28954#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28792#L635 assume 1 == ~m_pc~0; 28793#L636 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 27942#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28290#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 28918#L1598 assume !(0 != activate_threads_~tmp~1); 28120#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28121#L654 assume !(1 == ~t1_pc~0); 28818#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 28817#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 29812#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 28898#L1606 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 28899#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28168#L673 assume 1 == ~t2_pc~0; 28169#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 29296#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29297#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 29839#L1614 assume !(0 != activate_threads_~tmp___1~0); 29846#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 28977#L692 assume !(1 == ~t3_pc~0); 28794#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 28795#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28662#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 28632#L1622 assume !(0 != activate_threads_~tmp___2~0); 28633#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 28193#L711 assume 1 == ~t4_pc~0; 28194#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 28675#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 29120#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 27896#L1630 assume !(0 != activate_threads_~tmp___3~0); 27897#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 29835#L730 assume !(1 == ~t5_pc~0); 29230#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 28075#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 28076#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 28203#L1638 assume !(0 != activate_threads_~tmp___4~0); 28204#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 28546#L749 assume 1 == ~t6_pc~0; 28318#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 28080#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 28512#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 28513#L1646 assume !(0 != activate_threads_~tmp___5~0); 28730#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 27876#L768 assume 1 == ~t7_pc~0; 27877#L769 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 29167#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 28113#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 28114#L1654 assume !(0 != activate_threads_~tmp___6~0); 29184#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 28350#L787 assume !(1 == ~t8_pc~0); 28351#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 29525#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 29685#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 29686#L1662 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 27921#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 27922#L806 assume 1 == ~t9_pc~0; 29536#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 27956#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 27957#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 28205#L1670 assume !(0 != activate_threads_~tmp___8~0); 28206#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 29519#L825 assume !(1 == ~t10_pc~0); 29520#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 29134#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 29135#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 28291#L1678 assume !(0 != activate_threads_~tmp___9~0); 28292#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 28867#L844 assume 1 == ~t11_pc~0; 28567#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 28568#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 28924#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 28925#L1686 assume !(0 != activate_threads_~tmp___10~0); 29508#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 29509#L863 assume !(1 == ~t12_pc~0); 28055#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 28056#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 28281#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 29598#L1694 assume !(0 != activate_threads_~tmp___11~0); 29599#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 28991#L882 assume 1 == ~t13_pc~0; 28992#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 29269#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 29759#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 29567#L1702 assume !(0 != activate_threads_~tmp___12~0); 29256#L1702-2 assume !(1 == ~M_E~0); 29257#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29705#L1439-1 assume !(1 == ~T2_E~0); 28186#L1444-1 assume !(1 == ~T3_E~0); 28187#L1449-1 assume !(1 == ~T4_E~0); 28629#L1454-1 assume !(1 == ~T5_E~0); 28630#L1459-1 assume !(1 == ~T6_E~0); 29185#L1464-1 assume !(1 == ~T7_E~0); 29186#L1469-1 assume !(1 == ~T8_E~0); 29270#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28955#L1479-1 assume !(1 == ~T10_E~0); 28956#L1484-1 assume !(1 == ~T11_E~0); 29192#L1489-1 assume !(1 == ~T12_E~0); 28833#L1494-1 assume !(1 == ~T13_E~0); 28834#L1499-1 assume !(1 == ~E_M~0); 29012#L1504-1 assume !(1 == ~E_1~0); 29013#L1509-1 assume !(1 == ~E_2~0); 29614#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 29308#L1519-1 assume !(1 == ~E_4~0); 29309#L1524-1 assume !(1 == ~E_5~0); 29799#L1529-1 assume !(1 == ~E_6~0); 29800#L1534-1 assume !(1 == ~E_7~0); 27976#L1539-1 assume !(1 == ~E_8~0); 27977#L1544-1 assume !(1 == ~E_9~0); 28405#L1549-1 assume !(1 == ~E_10~0); 29778#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 29776#L1559-1 assume !(1 == ~E_12~0); 29643#L1564-1 assume !(1 == ~E_13~0); 28585#L1935-1 [2021-11-07 07:29:52,882 INFO L793 eck$LassoCheckResult]: Loop: 28585#L1935-1 assume !false; 27985#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 27986#L1261 assume !false; 29196#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 29197#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 28116#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 28284#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 28285#L1074 assume !(0 != eval_~tmp~0); 28644#L1276 start_simulation_~kernel_st~0 := 2; 29225#L902-1 start_simulation_~kernel_st~0 := 3; 29618#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 28693#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28694#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29399#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29825#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29784#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28911#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28220#L1316-3 assume !(0 == ~T7_E~0); 28221#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28324#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29049#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29311#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29312#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 28622#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 28614#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28557#L1356-3 assume !(0 == ~E_1~0); 28558#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29124#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27911#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27912#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29629#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29481#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29482#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29660#L1396-3 assume !(0 == ~E_9~0); 29661#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28289#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28122#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 28123#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 28745#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28000#L635-45 assume !(1 == ~m_pc~0); 28001#L635-47 is_master_triggered_~__retres1~0 := 0; 28785#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 29258#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 29507#L1598-45 assume !(0 != activate_threads_~tmp~1); 28307#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28308#L654-45 assume 1 == ~t1_pc~0; 29116#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 29456#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27963#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 27964#L1606-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 27989#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28806#L673-45 assume !(1 == ~t2_pc~0); 28807#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 29127#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29128#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 29740#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 29564#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 28434#L692-45 assume !(1 == ~t3_pc~0); 28160#L692-47 is_transmit3_triggered_~__retres1~3 := 0; 28161#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 29188#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 28488#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 28489#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 28791#L711-45 assume 1 == ~t4_pc~0; 28915#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 28917#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 28770#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 28771#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 29168#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 28331#L730-45 assume 1 == ~t5_pc~0; 28171#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 28172#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 28581#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 28582#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 29317#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 28144#L749-45 assume !(1 == ~t6_pc~0); 28145#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 29522#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 29291#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 29292#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 29439#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 28460#L768-45 assume 1 == ~t7_pc~0; 28461#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 28601#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 29386#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 29387#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 29424#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 29425#L787-45 assume 1 == ~t8_pc~0; 29589#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 28607#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 28608#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 29010#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 29011#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 29316#L806-45 assume !(1 == ~t9_pc~0); 28019#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 28020#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 28835#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 28671#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 28586#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 28587#L825-45 assume !(1 == ~t10_pc~0); 29096#L825-47 is_transmit10_triggered_~__retres1~10 := 0; 29097#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 29198#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 29199#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 29349#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 28228#L844-45 assume !(1 == ~t11_pc~0); 28229#L844-47 is_transmit11_triggered_~__retres1~11 := 0; 28746#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 28747#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 28760#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 29165#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 28268#L863-45 assume 1 == ~t12_pc~0; 28269#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 27869#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 27870#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 28383#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 28384#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 29171#L882-45 assume !(1 == ~t13_pc~0); 28711#L882-47 is_transmit13_triggered_~__retres1~13 := 0; 27888#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 27889#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 28497#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 29651#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 29275#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29276#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28182#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28183#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28343#L1454-3 assume !(1 == ~T5_E~0); 29265#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29266#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 29702#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29631#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29632#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29704#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28913#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28914#L1494-3 assume !(1 == ~T13_E~0); 29561#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29202#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29203#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29640#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29678#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28836#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28837#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29724#L1534-3 assume !(1 == ~E_7~0); 29133#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28602#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28603#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29104#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 28233#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 28234#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 29364#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 29365#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 28118#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 28681#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 29337#L1954 assume !(0 == start_simulation_~tmp~3); 29303#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 29304#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 28399#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 29422#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 29549#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 29550#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 29638#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 29698#L1967 assume !(0 != start_simulation_~tmp___0~1); 28585#L1935-1 [2021-11-07 07:29:52,882 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:52,883 INFO L85 PathProgramCache]: Analyzing trace with hash -988862365, now seen corresponding path program 1 times [2021-11-07 07:29:52,883 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:52,883 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1572133900] [2021-11-07 07:29:52,883 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:52,884 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:52,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:52,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:52,929 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:52,929 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1572133900] [2021-11-07 07:29:52,929 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1572133900] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:52,929 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:52,930 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:52,930 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2064717569] [2021-11-07 07:29:52,930 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:29:52,931 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:52,931 INFO L85 PathProgramCache]: Analyzing trace with hash -1038037640, now seen corresponding path program 2 times [2021-11-07 07:29:52,931 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:52,932 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [584608848] [2021-11-07 07:29:52,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:52,932 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:52,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:52,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:52,987 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:52,987 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [584608848] [2021-11-07 07:29:52,987 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [584608848] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:52,988 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:52,988 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:52,988 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1050565715] [2021-11-07 07:29:52,988 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:29:52,989 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:29:52,989 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:29:52,989 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:29:52,990 INFO L87 Difference]: Start difference. First operand 1986 states and 2950 transitions. cyclomatic complexity: 965 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:53,044 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:29:53,044 INFO L93 Difference]: Finished difference Result 1986 states and 2949 transitions. [2021-11-07 07:29:53,044 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:29:53,045 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2949 transitions. [2021-11-07 07:29:53,063 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:53,083 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2949 transitions. [2021-11-07 07:29:53,083 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-07 07:29:53,086 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-07 07:29:53,086 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2949 transitions. [2021-11-07 07:29:53,090 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:29:53,091 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2949 transitions. [2021-11-07 07:29:53,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2949 transitions. [2021-11-07 07:29:53,132 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-07 07:29:53,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.4848942598187311) internal successors, (2949), 1985 states have internal predecessors, (2949), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:53,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2949 transitions. [2021-11-07 07:29:53,145 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2949 transitions. [2021-11-07 07:29:53,145 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2949 transitions. [2021-11-07 07:29:53,146 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-07 07:29:53,146 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2949 transitions. [2021-11-07 07:29:53,158 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:53,159 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:29:53,159 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:29:53,162 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:53,163 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:53,163 INFO L791 eck$LassoCheckResult]: Stem: 32717#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 32718#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 32454#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 32455#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 32396#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32397#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32640#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32676#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33490#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33491#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33601#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33602#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32460#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 32461#L954-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33638#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32973#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 32974#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 33544#L974-1 assume !(0 == ~M_E~0); 33277#L1286-1 assume !(0 == ~T1_E~0); 32367#L1291-1 assume !(0 == ~T2_E~0); 32368#L1296-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33062#L1301-1 assume !(0 == ~T4_E~0); 33063#L1306-1 assume !(0 == ~T5_E~0); 33553#L1311-1 assume !(0 == ~T6_E~0); 32327#L1316-1 assume !(0 == ~T7_E~0); 32328#L1321-1 assume !(0 == ~T8_E~0); 33082#L1326-1 assume !(0 == ~T9_E~0); 32144#L1331-1 assume !(0 == ~T10_E~0); 31850#L1336-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 31851#L1341-1 assume !(0 == ~T12_E~0); 31902#L1346-1 assume !(0 == ~T13_E~0); 31903#L1351-1 assume !(0 == ~E_M~0); 32274#L1356-1 assume !(0 == ~E_1~0); 32275#L1361-1 assume !(0 == ~E_2~0); 33767#L1366-1 assume !(0 == ~E_3~0); 32320#L1371-1 assume !(0 == ~E_4~0); 32321#L1376-1 assume 0 == ~E_5~0;~E_5~0 := 1; 33122#L1381-1 assume !(0 == ~E_6~0); 33123#L1386-1 assume !(0 == ~E_7~0); 33794#L1391-1 assume !(0 == ~E_8~0); 33807#L1396-1 assume !(0 == ~E_9~0); 33006#L1401-1 assume !(0 == ~E_10~0); 33007#L1406-1 assume !(0 == ~E_11~0); 33305#L1411-1 assume !(0 == ~E_12~0); 33306#L1416-1 assume 0 == ~E_13~0;~E_13~0 := 1; 32933#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 32771#L635 assume 1 == ~m_pc~0; 32772#L636 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 31921#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 32269#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 32897#L1598 assume !(0 != activate_threads_~tmp~1); 32099#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32100#L654 assume !(1 == ~t1_pc~0); 32797#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 32796#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 33791#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 32877#L1606 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 32878#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 32147#L673 assume 1 == ~t2_pc~0; 32148#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 33275#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 33276#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 33818#L1614 assume !(0 != activate_threads_~tmp___1~0); 33825#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 32956#L692 assume !(1 == ~t3_pc~0); 32773#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 32774#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 32641#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 32611#L1622 assume !(0 != activate_threads_~tmp___2~0); 32612#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32172#L711 assume 1 == ~t4_pc~0; 32173#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 32654#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 33099#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 31875#L1630 assume !(0 != activate_threads_~tmp___3~0); 31876#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 33814#L730 assume !(1 == ~t5_pc~0); 33209#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 32054#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 32055#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 32182#L1638 assume !(0 != activate_threads_~tmp___4~0); 32183#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 32525#L749 assume 1 == ~t6_pc~0; 32297#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 32059#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 32491#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 32492#L1646 assume !(0 != activate_threads_~tmp___5~0); 32709#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 31855#L768 assume 1 == ~t7_pc~0; 31856#L769 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 33146#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 32092#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 32093#L1654 assume !(0 != activate_threads_~tmp___6~0); 33163#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 32329#L787 assume !(1 == ~t8_pc~0); 32330#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 33504#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 33664#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 33665#L1662 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 31900#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 31901#L806 assume 1 == ~t9_pc~0; 33515#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 31935#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 31936#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 32184#L1670 assume !(0 != activate_threads_~tmp___8~0); 32185#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 33498#L825 assume !(1 == ~t10_pc~0); 33499#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 33113#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 33114#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 32270#L1678 assume !(0 != activate_threads_~tmp___9~0); 32271#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 32846#L844 assume 1 == ~t11_pc~0; 32546#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 32547#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 32903#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 32904#L1686 assume !(0 != activate_threads_~tmp___10~0); 33487#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 33488#L863 assume !(1 == ~t12_pc~0); 32034#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 32035#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 32260#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 33577#L1694 assume !(0 != activate_threads_~tmp___11~0); 33578#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 32970#L882 assume 1 == ~t13_pc~0; 32971#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 33248#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 33738#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 33546#L1702 assume !(0 != activate_threads_~tmp___12~0); 33235#L1702-2 assume !(1 == ~M_E~0); 33236#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33684#L1439-1 assume !(1 == ~T2_E~0); 32165#L1444-1 assume !(1 == ~T3_E~0); 32166#L1449-1 assume !(1 == ~T4_E~0); 32608#L1454-1 assume !(1 == ~T5_E~0); 32609#L1459-1 assume !(1 == ~T6_E~0); 33164#L1464-1 assume !(1 == ~T7_E~0); 33165#L1469-1 assume !(1 == ~T8_E~0); 33249#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32934#L1479-1 assume !(1 == ~T10_E~0); 32935#L1484-1 assume !(1 == ~T11_E~0); 33171#L1489-1 assume !(1 == ~T12_E~0); 32812#L1494-1 assume !(1 == ~T13_E~0); 32813#L1499-1 assume !(1 == ~E_M~0); 32991#L1504-1 assume !(1 == ~E_1~0); 32992#L1509-1 assume !(1 == ~E_2~0); 33593#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 33287#L1519-1 assume !(1 == ~E_4~0); 33288#L1524-1 assume !(1 == ~E_5~0); 33778#L1529-1 assume !(1 == ~E_6~0); 33779#L1534-1 assume !(1 == ~E_7~0); 31955#L1539-1 assume !(1 == ~E_8~0); 31956#L1544-1 assume !(1 == ~E_9~0); 32384#L1549-1 assume !(1 == ~E_10~0); 33757#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 33755#L1559-1 assume !(1 == ~E_12~0); 33622#L1564-1 assume !(1 == ~E_13~0); 32564#L1935-1 [2021-11-07 07:29:53,164 INFO L793 eck$LassoCheckResult]: Loop: 32564#L1935-1 assume !false; 31964#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 31965#L1261 assume !false; 33175#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 33176#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 32095#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 32263#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 32264#L1074 assume !(0 != eval_~tmp~0); 32623#L1276 start_simulation_~kernel_st~0 := 2; 33204#L902-1 start_simulation_~kernel_st~0 := 3; 33597#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 32672#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32673#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33378#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33804#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33763#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32890#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32199#L1316-3 assume !(0 == ~T7_E~0); 32200#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32303#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33028#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 33290#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 33291#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 32601#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 32593#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32536#L1356-3 assume !(0 == ~E_1~0); 32537#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33103#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31890#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 31891#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 33608#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33460#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33461#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33639#L1396-3 assume !(0 == ~E_9~0); 33640#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 32268#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32101#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 32102#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 32724#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 31979#L635-45 assume !(1 == ~m_pc~0); 31980#L635-47 is_master_triggered_~__retres1~0 := 0; 32764#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 33237#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 33486#L1598-45 assume !(0 != activate_threads_~tmp~1); 32286#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32287#L654-45 assume 1 == ~t1_pc~0; 33095#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 33435#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 31942#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 31943#L1606-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 31968#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 32785#L673-45 assume !(1 == ~t2_pc~0); 32786#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 33106#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 33107#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 33719#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 33543#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 32413#L692-45 assume !(1 == ~t3_pc~0); 32139#L692-47 is_transmit3_triggered_~__retres1~3 := 0; 32140#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 33167#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 32467#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 32468#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32770#L711-45 assume 1 == ~t4_pc~0; 32894#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 32896#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 32749#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 32750#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 33147#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 32310#L730-45 assume 1 == ~t5_pc~0; 32150#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 32151#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 32560#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 32561#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 33296#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 32123#L749-45 assume !(1 == ~t6_pc~0); 32124#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 33501#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 33270#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 33271#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 33418#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 32439#L768-45 assume 1 == ~t7_pc~0; 32440#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 32580#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 33365#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 33366#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 33403#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 33404#L787-45 assume 1 == ~t8_pc~0; 33568#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 32586#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 32587#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 32989#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 32990#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 33295#L806-45 assume !(1 == ~t9_pc~0); 31998#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 31999#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 32814#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 32650#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 32565#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 32566#L825-45 assume !(1 == ~t10_pc~0); 33075#L825-47 is_transmit10_triggered_~__retres1~10 := 0; 33076#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 33177#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 33178#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 33328#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 32207#L844-45 assume !(1 == ~t11_pc~0); 32208#L844-47 is_transmit11_triggered_~__retres1~11 := 0; 32725#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 32726#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 32739#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 33144#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 32247#L863-45 assume 1 == ~t12_pc~0; 32248#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 31848#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 31849#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 32362#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 32363#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 33150#L882-45 assume !(1 == ~t13_pc~0); 32690#L882-47 is_transmit13_triggered_~__retres1~13 := 0; 31867#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 31868#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 32476#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 33630#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 33254#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33255#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32161#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32162#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32322#L1454-3 assume !(1 == ~T5_E~0); 33244#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33245#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33681#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33610#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33611#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 33683#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32892#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32893#L1494-3 assume !(1 == ~T13_E~0); 33540#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33181#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33182#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33619#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33657#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32815#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32816#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 33703#L1534-3 assume !(1 == ~E_7~0); 33112#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32581#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32582#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 33083#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32212#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 32213#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 33343#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 33344#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 32097#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 32660#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 33316#L1954 assume !(0 == start_simulation_~tmp~3); 33282#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 33283#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 32378#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 33401#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 33528#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 33529#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 33617#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 33677#L1967 assume !(0 != start_simulation_~tmp___0~1); 32564#L1935-1 [2021-11-07 07:29:53,164 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:53,164 INFO L85 PathProgramCache]: Analyzing trace with hash 334316581, now seen corresponding path program 1 times [2021-11-07 07:29:53,165 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:53,165 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2040137660] [2021-11-07 07:29:53,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:53,165 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:53,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:53,204 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:53,204 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:53,205 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2040137660] [2021-11-07 07:29:53,205 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2040137660] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:53,205 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:53,205 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:53,205 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [330514731] [2021-11-07 07:29:53,206 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:29:53,206 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:53,207 INFO L85 PathProgramCache]: Analyzing trace with hash -1038037640, now seen corresponding path program 3 times [2021-11-07 07:29:53,207 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:53,207 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082909412] [2021-11-07 07:29:53,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:53,207 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:53,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:53,262 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:53,262 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:53,262 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2082909412] [2021-11-07 07:29:53,262 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2082909412] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:53,263 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:53,263 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:53,263 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [24064370] [2021-11-07 07:29:53,264 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:29:53,264 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:29:53,264 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:29:53,264 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:29:53,265 INFO L87 Difference]: Start difference. First operand 1986 states and 2949 transitions. cyclomatic complexity: 964 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:53,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:29:53,308 INFO L93 Difference]: Finished difference Result 1986 states and 2948 transitions. [2021-11-07 07:29:53,308 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:29:53,308 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2948 transitions. [2021-11-07 07:29:53,325 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:53,345 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2948 transitions. [2021-11-07 07:29:53,345 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-07 07:29:53,348 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-07 07:29:53,348 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2948 transitions. [2021-11-07 07:29:53,353 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:29:53,353 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2948 transitions. [2021-11-07 07:29:53,358 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2948 transitions. [2021-11-07 07:29:53,437 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-07 07:29:53,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.4843907351460222) internal successors, (2948), 1985 states have internal predecessors, (2948), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:53,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2948 transitions. [2021-11-07 07:29:53,455 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2948 transitions. [2021-11-07 07:29:53,455 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2948 transitions. [2021-11-07 07:29:53,456 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-07 07:29:53,456 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2948 transitions. [2021-11-07 07:29:53,468 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:53,468 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:29:53,468 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:29:53,472 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:53,472 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:53,473 INFO L791 eck$LassoCheckResult]: Stem: 36696#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 36697#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 36433#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 36434#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 36375#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36376#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36619#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36655#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37469#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37470#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37580#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37581#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36439#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36440#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 37617#L959-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 36952#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 36953#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 37523#L974-1 assume !(0 == ~M_E~0); 37256#L1286-1 assume !(0 == ~T1_E~0); 36346#L1291-1 assume !(0 == ~T2_E~0); 36347#L1296-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37041#L1301-1 assume !(0 == ~T4_E~0); 37042#L1306-1 assume !(0 == ~T5_E~0); 37532#L1311-1 assume !(0 == ~T6_E~0); 36306#L1316-1 assume !(0 == ~T7_E~0); 36307#L1321-1 assume !(0 == ~T8_E~0); 37061#L1326-1 assume !(0 == ~T9_E~0); 36123#L1331-1 assume !(0 == ~T10_E~0); 35829#L1336-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 35830#L1341-1 assume !(0 == ~T12_E~0); 35881#L1346-1 assume !(0 == ~T13_E~0); 35882#L1351-1 assume !(0 == ~E_M~0); 36253#L1356-1 assume !(0 == ~E_1~0); 36254#L1361-1 assume !(0 == ~E_2~0); 37746#L1366-1 assume !(0 == ~E_3~0); 36299#L1371-1 assume !(0 == ~E_4~0); 36300#L1376-1 assume 0 == ~E_5~0;~E_5~0 := 1; 37101#L1381-1 assume !(0 == ~E_6~0); 37102#L1386-1 assume !(0 == ~E_7~0); 37773#L1391-1 assume !(0 == ~E_8~0); 37786#L1396-1 assume !(0 == ~E_9~0); 36985#L1401-1 assume !(0 == ~E_10~0); 36986#L1406-1 assume !(0 == ~E_11~0); 37284#L1411-1 assume !(0 == ~E_12~0); 37285#L1416-1 assume 0 == ~E_13~0;~E_13~0 := 1; 36912#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 36750#L635 assume 1 == ~m_pc~0; 36751#L636 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 35900#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 36248#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 36876#L1598 assume !(0 != activate_threads_~tmp~1); 36078#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 36079#L654 assume !(1 == ~t1_pc~0); 36776#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 36775#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 37770#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 36856#L1606 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 36857#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36126#L673 assume 1 == ~t2_pc~0; 36127#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 37254#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 37255#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 37797#L1614 assume !(0 != activate_threads_~tmp___1~0); 37804#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 36935#L692 assume !(1 == ~t3_pc~0); 36752#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 36753#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 36620#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 36590#L1622 assume !(0 != activate_threads_~tmp___2~0); 36591#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 36151#L711 assume 1 == ~t4_pc~0; 36152#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 36633#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 37078#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 35854#L1630 assume !(0 != activate_threads_~tmp___3~0); 35855#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 37793#L730 assume !(1 == ~t5_pc~0); 37188#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 36033#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 36034#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 36161#L1638 assume !(0 != activate_threads_~tmp___4~0); 36162#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 36504#L749 assume 1 == ~t6_pc~0; 36276#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 36038#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 36470#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 36471#L1646 assume !(0 != activate_threads_~tmp___5~0); 36688#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 35834#L768 assume 1 == ~t7_pc~0; 35835#L769 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 37125#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 36071#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 36072#L1654 assume !(0 != activate_threads_~tmp___6~0); 37142#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 36308#L787 assume !(1 == ~t8_pc~0); 36309#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 37483#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 37643#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 37644#L1662 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 35879#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 35880#L806 assume 1 == ~t9_pc~0; 37494#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 35914#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 35915#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 36163#L1670 assume !(0 != activate_threads_~tmp___8~0); 36164#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 37477#L825 assume !(1 == ~t10_pc~0); 37478#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 37092#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 37093#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 36249#L1678 assume !(0 != activate_threads_~tmp___9~0); 36250#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 36825#L844 assume 1 == ~t11_pc~0; 36525#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 36526#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 36882#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 36883#L1686 assume !(0 != activate_threads_~tmp___10~0); 37466#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 37467#L863 assume !(1 == ~t12_pc~0); 36013#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 36014#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 36239#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 37556#L1694 assume !(0 != activate_threads_~tmp___11~0); 37557#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 36949#L882 assume 1 == ~t13_pc~0; 36950#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 37227#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 37717#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 37525#L1702 assume !(0 != activate_threads_~tmp___12~0); 37214#L1702-2 assume !(1 == ~M_E~0); 37215#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37663#L1439-1 assume !(1 == ~T2_E~0); 36144#L1444-1 assume !(1 == ~T3_E~0); 36145#L1449-1 assume !(1 == ~T4_E~0); 36587#L1454-1 assume !(1 == ~T5_E~0); 36588#L1459-1 assume !(1 == ~T6_E~0); 37143#L1464-1 assume !(1 == ~T7_E~0); 37144#L1469-1 assume !(1 == ~T8_E~0); 37228#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36913#L1479-1 assume !(1 == ~T10_E~0); 36914#L1484-1 assume !(1 == ~T11_E~0); 37150#L1489-1 assume !(1 == ~T12_E~0); 36791#L1494-1 assume !(1 == ~T13_E~0); 36792#L1499-1 assume !(1 == ~E_M~0); 36970#L1504-1 assume !(1 == ~E_1~0); 36971#L1509-1 assume !(1 == ~E_2~0); 37572#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 37266#L1519-1 assume !(1 == ~E_4~0); 37267#L1524-1 assume !(1 == ~E_5~0); 37757#L1529-1 assume !(1 == ~E_6~0); 37758#L1534-1 assume !(1 == ~E_7~0); 35934#L1539-1 assume !(1 == ~E_8~0); 35935#L1544-1 assume !(1 == ~E_9~0); 36363#L1549-1 assume !(1 == ~E_10~0); 37736#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 37734#L1559-1 assume !(1 == ~E_12~0); 37601#L1564-1 assume !(1 == ~E_13~0); 36543#L1935-1 [2021-11-07 07:29:53,474 INFO L793 eck$LassoCheckResult]: Loop: 36543#L1935-1 assume !false; 35943#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 35944#L1261 assume !false; 37154#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 37155#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 36074#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 36242#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 36243#L1074 assume !(0 != eval_~tmp~0); 36602#L1276 start_simulation_~kernel_st~0 := 2; 37183#L902-1 start_simulation_~kernel_st~0 := 3; 37576#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 36651#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36652#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37357#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37783#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37742#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36869#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36178#L1316-3 assume !(0 == ~T7_E~0); 36179#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36282#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 37007#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37269#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37270#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 36580#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 36572#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 36515#L1356-3 assume !(0 == ~E_1~0); 36516#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37082#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35869#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35870#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37587#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37439#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37440#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37618#L1396-3 assume !(0 == ~E_9~0); 37619#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36247#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36080#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 36081#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 36703#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35958#L635-45 assume !(1 == ~m_pc~0); 35959#L635-47 is_master_triggered_~__retres1~0 := 0; 36743#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 37216#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 37465#L1598-45 assume !(0 != activate_threads_~tmp~1); 36265#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 36266#L654-45 assume 1 == ~t1_pc~0; 37074#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 37414#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35921#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 35922#L1606-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 35947#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36764#L673-45 assume !(1 == ~t2_pc~0); 36765#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 37085#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 37086#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 37698#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 37522#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 36392#L692-45 assume !(1 == ~t3_pc~0); 36118#L692-47 is_transmit3_triggered_~__retres1~3 := 0; 36119#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 37146#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 36446#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 36447#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 36749#L711-45 assume 1 == ~t4_pc~0; 36873#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 36875#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 36728#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 36729#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 37126#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36289#L730-45 assume 1 == ~t5_pc~0; 36129#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 36130#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 36539#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 36540#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 37275#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 36102#L749-45 assume !(1 == ~t6_pc~0); 36103#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 37480#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 37249#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 37250#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 37397#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 36418#L768-45 assume 1 == ~t7_pc~0; 36419#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 36559#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 37344#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 37345#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 37382#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 37383#L787-45 assume 1 == ~t8_pc~0; 37547#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 36565#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 36566#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 36968#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 36969#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 37274#L806-45 assume !(1 == ~t9_pc~0); 35977#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 35978#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 36793#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 36629#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 36544#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 36545#L825-45 assume 1 == ~t10_pc~0; 37140#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 37055#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 37156#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 37157#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 37307#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 36186#L844-45 assume !(1 == ~t11_pc~0); 36187#L844-47 is_transmit11_triggered_~__retres1~11 := 0; 36704#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 36705#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 36718#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 37123#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 36226#L863-45 assume 1 == ~t12_pc~0; 36227#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 35827#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 35828#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 36341#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 36342#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 37129#L882-45 assume 1 == ~t13_pc~0; 37474#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 35846#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 35847#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 36455#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 37609#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 37233#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37234#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36140#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36141#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36301#L1454-3 assume !(1 == ~T5_E~0); 37223#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 37224#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 37660#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 37589#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37590#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 37662#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 36871#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 36872#L1494-3 assume !(1 == ~T13_E~0); 37519#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37160#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37161#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 37598#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 37636#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36794#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36795#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37682#L1534-3 assume !(1 == ~E_7~0); 37091#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 36560#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 36561#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 37062#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 36191#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 36192#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 37322#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 37323#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 36076#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 36639#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 37295#L1954 assume !(0 == start_simulation_~tmp~3); 37261#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 37262#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 36357#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 37380#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 37507#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 37508#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 37596#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 37656#L1967 assume !(0 != start_simulation_~tmp___0~1); 36543#L1935-1 [2021-11-07 07:29:53,474 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:53,474 INFO L85 PathProgramCache]: Analyzing trace with hash -3970969, now seen corresponding path program 1 times [2021-11-07 07:29:53,475 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:53,475 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [579287724] [2021-11-07 07:29:53,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:53,475 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:53,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:53,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:53,518 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:53,518 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [579287724] [2021-11-07 07:29:53,518 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [579287724] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:53,518 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:53,519 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:53,519 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [872415698] [2021-11-07 07:29:53,519 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:29:53,520 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:53,520 INFO L85 PathProgramCache]: Analyzing trace with hash -434951558, now seen corresponding path program 2 times [2021-11-07 07:29:53,520 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:53,521 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [987707111] [2021-11-07 07:29:53,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:53,521 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:53,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:53,577 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:53,577 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:53,577 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [987707111] [2021-11-07 07:29:53,577 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [987707111] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:53,578 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:53,578 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:53,578 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2137651867] [2021-11-07 07:29:53,579 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:29:53,579 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:29:53,579 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:29:53,579 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:29:53,580 INFO L87 Difference]: Start difference. First operand 1986 states and 2948 transitions. cyclomatic complexity: 963 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:53,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:29:53,624 INFO L93 Difference]: Finished difference Result 1986 states and 2947 transitions. [2021-11-07 07:29:53,625 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:29:53,625 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2947 transitions. [2021-11-07 07:29:53,640 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:53,661 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2947 transitions. [2021-11-07 07:29:53,661 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-07 07:29:53,664 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-07 07:29:53,664 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2947 transitions. [2021-11-07 07:29:53,669 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:29:53,669 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2947 transitions. [2021-11-07 07:29:53,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2947 transitions. [2021-11-07 07:29:53,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-07 07:29:53,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.4838872104733132) internal successors, (2947), 1985 states have internal predecessors, (2947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:53,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2947 transitions. [2021-11-07 07:29:53,724 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2947 transitions. [2021-11-07 07:29:53,724 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2947 transitions. [2021-11-07 07:29:53,724 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-07 07:29:53,724 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2947 transitions. [2021-11-07 07:29:53,735 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:53,735 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:29:53,735 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:29:53,739 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:53,739 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:53,740 INFO L791 eck$LassoCheckResult]: Stem: 40675#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 40676#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 40412#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 40413#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 40354#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40355#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40598#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40634#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41448#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41449#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41559#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41560#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 40418#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 40419#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41596#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 40931#L964-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 40932#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 41502#L974-1 assume !(0 == ~M_E~0); 41235#L1286-1 assume !(0 == ~T1_E~0); 40325#L1291-1 assume !(0 == ~T2_E~0); 40326#L1296-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41020#L1301-1 assume !(0 == ~T4_E~0); 41021#L1306-1 assume !(0 == ~T5_E~0); 41511#L1311-1 assume !(0 == ~T6_E~0); 40285#L1316-1 assume !(0 == ~T7_E~0); 40286#L1321-1 assume !(0 == ~T8_E~0); 41040#L1326-1 assume !(0 == ~T9_E~0); 40102#L1331-1 assume !(0 == ~T10_E~0); 39808#L1336-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 39809#L1341-1 assume !(0 == ~T12_E~0); 39860#L1346-1 assume !(0 == ~T13_E~0); 39861#L1351-1 assume !(0 == ~E_M~0); 40232#L1356-1 assume !(0 == ~E_1~0); 40233#L1361-1 assume !(0 == ~E_2~0); 41725#L1366-1 assume !(0 == ~E_3~0); 40278#L1371-1 assume !(0 == ~E_4~0); 40279#L1376-1 assume 0 == ~E_5~0;~E_5~0 := 1; 41080#L1381-1 assume !(0 == ~E_6~0); 41081#L1386-1 assume !(0 == ~E_7~0); 41752#L1391-1 assume !(0 == ~E_8~0); 41765#L1396-1 assume !(0 == ~E_9~0); 40964#L1401-1 assume !(0 == ~E_10~0); 40965#L1406-1 assume !(0 == ~E_11~0); 41263#L1411-1 assume !(0 == ~E_12~0); 41264#L1416-1 assume 0 == ~E_13~0;~E_13~0 := 1; 40891#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 40729#L635 assume 1 == ~m_pc~0; 40730#L636 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 39879#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 40227#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 40855#L1598 assume !(0 != activate_threads_~tmp~1); 40057#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 40058#L654 assume !(1 == ~t1_pc~0); 40755#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 40754#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 41749#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 40835#L1606 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 40836#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 40105#L673 assume 1 == ~t2_pc~0; 40106#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 41233#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 41234#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 41776#L1614 assume !(0 != activate_threads_~tmp___1~0); 41783#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 40914#L692 assume !(1 == ~t3_pc~0); 40731#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 40732#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 40599#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 40569#L1622 assume !(0 != activate_threads_~tmp___2~0); 40570#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 40130#L711 assume 1 == ~t4_pc~0; 40131#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 40612#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 41057#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 39833#L1630 assume !(0 != activate_threads_~tmp___3~0); 39834#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 41772#L730 assume !(1 == ~t5_pc~0); 41167#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 40012#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 40013#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 40140#L1638 assume !(0 != activate_threads_~tmp___4~0); 40141#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 40483#L749 assume 1 == ~t6_pc~0; 40255#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 40017#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 40449#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 40450#L1646 assume !(0 != activate_threads_~tmp___5~0); 40667#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 39813#L768 assume 1 == ~t7_pc~0; 39814#L769 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 41104#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 40050#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 40051#L1654 assume !(0 != activate_threads_~tmp___6~0); 41121#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 40287#L787 assume !(1 == ~t8_pc~0); 40288#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 41462#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 41622#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 41623#L1662 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 39858#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 39859#L806 assume 1 == ~t9_pc~0; 41473#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 39893#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 39894#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 40142#L1670 assume !(0 != activate_threads_~tmp___8~0); 40143#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 41456#L825 assume !(1 == ~t10_pc~0); 41457#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 41071#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 41072#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 40228#L1678 assume !(0 != activate_threads_~tmp___9~0); 40229#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 40804#L844 assume 1 == ~t11_pc~0; 40504#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 40505#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 40861#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 40862#L1686 assume !(0 != activate_threads_~tmp___10~0); 41445#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 41446#L863 assume !(1 == ~t12_pc~0); 39992#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 39993#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 40218#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 41535#L1694 assume !(0 != activate_threads_~tmp___11~0); 41536#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 40928#L882 assume 1 == ~t13_pc~0; 40929#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 41206#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 41696#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 41504#L1702 assume !(0 != activate_threads_~tmp___12~0); 41193#L1702-2 assume !(1 == ~M_E~0); 41194#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41642#L1439-1 assume !(1 == ~T2_E~0); 40123#L1444-1 assume !(1 == ~T3_E~0); 40124#L1449-1 assume !(1 == ~T4_E~0); 40566#L1454-1 assume !(1 == ~T5_E~0); 40567#L1459-1 assume !(1 == ~T6_E~0); 41122#L1464-1 assume !(1 == ~T7_E~0); 41123#L1469-1 assume !(1 == ~T8_E~0); 41207#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 40892#L1479-1 assume !(1 == ~T10_E~0); 40893#L1484-1 assume !(1 == ~T11_E~0); 41129#L1489-1 assume !(1 == ~T12_E~0); 40770#L1494-1 assume !(1 == ~T13_E~0); 40771#L1499-1 assume !(1 == ~E_M~0); 40949#L1504-1 assume !(1 == ~E_1~0); 40950#L1509-1 assume !(1 == ~E_2~0); 41551#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 41245#L1519-1 assume !(1 == ~E_4~0); 41246#L1524-1 assume !(1 == ~E_5~0); 41736#L1529-1 assume !(1 == ~E_6~0); 41737#L1534-1 assume !(1 == ~E_7~0); 39913#L1539-1 assume !(1 == ~E_8~0); 39914#L1544-1 assume !(1 == ~E_9~0); 40342#L1549-1 assume !(1 == ~E_10~0); 41715#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 41713#L1559-1 assume !(1 == ~E_12~0); 41580#L1564-1 assume !(1 == ~E_13~0); 40522#L1935-1 [2021-11-07 07:29:53,740 INFO L793 eck$LassoCheckResult]: Loop: 40522#L1935-1 assume !false; 39922#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 39923#L1261 assume !false; 41133#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 41134#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 40053#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 40221#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 40222#L1074 assume !(0 != eval_~tmp~0); 40581#L1276 start_simulation_~kernel_st~0 := 2; 41162#L902-1 start_simulation_~kernel_st~0 := 3; 41555#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 40630#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40631#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 41336#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41762#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41721#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 40848#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 40157#L1316-3 assume !(0 == ~T7_E~0); 40158#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 40261#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 40986#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 41248#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41249#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 40559#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 40551#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 40494#L1356-3 assume !(0 == ~E_1~0); 40495#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41061#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 39848#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 39849#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 41566#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41418#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 41419#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41597#L1396-3 assume !(0 == ~E_9~0); 41598#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 40226#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 40059#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 40060#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 40682#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 39937#L635-45 assume !(1 == ~m_pc~0); 39938#L635-47 is_master_triggered_~__retres1~0 := 0; 40722#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 41195#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 41444#L1598-45 assume !(0 != activate_threads_~tmp~1); 40244#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 40245#L654-45 assume 1 == ~t1_pc~0; 41053#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 41393#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 39900#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 39901#L1606-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 39926#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 40743#L673-45 assume !(1 == ~t2_pc~0); 40744#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 41064#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 41065#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 41677#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 41501#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 40371#L692-45 assume !(1 == ~t3_pc~0); 40097#L692-47 is_transmit3_triggered_~__retres1~3 := 0; 40098#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 41125#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 40425#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 40426#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 40728#L711-45 assume 1 == ~t4_pc~0; 40852#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 40854#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 40707#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 40708#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 41105#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 40268#L730-45 assume 1 == ~t5_pc~0; 40108#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 40109#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 40518#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 40519#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 41254#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 40081#L749-45 assume !(1 == ~t6_pc~0); 40082#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 41459#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 41228#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 41229#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 41376#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 40397#L768-45 assume 1 == ~t7_pc~0; 40398#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 40538#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 41323#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 41324#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 41361#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 41362#L787-45 assume 1 == ~t8_pc~0; 41526#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 40544#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 40545#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 40947#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 40948#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 41253#L806-45 assume !(1 == ~t9_pc~0); 39956#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 39957#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 40772#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 40608#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 40523#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 40524#L825-45 assume !(1 == ~t10_pc~0); 41033#L825-47 is_transmit10_triggered_~__retres1~10 := 0; 41034#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 41135#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 41136#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 41286#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 40165#L844-45 assume !(1 == ~t11_pc~0); 40166#L844-47 is_transmit11_triggered_~__retres1~11 := 0; 40683#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 40684#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 40697#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 41102#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 40205#L863-45 assume 1 == ~t12_pc~0; 40206#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 39806#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 39807#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 40320#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 40321#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 41108#L882-45 assume !(1 == ~t13_pc~0); 40648#L882-47 is_transmit13_triggered_~__retres1~13 := 0; 39825#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 39826#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 40434#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 41588#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 41212#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41213#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40119#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40120#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40280#L1454-3 assume !(1 == ~T5_E~0); 41202#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41203#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41639#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41568#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41569#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 41641#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40850#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 40851#L1494-3 assume !(1 == ~T13_E~0); 41498#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41139#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41140#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41577#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 41615#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40773#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40774#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 41661#L1534-3 assume !(1 == ~E_7~0); 41070#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 40539#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40540#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 41041#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 40170#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 40171#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 41301#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 41302#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 40055#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 40618#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 41274#L1954 assume !(0 == start_simulation_~tmp~3); 41240#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 41241#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 40336#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 41359#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 41486#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 41487#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 41575#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 41635#L1967 assume !(0 != start_simulation_~tmp___0~1); 40522#L1935-1 [2021-11-07 07:29:53,741 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:53,741 INFO L85 PathProgramCache]: Analyzing trace with hash -430525467, now seen corresponding path program 1 times [2021-11-07 07:29:53,741 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:53,742 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [395414531] [2021-11-07 07:29:53,742 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:53,742 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:53,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:53,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:53,794 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:53,794 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [395414531] [2021-11-07 07:29:53,794 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [395414531] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:53,794 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:53,794 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:53,795 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [291920805] [2021-11-07 07:29:53,795 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:29:53,796 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:53,796 INFO L85 PathProgramCache]: Analyzing trace with hash -1038037640, now seen corresponding path program 4 times [2021-11-07 07:29:53,796 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:53,796 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1078982726] [2021-11-07 07:29:53,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:53,797 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:53,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:53,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:53,855 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:53,856 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1078982726] [2021-11-07 07:29:53,856 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1078982726] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:53,856 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:53,856 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:53,856 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [3486393] [2021-11-07 07:29:53,857 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:29:53,857 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:29:53,858 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:29:53,858 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:29:53,859 INFO L87 Difference]: Start difference. First operand 1986 states and 2947 transitions. cyclomatic complexity: 962 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:53,896 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:29:53,896 INFO L93 Difference]: Finished difference Result 1986 states and 2946 transitions. [2021-11-07 07:29:53,897 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:29:53,897 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2946 transitions. [2021-11-07 07:29:53,912 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:53,926 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2946 transitions. [2021-11-07 07:29:53,926 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-07 07:29:53,929 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-07 07:29:53,929 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2946 transitions. [2021-11-07 07:29:53,934 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:29:53,934 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2946 transitions. [2021-11-07 07:29:53,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2946 transitions. [2021-11-07 07:29:53,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-07 07:29:53,979 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.4833836858006042) internal successors, (2946), 1985 states have internal predecessors, (2946), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:53,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2946 transitions. [2021-11-07 07:29:53,987 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2946 transitions. [2021-11-07 07:29:53,987 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2946 transitions. [2021-11-07 07:29:53,987 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-07 07:29:53,987 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2946 transitions. [2021-11-07 07:29:53,998 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:53,998 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:29:53,999 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:29:54,002 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:54,002 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:54,003 INFO L791 eck$LassoCheckResult]: Stem: 44654#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 44655#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 44391#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 44392#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 44333#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44334#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 44577#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 44613#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45427#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 45428#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 45538#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45539#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44397#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44398#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 45575#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 44910#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 44911#L969-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 45481#L974-1 assume !(0 == ~M_E~0); 45214#L1286-1 assume !(0 == ~T1_E~0); 44304#L1291-1 assume !(0 == ~T2_E~0); 44305#L1296-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44999#L1301-1 assume !(0 == ~T4_E~0); 45000#L1306-1 assume !(0 == ~T5_E~0); 45490#L1311-1 assume !(0 == ~T6_E~0); 44264#L1316-1 assume !(0 == ~T7_E~0); 44265#L1321-1 assume !(0 == ~T8_E~0); 45019#L1326-1 assume !(0 == ~T9_E~0); 44081#L1331-1 assume !(0 == ~T10_E~0); 43787#L1336-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43788#L1341-1 assume !(0 == ~T12_E~0); 43839#L1346-1 assume !(0 == ~T13_E~0); 43840#L1351-1 assume !(0 == ~E_M~0); 44211#L1356-1 assume !(0 == ~E_1~0); 44212#L1361-1 assume !(0 == ~E_2~0); 45704#L1366-1 assume !(0 == ~E_3~0); 44257#L1371-1 assume !(0 == ~E_4~0); 44258#L1376-1 assume 0 == ~E_5~0;~E_5~0 := 1; 45059#L1381-1 assume !(0 == ~E_6~0); 45060#L1386-1 assume !(0 == ~E_7~0); 45731#L1391-1 assume !(0 == ~E_8~0); 45744#L1396-1 assume !(0 == ~E_9~0); 44943#L1401-1 assume !(0 == ~E_10~0); 44944#L1406-1 assume !(0 == ~E_11~0); 45242#L1411-1 assume !(0 == ~E_12~0); 45243#L1416-1 assume 0 == ~E_13~0;~E_13~0 := 1; 44870#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 44708#L635 assume 1 == ~m_pc~0; 44709#L636 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 43858#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 44206#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 44834#L1598 assume !(0 != activate_threads_~tmp~1); 44036#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 44037#L654 assume !(1 == ~t1_pc~0); 44734#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 44733#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 45728#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 44814#L1606 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 44815#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 44084#L673 assume 1 == ~t2_pc~0; 44085#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 45212#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 45213#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 45755#L1614 assume !(0 != activate_threads_~tmp___1~0); 45762#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 44893#L692 assume !(1 == ~t3_pc~0); 44710#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 44711#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 44578#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 44548#L1622 assume !(0 != activate_threads_~tmp___2~0); 44549#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 44109#L711 assume 1 == ~t4_pc~0; 44110#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 44591#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 45036#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 43812#L1630 assume !(0 != activate_threads_~tmp___3~0); 43813#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 45751#L730 assume !(1 == ~t5_pc~0); 45146#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 43991#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 43992#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 44119#L1638 assume !(0 != activate_threads_~tmp___4~0); 44120#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 44462#L749 assume 1 == ~t6_pc~0; 44234#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 43996#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 44428#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 44429#L1646 assume !(0 != activate_threads_~tmp___5~0); 44646#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 43792#L768 assume 1 == ~t7_pc~0; 43793#L769 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 45083#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 44029#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 44030#L1654 assume !(0 != activate_threads_~tmp___6~0); 45100#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 44266#L787 assume !(1 == ~t8_pc~0); 44267#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 45441#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 45601#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 45602#L1662 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 43837#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 43838#L806 assume 1 == ~t9_pc~0; 45452#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 43872#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 43873#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 44121#L1670 assume !(0 != activate_threads_~tmp___8~0); 44122#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 45435#L825 assume !(1 == ~t10_pc~0); 45436#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 45050#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 45051#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 44207#L1678 assume !(0 != activate_threads_~tmp___9~0); 44208#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 44783#L844 assume 1 == ~t11_pc~0; 44483#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 44484#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 44840#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 44841#L1686 assume !(0 != activate_threads_~tmp___10~0); 45424#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 45425#L863 assume !(1 == ~t12_pc~0); 43971#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 43972#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 44197#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 45514#L1694 assume !(0 != activate_threads_~tmp___11~0); 45515#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 44907#L882 assume 1 == ~t13_pc~0; 44908#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 45185#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 45675#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 45483#L1702 assume !(0 != activate_threads_~tmp___12~0); 45172#L1702-2 assume !(1 == ~M_E~0); 45173#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45621#L1439-1 assume !(1 == ~T2_E~0); 44102#L1444-1 assume !(1 == ~T3_E~0); 44103#L1449-1 assume !(1 == ~T4_E~0); 44545#L1454-1 assume !(1 == ~T5_E~0); 44546#L1459-1 assume !(1 == ~T6_E~0); 45101#L1464-1 assume !(1 == ~T7_E~0); 45102#L1469-1 assume !(1 == ~T8_E~0); 45186#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 44871#L1479-1 assume !(1 == ~T10_E~0); 44872#L1484-1 assume !(1 == ~T11_E~0); 45108#L1489-1 assume !(1 == ~T12_E~0); 44749#L1494-1 assume !(1 == ~T13_E~0); 44750#L1499-1 assume !(1 == ~E_M~0); 44928#L1504-1 assume !(1 == ~E_1~0); 44929#L1509-1 assume !(1 == ~E_2~0); 45530#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 45224#L1519-1 assume !(1 == ~E_4~0); 45225#L1524-1 assume !(1 == ~E_5~0); 45715#L1529-1 assume !(1 == ~E_6~0); 45716#L1534-1 assume !(1 == ~E_7~0); 43892#L1539-1 assume !(1 == ~E_8~0); 43893#L1544-1 assume !(1 == ~E_9~0); 44321#L1549-1 assume !(1 == ~E_10~0); 45694#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 45692#L1559-1 assume !(1 == ~E_12~0); 45559#L1564-1 assume !(1 == ~E_13~0); 44501#L1935-1 [2021-11-07 07:29:54,004 INFO L793 eck$LassoCheckResult]: Loop: 44501#L1935-1 assume !false; 43901#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 43902#L1261 assume !false; 45112#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 45113#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 44032#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 44200#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 44201#L1074 assume !(0 != eval_~tmp~0); 44560#L1276 start_simulation_~kernel_st~0 := 2; 45141#L902-1 start_simulation_~kernel_st~0 := 3; 45534#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 44609#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44610#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45315#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45741#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45700#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44827#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44136#L1316-3 assume !(0 == ~T7_E~0); 44137#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44240#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44965#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 45227#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 45228#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 44538#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 44530#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 44473#L1356-3 assume !(0 == ~E_1~0); 44474#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 45040#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43827#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43828#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 45545#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 45397#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 45398#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45576#L1396-3 assume !(0 == ~E_9~0); 45577#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 44205#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44038#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 44039#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 44661#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 43916#L635-45 assume !(1 == ~m_pc~0); 43917#L635-47 is_master_triggered_~__retres1~0 := 0; 44701#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 45174#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 45423#L1598-45 assume !(0 != activate_threads_~tmp~1); 44223#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 44224#L654-45 assume 1 == ~t1_pc~0; 45032#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 45372#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 43879#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 43880#L1606-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 43905#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 44722#L673-45 assume !(1 == ~t2_pc~0); 44723#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 45043#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 45044#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 45656#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 45480#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 44350#L692-45 assume !(1 == ~t3_pc~0); 44076#L692-47 is_transmit3_triggered_~__retres1~3 := 0; 44077#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 45104#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 44404#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 44405#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 44707#L711-45 assume !(1 == ~t4_pc~0); 44832#L711-47 is_transmit4_triggered_~__retres1~4 := 0; 44833#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 44686#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 44687#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 45084#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 44247#L730-45 assume 1 == ~t5_pc~0; 44087#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 44088#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 44497#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 44498#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 45233#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 44060#L749-45 assume !(1 == ~t6_pc~0); 44061#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 45438#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 45207#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 45208#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 45355#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 44376#L768-45 assume 1 == ~t7_pc~0; 44377#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 44517#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 45302#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 45303#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 45340#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 45341#L787-45 assume 1 == ~t8_pc~0; 45505#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 44523#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 44524#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 44926#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 44927#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 45232#L806-45 assume !(1 == ~t9_pc~0); 43935#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 43936#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 44751#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 44587#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 44502#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 44503#L825-45 assume !(1 == ~t10_pc~0); 45012#L825-47 is_transmit10_triggered_~__retres1~10 := 0; 45013#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 45114#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 45115#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 45265#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 44144#L844-45 assume !(1 == ~t11_pc~0); 44145#L844-47 is_transmit11_triggered_~__retres1~11 := 0; 44662#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 44663#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 44676#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 45081#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 44184#L863-45 assume 1 == ~t12_pc~0; 44185#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 43785#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 43786#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 44299#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 44300#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 45087#L882-45 assume !(1 == ~t13_pc~0); 44627#L882-47 is_transmit13_triggered_~__retres1~13 := 0; 43804#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 43805#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 44413#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 45567#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 45191#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45192#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44098#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44099#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 44259#L1454-3 assume !(1 == ~T5_E~0); 45181#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 45182#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 45618#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 45547#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45548#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 45620#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 44829#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 44830#L1494-3 assume !(1 == ~T13_E~0); 45477#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45118#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45119#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 45556#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 45594#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44752#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44753#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 45640#L1534-3 assume !(1 == ~E_7~0); 45049#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 44518#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 44519#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 45020#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 44149#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 44150#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 45280#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 45281#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 44034#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 44597#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 45253#L1954 assume !(0 == start_simulation_~tmp~3); 45219#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 45220#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 44315#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 45338#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 45465#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 45466#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 45554#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 45614#L1967 assume !(0 != start_simulation_~tmp___0~1); 44501#L1935-1 [2021-11-07 07:29:54,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:54,005 INFO L85 PathProgramCache]: Analyzing trace with hash 109904039, now seen corresponding path program 1 times [2021-11-07 07:29:54,005 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:54,005 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1494044629] [2021-11-07 07:29:54,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:54,006 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:54,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:54,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:54,046 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:54,046 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1494044629] [2021-11-07 07:29:54,046 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1494044629] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:54,046 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:54,047 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:54,047 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [580577771] [2021-11-07 07:29:54,047 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:29:54,048 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:54,048 INFO L85 PathProgramCache]: Analyzing trace with hash -2041094505, now seen corresponding path program 1 times [2021-11-07 07:29:54,048 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:54,048 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [851643191] [2021-11-07 07:29:54,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:54,049 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:54,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:54,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:54,102 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:54,102 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [851643191] [2021-11-07 07:29:54,102 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [851643191] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:54,102 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:54,102 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:54,103 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1040023625] [2021-11-07 07:29:54,103 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:29:54,103 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:29:54,104 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:29:54,104 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:29:54,104 INFO L87 Difference]: Start difference. First operand 1986 states and 2946 transitions. cyclomatic complexity: 961 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:54,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:29:54,180 INFO L93 Difference]: Finished difference Result 1986 states and 2945 transitions. [2021-11-07 07:29:54,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:29:54,181 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2945 transitions. [2021-11-07 07:29:54,197 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:54,212 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2945 transitions. [2021-11-07 07:29:54,212 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-07 07:29:54,215 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-07 07:29:54,215 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2945 transitions. [2021-11-07 07:29:54,220 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:29:54,220 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2945 transitions. [2021-11-07 07:29:54,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2945 transitions. [2021-11-07 07:29:54,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-07 07:29:54,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.4828801611278952) internal successors, (2945), 1985 states have internal predecessors, (2945), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:54,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2945 transitions. [2021-11-07 07:29:54,277 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2945 transitions. [2021-11-07 07:29:54,277 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2945 transitions. [2021-11-07 07:29:54,277 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-07 07:29:54,277 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2945 transitions. [2021-11-07 07:29:54,289 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:54,290 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:29:54,290 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:29:54,294 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:54,294 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:54,295 INFO L791 eck$LassoCheckResult]: Stem: 48633#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 48634#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 48370#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 48371#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 48312#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48313#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48556#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 48592#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49406#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49407#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49517#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49518#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48376#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 48377#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 49554#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 48889#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 48890#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 49460#L974-1 assume !(0 == ~M_E~0); 49193#L1286-1 assume !(0 == ~T1_E~0); 48283#L1291-1 assume !(0 == ~T2_E~0); 48284#L1296-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48978#L1301-1 assume !(0 == ~T4_E~0); 48979#L1306-1 assume !(0 == ~T5_E~0); 49469#L1311-1 assume !(0 == ~T6_E~0); 48243#L1316-1 assume !(0 == ~T7_E~0); 48244#L1321-1 assume !(0 == ~T8_E~0); 48998#L1326-1 assume !(0 == ~T9_E~0); 48060#L1331-1 assume !(0 == ~T10_E~0); 47766#L1336-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 47767#L1341-1 assume !(0 == ~T12_E~0); 47818#L1346-1 assume !(0 == ~T13_E~0); 47819#L1351-1 assume !(0 == ~E_M~0); 48190#L1356-1 assume !(0 == ~E_1~0); 48191#L1361-1 assume !(0 == ~E_2~0); 49683#L1366-1 assume !(0 == ~E_3~0); 48236#L1371-1 assume !(0 == ~E_4~0); 48237#L1376-1 assume 0 == ~E_5~0;~E_5~0 := 1; 49038#L1381-1 assume !(0 == ~E_6~0); 49039#L1386-1 assume !(0 == ~E_7~0); 49710#L1391-1 assume !(0 == ~E_8~0); 49723#L1396-1 assume !(0 == ~E_9~0); 48922#L1401-1 assume !(0 == ~E_10~0); 48923#L1406-1 assume !(0 == ~E_11~0); 49221#L1411-1 assume !(0 == ~E_12~0); 49222#L1416-1 assume 0 == ~E_13~0;~E_13~0 := 1; 48849#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 48687#L635 assume 1 == ~m_pc~0; 48688#L636 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 47837#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 48185#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 48813#L1598 assume !(0 != activate_threads_~tmp~1); 48015#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 48016#L654 assume !(1 == ~t1_pc~0); 48713#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 48712#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 49707#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 48793#L1606 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 48794#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 48063#L673 assume 1 == ~t2_pc~0; 48064#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 49191#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 49192#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 49734#L1614 assume !(0 != activate_threads_~tmp___1~0); 49741#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 48872#L692 assume !(1 == ~t3_pc~0); 48689#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 48690#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 48557#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 48527#L1622 assume !(0 != activate_threads_~tmp___2~0); 48528#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 48088#L711 assume 1 == ~t4_pc~0; 48089#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 48570#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 49015#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 47791#L1630 assume !(0 != activate_threads_~tmp___3~0); 47792#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 49730#L730 assume !(1 == ~t5_pc~0); 49125#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 47970#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 47971#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 48098#L1638 assume !(0 != activate_threads_~tmp___4~0); 48099#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 48441#L749 assume 1 == ~t6_pc~0; 48213#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 47975#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 48407#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 48408#L1646 assume !(0 != activate_threads_~tmp___5~0); 48625#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 47771#L768 assume 1 == ~t7_pc~0; 47772#L769 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 49062#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 48008#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 48009#L1654 assume !(0 != activate_threads_~tmp___6~0); 49079#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 48245#L787 assume !(1 == ~t8_pc~0); 48246#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 49420#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 49580#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 49581#L1662 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 47816#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 47817#L806 assume 1 == ~t9_pc~0; 49431#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 47851#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 47852#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 48100#L1670 assume !(0 != activate_threads_~tmp___8~0); 48101#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 49414#L825 assume !(1 == ~t10_pc~0); 49415#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 49029#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 49030#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 48186#L1678 assume !(0 != activate_threads_~tmp___9~0); 48187#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 48762#L844 assume 1 == ~t11_pc~0; 48462#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 48463#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 48819#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 48820#L1686 assume !(0 != activate_threads_~tmp___10~0); 49403#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 49404#L863 assume !(1 == ~t12_pc~0); 47950#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 47951#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 48176#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 49493#L1694 assume !(0 != activate_threads_~tmp___11~0); 49494#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 48886#L882 assume 1 == ~t13_pc~0; 48887#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 49164#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 49654#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 49462#L1702 assume !(0 != activate_threads_~tmp___12~0); 49151#L1702-2 assume !(1 == ~M_E~0); 49152#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49600#L1439-1 assume !(1 == ~T2_E~0); 48081#L1444-1 assume !(1 == ~T3_E~0); 48082#L1449-1 assume !(1 == ~T4_E~0); 48524#L1454-1 assume !(1 == ~T5_E~0); 48525#L1459-1 assume !(1 == ~T6_E~0); 49080#L1464-1 assume !(1 == ~T7_E~0); 49081#L1469-1 assume !(1 == ~T8_E~0); 49165#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 48850#L1479-1 assume !(1 == ~T10_E~0); 48851#L1484-1 assume !(1 == ~T11_E~0); 49087#L1489-1 assume !(1 == ~T12_E~0); 48728#L1494-1 assume !(1 == ~T13_E~0); 48729#L1499-1 assume !(1 == ~E_M~0); 48907#L1504-1 assume !(1 == ~E_1~0); 48908#L1509-1 assume !(1 == ~E_2~0); 49509#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 49203#L1519-1 assume !(1 == ~E_4~0); 49204#L1524-1 assume !(1 == ~E_5~0); 49694#L1529-1 assume !(1 == ~E_6~0); 49695#L1534-1 assume !(1 == ~E_7~0); 47871#L1539-1 assume !(1 == ~E_8~0); 47872#L1544-1 assume !(1 == ~E_9~0); 48300#L1549-1 assume !(1 == ~E_10~0); 49673#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 49671#L1559-1 assume !(1 == ~E_12~0); 49538#L1564-1 assume !(1 == ~E_13~0); 48480#L1935-1 [2021-11-07 07:29:54,295 INFO L793 eck$LassoCheckResult]: Loop: 48480#L1935-1 assume !false; 47880#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 47881#L1261 assume !false; 49091#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 49092#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 48011#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 48179#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 48180#L1074 assume !(0 != eval_~tmp~0); 48539#L1276 start_simulation_~kernel_st~0 := 2; 49120#L902-1 start_simulation_~kernel_st~0 := 3; 49513#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 48588#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 48589#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 49294#L1296-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 49720#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49679#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 48806#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 48115#L1316-3 assume !(0 == ~T7_E~0); 48116#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 48219#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 48944#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 49206#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 49207#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 48517#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 48509#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 48452#L1356-3 assume !(0 == ~E_1~0); 48453#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49019#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47806#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47807#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 49524#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 49376#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 49377#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49555#L1396-3 assume !(0 == ~E_9~0); 49556#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 48184#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 48017#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 48018#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 48640#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 47895#L635-45 assume !(1 == ~m_pc~0); 47896#L635-47 is_master_triggered_~__retres1~0 := 0; 48680#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 49153#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 49402#L1598-45 assume !(0 != activate_threads_~tmp~1); 48202#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 48203#L654-45 assume 1 == ~t1_pc~0; 49011#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 49351#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 47858#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 47859#L1606-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 47884#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 48701#L673-45 assume !(1 == ~t2_pc~0); 48702#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 49022#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 49023#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 49635#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 49459#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 48329#L692-45 assume !(1 == ~t3_pc~0); 48055#L692-47 is_transmit3_triggered_~__retres1~3 := 0; 48056#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 49083#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 48383#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 48384#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 48686#L711-45 assume 1 == ~t4_pc~0; 48810#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 48812#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 48665#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 48666#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 49063#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 48226#L730-45 assume 1 == ~t5_pc~0; 48066#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 48067#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 48476#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 48477#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 49212#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 48039#L749-45 assume !(1 == ~t6_pc~0); 48040#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 49417#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 49186#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 49187#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 49334#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 48355#L768-45 assume 1 == ~t7_pc~0; 48356#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 48496#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 49281#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 49282#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 49319#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 49320#L787-45 assume 1 == ~t8_pc~0; 49484#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 48502#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 48503#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 48905#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 48906#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 49211#L806-45 assume !(1 == ~t9_pc~0); 47914#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 47915#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 48730#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 48566#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 48481#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 48482#L825-45 assume 1 == ~t10_pc~0; 49077#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 48992#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 49093#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 49094#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 49244#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 48123#L844-45 assume !(1 == ~t11_pc~0); 48124#L844-47 is_transmit11_triggered_~__retres1~11 := 0; 48641#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 48642#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 48655#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 49060#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 48163#L863-45 assume 1 == ~t12_pc~0; 48164#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 47764#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 47765#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 48278#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 48279#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 49066#L882-45 assume 1 == ~t13_pc~0; 49411#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 47783#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 47784#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 48392#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 49546#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 49170#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49171#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48077#L1444-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48078#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48238#L1454-3 assume !(1 == ~T5_E~0); 49160#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49161#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49597#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49526#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49527#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 49599#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 48808#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 48809#L1494-3 assume !(1 == ~T13_E~0); 49456#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49097#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49098#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49535#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49573#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48731#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 48732#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49619#L1534-3 assume !(1 == ~E_7~0); 49028#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 48497#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 48498#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 48999#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 48128#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 48129#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 49259#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 49260#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 48013#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 48576#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 49232#L1954 assume !(0 == start_simulation_~tmp~3); 49198#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 49199#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 48294#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 49317#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 49444#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 49445#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 49533#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 49593#L1967 assume !(0 != start_simulation_~tmp___0~1); 48480#L1935-1 [2021-11-07 07:29:54,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:54,296 INFO L85 PathProgramCache]: Analyzing trace with hash 265884581, now seen corresponding path program 1 times [2021-11-07 07:29:54,296 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:54,297 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1046313410] [2021-11-07 07:29:54,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:54,297 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:54,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:54,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:54,347 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:54,347 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1046313410] [2021-11-07 07:29:54,348 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1046313410] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:54,348 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:54,348 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 07:29:54,348 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2082775703] [2021-11-07 07:29:54,349 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:29:54,349 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:54,350 INFO L85 PathProgramCache]: Analyzing trace with hash -434951558, now seen corresponding path program 3 times [2021-11-07 07:29:54,350 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:54,350 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [616971860] [2021-11-07 07:29:54,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:54,351 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:54,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:54,408 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:54,409 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:54,409 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [616971860] [2021-11-07 07:29:54,409 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [616971860] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:54,409 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:54,410 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:54,410 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [275667228] [2021-11-07 07:29:54,410 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:29:54,411 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:29:54,411 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:29:54,411 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:29:54,412 INFO L87 Difference]: Start difference. First operand 1986 states and 2945 transitions. cyclomatic complexity: 960 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:54,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:29:54,461 INFO L93 Difference]: Finished difference Result 1986 states and 2940 transitions. [2021-11-07 07:29:54,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:29:54,462 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2940 transitions. [2021-11-07 07:29:54,477 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:54,491 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2940 transitions. [2021-11-07 07:29:54,491 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-07 07:29:54,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-07 07:29:54,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2940 transitions. [2021-11-07 07:29:54,500 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:29:54,500 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2940 transitions. [2021-11-07 07:29:54,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2940 transitions. [2021-11-07 07:29:54,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-07 07:29:54,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.4803625377643506) internal successors, (2940), 1985 states have internal predecessors, (2940), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:54,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2940 transitions. [2021-11-07 07:29:54,557 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2940 transitions. [2021-11-07 07:29:54,557 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2940 transitions. [2021-11-07 07:29:54,558 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-07 07:29:54,558 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2940 transitions. [2021-11-07 07:29:54,570 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:54,570 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:29:54,570 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:29:54,574 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:54,575 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:54,575 INFO L791 eck$LassoCheckResult]: Stem: 52612#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 52613#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 52349#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 52350#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 52291#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 52292#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52535#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52571#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53385#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53386#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53496#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53497#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 52355#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 52356#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 53533#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 52868#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 52869#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 53439#L974-1 assume !(0 == ~M_E~0); 53172#L1286-1 assume !(0 == ~T1_E~0); 52262#L1291-1 assume !(0 == ~T2_E~0); 52263#L1296-1 assume !(0 == ~T3_E~0); 52957#L1301-1 assume !(0 == ~T4_E~0); 52958#L1306-1 assume !(0 == ~T5_E~0); 53448#L1311-1 assume !(0 == ~T6_E~0); 52222#L1316-1 assume !(0 == ~T7_E~0); 52223#L1321-1 assume !(0 == ~T8_E~0); 52977#L1326-1 assume !(0 == ~T9_E~0); 52039#L1331-1 assume !(0 == ~T10_E~0); 51745#L1336-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 51746#L1341-1 assume !(0 == ~T12_E~0); 51797#L1346-1 assume !(0 == ~T13_E~0); 51798#L1351-1 assume !(0 == ~E_M~0); 52169#L1356-1 assume !(0 == ~E_1~0); 52170#L1361-1 assume !(0 == ~E_2~0); 53662#L1366-1 assume !(0 == ~E_3~0); 52215#L1371-1 assume !(0 == ~E_4~0); 52216#L1376-1 assume 0 == ~E_5~0;~E_5~0 := 1; 53017#L1381-1 assume !(0 == ~E_6~0); 53018#L1386-1 assume !(0 == ~E_7~0); 53689#L1391-1 assume !(0 == ~E_8~0); 53702#L1396-1 assume !(0 == ~E_9~0); 52901#L1401-1 assume !(0 == ~E_10~0); 52902#L1406-1 assume !(0 == ~E_11~0); 53200#L1411-1 assume !(0 == ~E_12~0); 53201#L1416-1 assume 0 == ~E_13~0;~E_13~0 := 1; 52828#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 52666#L635 assume 1 == ~m_pc~0; 52667#L636 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 51816#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 52164#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 52792#L1598 assume !(0 != activate_threads_~tmp~1); 51994#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 51995#L654 assume !(1 == ~t1_pc~0); 52692#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 52691#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 53686#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 52772#L1606 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 52773#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 52042#L673 assume 1 == ~t2_pc~0; 52043#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 53170#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 53171#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 53713#L1614 assume !(0 != activate_threads_~tmp___1~0); 53720#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 52851#L692 assume !(1 == ~t3_pc~0); 52668#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 52669#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 52536#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 52506#L1622 assume !(0 != activate_threads_~tmp___2~0); 52507#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 52067#L711 assume 1 == ~t4_pc~0; 52068#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 52549#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 52994#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 51770#L1630 assume !(0 != activate_threads_~tmp___3~0); 51771#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 53709#L730 assume !(1 == ~t5_pc~0); 53104#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 51949#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 51950#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 52077#L1638 assume !(0 != activate_threads_~tmp___4~0); 52078#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 52420#L749 assume 1 == ~t6_pc~0; 52192#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 51954#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 52386#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 52387#L1646 assume !(0 != activate_threads_~tmp___5~0); 52604#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 51750#L768 assume 1 == ~t7_pc~0; 51751#L769 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 53041#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 51987#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 51988#L1654 assume !(0 != activate_threads_~tmp___6~0); 53058#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 52224#L787 assume !(1 == ~t8_pc~0); 52225#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 53399#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 53559#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 53560#L1662 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 51795#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 51796#L806 assume 1 == ~t9_pc~0; 53410#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 51830#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 51831#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 52079#L1670 assume !(0 != activate_threads_~tmp___8~0); 52080#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 53393#L825 assume !(1 == ~t10_pc~0); 53394#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 53008#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 53009#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 52165#L1678 assume !(0 != activate_threads_~tmp___9~0); 52166#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 52741#L844 assume 1 == ~t11_pc~0; 52441#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 52442#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 52798#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 52799#L1686 assume !(0 != activate_threads_~tmp___10~0); 53382#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 53383#L863 assume !(1 == ~t12_pc~0); 51929#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 51930#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 52155#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 53472#L1694 assume !(0 != activate_threads_~tmp___11~0); 53473#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 52865#L882 assume 1 == ~t13_pc~0; 52866#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 53143#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 53633#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 53441#L1702 assume !(0 != activate_threads_~tmp___12~0); 53130#L1702-2 assume !(1 == ~M_E~0); 53131#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53579#L1439-1 assume !(1 == ~T2_E~0); 52060#L1444-1 assume !(1 == ~T3_E~0); 52061#L1449-1 assume !(1 == ~T4_E~0); 52503#L1454-1 assume !(1 == ~T5_E~0); 52504#L1459-1 assume !(1 == ~T6_E~0); 53059#L1464-1 assume !(1 == ~T7_E~0); 53060#L1469-1 assume !(1 == ~T8_E~0); 53144#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52829#L1479-1 assume !(1 == ~T10_E~0); 52830#L1484-1 assume !(1 == ~T11_E~0); 53066#L1489-1 assume !(1 == ~T12_E~0); 52707#L1494-1 assume !(1 == ~T13_E~0); 52708#L1499-1 assume !(1 == ~E_M~0); 52886#L1504-1 assume !(1 == ~E_1~0); 52887#L1509-1 assume !(1 == ~E_2~0); 53488#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 53182#L1519-1 assume !(1 == ~E_4~0); 53183#L1524-1 assume !(1 == ~E_5~0); 53673#L1529-1 assume !(1 == ~E_6~0); 53674#L1534-1 assume !(1 == ~E_7~0); 51850#L1539-1 assume !(1 == ~E_8~0); 51851#L1544-1 assume !(1 == ~E_9~0); 52279#L1549-1 assume !(1 == ~E_10~0); 53652#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 53650#L1559-1 assume !(1 == ~E_12~0); 53517#L1564-1 assume !(1 == ~E_13~0); 52459#L1935-1 [2021-11-07 07:29:54,576 INFO L793 eck$LassoCheckResult]: Loop: 52459#L1935-1 assume !false; 51859#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 51860#L1261 assume !false; 53070#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 53071#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 51990#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 52158#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 52159#L1074 assume !(0 != eval_~tmp~0); 52518#L1276 start_simulation_~kernel_st~0 := 2; 53099#L902-1 start_simulation_~kernel_st~0 := 3; 53492#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 52567#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 52568#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 53273#L1296-3 assume !(0 == ~T3_E~0); 53699#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53658#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 52785#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 52094#L1316-3 assume !(0 == ~T7_E~0); 52095#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 52198#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 52923#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 53185#L1336-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 53186#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 52496#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 52488#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 52431#L1356-3 assume !(0 == ~E_1~0); 52432#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 52998#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 51785#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 51786#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 53503#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53355#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53356#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53534#L1396-3 assume !(0 == ~E_9~0); 53535#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 52163#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 51996#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 51997#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 52619#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 51874#L635-45 assume !(1 == ~m_pc~0); 51875#L635-47 is_master_triggered_~__retres1~0 := 0; 52659#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 53132#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 53381#L1598-45 assume !(0 != activate_threads_~tmp~1); 52181#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 52182#L654-45 assume 1 == ~t1_pc~0; 52990#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 53330#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 51837#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 51838#L1606-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 51863#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 52680#L673-45 assume !(1 == ~t2_pc~0); 52681#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 53001#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 53002#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 53614#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 53438#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 52308#L692-45 assume !(1 == ~t3_pc~0); 52034#L692-47 is_transmit3_triggered_~__retres1~3 := 0; 52035#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 53062#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 52362#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 52363#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 52665#L711-45 assume 1 == ~t4_pc~0; 52789#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 52791#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 52644#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 52645#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 53042#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 52205#L730-45 assume 1 == ~t5_pc~0; 52045#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 52046#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 52455#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 52456#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 53191#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 52018#L749-45 assume !(1 == ~t6_pc~0); 52019#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 53396#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 53165#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 53166#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 53313#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 52334#L768-45 assume !(1 == ~t7_pc~0); 52336#L768-47 is_transmit7_triggered_~__retres1~7 := 0; 52475#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 53260#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 53261#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 53298#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 53299#L787-45 assume 1 == ~t8_pc~0; 53463#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 52481#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 52482#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 52884#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 52885#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 53190#L806-45 assume !(1 == ~t9_pc~0); 51893#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 51894#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 52709#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 52545#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 52460#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 52461#L825-45 assume 1 == ~t10_pc~0; 53056#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 52971#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 53072#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 53073#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 53223#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 52102#L844-45 assume !(1 == ~t11_pc~0); 52103#L844-47 is_transmit11_triggered_~__retres1~11 := 0; 52620#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 52621#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 52634#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 53039#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 52142#L863-45 assume !(1 == ~t12_pc~0); 52144#L863-47 is_transmit12_triggered_~__retres1~12 := 0; 51743#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 51744#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 52257#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 52258#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 53045#L882-45 assume !(1 == ~t13_pc~0); 52585#L882-47 is_transmit13_triggered_~__retres1~13 := 0; 51762#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 51763#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 52371#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 53525#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 53149#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53150#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 52056#L1444-3 assume !(1 == ~T3_E~0); 52057#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 52217#L1454-3 assume !(1 == ~T5_E~0); 53139#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53140#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 53576#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 53505#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 53506#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 53578#L1484-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 52787#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 52788#L1494-3 assume !(1 == ~T13_E~0); 53435#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53076#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53077#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 53514#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 53552#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 52710#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 52711#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 53598#L1534-3 assume !(1 == ~E_7~0); 53007#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 52476#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 52477#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 52978#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 52107#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 52108#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 53238#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 53239#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 51992#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 52555#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 53211#L1954 assume !(0 == start_simulation_~tmp~3); 53177#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 53178#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 52273#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 53296#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 53423#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 53424#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 53512#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 53572#L1967 assume !(0 != start_simulation_~tmp___0~1); 52459#L1935-1 [2021-11-07 07:29:54,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:54,577 INFO L85 PathProgramCache]: Analyzing trace with hash 335532455, now seen corresponding path program 1 times [2021-11-07 07:29:54,577 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:54,577 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848160078] [2021-11-07 07:29:54,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:54,578 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:54,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:54,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:54,630 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:54,630 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [848160078] [2021-11-07 07:29:54,630 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [848160078] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:54,631 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:54,631 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 07:29:54,631 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1919109408] [2021-11-07 07:29:54,632 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:29:54,632 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:54,632 INFO L85 PathProgramCache]: Analyzing trace with hash -2086912685, now seen corresponding path program 1 times [2021-11-07 07:29:54,632 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:54,633 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [242860859] [2021-11-07 07:29:54,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:54,633 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:54,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:54,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:54,695 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:54,696 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [242860859] [2021-11-07 07:29:54,696 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [242860859] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:54,696 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:54,696 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:54,696 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1972982711] [2021-11-07 07:29:54,697 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:29:54,697 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:29:54,698 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:29:54,698 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:29:54,698 INFO L87 Difference]: Start difference. First operand 1986 states and 2940 transitions. cyclomatic complexity: 955 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:54,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:29:54,746 INFO L93 Difference]: Finished difference Result 1986 states and 2935 transitions. [2021-11-07 07:29:54,746 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:29:54,746 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2935 transitions. [2021-11-07 07:29:54,762 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:54,773 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2935 transitions. [2021-11-07 07:29:54,773 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-07 07:29:54,776 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-07 07:29:54,776 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2935 transitions. [2021-11-07 07:29:54,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:29:54,781 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2935 transitions. [2021-11-07 07:29:54,786 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2935 transitions. [2021-11-07 07:29:54,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-07 07:29:54,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.4778449144008057) internal successors, (2935), 1985 states have internal predecessors, (2935), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:54,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2935 transitions. [2021-11-07 07:29:54,831 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2935 transitions. [2021-11-07 07:29:54,832 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2935 transitions. [2021-11-07 07:29:54,832 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-07 07:29:54,832 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2935 transitions. [2021-11-07 07:29:54,843 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:54,843 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:29:54,843 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:29:54,847 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:54,847 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:54,847 INFO L791 eck$LassoCheckResult]: Stem: 56591#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 56592#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 56328#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 56329#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 56270#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56271#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 56514#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 56550#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 57364#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 57365#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 57475#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 57476#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 56334#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 56335#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 57512#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 56847#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 56848#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 57418#L974-1 assume !(0 == ~M_E~0); 57151#L1286-1 assume !(0 == ~T1_E~0); 56241#L1291-1 assume !(0 == ~T2_E~0); 56242#L1296-1 assume !(0 == ~T3_E~0); 56936#L1301-1 assume !(0 == ~T4_E~0); 56937#L1306-1 assume !(0 == ~T5_E~0); 57427#L1311-1 assume !(0 == ~T6_E~0); 56201#L1316-1 assume !(0 == ~T7_E~0); 56202#L1321-1 assume !(0 == ~T8_E~0); 56956#L1326-1 assume !(0 == ~T9_E~0); 56018#L1331-1 assume !(0 == ~T10_E~0); 55724#L1336-1 assume !(0 == ~T11_E~0); 55725#L1341-1 assume !(0 == ~T12_E~0); 55776#L1346-1 assume !(0 == ~T13_E~0); 55777#L1351-1 assume !(0 == ~E_M~0); 56148#L1356-1 assume !(0 == ~E_1~0); 56149#L1361-1 assume !(0 == ~E_2~0); 57641#L1366-1 assume !(0 == ~E_3~0); 56194#L1371-1 assume !(0 == ~E_4~0); 56195#L1376-1 assume 0 == ~E_5~0;~E_5~0 := 1; 56996#L1381-1 assume !(0 == ~E_6~0); 56997#L1386-1 assume !(0 == ~E_7~0); 57668#L1391-1 assume !(0 == ~E_8~0); 57681#L1396-1 assume !(0 == ~E_9~0); 56880#L1401-1 assume !(0 == ~E_10~0); 56881#L1406-1 assume !(0 == ~E_11~0); 57179#L1411-1 assume !(0 == ~E_12~0); 57180#L1416-1 assume 0 == ~E_13~0;~E_13~0 := 1; 56807#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 56645#L635 assume 1 == ~m_pc~0; 56646#L636 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 55795#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 56143#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 56771#L1598 assume !(0 != activate_threads_~tmp~1); 55973#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 55974#L654 assume !(1 == ~t1_pc~0); 56671#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 56670#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 57665#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 56751#L1606 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 56752#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 56021#L673 assume 1 == ~t2_pc~0; 56022#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 57149#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 57150#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 57692#L1614 assume !(0 != activate_threads_~tmp___1~0); 57699#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 56830#L692 assume !(1 == ~t3_pc~0); 56647#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 56648#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 56515#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 56485#L1622 assume !(0 != activate_threads_~tmp___2~0); 56486#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 56046#L711 assume 1 == ~t4_pc~0; 56047#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 56528#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 56973#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 55749#L1630 assume !(0 != activate_threads_~tmp___3~0); 55750#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 57688#L730 assume !(1 == ~t5_pc~0); 57083#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 55928#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 55929#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 56056#L1638 assume !(0 != activate_threads_~tmp___4~0); 56057#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 56399#L749 assume 1 == ~t6_pc~0; 56171#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 55933#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 56365#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 56366#L1646 assume !(0 != activate_threads_~tmp___5~0); 56583#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 55729#L768 assume 1 == ~t7_pc~0; 55730#L769 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 57020#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 55966#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 55967#L1654 assume !(0 != activate_threads_~tmp___6~0); 57037#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 56203#L787 assume !(1 == ~t8_pc~0); 56204#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 57378#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 57538#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 57539#L1662 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 55774#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 55775#L806 assume 1 == ~t9_pc~0; 57389#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 55809#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 55810#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 56058#L1670 assume !(0 != activate_threads_~tmp___8~0); 56059#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 57372#L825 assume !(1 == ~t10_pc~0); 57373#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 56987#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 56988#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 56144#L1678 assume !(0 != activate_threads_~tmp___9~0); 56145#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 56720#L844 assume 1 == ~t11_pc~0; 56420#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 56421#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 56777#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 56778#L1686 assume !(0 != activate_threads_~tmp___10~0); 57361#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 57362#L863 assume !(1 == ~t12_pc~0); 55908#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 55909#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 56134#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 57451#L1694 assume !(0 != activate_threads_~tmp___11~0); 57452#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 56844#L882 assume 1 == ~t13_pc~0; 56845#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 57122#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 57612#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 57420#L1702 assume !(0 != activate_threads_~tmp___12~0); 57109#L1702-2 assume !(1 == ~M_E~0); 57110#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 57558#L1439-1 assume !(1 == ~T2_E~0); 56039#L1444-1 assume !(1 == ~T3_E~0); 56040#L1449-1 assume !(1 == ~T4_E~0); 56482#L1454-1 assume !(1 == ~T5_E~0); 56483#L1459-1 assume !(1 == ~T6_E~0); 57038#L1464-1 assume !(1 == ~T7_E~0); 57039#L1469-1 assume !(1 == ~T8_E~0); 57123#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 56808#L1479-1 assume !(1 == ~T10_E~0); 56809#L1484-1 assume !(1 == ~T11_E~0); 57045#L1489-1 assume !(1 == ~T12_E~0); 56686#L1494-1 assume !(1 == ~T13_E~0); 56687#L1499-1 assume !(1 == ~E_M~0); 56865#L1504-1 assume !(1 == ~E_1~0); 56866#L1509-1 assume !(1 == ~E_2~0); 57467#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 57161#L1519-1 assume !(1 == ~E_4~0); 57162#L1524-1 assume !(1 == ~E_5~0); 57652#L1529-1 assume !(1 == ~E_6~0); 57653#L1534-1 assume !(1 == ~E_7~0); 55829#L1539-1 assume !(1 == ~E_8~0); 55830#L1544-1 assume !(1 == ~E_9~0); 56258#L1549-1 assume !(1 == ~E_10~0); 57631#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 57629#L1559-1 assume !(1 == ~E_12~0); 57496#L1564-1 assume !(1 == ~E_13~0); 56438#L1935-1 [2021-11-07 07:29:54,848 INFO L793 eck$LassoCheckResult]: Loop: 56438#L1935-1 assume !false; 55838#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 55839#L1261 assume !false; 57049#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 57050#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 55969#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 56137#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 56138#L1074 assume !(0 != eval_~tmp~0); 56497#L1276 start_simulation_~kernel_st~0 := 2; 57078#L902-1 start_simulation_~kernel_st~0 := 3; 57471#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 56546#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 56547#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 57252#L1296-3 assume !(0 == ~T3_E~0); 57678#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 57637#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 56764#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 56073#L1316-3 assume !(0 == ~T7_E~0); 56074#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 56177#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 56902#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 57164#L1336-3 assume !(0 == ~T11_E~0); 57165#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 56475#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 56467#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 56410#L1356-3 assume !(0 == ~E_1~0); 56411#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 56977#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 55764#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55765#L1376-3 assume 0 == ~E_5~0;~E_5~0 := 1; 57482#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 57334#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 57335#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 57513#L1396-3 assume !(0 == ~E_9~0); 57514#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 56142#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 55975#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 55976#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 56598#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 55853#L635-45 assume !(1 == ~m_pc~0); 55854#L635-47 is_master_triggered_~__retres1~0 := 0; 56638#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 57111#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 57360#L1598-45 assume !(0 != activate_threads_~tmp~1); 56160#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 56161#L654-45 assume 1 == ~t1_pc~0; 56969#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 57309#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 55816#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 55817#L1606-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 55842#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 56659#L673-45 assume !(1 == ~t2_pc~0); 56660#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 56980#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 56981#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 57593#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 57417#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 56287#L692-45 assume 1 == ~t3_pc~0; 56288#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 56014#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 57041#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 56341#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 56342#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 56644#L711-45 assume 1 == ~t4_pc~0; 56768#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 56770#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 56623#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 56624#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 57021#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 56184#L730-45 assume 1 == ~t5_pc~0; 56024#L731-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 56025#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 56434#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 56435#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 57170#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 55997#L749-45 assume !(1 == ~t6_pc~0); 55998#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 57375#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 57144#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 57145#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 57292#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 56313#L768-45 assume 1 == ~t7_pc~0; 56314#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 56454#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 57239#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 57240#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 57277#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 57278#L787-45 assume 1 == ~t8_pc~0; 57442#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 56460#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 56461#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 56863#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 56864#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 57169#L806-45 assume !(1 == ~t9_pc~0); 55872#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 55873#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 56688#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 56524#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 56439#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 56440#L825-45 assume !(1 == ~t10_pc~0); 56949#L825-47 is_transmit10_triggered_~__retres1~10 := 0; 56950#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 57051#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 57052#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 57202#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 56081#L844-45 assume !(1 == ~t11_pc~0); 56082#L844-47 is_transmit11_triggered_~__retres1~11 := 0; 56599#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 56600#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 56613#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 57018#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 56121#L863-45 assume 1 == ~t12_pc~0; 56122#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 55722#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 55723#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 56236#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 56237#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 57024#L882-45 assume !(1 == ~t13_pc~0); 56564#L882-47 is_transmit13_triggered_~__retres1~13 := 0; 55741#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 55742#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 56350#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 57504#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 57128#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 57129#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 56035#L1444-3 assume !(1 == ~T3_E~0); 56036#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56196#L1454-3 assume !(1 == ~T5_E~0); 57118#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 57119#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 57555#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 57484#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 57485#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 57557#L1484-3 assume !(1 == ~T11_E~0); 56766#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 56767#L1494-3 assume !(1 == ~T13_E~0); 57414#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 57055#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 57056#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 57493#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57531#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 56689#L1524-3 assume 1 == ~E_5~0;~E_5~0 := 2; 56690#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 57577#L1534-3 assume !(1 == ~E_7~0); 56986#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 56455#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 56456#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 56957#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 56086#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 56087#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 57217#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 57218#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 55971#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 56534#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 57190#L1954 assume !(0 == start_simulation_~tmp~3); 57156#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 57157#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 56252#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 57275#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 57402#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 57403#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 57491#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 57551#L1967 assume !(0 != start_simulation_~tmp___0~1); 56438#L1935-1 [2021-11-07 07:29:54,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:54,848 INFO L85 PathProgramCache]: Analyzing trace with hash -612519511, now seen corresponding path program 1 times [2021-11-07 07:29:54,849 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:54,849 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1829905527] [2021-11-07 07:29:54,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:54,849 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:54,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:54,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:54,893 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:54,893 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1829905527] [2021-11-07 07:29:54,893 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1829905527] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:54,893 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:54,894 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 07:29:54,894 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [618403319] [2021-11-07 07:29:54,894 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:29:54,895 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:54,895 INFO L85 PathProgramCache]: Analyzing trace with hash 465283217, now seen corresponding path program 1 times [2021-11-07 07:29:54,895 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:54,895 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [572085867] [2021-11-07 07:29:54,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:54,896 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:54,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:54,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:54,950 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:54,951 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [572085867] [2021-11-07 07:29:54,951 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [572085867] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:54,952 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:54,952 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:54,952 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [818332174] [2021-11-07 07:29:54,953 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:29:54,953 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:29:54,954 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:29:54,954 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:29:54,954 INFO L87 Difference]: Start difference. First operand 1986 states and 2935 transitions. cyclomatic complexity: 950 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:55,055 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:29:55,056 INFO L93 Difference]: Finished difference Result 1986 states and 2914 transitions. [2021-11-07 07:29:55,056 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:29:55,057 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2914 transitions. [2021-11-07 07:29:55,074 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:55,093 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2914 transitions. [2021-11-07 07:29:55,093 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-07 07:29:55,096 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-07 07:29:55,096 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2914 transitions. [2021-11-07 07:29:55,101 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:29:55,101 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2914 transitions. [2021-11-07 07:29:55,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2914 transitions. [2021-11-07 07:29:55,137 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-07 07:29:55,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.4672708962739174) internal successors, (2914), 1985 states have internal predecessors, (2914), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:55,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2914 transitions. [2021-11-07 07:29:55,148 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2914 transitions. [2021-11-07 07:29:55,148 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2914 transitions. [2021-11-07 07:29:55,148 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-07 07:29:55,148 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2914 transitions. [2021-11-07 07:29:55,161 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:55,162 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:29:55,162 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:29:55,165 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:55,166 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:55,166 INFO L791 eck$LassoCheckResult]: Stem: 60568#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 60569#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 60303#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 60304#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 60245#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 60246#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 60490#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60527#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 61343#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 61344#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 61454#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 61455#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 60309#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 60310#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 61491#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 60825#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 60826#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 61397#L974-1 assume !(0 == ~M_E~0); 61129#L1286-1 assume !(0 == ~T1_E~0); 60217#L1291-1 assume !(0 == ~T2_E~0); 60218#L1296-1 assume !(0 == ~T3_E~0); 60914#L1301-1 assume !(0 == ~T4_E~0); 60915#L1306-1 assume !(0 == ~T5_E~0); 61406#L1311-1 assume !(0 == ~T6_E~0); 60177#L1316-1 assume !(0 == ~T7_E~0); 60178#L1321-1 assume !(0 == ~T8_E~0); 60934#L1326-1 assume !(0 == ~T9_E~0); 59996#L1331-1 assume !(0 == ~T10_E~0); 59703#L1336-1 assume !(0 == ~T11_E~0); 59704#L1341-1 assume !(0 == ~T12_E~0); 59755#L1346-1 assume !(0 == ~T13_E~0); 59756#L1351-1 assume !(0 == ~E_M~0); 60125#L1356-1 assume !(0 == ~E_1~0); 60126#L1361-1 assume !(0 == ~E_2~0); 61620#L1366-1 assume !(0 == ~E_3~0); 60170#L1371-1 assume !(0 == ~E_4~0); 60171#L1376-1 assume !(0 == ~E_5~0); 60974#L1381-1 assume !(0 == ~E_6~0); 60975#L1386-1 assume !(0 == ~E_7~0); 61647#L1391-1 assume !(0 == ~E_8~0); 61660#L1396-1 assume !(0 == ~E_9~0); 60858#L1401-1 assume !(0 == ~E_10~0); 60859#L1406-1 assume !(0 == ~E_11~0); 61157#L1411-1 assume !(0 == ~E_12~0); 61158#L1416-1 assume 0 == ~E_13~0;~E_13~0 := 1; 60785#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 60622#L635 assume 1 == ~m_pc~0; 60623#L636 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 59774#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 60120#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 60748#L1598 assume !(0 != activate_threads_~tmp~1); 59952#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 59953#L654 assume !(1 == ~t1_pc~0); 60648#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 60647#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 61644#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 60728#L1606 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 60729#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 59999#L673 assume 1 == ~t2_pc~0; 60000#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 61127#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 61128#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 61671#L1614 assume !(0 != activate_threads_~tmp___1~0); 61678#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 60808#L692 assume !(1 == ~t3_pc~0); 60624#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 60625#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 60491#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 60461#L1622 assume !(0 != activate_threads_~tmp___2~0); 60462#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 60023#L711 assume 1 == ~t4_pc~0; 60024#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 60504#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 60951#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 59728#L1630 assume !(0 != activate_threads_~tmp___3~0); 59729#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 61667#L730 assume !(1 == ~t5_pc~0); 61061#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 59907#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 59908#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 60033#L1638 assume !(0 != activate_threads_~tmp___4~0); 60034#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 60374#L749 assume 1 == ~t6_pc~0; 60148#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 59912#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 60340#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 60341#L1646 assume !(0 != activate_threads_~tmp___5~0); 60560#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 59708#L768 assume 1 == ~t7_pc~0; 59709#L769 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 60998#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 59945#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 59946#L1654 assume !(0 != activate_threads_~tmp___6~0); 61015#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 60179#L787 assume !(1 == ~t8_pc~0); 60180#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 61357#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 61517#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 61518#L1662 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 59753#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 59754#L806 assume 1 == ~t9_pc~0; 61368#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 59788#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 59789#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 60035#L1670 assume !(0 != activate_threads_~tmp___8~0); 60036#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 61351#L825 assume !(1 == ~t10_pc~0); 61352#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 60965#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 60966#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 60121#L1678 assume !(0 != activate_threads_~tmp___9~0); 60122#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 60697#L844 assume 1 == ~t11_pc~0; 60395#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 60396#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 60755#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 60756#L1686 assume !(0 != activate_threads_~tmp___10~0); 61340#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 61341#L863 assume !(1 == ~t12_pc~0); 59887#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 59888#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 60111#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 61430#L1694 assume !(0 != activate_threads_~tmp___11~0); 61431#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 60822#L882 assume 1 == ~t13_pc~0; 60823#L883 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 61100#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 61591#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 61399#L1702 assume !(0 != activate_threads_~tmp___12~0); 61087#L1702-2 assume !(1 == ~M_E~0); 61088#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 61537#L1439-1 assume !(1 == ~T2_E~0); 60016#L1444-1 assume !(1 == ~T3_E~0); 60017#L1449-1 assume !(1 == ~T4_E~0); 60457#L1454-1 assume !(1 == ~T5_E~0); 60458#L1459-1 assume !(1 == ~T6_E~0); 61016#L1464-1 assume !(1 == ~T7_E~0); 61017#L1469-1 assume !(1 == ~T8_E~0); 61101#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 60786#L1479-1 assume !(1 == ~T10_E~0); 60787#L1484-1 assume !(1 == ~T11_E~0); 61023#L1489-1 assume !(1 == ~T12_E~0); 60663#L1494-1 assume !(1 == ~T13_E~0); 60664#L1499-1 assume !(1 == ~E_M~0); 60843#L1504-1 assume !(1 == ~E_1~0); 60844#L1509-1 assume !(1 == ~E_2~0); 61446#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 61139#L1519-1 assume !(1 == ~E_4~0); 61140#L1524-1 assume !(1 == ~E_5~0); 61631#L1529-1 assume !(1 == ~E_6~0); 61632#L1534-1 assume !(1 == ~E_7~0); 59808#L1539-1 assume !(1 == ~E_8~0); 59809#L1544-1 assume !(1 == ~E_9~0); 60233#L1549-1 assume !(1 == ~E_10~0); 61610#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 61608#L1559-1 assume !(1 == ~E_12~0); 61475#L1564-1 assume !(1 == ~E_13~0); 60413#L1935-1 [2021-11-07 07:29:55,167 INFO L793 eck$LassoCheckResult]: Loop: 60413#L1935-1 assume !false; 59817#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 59818#L1261 assume !false; 61027#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 61028#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 59948#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 60114#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 60115#L1074 assume !(0 != eval_~tmp~0); 60473#L1276 start_simulation_~kernel_st~0 := 2; 61056#L902-1 start_simulation_~kernel_st~0 := 3; 61450#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 60523#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 60524#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 61230#L1296-3 assume !(0 == ~T3_E~0); 61657#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 61616#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 60741#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 60050#L1316-3 assume !(0 == ~T7_E~0); 60051#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 60154#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 60880#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 61142#L1336-3 assume !(0 == ~T11_E~0); 61143#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 60451#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 60442#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 60385#L1356-3 assume !(0 == ~E_1~0); 60386#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 60955#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 59743#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 59744#L1376-3 assume !(0 == ~E_5~0); 61461#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 61313#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 61314#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 61492#L1396-3 assume !(0 == ~E_9~0); 61493#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 60119#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 59954#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 59955#L1416-3 assume 0 == ~E_13~0;~E_13~0 := 1; 60575#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 59832#L635-45 assume !(1 == ~m_pc~0); 59833#L635-47 is_master_triggered_~__retres1~0 := 0; 60615#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 61089#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 61339#L1598-45 assume !(0 != activate_threads_~tmp~1); 60137#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 60138#L654-45 assume 1 == ~t1_pc~0; 60947#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 61288#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 59795#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 59796#L1606-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 59821#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 60636#L673-45 assume !(1 == ~t2_pc~0); 60637#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 60958#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 60959#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 61572#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 61396#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 60262#L692-45 assume 1 == ~t3_pc~0; 60263#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 59992#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 61019#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 60316#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 60317#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 60621#L711-45 assume 1 == ~t4_pc~0; 60745#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 60747#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 60600#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 60601#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 60999#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 60160#L730-45 assume !(1 == ~t5_pc~0); 60003#L730-47 is_transmit5_triggered_~__retres1~5 := 0; 61240#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 60409#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 60410#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 61148#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 59975#L749-45 assume !(1 == ~t6_pc~0); 59976#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 61354#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 61122#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 61123#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 61271#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 60288#L768-45 assume 1 == ~t7_pc~0; 60289#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 60429#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 61217#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 61218#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 61256#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 61257#L787-45 assume 1 == ~t8_pc~0; 61421#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 60435#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 60436#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 60841#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 60842#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 61147#L806-45 assume !(1 == ~t9_pc~0); 59851#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 59852#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 60665#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 60500#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 60414#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 60415#L825-45 assume 1 == ~t10_pc~0; 61013#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 60928#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 61029#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 61030#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 61180#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 60058#L844-45 assume !(1 == ~t11_pc~0); 60059#L844-47 is_transmit11_triggered_~__retres1~11 := 0; 60576#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 60577#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 60590#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 60996#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 60098#L863-45 assume 1 == ~t12_pc~0; 60099#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 59701#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 59702#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 60212#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 60213#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 61002#L882-45 assume 1 == ~t13_pc~0; 61348#L883-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 59720#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 59721#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 60325#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 61483#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 61106#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 61107#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60012#L1444-3 assume !(1 == ~T3_E~0); 60013#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 60172#L1454-3 assume !(1 == ~T5_E~0); 61096#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 61097#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 61534#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 61463#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 61464#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 61536#L1484-3 assume !(1 == ~T11_E~0); 60743#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 60744#L1494-3 assume !(1 == ~T13_E~0); 61393#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 61033#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 61034#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 61472#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 61510#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 60666#L1524-3 assume !(1 == ~E_5~0); 60667#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 61556#L1534-3 assume !(1 == ~E_7~0); 60964#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 60430#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 60431#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 60935#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 60063#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 60064#L1564-3 assume 1 == ~E_13~0;~E_13~0 := 2; 61195#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 61196#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 59950#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 60511#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 61168#L1954 assume !(0 == start_simulation_~tmp~3); 61134#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 61135#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 60227#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 61254#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 61381#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 61382#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 61470#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 61530#L1967 assume !(0 != start_simulation_~tmp___0~1); 60413#L1935-1 [2021-11-07 07:29:55,167 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:55,167 INFO L85 PathProgramCache]: Analyzing trace with hash -124472405, now seen corresponding path program 1 times [2021-11-07 07:29:55,168 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:55,168 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1755960869] [2021-11-07 07:29:55,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:55,168 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:55,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:55,224 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:55,224 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:55,224 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1755960869] [2021-11-07 07:29:55,224 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1755960869] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:55,225 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:55,225 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 07:29:55,225 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1010657065] [2021-11-07 07:29:55,226 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:29:55,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:55,226 INFO L85 PathProgramCache]: Analyzing trace with hash -57221010, now seen corresponding path program 1 times [2021-11-07 07:29:55,226 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:55,227 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1123141061] [2021-11-07 07:29:55,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:55,227 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:55,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:55,283 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:55,284 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:55,284 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1123141061] [2021-11-07 07:29:55,284 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1123141061] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:55,284 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:55,284 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:55,285 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1826034761] [2021-11-07 07:29:55,285 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:29:55,285 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:29:55,286 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:29:55,286 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:29:55,286 INFO L87 Difference]: Start difference. First operand 1986 states and 2914 transitions. cyclomatic complexity: 929 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:55,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:29:55,418 INFO L93 Difference]: Finished difference Result 1986 states and 2893 transitions. [2021-11-07 07:29:55,418 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:29:55,419 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1986 states and 2893 transitions. [2021-11-07 07:29:55,431 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:55,441 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1986 states to 1986 states and 2893 transitions. [2021-11-07 07:29:55,441 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1986 [2021-11-07 07:29:55,444 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1986 [2021-11-07 07:29:55,444 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1986 states and 2893 transitions. [2021-11-07 07:29:55,449 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:29:55,449 INFO L681 BuchiCegarLoop]: Abstraction has 1986 states and 2893 transitions. [2021-11-07 07:29:55,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1986 states and 2893 transitions. [2021-11-07 07:29:55,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1986 to 1986. [2021-11-07 07:29:55,506 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1986 states, 1986 states have (on average 1.4566968781470293) internal successors, (2893), 1985 states have internal predecessors, (2893), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:55,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1986 states to 1986 states and 2893 transitions. [2021-11-07 07:29:55,513 INFO L704 BuchiCegarLoop]: Abstraction has 1986 states and 2893 transitions. [2021-11-07 07:29:55,513 INFO L587 BuchiCegarLoop]: Abstraction has 1986 states and 2893 transitions. [2021-11-07 07:29:55,514 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-07 07:29:55,514 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1986 states and 2893 transitions. [2021-11-07 07:29:55,523 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1815 [2021-11-07 07:29:55,523 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:29:55,523 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:29:55,528 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:55,528 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:55,529 INFO L791 eck$LassoCheckResult]: Stem: 64546#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 64547#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 64282#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 64283#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 64224#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 64225#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 64469#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 64506#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 65321#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 65322#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 65432#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 65433#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 64288#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 64289#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 65469#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 64803#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 64804#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 65375#L974-1 assume !(0 == ~M_E~0); 65107#L1286-1 assume !(0 == ~T1_E~0); 64196#L1291-1 assume !(0 == ~T2_E~0); 64197#L1296-1 assume !(0 == ~T3_E~0); 64892#L1301-1 assume !(0 == ~T4_E~0); 64893#L1306-1 assume !(0 == ~T5_E~0); 65384#L1311-1 assume !(0 == ~T6_E~0); 64156#L1316-1 assume !(0 == ~T7_E~0); 64157#L1321-1 assume !(0 == ~T8_E~0); 64912#L1326-1 assume !(0 == ~T9_E~0); 63974#L1331-1 assume !(0 == ~T10_E~0); 63682#L1336-1 assume !(0 == ~T11_E~0); 63683#L1341-1 assume !(0 == ~T12_E~0); 63734#L1346-1 assume !(0 == ~T13_E~0); 63735#L1351-1 assume !(0 == ~E_M~0); 64103#L1356-1 assume !(0 == ~E_1~0); 64104#L1361-1 assume !(0 == ~E_2~0); 65598#L1366-1 assume !(0 == ~E_3~0); 64149#L1371-1 assume !(0 == ~E_4~0); 64150#L1376-1 assume !(0 == ~E_5~0); 64953#L1381-1 assume !(0 == ~E_6~0); 64954#L1386-1 assume !(0 == ~E_7~0); 65626#L1391-1 assume !(0 == ~E_8~0); 65639#L1396-1 assume !(0 == ~E_9~0); 64836#L1401-1 assume !(0 == ~E_10~0); 64837#L1406-1 assume !(0 == ~E_11~0); 65135#L1411-1 assume !(0 == ~E_12~0); 65136#L1416-1 assume !(0 == ~E_13~0); 64763#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 64599#L635 assume 1 == ~m_pc~0; 64600#L636 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 63753#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 64098#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 64726#L1598 assume !(0 != activate_threads_~tmp~1); 63931#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 63932#L654 assume !(1 == ~t1_pc~0); 64625#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 64624#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 65623#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 64705#L1606 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 64706#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 63977#L673 assume 1 == ~t2_pc~0; 63978#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 65105#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 65106#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 65650#L1614 assume !(0 != activate_threads_~tmp___1~0); 65657#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 64786#L692 assume !(1 == ~t3_pc~0); 64601#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 64602#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 64470#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 64440#L1622 assume !(0 != activate_threads_~tmp___2~0); 64441#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 64001#L711 assume 1 == ~t4_pc~0; 64002#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 64483#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 64929#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 63707#L1630 assume !(0 != activate_threads_~tmp___3~0); 63708#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 65646#L730 assume !(1 == ~t5_pc~0); 65039#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 63886#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 63887#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 64011#L1638 assume !(0 != activate_threads_~tmp___4~0); 64012#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 64353#L749 assume 1 == ~t6_pc~0; 64127#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 63891#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 64319#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 64320#L1646 assume !(0 != activate_threads_~tmp___5~0); 64538#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 63687#L768 assume 1 == ~t7_pc~0; 63688#L769 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 64977#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 63924#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 63925#L1654 assume !(0 != activate_threads_~tmp___6~0); 64994#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 64158#L787 assume !(1 == ~t8_pc~0); 64159#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 65335#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 65495#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 65496#L1662 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 63732#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 63733#L806 assume 1 == ~t9_pc~0; 65346#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 63767#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 63768#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 64013#L1670 assume !(0 != activate_threads_~tmp___8~0); 64014#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 65329#L825 assume !(1 == ~t10_pc~0); 65330#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 64944#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 64945#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 64099#L1678 assume !(0 != activate_threads_~tmp___9~0); 64100#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 64674#L844 assume 1 == ~t11_pc~0; 64374#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 64375#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 64733#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 64734#L1686 assume !(0 != activate_threads_~tmp___10~0); 65318#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 65319#L863 assume !(1 == ~t12_pc~0); 63866#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 63867#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 64089#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 65408#L1694 assume !(0 != activate_threads_~tmp___11~0); 65409#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 64800#L882 assume !(1 == ~t13_pc~0); 64802#L882-2 is_transmit13_triggered_~__retres1~13 := 0; 65078#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 65569#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 65377#L1702 assume !(0 != activate_threads_~tmp___12~0); 65065#L1702-2 assume !(1 == ~M_E~0); 65066#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65515#L1439-1 assume !(1 == ~T2_E~0); 63994#L1444-1 assume !(1 == ~T3_E~0); 63995#L1449-1 assume !(1 == ~T4_E~0); 64436#L1454-1 assume !(1 == ~T5_E~0); 64437#L1459-1 assume !(1 == ~T6_E~0); 64995#L1464-1 assume !(1 == ~T7_E~0); 64996#L1469-1 assume !(1 == ~T8_E~0); 65079#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 64764#L1479-1 assume !(1 == ~T10_E~0); 64765#L1484-1 assume !(1 == ~T11_E~0); 65002#L1489-1 assume !(1 == ~T12_E~0); 64640#L1494-1 assume !(1 == ~T13_E~0); 64641#L1499-1 assume !(1 == ~E_M~0); 64821#L1504-1 assume !(1 == ~E_1~0); 64822#L1509-1 assume !(1 == ~E_2~0); 65424#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 65117#L1519-1 assume !(1 == ~E_4~0); 65118#L1524-1 assume !(1 == ~E_5~0); 65609#L1529-1 assume !(1 == ~E_6~0); 65610#L1534-1 assume !(1 == ~E_7~0); 63787#L1539-1 assume !(1 == ~E_8~0); 63788#L1544-1 assume !(1 == ~E_9~0); 64212#L1549-1 assume !(1 == ~E_10~0); 65588#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 65586#L1559-1 assume !(1 == ~E_12~0); 65453#L1564-1 assume !(1 == ~E_13~0); 64392#L1935-1 [2021-11-07 07:29:55,529 INFO L793 eck$LassoCheckResult]: Loop: 64392#L1935-1 assume !false; 63796#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 63797#L1261 assume !false; 65006#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 65007#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 63927#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 64092#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 64093#L1074 assume !(0 != eval_~tmp~0); 64452#L1276 start_simulation_~kernel_st~0 := 2; 65034#L902-1 start_simulation_~kernel_st~0 := 3; 65428#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 64502#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 64503#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 65208#L1296-3 assume !(0 == ~T3_E~0); 65636#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 65594#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 64719#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 64028#L1316-3 assume !(0 == ~T7_E~0); 64029#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 64133#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 64858#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 65120#L1336-3 assume !(0 == ~T11_E~0); 65121#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 64430#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 64421#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 64364#L1356-3 assume !(0 == ~E_1~0); 64365#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 64934#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 63722#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 63723#L1376-3 assume !(0 == ~E_5~0); 65439#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 65291#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 65292#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 65470#L1396-3 assume !(0 == ~E_9~0); 65471#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 64097#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 63933#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 63934#L1416-3 assume !(0 == ~E_13~0); 64552#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 63811#L635-45 assume !(1 == ~m_pc~0); 63812#L635-47 is_master_triggered_~__retres1~0 := 0; 64592#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 65067#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 65317#L1598-45 assume !(0 != activate_threads_~tmp~1); 64115#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 64116#L654-45 assume 1 == ~t1_pc~0; 64925#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 65266#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 63774#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 63775#L1606-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 63800#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 64613#L673-45 assume !(1 == ~t2_pc~0); 64614#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 64937#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 64938#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 65550#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 65374#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 64241#L692-45 assume !(1 == ~t3_pc~0); 63969#L692-47 is_transmit3_triggered_~__retres1~3 := 0; 63970#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 64998#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 64295#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 64296#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 64598#L711-45 assume 1 == ~t4_pc~0; 64723#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 64725#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 64577#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 64578#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 64978#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 64139#L730-45 assume !(1 == ~t5_pc~0); 63981#L730-47 is_transmit5_triggered_~__retres1~5 := 0; 65218#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 64388#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 64389#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 65126#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 63954#L749-45 assume !(1 == ~t6_pc~0); 63955#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 65332#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 65100#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 65101#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 65249#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 64267#L768-45 assume 1 == ~t7_pc~0; 64268#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 64408#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 65195#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 65196#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 65234#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 65235#L787-45 assume 1 == ~t8_pc~0; 65399#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 64414#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 64415#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 64819#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 64820#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 65125#L806-45 assume 1 == ~t9_pc~0; 65589#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 63831#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 64642#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 64479#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 64393#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 64394#L825-45 assume 1 == ~t10_pc~0; 64992#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 64906#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 65008#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 65009#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 65158#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 64036#L844-45 assume !(1 == ~t11_pc~0); 64037#L844-47 is_transmit11_triggered_~__retres1~11 := 0; 64553#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 64554#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 64567#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 64975#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 64076#L863-45 assume 1 == ~t12_pc~0; 64077#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 63680#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 63681#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 64191#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 64192#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 64981#L882-45 assume !(1 == ~t13_pc~0); 64520#L882-47 is_transmit13_triggered_~__retres1~13 := 0; 63699#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 63700#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 64304#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 65461#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 65084#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 65085#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63990#L1444-3 assume !(1 == ~T3_E~0); 63991#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 64151#L1454-3 assume !(1 == ~T5_E~0); 65074#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 65075#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 65512#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 65441#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 65442#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 65514#L1484-3 assume !(1 == ~T11_E~0); 64721#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 64722#L1494-3 assume !(1 == ~T13_E~0); 65371#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 65012#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 65013#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 65450#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 65488#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 64643#L1524-3 assume !(1 == ~E_5~0); 64644#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 65534#L1534-3 assume !(1 == ~E_7~0); 64943#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 64409#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 64410#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 64913#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 64041#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 64042#L1564-3 assume !(1 == ~E_13~0); 65173#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 65174#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 63929#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 64490#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 65146#L1954 assume !(0 == start_simulation_~tmp~3); 65112#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 65113#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 64206#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 65232#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 65359#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 65360#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 65448#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 65508#L1967 assume !(0 != start_simulation_~tmp___0~1); 64392#L1935-1 [2021-11-07 07:29:55,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:55,530 INFO L85 PathProgramCache]: Analyzing trace with hash 26114798, now seen corresponding path program 1 times [2021-11-07 07:29:55,530 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:55,530 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [906549944] [2021-11-07 07:29:55,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:55,531 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:55,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:55,578 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:55,578 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:55,578 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [906549944] [2021-11-07 07:29:55,579 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [906549944] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:55,579 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:55,579 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 07:29:55,579 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1507941559] [2021-11-07 07:29:55,580 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:29:55,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:55,580 INFO L85 PathProgramCache]: Analyzing trace with hash 903531977, now seen corresponding path program 1 times [2021-11-07 07:29:55,580 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:55,581 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [284850650] [2021-11-07 07:29:55,581 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:55,581 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:55,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:55,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:55,636 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:55,636 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [284850650] [2021-11-07 07:29:55,636 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [284850650] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:55,637 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:55,637 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:55,637 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2053843982] [2021-11-07 07:29:55,637 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:29:55,638 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:29:55,638 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:29:55,638 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:29:55,639 INFO L87 Difference]: Start difference. First operand 1986 states and 2893 transitions. cyclomatic complexity: 908 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:55,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:29:55,808 INFO L93 Difference]: Finished difference Result 3779 states and 5465 transitions. [2021-11-07 07:29:55,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:29:55,809 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3779 states and 5465 transitions. [2021-11-07 07:29:55,833 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3608 [2021-11-07 07:29:55,852 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3779 states to 3779 states and 5465 transitions. [2021-11-07 07:29:55,852 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3779 [2021-11-07 07:29:55,857 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3779 [2021-11-07 07:29:55,858 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3779 states and 5465 transitions. [2021-11-07 07:29:55,864 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:29:55,864 INFO L681 BuchiCegarLoop]: Abstraction has 3779 states and 5465 transitions. [2021-11-07 07:29:55,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3779 states and 5465 transitions. [2021-11-07 07:29:55,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3779 to 3683. [2021-11-07 07:29:55,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3683 states, 3683 states have (on average 1.4474613087157209) internal successors, (5331), 3682 states have internal predecessors, (5331), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:55,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3683 states to 3683 states and 5331 transitions. [2021-11-07 07:29:55,949 INFO L704 BuchiCegarLoop]: Abstraction has 3683 states and 5331 transitions. [2021-11-07 07:29:55,949 INFO L587 BuchiCegarLoop]: Abstraction has 3683 states and 5331 transitions. [2021-11-07 07:29:55,949 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-07 07:29:55,950 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3683 states and 5331 transitions. [2021-11-07 07:29:55,967 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3512 [2021-11-07 07:29:55,967 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:29:55,968 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:29:55,973 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:55,973 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:55,974 INFO L791 eck$LassoCheckResult]: Stem: 70318#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 70319#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 70053#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 70054#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 69995#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69996#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 70241#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 70278#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 71113#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 71114#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 71234#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 71235#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 70059#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 70060#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 71272#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 70578#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 70579#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 71172#L974-1 assume !(0 == ~M_E~0); 70889#L1286-1 assume !(0 == ~T1_E~0); 69967#L1291-1 assume !(0 == ~T2_E~0); 69968#L1296-1 assume !(0 == ~T3_E~0); 70668#L1301-1 assume !(0 == ~T4_E~0); 70669#L1306-1 assume !(0 == ~T5_E~0); 71182#L1311-1 assume !(0 == ~T6_E~0); 69927#L1316-1 assume !(0 == ~T7_E~0); 69928#L1321-1 assume !(0 == ~T8_E~0); 70688#L1326-1 assume !(0 == ~T9_E~0); 69746#L1331-1 assume !(0 == ~T10_E~0); 69454#L1336-1 assume !(0 == ~T11_E~0); 69455#L1341-1 assume !(0 == ~T12_E~0); 69506#L1346-1 assume !(0 == ~T13_E~0); 69507#L1351-1 assume !(0 == ~E_M~0); 69874#L1356-1 assume !(0 == ~E_1~0); 69875#L1361-1 assume !(0 == ~E_2~0); 71415#L1366-1 assume !(0 == ~E_3~0); 69920#L1371-1 assume !(0 == ~E_4~0); 69921#L1376-1 assume !(0 == ~E_5~0); 70729#L1381-1 assume !(0 == ~E_6~0); 70730#L1386-1 assume !(0 == ~E_7~0); 71447#L1391-1 assume !(0 == ~E_8~0); 71461#L1396-1 assume !(0 == ~E_9~0); 70611#L1401-1 assume !(0 == ~E_10~0); 70612#L1406-1 assume !(0 == ~E_11~0); 70922#L1411-1 assume !(0 == ~E_12~0); 70923#L1416-1 assume !(0 == ~E_13~0); 70537#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 70375#L635 assume !(1 == ~m_pc~0); 69524#L635-2 is_master_triggered_~__retres1~0 := 0; 69525#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 69869#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 70500#L1598 assume !(0 != activate_threads_~tmp~1); 69703#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 69704#L654 assume !(1 == ~t1_pc~0); 70400#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 70399#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 71443#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 70480#L1606 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 70481#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 69749#L673 assume 1 == ~t2_pc~0; 69750#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 70887#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 70888#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 71472#L1614 assume !(0 != activate_threads_~tmp___1~0); 71480#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 70561#L692 assume !(1 == ~t3_pc~0); 70376#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 70377#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 70242#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 70212#L1622 assume !(0 != activate_threads_~tmp___2~0); 70213#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 69773#L711 assume 1 == ~t4_pc~0; 69774#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 70255#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 70705#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 69479#L1630 assume !(0 != activate_threads_~tmp___3~0); 69480#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 71468#L730 assume !(1 == ~t5_pc~0); 70821#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 69659#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 69660#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 69783#L1638 assume !(0 != activate_threads_~tmp___4~0); 69784#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 70125#L749 assume 1 == ~t6_pc~0; 69898#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 69664#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 70091#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 70092#L1646 assume !(0 != activate_threads_~tmp___5~0); 70310#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 69459#L768 assume 1 == ~t7_pc~0; 69460#L769 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 70757#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 69696#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 69697#L1654 assume !(0 != activate_threads_~tmp___6~0); 70775#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 69929#L787 assume !(1 == ~t8_pc~0); 69930#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 71127#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 71299#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 71300#L1662 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 69504#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 69505#L806 assume 1 == ~t9_pc~0; 71138#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 69539#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 69540#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 69785#L1670 assume !(0 != activate_threads_~tmp___8~0); 69786#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 71121#L825 assume !(1 == ~t10_pc~0); 71122#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 70720#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 70721#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 69870#L1678 assume !(0 != activate_threads_~tmp___9~0); 69871#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 70449#L844 assume 1 == ~t11_pc~0; 70146#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 70147#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 70507#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 70508#L1686 assume !(0 != activate_threads_~tmp___10~0); 71110#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 71111#L863 assume !(1 == ~t12_pc~0); 69639#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 69640#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 69860#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 71207#L1694 assume !(0 != activate_threads_~tmp___11~0); 71208#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 70575#L882 assume !(1 == ~t13_pc~0); 70577#L882-2 is_transmit13_triggered_~__retres1~13 := 0; 70859#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 71383#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 71175#L1702 assume !(0 != activate_threads_~tmp___12~0); 70846#L1702-2 assume !(1 == ~M_E~0); 70847#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 71323#L1439-1 assume !(1 == ~T2_E~0); 69766#L1444-1 assume !(1 == ~T3_E~0); 69767#L1449-1 assume !(1 == ~T4_E~0); 70208#L1454-1 assume !(1 == ~T5_E~0); 70209#L1459-1 assume !(1 == ~T6_E~0); 70776#L1464-1 assume !(1 == ~T7_E~0); 70777#L1469-1 assume !(1 == ~T8_E~0); 70860#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 70538#L1479-1 assume !(1 == ~T10_E~0); 70539#L1484-1 assume !(1 == ~T11_E~0); 70783#L1489-1 assume !(1 == ~T12_E~0); 70415#L1494-1 assume !(1 == ~T13_E~0); 70416#L1499-1 assume !(1 == ~E_M~0); 70596#L1504-1 assume !(1 == ~E_1~0); 70597#L1509-1 assume !(1 == ~E_2~0); 71226#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 70900#L1519-1 assume !(1 == ~E_4~0); 70901#L1524-1 assume !(1 == ~E_5~0); 71428#L1529-1 assume !(1 == ~E_6~0); 71429#L1534-1 assume !(1 == ~E_7~0); 69559#L1539-1 assume !(1 == ~E_8~0); 69560#L1544-1 assume !(1 == ~E_9~0); 69983#L1549-1 assume !(1 == ~E_10~0); 71403#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 71401#L1559-1 assume !(1 == ~E_12~0); 71256#L1564-1 assume !(1 == ~E_13~0); 70164#L1935-1 [2021-11-07 07:29:55,974 INFO L793 eck$LassoCheckResult]: Loop: 70164#L1935-1 assume !false; 69568#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 69569#L1261 assume !false; 70788#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 70789#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 69699#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 69863#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 69864#L1074 assume !(0 != eval_~tmp~0); 70224#L1276 start_simulation_~kernel_st~0 := 2; 70816#L902-1 start_simulation_~kernel_st~0 := 3; 71230#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 70274#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 70275#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 70996#L1296-3 assume !(0 == ~T3_E~0); 71458#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 71411#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 70493#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 69800#L1316-3 assume !(0 == ~T7_E~0); 69801#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 69904#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 70633#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 70903#L1336-3 assume !(0 == ~T11_E~0); 70904#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 70202#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 70193#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 70136#L1356-3 assume !(0 == ~E_1~0); 70137#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 70710#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69494#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 69495#L1376-3 assume !(0 == ~E_5~0); 71241#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 71082#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 71083#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 71273#L1396-3 assume !(0 == ~E_9~0); 71274#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 69868#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 69705#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 69706#L1416-3 assume !(0 == ~E_13~0); 70324#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 69582#L635-45 assume !(1 == ~m_pc~0); 69583#L635-47 is_master_triggered_~__retres1~0 := 0; 70750#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 70848#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 71109#L1598-45 assume !(0 != activate_threads_~tmp~1); 69886#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 69887#L654-45 assume 1 == ~t1_pc~0; 70701#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 71056#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 69546#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 69547#L1606-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 69572#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 70388#L673-45 assume !(1 == ~t2_pc~0); 70389#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 70713#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 70714#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 71362#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 71171#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 70012#L692-45 assume 1 == ~t3_pc~0; 70013#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 69742#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 70779#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 70066#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 70067#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 70374#L711-45 assume 1 == ~t4_pc~0; 70497#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 70499#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 70349#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 70350#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 70758#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 69910#L730-45 assume !(1 == ~t5_pc~0); 69753#L730-47 is_transmit5_triggered_~__retres1~5 := 0; 71006#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 70160#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 70161#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 70909#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 69726#L749-45 assume 1 == ~t6_pc~0; 69728#L750-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 71124#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 70882#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 70883#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 71037#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 70038#L768-45 assume 1 == ~t7_pc~0; 70039#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 70180#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 70983#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 70984#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 71022#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 71023#L787-45 assume !(1 == ~t8_pc~0); 71199#L787-47 is_transmit8_triggered_~__retres1~8 := 0; 70186#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 70187#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 70594#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 70595#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 70908#L806-45 assume !(1 == ~t9_pc~0); 69603#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 69604#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 70417#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 70251#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 70165#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 70166#L825-45 assume 1 == ~t10_pc~0; 70773#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 70682#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 70790#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 70791#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 70945#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 69808#L844-45 assume !(1 == ~t11_pc~0); 69809#L844-47 is_transmit11_triggered_~__retres1~11 := 0; 70325#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 70326#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 70339#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 70755#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 69848#L863-45 assume 1 == ~t12_pc~0; 69849#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 69452#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 69453#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 69962#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 69963#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 70761#L882-45 assume !(1 == ~t13_pc~0); 70292#L882-47 is_transmit13_triggered_~__retres1~13 := 0; 69471#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 69472#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 70076#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 71264#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 70865#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 70866#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69762#L1444-3 assume !(1 == ~T3_E~0); 69763#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69922#L1454-3 assume !(1 == ~T5_E~0); 70855#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 70856#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 71319#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 71243#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 71244#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 71321#L1484-3 assume !(1 == ~T11_E~0); 70495#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 70496#L1494-3 assume !(1 == ~T13_E~0); 71168#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 70794#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 70795#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 71253#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 71292#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 70418#L1524-3 assume !(1 == ~E_5~0); 70419#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 71346#L1534-3 assume !(1 == ~E_7~0); 70719#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 70181#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 70182#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 70689#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 69813#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 69814#L1564-3 assume !(1 == ~E_13~0); 70959#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 70960#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 69701#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 70262#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 70933#L1954 assume !(0 == start_simulation_~tmp~3); 70894#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 70895#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 69977#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 71020#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 71156#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 71157#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 71251#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 71315#L1967 assume !(0 != start_simulation_~tmp___0~1); 70164#L1935-1 [2021-11-07 07:29:55,975 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:55,975 INFO L85 PathProgramCache]: Analyzing trace with hash 751194223, now seen corresponding path program 1 times [2021-11-07 07:29:55,976 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:55,976 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [401817999] [2021-11-07 07:29:55,977 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:55,977 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:55,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:56,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:56,040 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:56,041 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [401817999] [2021-11-07 07:29:56,041 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [401817999] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:56,041 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:56,041 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-07 07:29:56,041 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1642761400] [2021-11-07 07:29:56,042 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:29:56,043 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:56,043 INFO L85 PathProgramCache]: Analyzing trace with hash 365889481, now seen corresponding path program 1 times [2021-11-07 07:29:56,043 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:56,043 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [22840142] [2021-11-07 07:29:56,044 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:56,044 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:56,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:56,094 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:56,094 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:56,094 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [22840142] [2021-11-07 07:29:56,095 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [22840142] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:56,095 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:56,095 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:56,096 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [179624138] [2021-11-07 07:29:56,096 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:29:56,097 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:29:56,097 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-07 07:29:56,098 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-07 07:29:56,098 INFO L87 Difference]: Start difference. First operand 3683 states and 5331 transitions. cyclomatic complexity: 1650 Second operand has 5 states, 5 states have (on average 31.4) internal successors, (157), 5 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:56,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:29:56,692 INFO L93 Difference]: Finished difference Result 10454 states and 15089 transitions. [2021-11-07 07:29:56,693 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-07 07:29:56,693 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10454 states and 15089 transitions. [2021-11-07 07:29:56,757 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10054 [2021-11-07 07:29:56,914 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10454 states to 10454 states and 15089 transitions. [2021-11-07 07:29:56,915 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10454 [2021-11-07 07:29:56,925 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10454 [2021-11-07 07:29:56,926 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10454 states and 15089 transitions. [2021-11-07 07:29:56,940 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:29:56,940 INFO L681 BuchiCegarLoop]: Abstraction has 10454 states and 15089 transitions. [2021-11-07 07:29:56,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10454 states and 15089 transitions. [2021-11-07 07:29:57,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10454 to 3779. [2021-11-07 07:29:57,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3779 states, 3779 states have (on average 1.436094204816089) internal successors, (5427), 3778 states have internal predecessors, (5427), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:57,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3779 states to 3779 states and 5427 transitions. [2021-11-07 07:29:57,048 INFO L704 BuchiCegarLoop]: Abstraction has 3779 states and 5427 transitions. [2021-11-07 07:29:57,048 INFO L587 BuchiCegarLoop]: Abstraction has 3779 states and 5427 transitions. [2021-11-07 07:29:57,048 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-07 07:29:57,048 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3779 states and 5427 transitions. [2021-11-07 07:29:57,066 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3605 [2021-11-07 07:29:57,066 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:29:57,066 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:29:57,069 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:57,069 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:57,070 INFO L791 eck$LassoCheckResult]: Stem: 84469#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 84470#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 84203#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 84204#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 84145#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 84146#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 84392#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 84429#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 85284#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 85285#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 85411#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 85412#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 84209#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 84210#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 85450#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 84730#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 84731#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 85346#L974-1 assume !(0 == ~M_E~0); 85047#L1286-1 assume !(0 == ~T1_E~0); 84117#L1291-1 assume !(0 == ~T2_E~0); 84118#L1296-1 assume !(0 == ~T3_E~0); 84825#L1301-1 assume !(0 == ~T4_E~0); 84826#L1306-1 assume !(0 == ~T5_E~0); 85356#L1311-1 assume !(0 == ~T6_E~0); 84076#L1316-1 assume !(0 == ~T7_E~0); 84077#L1321-1 assume !(0 == ~T8_E~0); 84845#L1326-1 assume !(0 == ~T9_E~0); 83895#L1331-1 assume !(0 == ~T10_E~0); 83604#L1336-1 assume !(0 == ~T11_E~0); 83605#L1341-1 assume !(0 == ~T12_E~0); 83656#L1346-1 assume !(0 == ~T13_E~0); 83657#L1351-1 assume !(0 == ~E_M~0); 84023#L1356-1 assume !(0 == ~E_1~0); 84024#L1361-1 assume !(0 == ~E_2~0); 85610#L1366-1 assume !(0 == ~E_3~0); 84069#L1371-1 assume !(0 == ~E_4~0); 84070#L1376-1 assume !(0 == ~E_5~0); 84888#L1381-1 assume !(0 == ~E_6~0); 84889#L1386-1 assume !(0 == ~E_7~0); 85643#L1391-1 assume !(0 == ~E_8~0); 85664#L1396-1 assume !(0 == ~E_9~0); 84764#L1401-1 assume !(0 == ~E_10~0); 84765#L1406-1 assume !(0 == ~E_11~0); 85081#L1411-1 assume !(0 == ~E_12~0); 85082#L1416-1 assume !(0 == ~E_13~0); 84688#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 84524#L635 assume !(1 == ~m_pc~0); 83674#L635-2 is_master_triggered_~__retres1~0 := 0; 83675#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 84020#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 84651#L1598 assume !(0 != activate_threads_~tmp~1); 83852#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 83853#L654 assume !(1 == ~t1_pc~0); 84549#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 85451#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 85640#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 84631#L1606 assume !(0 != activate_threads_~tmp___0~0); 84632#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 83900#L673 assume 1 == ~t2_pc~0; 83901#L674 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 85045#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 85046#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 85684#L1614 assume !(0 != activate_threads_~tmp___1~0); 85694#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 84713#L692 assume !(1 == ~t3_pc~0); 84525#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 84526#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 84393#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 84363#L1622 assume !(0 != activate_threads_~tmp___2~0); 84364#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 83922#L711 assume 1 == ~t4_pc~0; 83923#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 84406#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 84863#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 83629#L1630 assume !(0 != activate_threads_~tmp___3~0); 83630#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 85674#L730 assume !(1 == ~t5_pc~0); 84980#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 83808#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 83809#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 83932#L1638 assume !(0 != activate_threads_~tmp___4~0); 83933#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 84275#L749 assume 1 == ~t6_pc~0; 84047#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 83813#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 84241#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 84242#L1646 assume !(0 != activate_threads_~tmp___5~0); 84461#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 83609#L768 assume 1 == ~t7_pc~0; 83610#L769 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 84915#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 83845#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 83846#L1654 assume !(0 != activate_threads_~tmp___6~0); 84934#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 84078#L787 assume !(1 == ~t8_pc~0); 84079#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 85299#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 85479#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 85480#L1662 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 83654#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 83655#L806 assume 1 == ~t9_pc~0; 85312#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 83689#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 83690#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 83934#L1670 assume !(0 != activate_threads_~tmp___8~0); 83935#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 85292#L825 assume !(1 == ~t10_pc~0); 85293#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 84878#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 84879#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 84021#L1678 assume !(0 != activate_threads_~tmp___9~0); 84022#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 84598#L844 assume 1 == ~t11_pc~0; 84296#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 84297#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 84658#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 84659#L1686 assume !(0 != activate_threads_~tmp___10~0); 85281#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 85282#L863 assume !(1 == ~t12_pc~0); 83787#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 83788#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 84009#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 85384#L1694 assume !(0 != activate_threads_~tmp___11~0); 85385#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 84727#L882 assume !(1 == ~t13_pc~0); 84729#L882-2 is_transmit13_triggered_~__retres1~13 := 0; 85018#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 85567#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 85349#L1702 assume !(0 != activate_threads_~tmp___12~0); 85005#L1702-2 assume !(1 == ~M_E~0); 85006#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 85504#L1439-1 assume !(1 == ~T2_E~0); 83915#L1444-1 assume !(1 == ~T3_E~0); 83916#L1449-1 assume !(1 == ~T4_E~0); 84359#L1454-1 assume !(1 == ~T5_E~0); 84360#L1459-1 assume !(1 == ~T6_E~0); 84935#L1464-1 assume !(1 == ~T7_E~0); 84936#L1469-1 assume !(1 == ~T8_E~0); 85019#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 84689#L1479-1 assume !(1 == ~T10_E~0); 84690#L1484-1 assume !(1 == ~T11_E~0); 84942#L1489-1 assume !(1 == ~T12_E~0); 84564#L1494-1 assume !(1 == ~T13_E~0); 84565#L1499-1 assume !(1 == ~E_M~0); 84749#L1504-1 assume !(1 == ~E_1~0); 84750#L1509-1 assume !(1 == ~E_2~0); 85402#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 85058#L1519-1 assume !(1 == ~E_4~0); 85059#L1524-1 assume !(1 == ~E_5~0); 85622#L1529-1 assume !(1 == ~E_6~0); 85623#L1534-1 assume !(1 == ~E_7~0); 83709#L1539-1 assume !(1 == ~E_8~0); 83710#L1544-1 assume !(1 == ~E_9~0); 84133#L1549-1 assume !(1 == ~E_10~0); 85593#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 85590#L1559-1 assume !(1 == ~E_12~0); 85434#L1564-1 assume !(1 == ~E_13~0); 84314#L1935-1 [2021-11-07 07:29:57,071 INFO L793 eck$LassoCheckResult]: Loop: 84314#L1935-1 assume !false; 83718#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 83719#L1261 assume !false; 84949#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 84950#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 83848#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 84012#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 84013#L1074 assume !(0 != eval_~tmp~0); 84375#L1276 start_simulation_~kernel_st~0 := 2; 84975#L902-1 start_simulation_~kernel_st~0 := 3; 85407#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 84425#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 84426#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 85161#L1296-3 assume !(0 == ~T3_E~0); 85661#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 85606#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 84644#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 83949#L1316-3 assume !(0 == ~T7_E~0); 83950#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 84053#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 84786#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 85062#L1336-3 assume !(0 == ~T11_E~0); 85063#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 84353#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 84344#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 84286#L1356-3 assume !(0 == ~E_1~0); 84287#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 84868#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 83646#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 83647#L1376-3 assume !(0 == ~E_5~0); 85420#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 85576#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 87303#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 85452#L1396-3 assume !(0 == ~E_9~0); 85453#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 84017#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 83854#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 83855#L1416-3 assume !(0 == ~E_13~0); 84475#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 83732#L635-45 assume !(1 == ~m_pc~0); 83733#L635-47 is_master_triggered_~__retres1~0 := 0; 84911#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 85007#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 85280#L1598-45 assume !(0 != activate_threads_~tmp~1); 84035#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 84036#L654-45 assume 1 == ~t1_pc~0; 85651#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 85221#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 85222#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 87171#L1606-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 83722#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 84537#L673-45 assume 1 == ~t2_pc~0; 84539#L674-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 84871#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 84872#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 85543#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 85345#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 84162#L692-45 assume 1 == ~t3_pc~0; 84163#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 83894#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 84938#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 84217#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 84218#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 84523#L711-45 assume !(1 == ~t4_pc~0); 84649#L711-47 is_transmit4_triggered_~__retres1~4 := 0; 84650#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 84501#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 84502#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 84917#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 84059#L730-45 assume !(1 == ~t5_pc~0); 83899#L730-47 is_transmit5_triggered_~__retres1~5 := 0; 85170#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 84310#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 84311#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 85067#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 83872#L749-45 assume !(1 == ~t6_pc~0); 83873#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 85295#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 85038#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 85039#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 85202#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 84185#L768-45 assume !(1 == ~t7_pc~0); 84187#L768-47 is_transmit7_triggered_~__retres1~7 := 0; 84330#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 85147#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 85148#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 85186#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 85187#L787-45 assume !(1 == ~t8_pc~0); 85373#L787-47 is_transmit8_triggered_~__retres1~8 := 0; 84336#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 84337#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 84746#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 84747#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 85066#L806-45 assume !(1 == ~t9_pc~0); 83751#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 83752#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 84566#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 84402#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 84315#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 84316#L825-45 assume 1 == ~t10_pc~0; 84933#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 84839#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 84947#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 84948#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 85104#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 83956#L844-45 assume !(1 == ~t11_pc~0); 83957#L844-47 is_transmit11_triggered_~__retres1~11 := 0; 84476#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 84477#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 84490#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 84912#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 83997#L863-45 assume !(1 == ~t12_pc~0); 83999#L863-47 is_transmit12_triggered_~__retres1~12 := 0; 83602#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 83603#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 84109#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 84110#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 84918#L882-45 assume !(1 == ~t13_pc~0); 84443#L882-47 is_transmit13_triggered_~__retres1~13 := 0; 83621#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 83622#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 84226#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 85442#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 85024#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 85025#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 83911#L1444-3 assume !(1 == ~T3_E~0); 83912#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 84071#L1454-3 assume !(1 == ~T5_E~0); 85014#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 85015#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 85501#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 85422#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 85423#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 85503#L1484-3 assume !(1 == ~T11_E~0); 84646#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 84647#L1494-3 assume !(1 == ~T13_E~0); 85342#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 84951#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 84952#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 85431#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 85472#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 84567#L1524-3 assume !(1 == ~E_5~0); 84568#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 85527#L1534-3 assume !(1 == ~E_7~0); 84874#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 84331#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 84332#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 84846#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 83962#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 83963#L1564-3 assume !(1 == ~E_13~0); 85118#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 85119#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 83850#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 84413#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 85092#L1954 assume !(0 == start_simulation_~tmp~3); 85053#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 85054#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 84127#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 85184#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 85329#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 85330#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 85429#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 85495#L1967 assume !(0 != start_simulation_~tmp___0~1); 84314#L1935-1 [2021-11-07 07:29:57,071 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:57,072 INFO L85 PathProgramCache]: Analyzing trace with hash -555948175, now seen corresponding path program 1 times [2021-11-07 07:29:57,072 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:57,072 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [216270491] [2021-11-07 07:29:57,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:57,073 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:57,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:57,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:57,129 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:57,129 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [216270491] [2021-11-07 07:29:57,130 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [216270491] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:57,130 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:57,130 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:57,130 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [978506864] [2021-11-07 07:29:57,132 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:29:57,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:57,132 INFO L85 PathProgramCache]: Analyzing trace with hash 1170971622, now seen corresponding path program 1 times [2021-11-07 07:29:57,133 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:57,133 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1789870382] [2021-11-07 07:29:57,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:57,133 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:57,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:57,194 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:57,194 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:57,194 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1789870382] [2021-11-07 07:29:57,195 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1789870382] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:57,195 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:57,195 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:57,195 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [219852517] [2021-11-07 07:29:57,197 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:29:57,197 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:29:57,198 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-07 07:29:57,198 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-07 07:29:57,198 INFO L87 Difference]: Start difference. First operand 3779 states and 5427 transitions. cyclomatic complexity: 1650 Second operand has 4 states, 4 states have (on average 39.25) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:57,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:29:57,588 INFO L93 Difference]: Finished difference Result 9042 states and 12886 transitions. [2021-11-07 07:29:57,588 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 07:29:57,589 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9042 states and 12886 transitions. [2021-11-07 07:29:57,645 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 8762 [2021-11-07 07:29:57,687 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9042 states to 9042 states and 12886 transitions. [2021-11-07 07:29:57,688 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9042 [2021-11-07 07:29:57,699 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9042 [2021-11-07 07:29:57,699 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9042 states and 12886 transitions. [2021-11-07 07:29:57,709 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:29:57,709 INFO L681 BuchiCegarLoop]: Abstraction has 9042 states and 12886 transitions. [2021-11-07 07:29:57,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9042 states and 12886 transitions. [2021-11-07 07:29:57,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9042 to 7148. [2021-11-07 07:29:57,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7148 states, 7148 states have (on average 1.4292109681029659) internal successors, (10216), 7147 states have internal predecessors, (10216), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:57,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7148 states to 7148 states and 10216 transitions. [2021-11-07 07:29:57,863 INFO L704 BuchiCegarLoop]: Abstraction has 7148 states and 10216 transitions. [2021-11-07 07:29:57,863 INFO L587 BuchiCegarLoop]: Abstraction has 7148 states and 10216 transitions. [2021-11-07 07:29:57,863 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-07 07:29:57,863 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7148 states and 10216 transitions. [2021-11-07 07:29:57,897 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6974 [2021-11-07 07:29:57,901 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:29:57,901 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:29:57,905 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:57,905 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:57,906 INFO L791 eck$LassoCheckResult]: Stem: 97299#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 97300#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 97031#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 97032#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 96973#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96974#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 97223#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 97260#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 98115#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 98116#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 98233#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 98234#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 97037#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 97038#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 98275#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 97557#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 97558#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 98172#L974-1 assume !(0 == ~M_E~0); 97880#L1286-1 assume !(0 == ~T1_E~0); 96945#L1291-1 assume !(0 == ~T2_E~0); 96946#L1296-1 assume !(0 == ~T3_E~0); 97653#L1301-1 assume !(0 == ~T4_E~0); 97654#L1306-1 assume !(0 == ~T5_E~0); 98181#L1311-1 assume !(0 == ~T6_E~0); 96903#L1316-1 assume !(0 == ~T7_E~0); 96904#L1321-1 assume !(0 == ~T8_E~0); 97673#L1326-1 assume !(0 == ~T9_E~0); 96724#L1331-1 assume !(0 == ~T10_E~0); 96435#L1336-1 assume !(0 == ~T11_E~0); 96436#L1341-1 assume !(0 == ~T12_E~0); 96486#L1346-1 assume !(0 == ~T13_E~0); 96487#L1351-1 assume !(0 == ~E_M~0); 96850#L1356-1 assume !(0 == ~E_1~0); 96851#L1361-1 assume !(0 == ~E_2~0); 98434#L1366-1 assume !(0 == ~E_3~0); 96896#L1371-1 assume !(0 == ~E_4~0); 96897#L1376-1 assume !(0 == ~E_5~0); 97716#L1381-1 assume !(0 == ~E_6~0); 97717#L1386-1 assume !(0 == ~E_7~0); 98467#L1391-1 assume !(0 == ~E_8~0); 98484#L1396-1 assume !(0 == ~E_9~0); 97591#L1401-1 assume !(0 == ~E_10~0); 97592#L1406-1 assume !(0 == ~E_11~0); 97913#L1411-1 assume !(0 == ~E_12~0); 97914#L1416-1 assume !(0 == ~E_13~0); 97515#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 97353#L635 assume !(1 == ~m_pc~0); 96504#L635-2 is_master_triggered_~__retres1~0 := 0; 96505#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 96845#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 97478#L1598 assume !(0 != activate_threads_~tmp~1); 96681#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 96682#L654 assume !(1 == ~t1_pc~0); 97376#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 98277#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 98464#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 97456#L1606 assume !(0 != activate_threads_~tmp___0~0); 97457#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 96727#L673 assume !(1 == ~t2_pc~0); 96728#L673-2 is_transmit2_triggered_~__retres1~2 := 0; 97878#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 97879#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 98497#L1614 assume !(0 != activate_threads_~tmp___1~0); 98504#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 97539#L692 assume !(1 == ~t3_pc~0); 97354#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 97355#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 97224#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 97194#L1622 assume !(0 != activate_threads_~tmp___2~0); 97195#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 96750#L711 assume 1 == ~t4_pc~0; 96751#L712 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 97237#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 97691#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 96459#L1630 assume !(0 != activate_threads_~tmp___3~0); 96460#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 98493#L730 assume !(1 == ~t5_pc~0); 97808#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 96637#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 96638#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 96760#L1638 assume !(0 != activate_threads_~tmp___4~0); 96761#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 97105#L749 assume 1 == ~t6_pc~0; 96874#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 96642#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 97071#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 97072#L1646 assume !(0 != activate_threads_~tmp___5~0); 97291#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 96440#L768 assume 1 == ~t7_pc~0; 96441#L769 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 97743#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 96674#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 96675#L1654 assume !(0 != activate_threads_~tmp___6~0); 97761#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 96905#L787 assume !(1 == ~t8_pc~0); 96906#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 98129#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 98309#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 98310#L1662 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 96484#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 96485#L806 assume 1 == ~t9_pc~0; 98140#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 96519#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 96520#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 96762#L1670 assume !(0 != activate_threads_~tmp___8~0); 96763#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 98123#L825 assume !(1 == ~t10_pc~0); 98124#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 97706#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 97707#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 96846#L1678 assume !(0 != activate_threads_~tmp___9~0); 96847#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 97425#L844 assume 1 == ~t11_pc~0; 97126#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 97127#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 97485#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 97486#L1686 assume !(0 != activate_threads_~tmp___10~0); 98112#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 98113#L863 assume !(1 == ~t12_pc~0); 96617#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 96618#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 96836#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 98208#L1694 assume !(0 != activate_threads_~tmp___11~0); 98209#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 97554#L882 assume !(1 == ~t13_pc~0); 97556#L882-2 is_transmit13_triggered_~__retres1~13 := 0; 97847#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 98398#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 98174#L1702 assume !(0 != activate_threads_~tmp___12~0); 97834#L1702-2 assume !(1 == ~M_E~0); 97835#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 98335#L1439-1 assume !(1 == ~T2_E~0); 96743#L1444-1 assume !(1 == ~T3_E~0); 96744#L1449-1 assume !(1 == ~T4_E~0); 97190#L1454-1 assume !(1 == ~T5_E~0); 97191#L1459-1 assume !(1 == ~T6_E~0); 97762#L1464-1 assume !(1 == ~T7_E~0); 97763#L1469-1 assume !(1 == ~T8_E~0); 97848#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 97516#L1479-1 assume !(1 == ~T10_E~0); 97517#L1484-1 assume !(1 == ~T11_E~0); 97769#L1489-1 assume !(1 == ~T12_E~0); 97391#L1494-1 assume !(1 == ~T13_E~0); 97392#L1499-1 assume !(1 == ~E_M~0); 97576#L1504-1 assume !(1 == ~E_1~0); 97577#L1509-1 assume !(1 == ~E_2~0); 98224#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 97891#L1519-1 assume !(1 == ~E_4~0); 97892#L1524-1 assume !(1 == ~E_5~0); 98449#L1529-1 assume !(1 == ~E_6~0); 98450#L1534-1 assume !(1 == ~E_7~0); 96539#L1539-1 assume !(1 == ~E_8~0); 96540#L1544-1 assume !(1 == ~E_9~0); 96961#L1549-1 assume !(1 == ~E_10~0); 98422#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 98420#L1559-1 assume !(1 == ~E_12~0); 98259#L1564-1 assume !(1 == ~E_13~0); 97144#L1935-1 [2021-11-07 07:29:57,906 INFO L793 eck$LassoCheckResult]: Loop: 97144#L1935-1 assume !false; 96548#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 96549#L1261 assume !false; 97774#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 97775#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 96677#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 96839#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 96840#L1074 assume !(0 != eval_~tmp~0); 97206#L1276 start_simulation_~kernel_st~0 := 2; 103304#L902-1 start_simulation_~kernel_st~0 := 3; 103303#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 103302#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 103301#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 103300#L1296-3 assume !(0 == ~T3_E~0); 103299#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 103298#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 103297#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 103296#L1316-3 assume !(0 == ~T7_E~0); 103295#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 103294#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 98417#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 97894#L1336-3 assume !(0 == ~T11_E~0); 97895#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 97184#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 97175#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 97116#L1356-3 assume !(0 == ~E_1~0); 97117#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 97696#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 96474#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 96475#L1376-3 assume !(0 == ~E_5~0); 98241#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 98084#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 98085#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 98278#L1396-3 assume !(0 == ~E_9~0); 98279#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 96844#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 96683#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 96684#L1416-3 assume !(0 == ~E_13~0); 97305#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 96562#L635-45 assume !(1 == ~m_pc~0); 96563#L635-47 is_master_triggered_~__retres1~0 := 0; 97736#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 97836#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 98111#L1598-45 assume !(0 != activate_threads_~tmp~1); 96862#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 96863#L654-45 assume 1 == ~t1_pc~0; 97687#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 98474#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 103306#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 103305#L1606-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 96552#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 97366#L673-45 assume !(1 == ~t2_pc~0); 97367#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 97699#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 97700#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 98377#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 98171#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 96990#L692-45 assume 1 == ~t3_pc~0; 96991#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 96720#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 97765#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 97045#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 97046#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 97352#L711-45 assume 1 == ~t4_pc~0; 97475#L712-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 97477#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 97330#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 97331#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 97744#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 96886#L730-45 assume !(1 == ~t5_pc~0); 96730#L730-47 is_transmit5_triggered_~__retres1~5 := 0; 98004#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 97140#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 97141#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 97900#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 96704#L749-45 assume !(1 == ~t6_pc~0); 96705#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 98126#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 97873#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 97874#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 98038#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 97016#L768-45 assume 1 == ~t7_pc~0; 97017#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 97160#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 97980#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 97981#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 98022#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 98023#L787-45 assume !(1 == ~t8_pc~0); 98199#L787-47 is_transmit8_triggered_~__retres1~8 := 0; 97168#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 97169#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 97574#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 97575#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 97899#L806-45 assume 1 == ~t9_pc~0; 98423#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 96583#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 97393#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 97233#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 97145#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 97146#L825-45 assume !(1 == ~t10_pc~0); 97666#L825-47 is_transmit10_triggered_~__retres1~10 := 0; 97667#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 97776#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 97777#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 97939#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 96785#L844-45 assume 1 == ~t11_pc~0; 96787#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 97306#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 97307#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 97320#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 97741#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 96824#L863-45 assume 1 == ~t12_pc~0; 96825#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 96433#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 96434#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 96940#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 96941#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 97748#L882-45 assume !(1 == ~t13_pc~0); 97273#L882-47 is_transmit13_triggered_~__retres1~13 := 0; 96451#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 96452#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 97056#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 98267#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 97856#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 97857#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 96739#L1444-3 assume !(1 == ~T3_E~0); 96740#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 96898#L1454-3 assume !(1 == ~T5_E~0); 97843#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 97844#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 98331#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 98243#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 98244#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 98333#L1484-3 assume !(1 == ~T11_E~0); 97473#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 97474#L1494-3 assume !(1 == ~T13_E~0); 98168#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 97780#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 97781#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 98252#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 98302#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 97394#L1524-3 assume !(1 == ~E_5~0); 97395#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 98361#L1534-3 assume !(1 == ~E_7~0); 97705#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 97161#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 97162#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 97674#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 96790#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 96791#L1564-3 assume !(1 == ~E_13~0); 97954#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 97955#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 96679#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 97244#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 97925#L1954 assume !(0 == start_simulation_~tmp~3); 97886#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 97887#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 96955#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 98020#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 98157#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 98158#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 98250#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 98325#L1967 assume !(0 != start_simulation_~tmp___0~1); 97144#L1935-1 [2021-11-07 07:29:57,907 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:57,907 INFO L85 PathProgramCache]: Analyzing trace with hash 1628452466, now seen corresponding path program 1 times [2021-11-07 07:29:57,908 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:57,908 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [34255213] [2021-11-07 07:29:57,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:57,908 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:57,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:57,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:57,973 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:57,973 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [34255213] [2021-11-07 07:29:57,974 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [34255213] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:57,974 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:57,974 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 07:29:57,974 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1389996766] [2021-11-07 07:29:57,975 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:29:57,975 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:57,976 INFO L85 PathProgramCache]: Analyzing trace with hash -1787073847, now seen corresponding path program 1 times [2021-11-07 07:29:57,976 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:57,976 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [592539600] [2021-11-07 07:29:57,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:57,977 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:57,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:58,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:58,125 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:58,125 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [592539600] [2021-11-07 07:29:58,125 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [592539600] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:58,125 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:58,125 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:58,125 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1496806550] [2021-11-07 07:29:58,126 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:29:58,126 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:29:58,127 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:29:58,127 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:29:58,128 INFO L87 Difference]: Start difference. First operand 7148 states and 10216 transitions. cyclomatic complexity: 3070 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:58,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:29:58,312 INFO L93 Difference]: Finished difference Result 13663 states and 19439 transitions. [2021-11-07 07:29:58,312 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:29:58,313 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13663 states and 19439 transitions. [2021-11-07 07:29:58,402 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13480 [2021-11-07 07:29:58,466 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13663 states to 13663 states and 19439 transitions. [2021-11-07 07:29:58,466 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13663 [2021-11-07 07:29:58,484 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13663 [2021-11-07 07:29:58,486 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13663 states and 19439 transitions. [2021-11-07 07:29:58,500 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:29:58,500 INFO L681 BuchiCegarLoop]: Abstraction has 13663 states and 19439 transitions. [2021-11-07 07:29:58,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13663 states and 19439 transitions. [2021-11-07 07:29:58,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13663 to 13655. [2021-11-07 07:29:58,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13655 states, 13655 states have (on average 1.4229952398388868) internal successors, (19431), 13654 states have internal predecessors, (19431), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:58,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13655 states to 13655 states and 19431 transitions. [2021-11-07 07:29:58,779 INFO L704 BuchiCegarLoop]: Abstraction has 13655 states and 19431 transitions. [2021-11-07 07:29:58,780 INFO L587 BuchiCegarLoop]: Abstraction has 13655 states and 19431 transitions. [2021-11-07 07:29:58,780 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-07 07:29:58,780 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13655 states and 19431 transitions. [2021-11-07 07:29:58,845 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13472 [2021-11-07 07:29:58,845 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:29:58,845 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:29:58,849 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:58,849 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:29:58,850 INFO L791 eck$LassoCheckResult]: Stem: 118119#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 118120#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 117851#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 117852#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 117793#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 117794#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 118044#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 118079#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 118947#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 118948#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 119071#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 119072#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 117857#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 117858#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 119125#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 118383#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 118384#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 119004#L974-1 assume !(0 == ~M_E~0); 118706#L1286-1 assume !(0 == ~T1_E~0); 117763#L1291-1 assume !(0 == ~T2_E~0); 117764#L1296-1 assume !(0 == ~T3_E~0); 118478#L1301-1 assume !(0 == ~T4_E~0); 118479#L1306-1 assume !(0 == ~T5_E~0); 119014#L1311-1 assume !(0 == ~T6_E~0); 117720#L1316-1 assume !(0 == ~T7_E~0); 117721#L1321-1 assume !(0 == ~T8_E~0); 118498#L1326-1 assume !(0 == ~T9_E~0); 117542#L1331-1 assume !(0 == ~T10_E~0); 117253#L1336-1 assume !(0 == ~T11_E~0); 117254#L1341-1 assume !(0 == ~T12_E~0); 117304#L1346-1 assume !(0 == ~T13_E~0); 117305#L1351-1 assume !(0 == ~E_M~0); 117668#L1356-1 assume !(0 == ~E_1~0); 117669#L1361-1 assume !(0 == ~E_2~0); 119282#L1366-1 assume !(0 == ~E_3~0); 117713#L1371-1 assume !(0 == ~E_4~0); 117714#L1376-1 assume !(0 == ~E_5~0); 118544#L1381-1 assume !(0 == ~E_6~0); 118545#L1386-1 assume !(0 == ~E_7~0); 119322#L1391-1 assume !(0 == ~E_8~0); 119339#L1396-1 assume !(0 == ~E_9~0); 118416#L1401-1 assume !(0 == ~E_10~0); 118417#L1406-1 assume !(0 == ~E_11~0); 118739#L1411-1 assume !(0 == ~E_12~0); 118740#L1416-1 assume !(0 == ~E_13~0); 118340#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 118175#L635 assume !(1 == ~m_pc~0); 117322#L635-2 is_master_triggered_~__retres1~0 := 0; 117323#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 117663#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 118302#L1598 assume !(0 != activate_threads_~tmp~1); 117499#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 117500#L654 assume !(1 == ~t1_pc~0); 118198#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 119126#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 119379#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 118281#L1606 assume !(0 != activate_threads_~tmp___0~0); 118282#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 117545#L673 assume !(1 == ~t2_pc~0); 117546#L673-2 is_transmit2_triggered_~__retres1~2 := 0; 118704#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 118705#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 119360#L1614 assume !(0 != activate_threads_~tmp___1~0); 119368#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 118364#L692 assume !(1 == ~t3_pc~0); 118176#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 118177#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 118045#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 118015#L1622 assume !(0 != activate_threads_~tmp___2~0); 118016#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 117568#L711 assume !(1 == ~t4_pc~0); 117569#L711-2 is_transmit4_triggered_~__retres1~4 := 0; 119116#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 118518#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 117277#L1630 assume !(0 != activate_threads_~tmp___3~0); 117278#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 119350#L730 assume !(1 == ~t5_pc~0); 118634#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 117456#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 117457#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 117577#L1638 assume !(0 != activate_threads_~tmp___4~0); 117578#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 117926#L749 assume 1 == ~t6_pc~0; 117692#L750 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 117461#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 117890#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 117891#L1646 assume !(0 != activate_threads_~tmp___5~0); 118111#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 117258#L768 assume 1 == ~t7_pc~0; 117259#L769 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 118569#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 117492#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 117493#L1654 assume !(0 != activate_threads_~tmp___6~0); 118587#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 117722#L787 assume !(1 == ~t8_pc~0); 117723#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 118961#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 119156#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 119157#L1662 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 117302#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 117303#L806 assume 1 == ~t9_pc~0; 118972#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 117337#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 117338#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 117579#L1670 assume !(0 != activate_threads_~tmp___8~0); 117580#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 118955#L825 assume !(1 == ~t10_pc~0); 118956#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 118534#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 118535#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 117664#L1678 assume !(0 != activate_threads_~tmp___9~0); 117665#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 118247#L844 assume 1 == ~t11_pc~0; 117947#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 117948#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 118309#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 118310#L1686 assume !(0 != activate_threads_~tmp___10~0); 118944#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 118945#L863 assume !(1 == ~t12_pc~0); 117435#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 117436#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 117654#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 119045#L1694 assume !(0 != activate_threads_~tmp___11~0); 119046#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 118380#L882 assume !(1 == ~t13_pc~0); 118382#L882-2 is_transmit13_triggered_~__retres1~13 := 0; 118674#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 119241#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 119006#L1702 assume !(0 != activate_threads_~tmp___12~0); 118661#L1702-2 assume !(1 == ~M_E~0); 118662#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 119179#L1439-1 assume !(1 == ~T2_E~0); 117561#L1444-1 assume !(1 == ~T3_E~0); 117562#L1449-1 assume !(1 == ~T4_E~0); 118011#L1454-1 assume !(1 == ~T5_E~0); 118012#L1459-1 assume !(1 == ~T6_E~0); 118588#L1464-1 assume !(1 == ~T7_E~0); 118589#L1469-1 assume !(1 == ~T8_E~0); 118675#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 118341#L1479-1 assume !(1 == ~T10_E~0); 118342#L1484-1 assume !(1 == ~T11_E~0); 118596#L1489-1 assume !(1 == ~T12_E~0); 118213#L1494-1 assume !(1 == ~T13_E~0); 118214#L1499-1 assume !(1 == ~E_M~0); 118401#L1504-1 assume !(1 == ~E_1~0); 118402#L1509-1 assume !(1 == ~E_2~0); 119063#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 118718#L1519-1 assume !(1 == ~E_4~0); 118719#L1524-1 assume !(1 == ~E_5~0); 119299#L1529-1 assume !(1 == ~E_6~0); 119300#L1534-1 assume !(1 == ~E_7~0); 117357#L1539-1 assume !(1 == ~E_8~0); 117358#L1544-1 assume !(1 == ~E_9~0); 117781#L1549-1 assume !(1 == ~E_10~0); 119270#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 119268#L1559-1 assume !(1 == ~E_12~0); 119101#L1564-1 assume !(1 == ~E_13~0); 119102#L1935-1 [2021-11-07 07:29:58,851 INFO L793 eck$LassoCheckResult]: Loop: 119102#L1935-1 assume !false; 123014#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 123010#L1261 assume !false; 123008#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 122987#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 122979#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 122977#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 122974#L1074 assume !(0 != eval_~tmp~0); 122975#L1276 start_simulation_~kernel_st~0 := 2; 130732#L902-1 start_simulation_~kernel_st~0 := 3; 130731#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 130730#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 130729#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 130727#L1296-3 assume !(0 == ~T3_E~0); 130725#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 130723#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 130721#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 130719#L1316-3 assume !(0 == ~T7_E~0); 130717#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 130715#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 130714#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 130713#L1336-3 assume !(0 == ~T11_E~0); 119231#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 118005#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 117995#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 117937#L1356-3 assume !(0 == ~E_1~0); 117938#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 118524#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 117292#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 117293#L1376-3 assume !(0 == ~E_5~0); 119079#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 118917#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 118918#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 119127#L1396-3 assume !(0 == ~E_9~0); 119128#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 117662#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 117501#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 117502#L1416-3 assume !(0 == ~E_13~0); 118125#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 117381#L635-45 assume !(1 == ~m_pc~0); 117382#L635-47 is_master_triggered_~__retres1~0 := 0; 118564#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 118663#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 118943#L1598-45 assume !(0 != activate_threads_~tmp~1); 117680#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 117681#L654-45 assume !(1 == ~t1_pc~0); 118515#L654-47 is_transmit1_triggered_~__retres1~1 := 0; 130813#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 130812#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 130555#L1606-45 assume !(0 != activate_threads_~tmp___0~0); 119194#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 119195#L673-45 assume !(1 == ~t2_pc~0); 124346#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 124344#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 124341#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 124339#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 124337#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 124335#L692-45 assume !(1 == ~t3_pc~0); 124333#L692-47 is_transmit3_triggered_~__retres1~3 := 0; 124330#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 124327#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 124325#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 124323#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 124321#L711-45 assume !(1 == ~t4_pc~0); 124319#L711-47 is_transmit4_triggered_~__retres1~4 := 0; 124317#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 124314#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 124312#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 124310#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 124308#L730-45 assume !(1 == ~t5_pc~0); 124305#L730-47 is_transmit5_triggered_~__retres1~5 := 0; 124303#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 124300#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 124298#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 124296#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 124294#L749-45 assume !(1 == ~t6_pc~0); 124291#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 124289#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 124286#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 124284#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 124282#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 124280#L768-45 assume 1 == ~t7_pc~0; 124277#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 124275#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 124272#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 124270#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 124268#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 124266#L787-45 assume !(1 == ~t8_pc~0); 124263#L787-47 is_transmit8_triggered_~__retres1~8 := 0; 124260#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 124258#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 124256#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 124254#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 124252#L806-45 assume 1 == ~t9_pc~0; 124249#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 124247#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 124245#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 124243#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 124241#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 124239#L825-45 assume !(1 == ~t10_pc~0); 124237#L825-47 is_transmit10_triggered_~__retres1~10 := 0; 124234#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 124232#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 124230#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 124228#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 124226#L844-45 assume 1 == ~t11_pc~0; 124224#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 124221#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 124219#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 124217#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 124215#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 124213#L863-45 assume !(1 == ~t12_pc~0); 124211#L863-47 is_transmit12_triggered_~__retres1~12 := 0; 124208#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 124206#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 124204#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 124202#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 124198#L882-45 assume !(1 == ~t13_pc~0); 124196#L882-47 is_transmit13_triggered_~__retres1~13 := 0; 124194#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 124193#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 124192#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 124191#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 124190#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 124189#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 124188#L1444-3 assume !(1 == ~T3_E~0); 124187#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 124186#L1454-3 assume !(1 == ~T5_E~0); 124185#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 124184#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 124183#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 124181#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 124179#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 124177#L1484-3 assume !(1 == ~T11_E~0); 124175#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 124172#L1494-3 assume !(1 == ~T13_E~0); 124170#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 124168#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 124166#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 124164#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 124162#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 124159#L1524-3 assume !(1 == ~E_5~0); 124157#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 124155#L1534-3 assume !(1 == ~E_7~0); 124153#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 124151#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 124148#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 124146#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 124144#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 124142#L1564-3 assume !(1 == ~E_13~0); 124140#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 124118#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 124110#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 124108#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 124104#L1954 assume !(0 == start_simulation_~tmp~3); 124101#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 124081#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 124073#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 124071#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 124069#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 124067#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 124065#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 124063#L1967 assume !(0 != start_simulation_~tmp___0~1); 119102#L1935-1 [2021-11-07 07:29:58,851 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:58,852 INFO L85 PathProgramCache]: Analyzing trace with hash 143212275, now seen corresponding path program 1 times [2021-11-07 07:29:58,852 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:58,852 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2124451663] [2021-11-07 07:29:58,852 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:58,853 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:58,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:58,917 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:58,917 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:58,918 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2124451663] [2021-11-07 07:29:58,918 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2124451663] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:58,918 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:58,918 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:58,919 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [352257170] [2021-11-07 07:29:58,919 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:29:58,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:29:58,920 INFO L85 PathProgramCache]: Analyzing trace with hash -2045745021, now seen corresponding path program 1 times [2021-11-07 07:29:58,920 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:29:58,920 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1217262401] [2021-11-07 07:29:58,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:29:58,921 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:29:58,945 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:29:58,982 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:29:58,982 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:29:58,983 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1217262401] [2021-11-07 07:29:58,983 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1217262401] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:29:58,983 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:29:58,983 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:29:58,984 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [206514689] [2021-11-07 07:29:58,984 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:29:58,985 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:29:58,985 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-07 07:29:58,986 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-07 07:29:58,986 INFO L87 Difference]: Start difference. First operand 13655 states and 19431 transitions. cyclomatic complexity: 5780 Second operand has 4 states, 4 states have (on average 39.25) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:29:59,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:29:59,591 INFO L93 Difference]: Finished difference Result 33100 states and 46804 transitions. [2021-11-07 07:29:59,592 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 07:29:59,592 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33100 states and 46804 transitions. [2021-11-07 07:29:59,827 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 32482 [2021-11-07 07:30:00,011 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33100 states to 33100 states and 46804 transitions. [2021-11-07 07:30:00,012 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33100 [2021-11-07 07:30:00,037 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33100 [2021-11-07 07:30:00,038 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33100 states and 46804 transitions. [2021-11-07 07:30:00,073 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:30:00,073 INFO L681 BuchiCegarLoop]: Abstraction has 33100 states and 46804 transitions. [2021-11-07 07:30:00,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33100 states and 46804 transitions. [2021-11-07 07:30:00,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33100 to 26210. [2021-11-07 07:30:00,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26210 states, 26210 states have (on average 1.417626859977108) internal successors, (37156), 26209 states have internal predecessors, (37156), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:30:01,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26210 states to 26210 states and 37156 transitions. [2021-11-07 07:30:01,045 INFO L704 BuchiCegarLoop]: Abstraction has 26210 states and 37156 transitions. [2021-11-07 07:30:01,045 INFO L587 BuchiCegarLoop]: Abstraction has 26210 states and 37156 transitions. [2021-11-07 07:30:01,045 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-07 07:30:01,046 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26210 states and 37156 transitions. [2021-11-07 07:30:01,189 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 26016 [2021-11-07 07:30:01,191 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:30:01,191 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:30:01,195 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:30:01,195 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:30:01,196 INFO L791 eck$LassoCheckResult]: Stem: 164883#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 164884#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 164617#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 164618#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 164559#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 164560#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 164808#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 164844#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 165728#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 165729#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 165865#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 165866#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 164623#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 164624#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 165911#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 165146#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 165147#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 165794#L974-1 assume !(0 == ~M_E~0); 165478#L1286-1 assume !(0 == ~T1_E~0); 164529#L1291-1 assume !(0 == ~T2_E~0); 164530#L1296-1 assume !(0 == ~T3_E~0); 165244#L1301-1 assume !(0 == ~T4_E~0); 165245#L1306-1 assume !(0 == ~T5_E~0); 165804#L1311-1 assume !(0 == ~T6_E~0); 164487#L1316-1 assume !(0 == ~T7_E~0); 164488#L1321-1 assume !(0 == ~T8_E~0); 165263#L1326-1 assume !(0 == ~T9_E~0); 164307#L1331-1 assume !(0 == ~T10_E~0); 164018#L1336-1 assume !(0 == ~T11_E~0); 164019#L1341-1 assume !(0 == ~T12_E~0); 164069#L1346-1 assume !(0 == ~T13_E~0); 164070#L1351-1 assume !(0 == ~E_M~0); 164433#L1356-1 assume !(0 == ~E_1~0); 164434#L1361-1 assume !(0 == ~E_2~0); 166100#L1366-1 assume !(0 == ~E_3~0); 164480#L1371-1 assume !(0 == ~E_4~0); 164481#L1376-1 assume !(0 == ~E_5~0); 165307#L1381-1 assume !(0 == ~E_6~0); 165308#L1386-1 assume !(0 == ~E_7~0); 166145#L1391-1 assume !(0 == ~E_8~0); 166172#L1396-1 assume !(0 == ~E_9~0); 165180#L1401-1 assume !(0 == ~E_10~0); 165181#L1406-1 assume !(0 == ~E_11~0); 165511#L1411-1 assume !(0 == ~E_12~0); 165512#L1416-1 assume !(0 == ~E_13~0); 165102#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 164936#L635 assume !(1 == ~m_pc~0); 164089#L635-2 is_master_triggered_~__retres1~0 := 0; 164090#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 164430#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 165064#L1598 assume !(0 != activate_threads_~tmp~1); 164265#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 164266#L654 assume !(1 == ~t1_pc~0); 164959#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 165913#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 166139#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 165044#L1606 assume !(0 != activate_threads_~tmp___0~0); 165045#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 164312#L673 assume !(1 == ~t2_pc~0); 164313#L673-2 is_transmit2_triggered_~__retres1~2 := 0; 165476#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 165477#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 166189#L1614 assume !(0 != activate_threads_~tmp___1~0); 166198#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 165127#L692 assume !(1 == ~t3_pc~0); 164937#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 164938#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 164811#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 164776#L1622 assume !(0 != activate_threads_~tmp___2~0); 164777#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 164333#L711 assume !(1 == ~t4_pc~0); 164334#L711-2 is_transmit4_triggered_~__retres1~4 := 0; 165903#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 165281#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 164042#L1630 assume !(0 != activate_threads_~tmp___3~0); 164043#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 166181#L730 assume !(1 == ~t5_pc~0); 165401#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 164222#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 164223#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 164342#L1638 assume !(0 != activate_threads_~tmp___4~0); 164343#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 164689#L749 assume !(1 == ~t6_pc~0); 164231#L749-2 is_transmit6_triggered_~__retres1~6 := 0; 164232#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 164657#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 164658#L1646 assume !(0 != activate_threads_~tmp___5~0); 164875#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 164025#L768 assume 1 == ~t7_pc~0; 164026#L769 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 165333#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 164258#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 164259#L1654 assume !(0 != activate_threads_~tmp___6~0); 165352#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 164489#L787 assume !(1 == ~t8_pc~0); 164490#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 165746#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 165943#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 165944#L1662 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 164067#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 164068#L806 assume 1 == ~t9_pc~0; 165758#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 164102#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 164103#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 164344#L1670 assume !(0 != activate_threads_~tmp___8~0); 164345#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 165737#L825 assume !(1 == ~t10_pc~0); 165738#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 165296#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 165297#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 164431#L1678 assume !(0 != activate_threads_~tmp___9~0); 164432#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 165010#L844 assume 1 == ~t11_pc~0; 164713#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 164714#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 165071#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 165072#L1686 assume !(0 != activate_threads_~tmp___10~0); 165725#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 165726#L863 assume !(1 == ~t12_pc~0); 164206#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 164207#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 164420#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 165834#L1694 assume !(0 != activate_threads_~tmp___11~0); 165835#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 165143#L882 assume !(1 == ~t13_pc~0); 165145#L882-2 is_transmit13_triggered_~__retres1~13 := 0; 165445#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 166061#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 165797#L1702 assume !(0 != activate_threads_~tmp___12~0); 165432#L1702-2 assume !(1 == ~M_E~0); 165433#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 165973#L1439-1 assume !(1 == ~T2_E~0); 164326#L1444-1 assume !(1 == ~T3_E~0); 164327#L1449-1 assume !(1 == ~T4_E~0); 164774#L1454-1 assume !(1 == ~T5_E~0); 164775#L1459-1 assume !(1 == ~T6_E~0); 165353#L1464-1 assume !(1 == ~T7_E~0); 165354#L1469-1 assume !(1 == ~T8_E~0); 165448#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 165103#L1479-1 assume !(1 == ~T10_E~0); 165104#L1484-1 assume !(1 == ~T11_E~0); 165360#L1489-1 assume !(1 == ~T12_E~0); 164975#L1494-1 assume !(1 == ~T13_E~0); 164976#L1499-1 assume !(1 == ~E_M~0); 165164#L1504-1 assume !(1 == ~E_1~0); 165165#L1509-1 assume !(1 == ~E_2~0); 165852#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 165489#L1519-1 assume !(1 == ~E_4~0); 165490#L1524-1 assume !(1 == ~E_5~0); 166118#L1529-1 assume !(1 == ~E_6~0); 166119#L1534-1 assume !(1 == ~E_7~0); 164122#L1539-1 assume !(1 == ~E_8~0); 164123#L1544-1 assume !(1 == ~E_9~0); 164546#L1549-1 assume !(1 == ~E_10~0); 166086#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 166084#L1559-1 assume !(1 == ~E_12~0); 165891#L1564-1 assume !(1 == ~E_13~0); 164728#L1935-1 [2021-11-07 07:30:01,197 INFO L793 eck$LassoCheckResult]: Loop: 164728#L1935-1 assume !false; 164131#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 164132#L1261 assume !false; 165365#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 165366#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 164261#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 164421#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 164422#L1074 assume !(0 != eval_~tmp~0); 164790#L1276 start_simulation_~kernel_st~0 := 2; 189925#L902-1 start_simulation_~kernel_st~0 := 3; 189924#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 189923#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 189922#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 189921#L1296-3 assume !(0 == ~T3_E~0); 189920#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 189919#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 189918#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 189917#L1316-3 assume !(0 == ~T7_E~0); 189916#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 189915#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 189914#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 189913#L1336-3 assume !(0 == ~T11_E~0); 189912#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 189911#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 189910#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 189909#L1356-3 assume !(0 == ~E_1~0); 189908#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 189907#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 189906#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 189905#L1376-3 assume !(0 == ~E_5~0); 189904#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 189903#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 189902#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 189901#L1396-3 assume !(0 == ~E_9~0); 189900#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 189899#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 189898#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 189897#L1416-3 assume !(0 == ~E_13~0); 189896#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 189895#L635-45 assume !(1 == ~m_pc~0); 189894#L635-47 is_master_triggered_~__retres1~0 := 0; 189893#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 189892#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 189891#L1598-45 assume !(0 != activate_threads_~tmp~1); 189890#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 165276#L654-45 assume !(1 == ~t1_pc~0); 165278#L654-47 is_transmit1_triggered_~__retres1~1 := 0; 189772#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 189771#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 164135#L1606-45 assume !(0 != activate_threads_~tmp___0~0); 164136#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 164949#L673-45 assume !(1 == ~t2_pc~0); 164950#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 165289#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 165290#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 166027#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 166028#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 189141#L692-45 assume 1 == ~t3_pc~0; 189139#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 189138#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 189137#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 189136#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 189135#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 189134#L711-45 assume !(1 == ~t4_pc~0); 189133#L711-47 is_transmit4_triggered_~__retres1~4 := 0; 189132#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 189131#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 189130#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 189129#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 189128#L730-45 assume !(1 == ~t5_pc~0); 189126#L730-47 is_transmit5_triggered_~__retres1~5 := 0; 166240#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 164724#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 164725#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 165498#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 164288#L749-45 assume !(1 == ~t6_pc~0); 164289#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 189121#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 189120#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 189119#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 189118#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 189117#L768-45 assume 1 == ~t7_pc~0; 189115#L769-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 165795#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 165585#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 165586#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 165627#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 165628#L787-45 assume !(1 == ~t8_pc~0); 165825#L787-47 is_transmit8_triggered_~__retres1~8 := 0; 165824#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 189108#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 189107#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 189106#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 189105#L806-45 assume !(1 == ~t9_pc~0); 164167#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 164168#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 164977#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 189103#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 189102#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 189101#L825-45 assume 1 == ~t10_pc~0; 189099#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 189098#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 189097#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 189096#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 189095#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 189094#L844-45 assume 1 == ~t11_pc~0; 166030#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 164890#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 164891#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 164904#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 165331#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 164406#L863-45 assume 1 == ~t12_pc~0; 164407#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 165170#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 189086#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 189085#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 189084#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 165733#L882-45 assume !(1 == ~t13_pc~0); 164858#L882-47 is_transmit13_triggered_~__retres1~13 := 0; 164034#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 164035#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 164641#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 165902#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 165454#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 165455#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 164322#L1444-3 assume !(1 == ~T3_E~0); 164323#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 164482#L1454-3 assume !(1 == ~T5_E~0); 189073#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 189072#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 189071#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 189070#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 189069#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 189068#L1484-3 assume !(1 == ~T11_E~0); 189067#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 165789#L1494-3 assume !(1 == ~T13_E~0); 165790#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 165371#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 165372#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 165884#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 165936#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 164978#L1524-3 assume !(1 == ~E_5~0); 164979#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 189060#L1534-3 assume !(1 == ~E_7~0); 189059#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 189058#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 189057#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 189056#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 189055#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 189054#L1564-3 assume !(1 == ~E_13~0); 189053#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 165740#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 164263#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 164828#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 165527#L1954 assume !(0 == start_simulation_~tmp~3); 165484#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 165485#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 164540#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 165625#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 165778#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 165779#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 165882#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 165963#L1967 assume !(0 != start_simulation_~tmp___0~1); 164728#L1935-1 [2021-11-07 07:30:01,197 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:30:01,198 INFO L85 PathProgramCache]: Analyzing trace with hash 284311796, now seen corresponding path program 1 times [2021-11-07 07:30:01,198 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:30:01,198 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [242966307] [2021-11-07 07:30:01,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:30:01,200 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:30:01,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:30:01,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:30:01,445 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:30:01,446 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [242966307] [2021-11-07 07:30:01,447 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [242966307] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:30:01,447 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:30:01,447 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:30:01,447 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1606725795] [2021-11-07 07:30:01,448 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:30:01,449 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:30:01,449 INFO L85 PathProgramCache]: Analyzing trace with hash -1463661499, now seen corresponding path program 1 times [2021-11-07 07:30:01,449 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:30:01,449 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1478896592] [2021-11-07 07:30:01,450 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:30:01,453 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:30:01,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:30:01,502 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:30:01,502 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:30:01,503 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1478896592] [2021-11-07 07:30:01,503 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1478896592] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:30:01,504 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:30:01,504 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:30:01,504 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [440941824] [2021-11-07 07:30:01,505 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:30:01,505 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:30:01,506 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-07 07:30:01,507 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-07 07:30:01,507 INFO L87 Difference]: Start difference. First operand 26210 states and 37156 transitions. cyclomatic complexity: 10950 Second operand has 4 states, 4 states have (on average 39.25) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:30:02,281 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:30:02,281 INFO L93 Difference]: Finished difference Result 63621 states and 89645 transitions. [2021-11-07 07:30:02,281 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 07:30:02,282 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63621 states and 89645 transitions. [2021-11-07 07:30:02,839 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 62560 [2021-11-07 07:30:03,207 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63621 states to 63621 states and 89645 transitions. [2021-11-07 07:30:03,207 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63621 [2021-11-07 07:30:03,234 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63621 [2021-11-07 07:30:03,234 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63621 states and 89645 transitions. [2021-11-07 07:30:03,268 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:30:03,268 INFO L681 BuchiCegarLoop]: Abstraction has 63621 states and 89645 transitions. [2021-11-07 07:30:03,305 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63621 states and 89645 transitions. [2021-11-07 07:30:04,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63621 to 50409. [2021-11-07 07:30:04,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50409 states, 50409 states have (on average 1.4126247297109644) internal successors, (71209), 50408 states have internal predecessors, (71209), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:30:04,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50409 states to 50409 states and 71209 transitions. [2021-11-07 07:30:04,296 INFO L704 BuchiCegarLoop]: Abstraction has 50409 states and 71209 transitions. [2021-11-07 07:30:04,297 INFO L587 BuchiCegarLoop]: Abstraction has 50409 states and 71209 transitions. [2021-11-07 07:30:04,297 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-11-07 07:30:04,297 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50409 states and 71209 transitions. [2021-11-07 07:30:04,483 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 50192 [2021-11-07 07:30:04,483 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:30:04,483 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:30:04,493 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:30:04,495 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:30:04,496 INFO L791 eck$LassoCheckResult]: Stem: 254722#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 254723#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 254455#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 254456#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 254398#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 254399#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 254647#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 254683#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 255571#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 255572#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 255701#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 255702#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 254461#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 254462#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 255745#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 254987#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 254988#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 255634#L974-1 assume !(0 == ~M_E~0); 255312#L1286-1 assume !(0 == ~T1_E~0); 254370#L1291-1 assume !(0 == ~T2_E~0); 254371#L1296-1 assume !(0 == ~T3_E~0); 255081#L1301-1 assume !(0 == ~T4_E~0); 255082#L1306-1 assume !(0 == ~T5_E~0); 255644#L1311-1 assume !(0 == ~T6_E~0); 254329#L1316-1 assume !(0 == ~T7_E~0); 254330#L1321-1 assume !(0 == ~T8_E~0); 255101#L1326-1 assume !(0 == ~T9_E~0); 254146#L1331-1 assume !(0 == ~T10_E~0); 253859#L1336-1 assume !(0 == ~T11_E~0); 253860#L1341-1 assume !(0 == ~T12_E~0); 253909#L1346-1 assume !(0 == ~T13_E~0); 253910#L1351-1 assume !(0 == ~E_M~0); 254273#L1356-1 assume !(0 == ~E_1~0); 254274#L1361-1 assume !(0 == ~E_2~0); 255948#L1366-1 assume !(0 == ~E_3~0); 254322#L1371-1 assume !(0 == ~E_4~0); 254323#L1376-1 assume !(0 == ~E_5~0); 255146#L1381-1 assume !(0 == ~E_6~0); 255147#L1386-1 assume !(0 == ~E_7~0); 255989#L1391-1 assume !(0 == ~E_8~0); 256013#L1396-1 assume !(0 == ~E_9~0); 255020#L1401-1 assume !(0 == ~E_10~0); 255021#L1406-1 assume !(0 == ~E_11~0); 255347#L1411-1 assume !(0 == ~E_12~0); 255348#L1416-1 assume !(0 == ~E_13~0); 254943#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 254777#L635 assume !(1 == ~m_pc~0); 253927#L635-2 is_master_triggered_~__retres1~0 := 0; 253928#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 254268#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 254906#L1598 assume !(0 != activate_threads_~tmp~1); 254104#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 254105#L654 assume !(1 == ~t1_pc~0); 254800#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 255746#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 255985#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 254885#L1606 assume !(0 != activate_threads_~tmp___0~0); 254886#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 254150#L673 assume !(1 == ~t2_pc~0); 254151#L673-2 is_transmit2_triggered_~__retres1~2 := 0; 255310#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 255311#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 256033#L1614 assume !(0 != activate_threads_~tmp___1~0); 256042#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 254968#L692 assume !(1 == ~t3_pc~0); 254778#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 254779#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 254648#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 254614#L1622 assume !(0 != activate_threads_~tmp___2~0); 254615#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 254173#L711 assume !(1 == ~t4_pc~0); 254174#L711-2 is_transmit4_triggered_~__retres1~4 := 0; 255736#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 255120#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 253882#L1630 assume !(0 != activate_threads_~tmp___3~0); 253883#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 256027#L730 assume !(1 == ~t5_pc~0); 255243#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 254061#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 254062#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 254182#L1638 assume !(0 != activate_threads_~tmp___4~0); 254183#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 254525#L749 assume !(1 == ~t6_pc~0); 254065#L749-2 is_transmit6_triggered_~__retres1~6 := 0; 254066#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 254494#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 254495#L1646 assume !(0 != activate_threads_~tmp___5~0); 254714#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 253864#L768 assume !(1 == ~t7_pc~0); 253865#L768-2 is_transmit7_triggered_~__retres1~7 := 0; 255795#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 254097#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 254098#L1654 assume !(0 != activate_threads_~tmp___6~0); 255195#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 254331#L787 assume !(1 == ~t8_pc~0); 254332#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 255587#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 255780#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 255781#L1662 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 253907#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 253908#L806 assume 1 == ~t9_pc~0; 255598#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 253942#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 253943#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 254184#L1670 assume !(0 != activate_threads_~tmp___8~0); 254185#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 255579#L825 assume !(1 == ~t10_pc~0); 255580#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 255135#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 255136#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 254269#L1678 assume !(0 != activate_threads_~tmp___9~0); 254270#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 254851#L844 assume 1 == ~t11_pc~0; 254546#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 254547#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 254913#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 254914#L1686 assume !(0 != activate_threads_~tmp___10~0); 255568#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 255569#L863 assume !(1 == ~t12_pc~0); 254041#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 254042#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 254259#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 255672#L1694 assume !(0 != activate_threads_~tmp___11~0); 255673#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 254984#L882 assume !(1 == ~t13_pc~0); 254986#L882-2 is_transmit13_triggered_~__retres1~13 := 0; 255282#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 255906#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 255637#L1702 assume !(0 != activate_threads_~tmp___12~0); 255268#L1702-2 assume !(1 == ~M_E~0); 255269#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 255817#L1439-1 assume !(1 == ~T2_E~0); 254166#L1444-1 assume !(1 == ~T3_E~0); 254167#L1449-1 assume !(1 == ~T4_E~0); 254610#L1454-1 assume !(1 == ~T5_E~0); 254611#L1459-1 assume !(1 == ~T6_E~0); 255196#L1464-1 assume !(1 == ~T7_E~0); 255197#L1469-1 assume !(1 == ~T8_E~0); 255283#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 254944#L1479-1 assume !(1 == ~T10_E~0); 254945#L1484-1 assume !(1 == ~T11_E~0); 255204#L1489-1 assume !(1 == ~T12_E~0); 254816#L1494-1 assume !(1 == ~T13_E~0); 254817#L1499-1 assume !(1 == ~E_M~0); 255005#L1504-1 assume !(1 == ~E_1~0); 255006#L1509-1 assume !(1 == ~E_2~0); 255690#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 255323#L1519-1 assume !(1 == ~E_4~0); 255324#L1524-1 assume !(1 == ~E_5~0); 255966#L1529-1 assume !(1 == ~E_6~0); 255967#L1534-1 assume !(1 == ~E_7~0); 253962#L1539-1 assume !(1 == ~E_8~0); 253963#L1544-1 assume !(1 == ~E_9~0); 254386#L1549-1 assume !(1 == ~E_10~0); 255933#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 255931#L1559-1 assume !(1 == ~E_12~0); 255726#L1564-1 assume !(1 == ~E_13~0); 254563#L1935-1 [2021-11-07 07:30:04,496 INFO L793 eck$LassoCheckResult]: Loop: 254563#L1935-1 assume !false; 253971#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 253972#L1261 assume !false; 255209#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 255210#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 254100#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 254262#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 254263#L1074 assume !(0 != eval_~tmp~0); 254630#L1276 start_simulation_~kernel_st~0 := 2; 304068#L902-1 start_simulation_~kernel_st~0 := 3; 304067#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 304066#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 303817#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 303816#L1296-3 assume !(0 == ~T3_E~0); 303815#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 303814#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 303813#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 303812#L1316-3 assume !(0 == ~T7_E~0); 303811#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 303810#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 303809#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 303808#L1336-3 assume !(0 == ~T11_E~0); 303807#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 303806#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 303805#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 303804#L1356-3 assume !(0 == ~E_1~0); 303803#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 303801#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 303799#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 303798#L1376-3 assume !(0 == ~E_5~0); 303797#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 303795#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 303793#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 303792#L1396-3 assume !(0 == ~E_9~0); 303790#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 303788#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 303786#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 303784#L1416-3 assume !(0 == ~E_13~0); 303781#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 303779#L635-45 assume !(1 == ~m_pc~0); 303778#L635-47 is_master_triggered_~__retres1~0 := 0; 303777#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 303775#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 303774#L1598-45 assume !(0 != activate_threads_~tmp~1); 303773#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 303772#L654-45 assume !(1 == ~t1_pc~0); 303768#L654-47 is_transmit1_triggered_~__retres1~1 := 0; 303766#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 303764#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 303762#L1606-45 assume !(0 != activate_threads_~tmp___0~0); 303760#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 302552#L673-45 assume !(1 == ~t2_pc~0); 302551#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 302550#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 302548#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 302546#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 302544#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 302542#L692-45 assume !(1 == ~t3_pc~0); 302540#L692-47 is_transmit3_triggered_~__retres1~3 := 0; 302537#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 302534#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 302532#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 302530#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 302528#L711-45 assume !(1 == ~t4_pc~0); 302526#L711-47 is_transmit4_triggered_~__retres1~4 := 0; 302524#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 302522#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 302521#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 302520#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 302519#L730-45 assume !(1 == ~t5_pc~0); 302517#L730-47 is_transmit5_triggered_~__retres1~5 := 0; 302515#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 302513#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 302512#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 302510#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 302508#L749-45 assume !(1 == ~t6_pc~0); 298557#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 302505#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 302503#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 302501#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 302498#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 302496#L768-45 assume !(1 == ~t7_pc~0); 272435#L768-47 is_transmit7_triggered_~__retres1~7 := 0; 302493#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 302491#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 302489#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 302487#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 302485#L787-45 assume !(1 == ~t8_pc~0); 302482#L787-47 is_transmit8_triggered_~__retres1~8 := 0; 302480#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 302478#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 302475#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 302473#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 302471#L806-45 assume 1 == ~t9_pc~0; 302468#L807-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 302466#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 302464#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 302462#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 302461#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 302459#L825-45 assume 1 == ~t10_pc~0; 302455#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 302453#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 302451#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 302450#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 302448#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 302446#L844-45 assume 1 == ~t11_pc~0; 302444#L845-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 302441#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 302439#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 302436#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 302434#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 302432#L863-45 assume 1 == ~t12_pc~0; 302429#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 302427#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 302425#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 302422#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 302420#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 302415#L882-45 assume !(1 == ~t13_pc~0); 302413#L882-47 is_transmit13_triggered_~__retres1~13 := 0; 302410#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 302408#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 302406#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 302404#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 302402#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 302400#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 302397#L1444-3 assume !(1 == ~T3_E~0); 302395#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 302393#L1454-3 assume !(1 == ~T5_E~0); 302391#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 302389#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 302387#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 302384#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 302382#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 302380#L1484-3 assume !(1 == ~T11_E~0); 302378#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 302376#L1494-3 assume !(1 == ~T13_E~0); 302373#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 302371#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 302369#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 302367#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 302365#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 302363#L1524-3 assume !(1 == ~E_5~0); 302361#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 302359#L1534-3 assume !(1 == ~E_7~0); 302357#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 302355#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 302353#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 302351#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 302349#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 302347#L1564-3 assume !(1 == ~E_13~0); 302345#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 302322#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 302314#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 302312#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 302310#L1954 assume !(0 == start_simulation_~tmp~3); 302308#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 255653#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 254380#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 255460#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 255614#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 255615#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 255719#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 255805#L1967 assume !(0 != start_simulation_~tmp___0~1); 254563#L1935-1 [2021-11-07 07:30:04,498 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:30:04,498 INFO L85 PathProgramCache]: Analyzing trace with hash 1421940661, now seen corresponding path program 1 times [2021-11-07 07:30:04,498 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:30:04,498 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2051408831] [2021-11-07 07:30:04,499 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:30:04,499 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:30:04,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:30:04,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:30:04,588 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:30:04,588 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2051408831] [2021-11-07 07:30:04,588 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2051408831] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:30:04,589 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:30:04,589 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-07 07:30:04,589 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [117072934] [2021-11-07 07:30:04,590 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:30:04,590 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:30:04,591 INFO L85 PathProgramCache]: Analyzing trace with hash 261043108, now seen corresponding path program 1 times [2021-11-07 07:30:04,591 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:30:04,591 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1212028135] [2021-11-07 07:30:04,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:30:04,592 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:30:04,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:30:04,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:30:04,853 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:30:04,854 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1212028135] [2021-11-07 07:30:04,854 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1212028135] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:30:04,854 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:30:04,854 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:30:04,855 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [93308440] [2021-11-07 07:30:04,855 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:30:04,855 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:30:04,856 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-07 07:30:04,856 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-07 07:30:04,856 INFO L87 Difference]: Start difference. First operand 50409 states and 71209 transitions. cyclomatic complexity: 20804 Second operand has 5 states, 5 states have (on average 31.4) internal successors, (157), 5 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:30:05,723 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:30:05,724 INFO L93 Difference]: Finished difference Result 122666 states and 174518 transitions. [2021-11-07 07:30:05,724 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-07 07:30:05,724 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122666 states and 174518 transitions. [2021-11-07 07:30:06,602 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 122224 [2021-11-07 07:30:06,973 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122666 states to 122666 states and 174518 transitions. [2021-11-07 07:30:06,973 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 122666 [2021-11-07 07:30:07,042 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 122666 [2021-11-07 07:30:07,042 INFO L73 IsDeterministic]: Start isDeterministic. Operand 122666 states and 174518 transitions. [2021-11-07 07:30:07,178 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:30:07,178 INFO L681 BuchiCegarLoop]: Abstraction has 122666 states and 174518 transitions. [2021-11-07 07:30:07,258 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122666 states and 174518 transitions. [2021-11-07 07:30:08,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122666 to 51708. [2021-11-07 07:30:08,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51708 states, 51708 states have (on average 1.4022588380908176) internal successors, (72508), 51707 states have internal predecessors, (72508), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:30:08,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51708 states to 51708 states and 72508 transitions. [2021-11-07 07:30:08,324 INFO L704 BuchiCegarLoop]: Abstraction has 51708 states and 72508 transitions. [2021-11-07 07:30:08,324 INFO L587 BuchiCegarLoop]: Abstraction has 51708 states and 72508 transitions. [2021-11-07 07:30:08,324 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-11-07 07:30:08,324 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51708 states and 72508 transitions. [2021-11-07 07:30:08,495 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 51488 [2021-11-07 07:30:08,495 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:30:08,495 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:30:08,499 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:30:08,499 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:30:08,499 INFO L791 eck$LassoCheckResult]: Stem: 427814#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 427815#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 427545#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 427546#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 427487#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 427488#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 427738#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 427775#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 428653#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 428654#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 428787#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 428788#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 427551#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 427552#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 428836#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 428073#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 428074#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 428716#L974-1 assume !(0 == ~M_E~0); 428398#L1286-1 assume !(0 == ~T1_E~0); 427459#L1291-1 assume !(0 == ~T2_E~0); 427460#L1296-1 assume !(0 == ~T3_E~0); 428169#L1301-1 assume !(0 == ~T4_E~0); 428170#L1306-1 assume !(0 == ~T5_E~0); 428725#L1311-1 assume !(0 == ~T6_E~0); 427417#L1316-1 assume !(0 == ~T7_E~0); 427418#L1321-1 assume !(0 == ~T8_E~0); 428189#L1326-1 assume !(0 == ~T9_E~0); 427234#L1331-1 assume !(0 == ~T10_E~0); 426947#L1336-1 assume !(0 == ~T11_E~0); 426948#L1341-1 assume !(0 == ~T12_E~0); 426997#L1346-1 assume !(0 == ~T13_E~0); 426998#L1351-1 assume !(0 == ~E_M~0); 427361#L1356-1 assume !(0 == ~E_1~0); 427362#L1361-1 assume !(0 == ~E_2~0); 429031#L1366-1 assume !(0 == ~E_3~0); 427410#L1371-1 assume !(0 == ~E_4~0); 427411#L1376-1 assume !(0 == ~E_5~0); 428233#L1381-1 assume !(0 == ~E_6~0); 428234#L1386-1 assume !(0 == ~E_7~0); 429068#L1391-1 assume !(0 == ~E_8~0); 429091#L1396-1 assume !(0 == ~E_9~0); 428108#L1401-1 assume !(0 == ~E_10~0); 428109#L1406-1 assume !(0 == ~E_11~0); 428429#L1411-1 assume !(0 == ~E_12~0); 428430#L1416-1 assume !(0 == ~E_13~0); 428030#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 427865#L635 assume !(1 == ~m_pc~0); 427015#L635-2 is_master_triggered_~__retres1~0 := 0; 427016#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 427356#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 427993#L1598 assume !(0 != activate_threads_~tmp~1); 427192#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 427193#L654 assume !(1 == ~t1_pc~0); 427888#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 428838#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 429065#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 427972#L1606 assume !(0 != activate_threads_~tmp___0~0); 427973#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 427237#L673 assume !(1 == ~t2_pc~0); 427238#L673-2 is_transmit2_triggered_~__retres1~2 := 0; 428396#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 428397#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 429113#L1614 assume !(0 != activate_threads_~tmp___1~0); 429127#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 428054#L692 assume !(1 == ~t3_pc~0); 427866#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 427867#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 427739#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 427706#L1622 assume !(0 != activate_threads_~tmp___2~0); 427707#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 427260#L711 assume !(1 == ~t4_pc~0); 427261#L711-2 is_transmit4_triggered_~__retres1~4 := 0; 428827#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 428207#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 426970#L1630 assume !(0 != activate_threads_~tmp___3~0); 426971#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 429105#L730 assume !(1 == ~t5_pc~0); 428323#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 427149#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 427150#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 427269#L1638 assume !(0 != activate_threads_~tmp___4~0); 427270#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 427617#L749 assume !(1 == ~t6_pc~0); 427153#L749-2 is_transmit6_triggered_~__retres1~6 := 0; 427154#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 427585#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 427586#L1646 assume !(0 != activate_threads_~tmp___5~0); 427806#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 426952#L768 assume !(1 == ~t7_pc~0); 426953#L768-2 is_transmit7_triggered_~__retres1~7 := 0; 428880#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 427185#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 427186#L1654 assume !(0 != activate_threads_~tmp___6~0); 428277#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 427419#L787 assume !(1 == ~t8_pc~0); 427420#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 428936#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 429046#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 429134#L1662 assume !(0 != activate_threads_~tmp___7~0); 426995#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 426996#L806 assume 1 == ~t9_pc~0; 428682#L807 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 427030#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 427031#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 427271#L1670 assume !(0 != activate_threads_~tmp___8~0); 427272#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 428661#L825 assume !(1 == ~t10_pc~0); 428662#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 428223#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 428224#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 427357#L1678 assume !(0 != activate_threads_~tmp___9~0); 427358#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 427938#L844 assume 1 == ~t11_pc~0; 427638#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 427639#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 428000#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 428001#L1686 assume !(0 != activate_threads_~tmp___10~0); 428650#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 428651#L863 assume !(1 == ~t12_pc~0); 427129#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 427130#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 427347#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 428753#L1694 assume !(0 != activate_threads_~tmp___11~0); 428754#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 428070#L882 assume !(1 == ~t13_pc~0); 428072#L882-2 is_transmit13_triggered_~__retres1~13 := 0; 428365#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 428984#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 428718#L1702 assume !(0 != activate_threads_~tmp___12~0); 428352#L1702-2 assume !(1 == ~M_E~0); 428353#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 428901#L1439-1 assume !(1 == ~T2_E~0); 427253#L1444-1 assume !(1 == ~T3_E~0); 427254#L1449-1 assume !(1 == ~T4_E~0); 427702#L1454-1 assume !(1 == ~T5_E~0); 427703#L1459-1 assume !(1 == ~T6_E~0); 428278#L1464-1 assume !(1 == ~T7_E~0); 428279#L1469-1 assume !(1 == ~T8_E~0); 428366#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 428031#L1479-1 assume !(1 == ~T10_E~0); 428032#L1484-1 assume !(1 == ~T11_E~0); 428285#L1489-1 assume !(1 == ~T12_E~0); 427903#L1494-1 assume !(1 == ~T13_E~0); 427904#L1499-1 assume !(1 == ~E_M~0); 428092#L1504-1 assume !(1 == ~E_1~0); 428093#L1509-1 assume !(1 == ~E_2~0); 428775#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 428409#L1519-1 assume !(1 == ~E_4~0); 428410#L1524-1 assume !(1 == ~E_5~0); 429047#L1529-1 assume !(1 == ~E_6~0); 429048#L1534-1 assume !(1 == ~E_7~0); 427050#L1539-1 assume !(1 == ~E_8~0); 427051#L1544-1 assume !(1 == ~E_9~0); 427475#L1549-1 assume !(1 == ~E_10~0); 429014#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 429012#L1559-1 assume !(1 == ~E_12~0); 428816#L1564-1 assume !(1 == ~E_13~0); 428817#L1935-1 [2021-11-07 07:30:08,500 INFO L793 eck$LassoCheckResult]: Loop: 428817#L1935-1 assume !false; 441862#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 441857#L1261 assume !false; 441856#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 441723#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 441716#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 441714#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 441711#L1074 assume !(0 != eval_~tmp~0); 441712#L1276 start_simulation_~kernel_st~0 := 2; 451764#L902-1 start_simulation_~kernel_st~0 := 3; 451760#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 451756#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 451752#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 451748#L1296-3 assume !(0 == ~T3_E~0); 451744#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 451740#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 451736#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 451732#L1316-3 assume !(0 == ~T7_E~0); 451728#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 451724#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 451720#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 451716#L1336-3 assume !(0 == ~T11_E~0); 451712#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 451708#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 451704#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 451700#L1356-3 assume !(0 == ~E_1~0); 451696#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 451692#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 451688#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 451684#L1376-3 assume !(0 == ~E_5~0); 451680#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 451676#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 451672#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 451668#L1396-3 assume !(0 == ~E_9~0); 451664#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 451660#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 451656#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 451652#L1416-3 assume !(0 == ~E_13~0); 451647#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 451427#L635-45 assume !(1 == ~m_pc~0); 451428#L635-47 is_master_triggered_~__retres1~0 := 0; 451408#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 451409#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 451388#L1598-45 assume !(0 != activate_threads_~tmp~1); 451389#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 451320#L654-45 assume !(1 == ~t1_pc~0); 451322#L654-47 is_transmit1_triggered_~__retres1~1 := 0; 451296#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 451297#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 451173#L1606-45 assume !(0 != activate_threads_~tmp___0~0); 451172#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 450746#L673-45 assume !(1 == ~t2_pc~0); 450744#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 450742#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 450740#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 450738#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 450735#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 450733#L692-45 assume 1 == ~t3_pc~0; 450730#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 450729#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 450727#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 450725#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 450724#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 450722#L711-45 assume !(1 == ~t4_pc~0); 450720#L711-47 is_transmit4_triggered_~__retres1~4 := 0; 450718#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 450716#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 450714#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 450712#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 450710#L730-45 assume !(1 == ~t5_pc~0); 450706#L730-47 is_transmit5_triggered_~__retres1~5 := 0; 450704#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 450702#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 450679#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 450671#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 443694#L749-45 assume !(1 == ~t6_pc~0); 443693#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 443692#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 443691#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 443690#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 443689#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 443688#L768-45 assume !(1 == ~t7_pc~0); 438523#L768-47 is_transmit7_triggered_~__retres1~7 := 0; 443687#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 443686#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 443685#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 443684#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 443683#L787-45 assume !(1 == ~t8_pc~0); 443682#L787-47 is_transmit8_triggered_~__retres1~8 := 0; 443680#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 443678#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 443676#L1662-45 assume !(0 != activate_threads_~tmp___7~0); 443672#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 443669#L806-45 assume !(1 == ~t9_pc~0); 443666#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 443662#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 443639#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 443634#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 443630#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 443625#L825-45 assume 1 == ~t10_pc~0; 443620#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 443616#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 443592#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 443586#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 443581#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 443574#L844-45 assume !(1 == ~t11_pc~0); 443568#L844-47 is_transmit11_triggered_~__retres1~11 := 0; 443563#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 443493#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 443488#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 443419#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 443410#L863-45 assume !(1 == ~t12_pc~0); 443404#L863-47 is_transmit12_triggered_~__retres1~12 := 0; 443394#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 443388#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 443383#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 443314#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 443304#L882-45 assume !(1 == ~t13_pc~0); 443299#L882-47 is_transmit13_triggered_~__retres1~13 := 0; 443228#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 443222#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 443216#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 443208#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 443201#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 443195#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 443187#L1444-3 assume !(1 == ~T3_E~0); 443181#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 443175#L1454-3 assume !(1 == ~T5_E~0); 443168#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 443161#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 443155#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 443147#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 443141#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 443135#L1484-3 assume !(1 == ~T11_E~0); 443127#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 443121#L1494-3 assume !(1 == ~T13_E~0); 443114#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 443107#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 443101#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 443095#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 443088#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 443083#L1524-3 assume !(1 == ~E_5~0); 443077#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 443072#L1534-3 assume !(1 == ~E_7~0); 443067#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 442997#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 442991#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 442983#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 442976#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 442971#L1564-3 assume !(1 == ~E_13~0); 442950#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 442918#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 442906#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 442900#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 442893#L1954 assume !(0 == start_simulation_~tmp~3); 442865#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 441920#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 441913#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 441912#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 441908#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 441904#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 441902#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 441879#L1967 assume !(0 != start_simulation_~tmp___0~1); 428817#L1935-1 [2021-11-07 07:30:08,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:30:08,501 INFO L85 PathProgramCache]: Analyzing trace with hash 1982640439, now seen corresponding path program 1 times [2021-11-07 07:30:08,501 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:30:08,502 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [408437852] [2021-11-07 07:30:08,502 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:30:08,502 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:30:08,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:30:08,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:30:08,553 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:30:08,553 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [408437852] [2021-11-07 07:30:08,554 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [408437852] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:30:08,554 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:30:08,554 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:30:08,554 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [66896323] [2021-11-07 07:30:08,555 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:30:08,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:30:08,555 INFO L85 PathProgramCache]: Analyzing trace with hash -919837728, now seen corresponding path program 1 times [2021-11-07 07:30:08,555 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:30:08,556 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [179217189] [2021-11-07 07:30:08,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:30:08,556 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:30:08,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:30:08,597 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:30:08,597 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:30:08,597 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [179217189] [2021-11-07 07:30:08,597 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [179217189] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:30:08,597 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:30:08,598 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:30:08,598 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1013374503] [2021-11-07 07:30:08,598 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:30:08,599 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:30:08,599 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-07 07:30:08,599 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-07 07:30:08,600 INFO L87 Difference]: Start difference. First operand 51708 states and 72508 transitions. cyclomatic complexity: 20804 Second operand has 4 states, 4 states have (on average 39.25) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:30:09,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:30:09,597 INFO L93 Difference]: Finished difference Result 125195 states and 174545 transitions. [2021-11-07 07:30:09,598 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 07:30:09,598 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 125195 states and 174545 transitions. [2021-11-07 07:30:10,082 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 123200 [2021-11-07 07:30:10,982 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 125195 states to 125195 states and 174545 transitions. [2021-11-07 07:30:10,982 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 125195 [2021-11-07 07:30:11,032 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 125195 [2021-11-07 07:30:11,032 INFO L73 IsDeterministic]: Start isDeterministic. Operand 125195 states and 174545 transitions. [2021-11-07 07:30:11,075 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:30:11,075 INFO L681 BuchiCegarLoop]: Abstraction has 125195 states and 174545 transitions. [2021-11-07 07:30:11,147 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125195 states and 174545 transitions. [2021-11-07 07:30:12,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125195 to 99499. [2021-11-07 07:30:12,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99499 states, 99499 states have (on average 1.3976522377109317) internal successors, (139065), 99498 states have internal predecessors, (139065), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:30:12,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99499 states to 99499 states and 139065 transitions. [2021-11-07 07:30:12,617 INFO L704 BuchiCegarLoop]: Abstraction has 99499 states and 139065 transitions. [2021-11-07 07:30:12,618 INFO L587 BuchiCegarLoop]: Abstraction has 99499 states and 139065 transitions. [2021-11-07 07:30:12,618 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-11-07 07:30:12,618 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99499 states and 139065 transitions. [2021-11-07 07:30:12,957 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 99232 [2021-11-07 07:30:12,957 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:30:12,957 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:30:12,965 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:30:12,965 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:30:12,966 INFO L791 eck$LassoCheckResult]: Stem: 604727#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 604728#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 604453#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 604454#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 604396#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 604397#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 604647#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 604687#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 605584#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 605585#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 605722#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 605723#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 604459#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 604460#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 605769#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 604997#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 604998#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 605650#L974-1 assume !(0 == ~M_E~0); 605324#L1286-1 assume !(0 == ~T1_E~0); 604367#L1291-1 assume !(0 == ~T2_E~0); 604368#L1296-1 assume !(0 == ~T3_E~0); 605095#L1301-1 assume !(0 == ~T4_E~0); 605096#L1306-1 assume !(0 == ~T5_E~0); 605661#L1311-1 assume !(0 == ~T6_E~0); 604328#L1316-1 assume !(0 == ~T7_E~0); 604329#L1321-1 assume !(0 == ~T8_E~0); 605115#L1326-1 assume !(0 == ~T9_E~0); 604148#L1331-1 assume !(0 == ~T10_E~0); 603860#L1336-1 assume !(0 == ~T11_E~0); 603861#L1341-1 assume !(0 == ~T12_E~0); 603910#L1346-1 assume !(0 == ~T13_E~0); 603911#L1351-1 assume !(0 == ~E_M~0); 604276#L1356-1 assume !(0 == ~E_1~0); 604277#L1361-1 assume !(0 == ~E_2~0); 605986#L1366-1 assume !(0 == ~E_3~0); 604321#L1371-1 assume !(0 == ~E_4~0); 604322#L1376-1 assume !(0 == ~E_5~0); 605161#L1381-1 assume !(0 == ~E_6~0); 605162#L1386-1 assume !(0 == ~E_7~0); 606036#L1391-1 assume !(0 == ~E_8~0); 606058#L1396-1 assume !(0 == ~E_9~0); 605032#L1401-1 assume !(0 == ~E_10~0); 605033#L1406-1 assume !(0 == ~E_11~0); 605361#L1411-1 assume !(0 == ~E_12~0); 605362#L1416-1 assume !(0 == ~E_13~0); 604951#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 604782#L635 assume !(1 == ~m_pc~0); 603930#L635-2 is_master_triggered_~__retres1~0 := 0; 603931#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 604273#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 604913#L1598 assume !(0 != activate_threads_~tmp~1); 604106#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 604107#L654 assume !(1 == ~t1_pc~0); 604805#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 605771#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 606031#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 604893#L1606 assume !(0 != activate_threads_~tmp___0~0); 604894#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 604153#L673 assume !(1 == ~t2_pc~0); 604154#L673-2 is_transmit2_triggered_~__retres1~2 := 0; 605322#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 605323#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 606075#L1614 assume !(0 != activate_threads_~tmp___1~0); 606090#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 604975#L692 assume !(1 == ~t3_pc~0); 604783#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 604784#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 604653#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 604615#L1622 assume !(0 != activate_threads_~tmp___2~0); 604616#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 604174#L711 assume !(1 == ~t4_pc~0); 604175#L711-2 is_transmit4_triggered_~__retres1~4 := 0; 605759#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 605134#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 603883#L1630 assume !(0 != activate_threads_~tmp___3~0); 603884#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 606067#L730 assume !(1 == ~t5_pc~0); 605254#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 604063#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 604064#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 604183#L1638 assume !(0 != activate_threads_~tmp___4~0); 604184#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 604525#L749 assume !(1 == ~t6_pc~0); 604072#L749-2 is_transmit6_triggered_~__retres1~6 := 0; 604073#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 604494#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 604495#L1646 assume !(0 != activate_threads_~tmp___5~0); 604719#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 603867#L768 assume !(1 == ~t7_pc~0); 603868#L768-2 is_transmit7_triggered_~__retres1~7 := 0; 605822#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 604099#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 604100#L1654 assume !(0 != activate_threads_~tmp___6~0); 605206#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 604330#L787 assume !(1 == ~t8_pc~0); 604331#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 605886#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 606008#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 606095#L1662 assume !(0 != activate_threads_~tmp___7~0); 603908#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 603909#L806 assume !(1 == ~t9_pc~0); 604698#L806-2 is_transmit9_triggered_~__retres1~9 := 0; 603943#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 603944#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 604185#L1670 assume !(0 != activate_threads_~tmp___8~0); 604186#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 605592#L825 assume !(1 == ~t10_pc~0); 605593#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 605150#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 605151#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 604274#L1678 assume !(0 != activate_threads_~tmp___9~0); 604275#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 604856#L844 assume 1 == ~t11_pc~0; 604549#L845 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 604550#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 604920#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 604921#L1686 assume !(0 != activate_threads_~tmp___10~0); 605581#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 605582#L863 assume !(1 == ~t12_pc~0); 604046#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 604047#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 604262#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 605692#L1694 assume !(0 != activate_threads_~tmp___11~0); 605693#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 604994#L882 assume !(1 == ~t13_pc~0); 604996#L882-2 is_transmit13_triggered_~__retres1~13 := 0; 605292#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 605938#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 605653#L1702 assume !(0 != activate_threads_~tmp___12~0); 605279#L1702-2 assume !(1 == ~M_E~0); 605280#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 605844#L1439-1 assume !(1 == ~T2_E~0); 604167#L1444-1 assume !(1 == ~T3_E~0); 604168#L1449-1 assume !(1 == ~T4_E~0); 604613#L1454-1 assume !(1 == ~T5_E~0); 604614#L1459-1 assume !(1 == ~T6_E~0); 605207#L1464-1 assume !(1 == ~T7_E~0); 605208#L1469-1 assume !(1 == ~T8_E~0); 605295#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 604952#L1479-1 assume !(1 == ~T10_E~0); 604953#L1484-1 assume !(1 == ~T11_E~0); 605214#L1489-1 assume !(1 == ~T12_E~0); 604821#L1494-1 assume !(1 == ~T13_E~0); 604822#L1499-1 assume !(1 == ~E_M~0); 605017#L1504-1 assume !(1 == ~E_1~0); 605018#L1509-1 assume !(1 == ~E_2~0); 605710#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 605336#L1519-1 assume !(1 == ~E_4~0); 605337#L1524-1 assume !(1 == ~E_5~0); 606009#L1529-1 assume !(1 == ~E_6~0); 606010#L1534-1 assume !(1 == ~E_7~0); 603965#L1539-1 assume !(1 == ~E_8~0); 603966#L1544-1 assume !(1 == ~E_9~0); 604384#L1549-1 assume !(1 == ~E_10~0); 605962#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 605959#L1559-1 assume !(1 == ~E_12~0); 605751#L1564-1 assume !(1 == ~E_13~0); 605752#L1935-1 [2021-11-07 07:30:12,967 INFO L793 eck$LassoCheckResult]: Loop: 605752#L1935-1 assume !false; 677645#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 677640#L1261 assume !false; 677637#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 675436#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 675428#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 675425#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 675402#L1074 assume !(0 != eval_~tmp~0); 675403#L1276 start_simulation_~kernel_st~0 := 2; 702424#L902-1 start_simulation_~kernel_st~0 := 3; 702422#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 702420#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 702418#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 702416#L1296-3 assume !(0 == ~T3_E~0); 702414#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 702412#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 702411#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 702410#L1316-3 assume !(0 == ~T7_E~0); 702409#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 702407#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 702406#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 702405#L1336-3 assume !(0 == ~T11_E~0); 702403#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 702402#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 702401#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 702400#L1356-3 assume !(0 == ~E_1~0); 702399#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 702398#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 702396#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 702394#L1376-3 assume !(0 == ~E_5~0); 702392#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 702390#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 702388#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 702386#L1396-3 assume !(0 == ~E_9~0); 702382#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 702380#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 702378#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 702376#L1416-3 assume !(0 == ~E_13~0); 702373#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 702371#L635-45 assume !(1 == ~m_pc~0); 702370#L635-47 is_master_triggered_~__retres1~0 := 0; 702369#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 702368#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 702367#L1598-45 assume !(0 != activate_threads_~tmp~1); 604288#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 604289#L654-45 assume !(1 == ~t1_pc~0); 605131#L654-47 is_transmit1_triggered_~__retres1~1 := 0; 690025#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 690023#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 690021#L1606-45 assume !(0 != activate_threads_~tmp___0~0); 690019#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 678010#L673-45 assume !(1 == ~t2_pc~0); 678008#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 678006#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 678004#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 678002#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 677999#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 677997#L692-45 assume 1 == ~t3_pc~0; 677994#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 677992#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 677990#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 677988#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 677986#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 677984#L711-45 assume !(1 == ~t4_pc~0); 677982#L711-47 is_transmit4_triggered_~__retres1~4 := 0; 677980#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 677978#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 677975#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 677973#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 677971#L730-45 assume !(1 == ~t5_pc~0); 677968#L730-47 is_transmit5_triggered_~__retres1~5 := 0; 677966#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 677964#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 677962#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 677961#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 677959#L749-45 assume !(1 == ~t6_pc~0); 673614#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 677956#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 677954#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 677952#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 677951#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 677949#L768-45 assume !(1 == ~t7_pc~0); 676680#L768-47 is_transmit7_triggered_~__retres1~7 := 0; 677946#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 677944#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 677940#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 677938#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 677936#L787-45 assume 1 == ~t8_pc~0; 677934#L788-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 677935#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 678019#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 677924#L1662-45 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 677923#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 677921#L806-45 assume !(1 == ~t9_pc~0); 622964#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 677918#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 677916#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 677914#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 677911#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 677909#L825-45 assume 1 == ~t10_pc~0; 677906#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 677904#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 677902#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 677900#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 677897#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 677895#L844-45 assume !(1 == ~t11_pc~0); 677892#L844-47 is_transmit11_triggered_~__retres1~11 := 0; 677890#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 677888#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 677886#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 677883#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 677881#L863-45 assume 1 == ~t12_pc~0; 677878#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 677876#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 677874#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 677871#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 677869#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 677865#L882-45 assume !(1 == ~t13_pc~0); 677863#L882-47 is_transmit13_triggered_~__retres1~13 := 0; 677861#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 677859#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 677857#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 677855#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 677853#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 677851#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 677849#L1444-3 assume !(1 == ~T3_E~0); 677847#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 677845#L1454-3 assume !(1 == ~T5_E~0); 677843#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 677841#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 677839#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 677837#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 677835#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 677833#L1484-3 assume !(1 == ~T11_E~0); 677831#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 677829#L1494-3 assume !(1 == ~T13_E~0); 677827#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 677825#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 677823#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 677821#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 677819#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 677817#L1524-3 assume !(1 == ~E_5~0); 677815#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 677813#L1534-3 assume !(1 == ~E_7~0); 677811#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 677809#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 677808#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 677807#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 677806#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 677805#L1564-3 assume !(1 == ~E_13~0); 677804#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 677790#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 677782#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 677779#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 677776#L1954 assume !(0 == start_simulation_~tmp~3); 677773#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 677753#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 677745#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 677743#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 677741#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 677739#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 677738#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 677736#L1967 assume !(0 != start_simulation_~tmp___0~1); 605752#L1935-1 [2021-11-07 07:30:12,968 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:30:12,968 INFO L85 PathProgramCache]: Analyzing trace with hash -2072059528, now seen corresponding path program 1 times [2021-11-07 07:30:12,968 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:30:12,968 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2027181426] [2021-11-07 07:30:12,969 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:30:12,969 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:30:12,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:30:13,025 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:30:13,026 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:30:13,026 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2027181426] [2021-11-07 07:30:13,026 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2027181426] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:30:13,027 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:30:13,027 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:30:13,027 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [70703842] [2021-11-07 07:30:13,028 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:30:13,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:30:13,028 INFO L85 PathProgramCache]: Analyzing trace with hash -374288156, now seen corresponding path program 1 times [2021-11-07 07:30:13,029 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:30:13,029 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [145430943] [2021-11-07 07:30:13,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:30:13,029 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:30:13,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:30:13,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:30:13,081 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:30:13,081 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [145430943] [2021-11-07 07:30:13,081 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [145430943] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:30:13,081 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:30:13,082 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:30:13,082 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [149331866] [2021-11-07 07:30:13,082 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:30:13,082 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:30:13,083 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-07 07:30:13,083 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-07 07:30:13,083 INFO L87 Difference]: Start difference. First operand 99499 states and 139065 transitions. cyclomatic complexity: 39570 Second operand has 4 states, 4 states have (on average 39.25) internal successors, (157), 3 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:30:14,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:30:14,650 INFO L93 Difference]: Finished difference Result 240058 states and 333606 transitions. [2021-11-07 07:30:14,651 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 07:30:14,651 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 240058 states and 333606 transitions. [2021-11-07 07:30:16,406 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 236256 [2021-11-07 07:30:16,936 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 240058 states to 240058 states and 333606 transitions. [2021-11-07 07:30:16,936 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 240058 [2021-11-07 07:30:17,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 240058 [2021-11-07 07:30:17,025 INFO L73 IsDeterministic]: Start isDeterministic. Operand 240058 states and 333606 transitions. [2021-11-07 07:30:17,107 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:30:17,107 INFO L681 BuchiCegarLoop]: Abstraction has 240058 states and 333606 transitions. [2021-11-07 07:30:17,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 240058 states and 333606 transitions. [2021-11-07 07:30:19,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 240058 to 191402. [2021-11-07 07:30:19,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 191402 states, 191402 states have (on average 1.3932874264636732) internal successors, (266678), 191401 states have internal predecessors, (266678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:30:19,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191402 states to 191402 states and 266678 transitions. [2021-11-07 07:30:19,890 INFO L704 BuchiCegarLoop]: Abstraction has 191402 states and 266678 transitions. [2021-11-07 07:30:19,890 INFO L587 BuchiCegarLoop]: Abstraction has 191402 states and 266678 transitions. [2021-11-07 07:30:19,890 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-11-07 07:30:19,891 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191402 states and 266678 transitions. [2021-11-07 07:30:21,358 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 191040 [2021-11-07 07:30:21,358 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:30:21,359 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:30:21,368 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:30:21,368 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:30:21,369 INFO L791 eck$LassoCheckResult]: Stem: 944294#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 944295#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 944024#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 944025#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 943967#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 943968#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 944212#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 944251#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 945168#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 945169#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 945299#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 945300#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 944030#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 944031#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 945348#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 944561#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 944562#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 945229#L974-1 assume !(0 == ~M_E~0); 944906#L1286-1 assume !(0 == ~T1_E~0); 943937#L1291-1 assume !(0 == ~T2_E~0); 943938#L1296-1 assume !(0 == ~T3_E~0); 944662#L1301-1 assume !(0 == ~T4_E~0); 944663#L1306-1 assume !(0 == ~T5_E~0); 945240#L1311-1 assume !(0 == ~T6_E~0); 943896#L1316-1 assume !(0 == ~T7_E~0); 943897#L1321-1 assume !(0 == ~T8_E~0); 944683#L1326-1 assume !(0 == ~T9_E~0); 943713#L1331-1 assume !(0 == ~T10_E~0); 943427#L1336-1 assume !(0 == ~T11_E~0); 943428#L1341-1 assume !(0 == ~T12_E~0); 943477#L1346-1 assume !(0 == ~T13_E~0); 943478#L1351-1 assume !(0 == ~E_M~0); 943841#L1356-1 assume !(0 == ~E_1~0); 943842#L1361-1 assume !(0 == ~E_2~0); 945585#L1366-1 assume !(0 == ~E_3~0); 943889#L1371-1 assume !(0 == ~E_4~0); 943890#L1376-1 assume !(0 == ~E_5~0); 944729#L1381-1 assume !(0 == ~E_6~0); 944730#L1386-1 assume !(0 == ~E_7~0); 945636#L1391-1 assume !(0 == ~E_8~0); 945672#L1396-1 assume !(0 == ~E_9~0); 944596#L1401-1 assume !(0 == ~E_10~0); 944597#L1406-1 assume !(0 == ~E_11~0); 944939#L1411-1 assume !(0 == ~E_12~0); 944940#L1416-1 assume !(0 == ~E_13~0); 944518#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 944352#L635 assume !(1 == ~m_pc~0); 943495#L635-2 is_master_triggered_~__retres1~0 := 0; 943496#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 943834#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 944479#L1598 assume !(0 != activate_threads_~tmp~1); 943670#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 943671#L654 assume !(1 == ~t1_pc~0); 944375#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 945349#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 945631#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 944458#L1606 assume !(0 != activate_threads_~tmp___0~0); 944459#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 943716#L673 assume !(1 == ~t2_pc~0); 943717#L673-2 is_transmit2_triggered_~__retres1~2 := 0; 944903#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 944904#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 945693#L1614 assume !(0 != activate_threads_~tmp___1~0); 945711#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 944542#L692 assume !(1 == ~t3_pc~0); 944353#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 944354#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 944213#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 944181#L1622 assume !(0 != activate_threads_~tmp___2~0); 944182#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 943739#L711 assume !(1 == ~t4_pc~0); 943740#L711-2 is_transmit4_triggered_~__retres1~4 := 0; 945339#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 944702#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 943450#L1630 assume !(0 != activate_threads_~tmp___3~0); 943451#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 945686#L730 assume !(1 == ~t5_pc~0); 944831#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 943628#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 943629#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 943748#L1638 assume !(0 != activate_threads_~tmp___4~0); 943749#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 944094#L749 assume !(1 == ~t6_pc~0); 943632#L749-2 is_transmit6_triggered_~__retres1~6 := 0; 943633#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 944064#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 944065#L1646 assume !(0 != activate_threads_~tmp___5~0); 944286#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 943432#L768 assume !(1 == ~t7_pc~0); 943433#L768-2 is_transmit7_triggered_~__retres1~7 := 0; 945397#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 943663#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 943664#L1654 assume !(0 != activate_threads_~tmp___6~0); 944781#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 943898#L787 assume !(1 == ~t8_pc~0); 943899#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 945469#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 945385#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 945386#L1662 assume !(0 != activate_threads_~tmp___7~0); 943475#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 943476#L806 assume !(1 == ~t9_pc~0); 944261#L806-2 is_transmit9_triggered_~__retres1~9 := 0; 943510#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 943511#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 943750#L1670 assume !(0 != activate_threads_~tmp___8~0); 943751#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 945176#L825 assume !(1 == ~t10_pc~0); 945177#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 944719#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 944720#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 943835#L1678 assume !(0 != activate_threads_~tmp___9~0); 943836#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 944425#L844 assume !(1 == ~t11_pc~0); 944426#L844-2 is_transmit11_triggered_~__retres1~11 := 0; 944665#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 944486#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 944487#L1686 assume !(0 != activate_threads_~tmp___10~0); 945165#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 945166#L863 assume !(1 == ~t12_pc~0); 943608#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 943609#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 943825#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 945273#L1694 assume !(0 != activate_threads_~tmp___11~0); 945274#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 944558#L882 assume !(1 == ~t13_pc~0); 944560#L882-2 is_transmit13_triggered_~__retres1~13 := 0; 944873#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 945526#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 945231#L1702 assume !(0 != activate_threads_~tmp___12~0); 944859#L1702-2 assume !(1 == ~M_E~0); 944860#L1434-1 assume 1 == ~T1_E~0;~T1_E~0 := 2; 945425#L1439-1 assume !(1 == ~T2_E~0); 943732#L1444-1 assume !(1 == ~T3_E~0); 943733#L1449-1 assume !(1 == ~T4_E~0); 944177#L1454-1 assume !(1 == ~T5_E~0); 944178#L1459-1 assume !(1 == ~T6_E~0); 944782#L1464-1 assume !(1 == ~T7_E~0); 944783#L1469-1 assume !(1 == ~T8_E~0); 944874#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 944519#L1479-1 assume !(1 == ~T10_E~0); 944520#L1484-1 assume !(1 == ~T11_E~0); 944790#L1489-1 assume !(1 == ~T12_E~0); 944391#L1494-1 assume !(1 == ~T13_E~0); 944392#L1499-1 assume !(1 == ~E_M~0); 944580#L1504-1 assume !(1 == ~E_1~0); 944581#L1509-1 assume !(1 == ~E_2~0); 945289#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 944917#L1519-1 assume !(1 == ~E_4~0); 944918#L1524-1 assume !(1 == ~E_5~0); 945609#L1529-1 assume !(1 == ~E_6~0); 945610#L1534-1 assume !(1 == ~E_7~0); 943530#L1539-1 assume !(1 == ~E_8~0); 943531#L1544-1 assume !(1 == ~E_9~0); 943955#L1549-1 assume !(1 == ~E_10~0); 945562#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 945560#L1559-1 assume !(1 == ~E_12~0); 945328#L1564-1 assume !(1 == ~E_13~0); 945329#L1935-1 [2021-11-07 07:30:21,370 INFO L793 eck$LassoCheckResult]: Loop: 945329#L1935-1 assume !false; 1126292#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 1126260#L1261 assume !false; 1126258#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1126195#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1126183#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1126176#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1126168#L1074 assume !(0 != eval_~tmp~0); 1126169#L1276 start_simulation_~kernel_st~0 := 2; 1133177#L902-1 start_simulation_~kernel_st~0 := 3; 1133175#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1133173#L1286-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1133171#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1133169#L1296-3 assume !(0 == ~T3_E~0); 1133167#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1133165#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1133163#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1133161#L1316-3 assume !(0 == ~T7_E~0); 1133159#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1133157#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1133155#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1133153#L1336-3 assume !(0 == ~T11_E~0); 1133151#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1133149#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1133147#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1133145#L1356-3 assume !(0 == ~E_1~0); 1133143#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1133141#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1133139#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1133137#L1376-3 assume !(0 == ~E_5~0); 1133135#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1133133#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1133120#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1133116#L1396-3 assume !(0 == ~E_9~0); 1133111#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1133107#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1133105#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1133103#L1416-3 assume !(0 == ~E_13~0); 1133101#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1133098#L635-45 assume !(1 == ~m_pc~0); 1133096#L635-47 is_master_triggered_~__retres1~0 := 0; 1133094#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1133093#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1133090#L1598-45 assume !(0 != activate_threads_~tmp~1); 1133089#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1133085#L654-45 assume 1 == ~t1_pc~0; 1133079#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1133073#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1133067#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1133062#L1606-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1133057#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1133053#L673-45 assume !(1 == ~t2_pc~0); 1114726#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 1133045#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1133040#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1133034#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1133028#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1133021#L692-45 assume 1 == ~t3_pc~0; 1133015#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1133010#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1133003#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1132995#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1132988#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1132983#L711-45 assume !(1 == ~t4_pc~0); 1132980#L711-47 is_transmit4_triggered_~__retres1~4 := 0; 1132922#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1132920#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1132918#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1132584#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1132578#L730-45 assume !(1 == ~t5_pc~0); 1132575#L730-47 is_transmit5_triggered_~__retres1~5 := 0; 1132573#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1132570#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1132568#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1132566#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1132565#L749-45 assume !(1 == ~t6_pc~0); 1127095#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 1132482#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1132481#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1132480#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1132479#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1127003#L768-45 assume !(1 == ~t7_pc~0); 1127001#L768-47 is_transmit7_triggered_~__retres1~7 := 0; 1127000#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1126999#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1126998#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1126997#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1126996#L787-45 assume !(1 == ~t8_pc~0); 1126992#L787-47 is_transmit8_triggered_~__retres1~8 := 0; 1126991#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1126989#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1126988#L1662-45 assume !(0 != activate_threads_~tmp___7~0); 1126985#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1126983#L806-45 assume !(1 == ~t9_pc~0); 1084340#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 1126980#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1126978#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 1126974#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 1126972#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1126970#L825-45 assume 1 == ~t10_pc~0; 1126967#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 1126964#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1126962#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 1126960#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 1126959#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1126957#L844-45 assume !(1 == ~t11_pc~0); 972496#L844-47 is_transmit11_triggered_~__retres1~11 := 0; 1126954#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1126952#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 1126950#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 1126947#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1126945#L863-45 assume !(1 == ~t12_pc~0); 1126943#L863-47 is_transmit12_triggered_~__retres1~12 := 0; 1126940#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1126938#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 1126936#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 1126935#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 1126931#L882-45 assume !(1 == ~t13_pc~0); 1126929#L882-47 is_transmit13_triggered_~__retres1~13 := 0; 1126927#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 1126925#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 1126923#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 1126921#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 1126919#L1434-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1126915#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1126913#L1444-3 assume !(1 == ~T3_E~0); 1126911#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1126909#L1454-3 assume !(1 == ~T5_E~0); 1126906#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1126904#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1126902#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1126901#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1126793#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1126789#L1484-3 assume !(1 == ~T11_E~0); 1126786#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1126784#L1494-3 assume !(1 == ~T13_E~0); 1126782#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1126780#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1126778#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1126750#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1126670#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1126662#L1524-3 assume !(1 == ~E_5~0); 1126654#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1126648#L1534-3 assume !(1 == ~E_7~0); 1126623#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1126510#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1126468#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1126458#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1126448#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1126414#L1564-3 assume !(1 == ~E_13~0); 1126411#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1126395#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1126387#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1126385#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 1126383#L1954 assume !(0 == start_simulation_~tmp~3); 1126381#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1126351#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1126343#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1126341#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 1126339#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1126336#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 1126334#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 1126332#L1967 assume !(0 != start_simulation_~tmp___0~1); 945329#L1935-1 [2021-11-07 07:30:21,370 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:30:21,370 INFO L85 PathProgramCache]: Analyzing trace with hash 1349430073, now seen corresponding path program 1 times [2021-11-07 07:30:21,371 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:30:21,371 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1380341601] [2021-11-07 07:30:21,371 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:30:21,371 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:30:21,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:30:21,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:30:21,428 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:30:21,428 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1380341601] [2021-11-07 07:30:21,428 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1380341601] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:30:21,429 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:30:21,429 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 07:30:21,429 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [636338917] [2021-11-07 07:30:21,429 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:30:21,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:30:21,430 INFO L85 PathProgramCache]: Analyzing trace with hash -2044469181, now seen corresponding path program 1 times [2021-11-07 07:30:21,430 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:30:21,430 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1742679988] [2021-11-07 07:30:21,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:30:21,431 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:30:21,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:30:21,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:30:21,477 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:30:21,478 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1742679988] [2021-11-07 07:30:21,478 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1742679988] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:30:21,478 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:30:21,478 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:30:21,478 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1248723503] [2021-11-07 07:30:21,479 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:30:21,479 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:30:21,480 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:30:21,480 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:30:21,480 INFO L87 Difference]: Start difference. First operand 191402 states and 266678 transitions. cyclomatic complexity: 75280 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:30:22,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:30:22,078 INFO L93 Difference]: Finished difference Result 191402 states and 266292 transitions. [2021-11-07 07:30:22,079 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:30:22,079 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191402 states and 266292 transitions. [2021-11-07 07:30:23,681 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 191040 [2021-11-07 07:30:24,160 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191402 states to 191402 states and 266292 transitions. [2021-11-07 07:30:24,161 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 191402 [2021-11-07 07:30:24,260 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 191402 [2021-11-07 07:30:24,260 INFO L73 IsDeterministic]: Start isDeterministic. Operand 191402 states and 266292 transitions. [2021-11-07 07:30:24,345 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:30:24,345 INFO L681 BuchiCegarLoop]: Abstraction has 191402 states and 266292 transitions. [2021-11-07 07:30:24,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191402 states and 266292 transitions. [2021-11-07 07:30:26,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191402 to 191402. [2021-11-07 07:30:26,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 191402 states, 191402 states have (on average 1.3912707286235253) internal successors, (266292), 191401 states have internal predecessors, (266292), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:30:27,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191402 states to 191402 states and 266292 transitions. [2021-11-07 07:30:27,578 INFO L704 BuchiCegarLoop]: Abstraction has 191402 states and 266292 transitions. [2021-11-07 07:30:27,578 INFO L587 BuchiCegarLoop]: Abstraction has 191402 states and 266292 transitions. [2021-11-07 07:30:27,578 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-11-07 07:30:27,579 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191402 states and 266292 transitions. [2021-11-07 07:30:28,219 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 191040 [2021-11-07 07:30:28,219 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:30:28,219 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:30:28,227 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:30:28,227 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:30:28,228 INFO L791 eck$LassoCheckResult]: Stem: 1327103#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1327104#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1326832#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1326833#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 1326774#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1326775#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1327021#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1327061#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1327981#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1327982#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1328125#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1328126#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1326838#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1326839#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1328176#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1327370#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1327371#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1328045#L974-1 assume !(0 == ~M_E~0); 1327713#L1286-1 assume !(0 == ~T1_E~0); 1326746#L1291-1 assume !(0 == ~T2_E~0); 1326747#L1296-1 assume !(0 == ~T3_E~0); 1327470#L1301-1 assume !(0 == ~T4_E~0); 1327471#L1306-1 assume !(0 == ~T5_E~0); 1328057#L1311-1 assume !(0 == ~T6_E~0); 1326705#L1316-1 assume !(0 == ~T7_E~0); 1326706#L1321-1 assume !(0 == ~T8_E~0); 1327492#L1326-1 assume !(0 == ~T9_E~0); 1326524#L1331-1 assume !(0 == ~T10_E~0); 1326238#L1336-1 assume !(0 == ~T11_E~0); 1326239#L1341-1 assume !(0 == ~T12_E~0); 1326288#L1346-1 assume !(0 == ~T13_E~0); 1326289#L1351-1 assume !(0 == ~E_M~0); 1326650#L1356-1 assume !(0 == ~E_1~0); 1326651#L1361-1 assume !(0 == ~E_2~0); 1328447#L1366-1 assume !(0 == ~E_3~0); 1326697#L1371-1 assume !(0 == ~E_4~0); 1326698#L1376-1 assume !(0 == ~E_5~0); 1327537#L1381-1 assume !(0 == ~E_6~0); 1327538#L1386-1 assume !(0 == ~E_7~0); 1328503#L1391-1 assume !(0 == ~E_8~0); 1328533#L1396-1 assume !(0 == ~E_9~0); 1327404#L1401-1 assume !(0 == ~E_10~0); 1327405#L1406-1 assume !(0 == ~E_11~0); 1327748#L1411-1 assume !(0 == ~E_12~0); 1327749#L1416-1 assume !(0 == ~E_13~0); 1327328#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1327158#L635 assume !(1 == ~m_pc~0); 1326306#L635-2 is_master_triggered_~__retres1~0 := 0; 1326307#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1326645#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1327290#L1598 assume !(0 != activate_threads_~tmp~1); 1326481#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1326482#L654 assume !(1 == ~t1_pc~0); 1327181#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 1328178#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1328499#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1327267#L1606 assume !(0 != activate_threads_~tmp___0~0); 1327268#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1326527#L673 assume !(1 == ~t2_pc~0); 1326528#L673-2 is_transmit2_triggered_~__retres1~2 := 0; 1327710#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1327711#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1328560#L1614 assume !(0 != activate_threads_~tmp___1~0); 1328578#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1327351#L692 assume !(1 == ~t3_pc~0); 1327159#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 1327160#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1327022#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1326988#L1622 assume !(0 != activate_threads_~tmp___2~0); 1326989#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1326550#L711 assume !(1 == ~t4_pc~0); 1326551#L711-2 is_transmit4_triggered_~__retres1~4 := 0; 1328168#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1327511#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1326261#L1630 assume !(0 != activate_threads_~tmp___3~0); 1326262#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1328549#L730 assume !(1 == ~t5_pc~0); 1327634#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 1326439#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1326440#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1326559#L1638 assume !(0 != activate_threads_~tmp___4~0); 1326560#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1326902#L749 assume !(1 == ~t6_pc~0); 1326443#L749-2 is_transmit6_triggered_~__retres1~6 := 0; 1326444#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1326872#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1326873#L1646 assume !(0 != activate_threads_~tmp___5~0); 1327095#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1326243#L768 assume !(1 == ~t7_pc~0); 1326244#L768-2 is_transmit7_triggered_~__retres1~7 := 0; 1328230#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1326474#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1326475#L1654 assume !(0 != activate_threads_~tmp___6~0); 1327585#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1326707#L787 assume !(1 == ~t8_pc~0); 1326708#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 1328308#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1328218#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1328219#L1662 assume !(0 != activate_threads_~tmp___7~0); 1326286#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1326287#L806 assume !(1 == ~t9_pc~0); 1327071#L806-2 is_transmit9_triggered_~__retres1~9 := 0; 1326321#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1326322#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 1326561#L1670 assume !(0 != activate_threads_~tmp___8~0); 1326562#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1327989#L825 assume !(1 == ~t10_pc~0); 1327990#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 1327527#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1327528#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 1326646#L1678 assume !(0 != activate_threads_~tmp___9~0); 1326647#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1327231#L844 assume !(1 == ~t11_pc~0); 1327232#L844-2 is_transmit11_triggered_~__retres1~11 := 0; 1327473#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1327297#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 1327298#L1686 assume !(0 != activate_threads_~tmp___10~0); 1327977#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1327978#L863 assume !(1 == ~t12_pc~0); 1326419#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 1326420#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1326636#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 1328093#L1694 assume !(0 != activate_threads_~tmp___11~0); 1328094#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 1327367#L882 assume !(1 == ~t13_pc~0); 1327369#L882-2 is_transmit13_triggered_~__retres1~13 := 0; 1327679#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 1328381#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 1328047#L1702 assume !(0 != activate_threads_~tmp___12~0); 1327665#L1702-2 assume !(1 == ~M_E~0); 1327666#L1434-1 assume !(1 == ~T1_E~0); 1328257#L1439-1 assume !(1 == ~T2_E~0); 1326543#L1444-1 assume !(1 == ~T3_E~0); 1326544#L1449-1 assume !(1 == ~T4_E~0); 1326984#L1454-1 assume !(1 == ~T5_E~0); 1326985#L1459-1 assume !(1 == ~T6_E~0); 1327586#L1464-1 assume !(1 == ~T7_E~0); 1327587#L1469-1 assume !(1 == ~T8_E~0); 1327680#L1474-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1327329#L1479-1 assume !(1 == ~T10_E~0); 1327330#L1484-1 assume !(1 == ~T11_E~0); 1327593#L1489-1 assume !(1 == ~T12_E~0); 1327197#L1494-1 assume !(1 == ~T13_E~0); 1327198#L1499-1 assume !(1 == ~E_M~0); 1327389#L1504-1 assume !(1 == ~E_1~0); 1327390#L1509-1 assume !(1 == ~E_2~0); 1328112#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1327726#L1519-1 assume !(1 == ~E_4~0); 1327727#L1524-1 assume !(1 == ~E_5~0); 1328474#L1529-1 assume !(1 == ~E_6~0); 1328475#L1534-1 assume !(1 == ~E_7~0); 1326341#L1539-1 assume !(1 == ~E_8~0); 1326342#L1544-1 assume !(1 == ~E_9~0); 1326762#L1549-1 assume !(1 == ~E_10~0); 1328422#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 1328420#L1559-1 assume !(1 == ~E_12~0); 1328158#L1564-1 assume !(1 == ~E_13~0); 1328159#L1935-1 [2021-11-07 07:30:28,229 INFO L793 eck$LassoCheckResult]: Loop: 1328159#L1935-1 assume !false; 1436527#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 1436523#L1261 assume !false; 1436521#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1436459#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1436448#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1436442#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1436432#L1074 assume !(0 != eval_~tmp~0); 1436433#L1276 start_simulation_~kernel_st~0 := 2; 1517130#L902-1 start_simulation_~kernel_st~0 := 3; 1517129#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1515983#L1286-4 assume !(0 == ~T1_E~0); 1515643#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1515642#L1296-3 assume !(0 == ~T3_E~0); 1515640#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1515639#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1515637#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1515635#L1316-3 assume !(0 == ~T7_E~0); 1515634#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1515633#L1326-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1515631#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1515629#L1336-3 assume !(0 == ~T11_E~0); 1515627#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1515625#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1515623#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1515622#L1356-3 assume !(0 == ~E_1~0); 1515621#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1515618#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1515616#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1515614#L1376-3 assume !(0 == ~E_5~0); 1515612#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1515610#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1515609#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1515608#L1396-3 assume !(0 == ~E_9~0); 1515607#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1515606#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1515605#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1515604#L1416-3 assume !(0 == ~E_13~0); 1515603#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1515602#L635-45 assume !(1 == ~m_pc~0); 1515601#L635-47 is_master_triggered_~__retres1~0 := 0; 1515600#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1515599#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1515598#L1598-45 assume !(0 != activate_threads_~tmp~1); 1515597#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1515596#L654-45 assume 1 == ~t1_pc~0; 1515595#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1515433#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1515431#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1515427#L1606-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1515426#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1515425#L673-45 assume !(1 == ~t2_pc~0); 1503611#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 1515424#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1515423#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1515422#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1515421#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1515420#L692-45 assume !(1 == ~t3_pc~0); 1515419#L692-47 is_transmit3_triggered_~__retres1~3 := 0; 1515417#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1515415#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1515416#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1515574#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1515572#L711-45 assume !(1 == ~t4_pc~0); 1515570#L711-47 is_transmit4_triggered_~__retres1~4 := 0; 1515568#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1515566#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1515564#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1515562#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1515404#L730-45 assume !(1 == ~t5_pc~0); 1515403#L730-47 is_transmit5_triggered_~__retres1~5 := 0; 1515507#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1515505#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1515502#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1514594#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1514533#L749-45 assume !(1 == ~t6_pc~0); 1514531#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 1514529#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1514527#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1514525#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1514524#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1437299#L768-45 assume !(1 == ~t7_pc~0); 1437296#L768-47 is_transmit7_triggered_~__retres1~7 := 0; 1437294#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1437292#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1437290#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1437288#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1437285#L787-45 assume !(1 == ~t8_pc~0); 1437281#L787-47 is_transmit8_triggered_~__retres1~8 := 0; 1437279#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1437277#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1437275#L1662-45 assume !(0 != activate_threads_~tmp___7~0); 1437272#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1437270#L806-45 assume !(1 == ~t9_pc~0); 1436321#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 1437265#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1437263#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 1437261#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 1437259#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1437256#L825-45 assume 1 == ~t10_pc~0; 1437253#L826-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 1437245#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1437239#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 1437231#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 1437223#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1437210#L844-45 assume !(1 == ~t11_pc~0); 1431152#L844-47 is_transmit11_triggered_~__retres1~11 := 0; 1437198#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1437189#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 1437181#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 1437173#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1437164#L863-45 assume 1 == ~t12_pc~0; 1437153#L864-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 1437146#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1437139#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 1437131#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 1437124#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 1437116#L882-45 assume !(1 == ~t13_pc~0); 1437110#L882-47 is_transmit13_triggered_~__retres1~13 := 0; 1437100#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 1437091#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 1437083#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 1437076#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 1437068#L1434-3 assume !(1 == ~T1_E~0); 1437059#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1437050#L1444-3 assume !(1 == ~T3_E~0); 1437043#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1437036#L1454-3 assume !(1 == ~T5_E~0); 1437029#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1437023#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1437016#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1437008#L1474-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1437000#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1436992#L1484-3 assume !(1 == ~T11_E~0); 1436984#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1436977#L1494-3 assume !(1 == ~T13_E~0); 1436969#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1436960#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1436952#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1436944#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1436936#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1436927#L1524-3 assume !(1 == ~E_5~0); 1436918#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1436909#L1534-3 assume !(1 == ~E_7~0); 1436904#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1436898#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1436889#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1436881#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1436876#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1436871#L1564-3 assume !(1 == ~E_13~0); 1436865#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1436802#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1436788#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1436782#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 1436773#L1954 assume !(0 == start_simulation_~tmp~3); 1436768#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1436697#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1436685#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1436677#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 1436669#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1436661#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 1436654#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 1436646#L1967 assume !(0 != start_simulation_~tmp___0~1); 1328159#L1935-1 [2021-11-07 07:30:28,230 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:30:28,230 INFO L85 PathProgramCache]: Analyzing trace with hash -1022309189, now seen corresponding path program 1 times [2021-11-07 07:30:28,230 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:30:28,230 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1275815504] [2021-11-07 07:30:28,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:30:28,231 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:30:28,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:30:28,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:30:28,307 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:30:28,307 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1275815504] [2021-11-07 07:30:28,307 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1275815504] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:30:28,308 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:30:28,308 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 07:30:28,308 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1092210889] [2021-11-07 07:30:28,309 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:30:28,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:30:28,309 INFO L85 PathProgramCache]: Analyzing trace with hash -499051905, now seen corresponding path program 1 times [2021-11-07 07:30:28,310 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:30:28,310 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1108331357] [2021-11-07 07:30:28,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:30:28,310 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:30:28,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:30:28,360 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:30:28,360 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:30:28,361 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1108331357] [2021-11-07 07:30:28,361 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1108331357] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:30:28,361 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:30:28,361 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:30:28,362 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [621912612] [2021-11-07 07:30:28,362 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:30:28,362 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:30:28,363 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:30:28,363 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:30:28,363 INFO L87 Difference]: Start difference. First operand 191402 states and 266292 transitions. cyclomatic complexity: 74894 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:30:29,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:30:29,905 INFO L93 Difference]: Finished difference Result 191402 states and 265906 transitions. [2021-11-07 07:30:29,929 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:30:29,929 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191402 states and 265906 transitions. [2021-11-07 07:30:30,749 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 191040 [2021-11-07 07:30:31,235 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191402 states to 191402 states and 265906 transitions. [2021-11-07 07:30:31,235 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 191402 [2021-11-07 07:30:31,342 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 191402 [2021-11-07 07:30:31,342 INFO L73 IsDeterministic]: Start isDeterministic. Operand 191402 states and 265906 transitions. [2021-11-07 07:30:31,425 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:30:31,425 INFO L681 BuchiCegarLoop]: Abstraction has 191402 states and 265906 transitions. [2021-11-07 07:30:31,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191402 states and 265906 transitions. [2021-11-07 07:30:34,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191402 to 191402. [2021-11-07 07:30:34,202 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 191402 states, 191402 states have (on average 1.3892540307833774) internal successors, (265906), 191401 states have internal predecessors, (265906), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:30:34,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191402 states to 191402 states and 265906 transitions. [2021-11-07 07:30:34,809 INFO L704 BuchiCegarLoop]: Abstraction has 191402 states and 265906 transitions. [2021-11-07 07:30:34,809 INFO L587 BuchiCegarLoop]: Abstraction has 191402 states and 265906 transitions. [2021-11-07 07:30:34,809 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-11-07 07:30:34,809 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 191402 states and 265906 transitions. [2021-11-07 07:30:35,332 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 191040 [2021-11-07 07:30:35,332 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:30:35,332 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:30:35,338 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:30:35,338 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:30:35,339 INFO L791 eck$LassoCheckResult]: Stem: 1709916#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(20);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1709917#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1709648#L1898 havoc start_simulation_#t~ret39, start_simulation_#t~ret40, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1709649#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 1709590#L909-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1709591#L914-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1709839#L919-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1709877#L924-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1710796#L929-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1710797#L934-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1710950#L939-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1710951#L944-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1709654#L949-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1709655#L954-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1711004#L959-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1710188#L964-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1710189#L969-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1710864#L974-1 assume !(0 == ~M_E~0); 1710529#L1286-1 assume !(0 == ~T1_E~0); 1709561#L1291-1 assume !(0 == ~T2_E~0); 1709562#L1296-1 assume !(0 == ~T3_E~0); 1710286#L1301-1 assume !(0 == ~T4_E~0); 1710287#L1306-1 assume !(0 == ~T5_E~0); 1710876#L1311-1 assume !(0 == ~T6_E~0); 1709518#L1316-1 assume !(0 == ~T7_E~0); 1709519#L1321-1 assume !(0 == ~T8_E~0); 1710310#L1326-1 assume !(0 == ~T9_E~0); 1709335#L1331-1 assume !(0 == ~T10_E~0); 1709049#L1336-1 assume !(0 == ~T11_E~0); 1709050#L1341-1 assume !(0 == ~T12_E~0); 1709099#L1346-1 assume !(0 == ~T13_E~0); 1709100#L1351-1 assume !(0 == ~E_M~0); 1709463#L1356-1 assume !(0 == ~E_1~0); 1709464#L1361-1 assume !(0 == ~E_2~0); 1711258#L1366-1 assume !(0 == ~E_3~0); 1709510#L1371-1 assume !(0 == ~E_4~0); 1709511#L1376-1 assume !(0 == ~E_5~0); 1710356#L1381-1 assume !(0 == ~E_6~0); 1710357#L1386-1 assume !(0 == ~E_7~0); 1711309#L1391-1 assume !(0 == ~E_8~0); 1711344#L1396-1 assume !(0 == ~E_9~0); 1710220#L1401-1 assume !(0 == ~E_10~0); 1710221#L1406-1 assume !(0 == ~E_11~0); 1710564#L1411-1 assume !(0 == ~E_12~0); 1710565#L1416-1 assume !(0 == ~E_13~0); 1710144#L1421-1 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1709976#L635 assume !(1 == ~m_pc~0); 1709119#L635-2 is_master_triggered_~__retres1~0 := 0; 1709120#L646 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1709460#L647 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1710105#L1598 assume !(0 != activate_threads_~tmp~1); 1709293#L1598-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1709294#L654 assume !(1 == ~t1_pc~0); 1709999#L654-2 is_transmit1_triggered_~__retres1~1 := 0; 1711006#L665 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1711305#L666 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1710084#L1606 assume !(0 != activate_threads_~tmp___0~0); 1710085#L1606-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1709340#L673 assume !(1 == ~t2_pc~0); 1709341#L673-2 is_transmit2_triggered_~__retres1~2 := 0; 1710527#L684 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1710528#L685 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1711376#L1614 assume !(0 != activate_threads_~tmp___1~0); 1711391#L1614-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1710167#L692 assume !(1 == ~t3_pc~0); 1709977#L692-2 is_transmit3_triggered_~__retres1~3 := 0; 1709978#L703 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1709843#L704 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1709809#L1622 assume !(0 != activate_threads_~tmp___2~0); 1709810#L1622-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1709361#L711 assume !(1 == ~t4_pc~0); 1709362#L711-2 is_transmit4_triggered_~__retres1~4 := 0; 1710997#L722 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1710329#L723 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1709072#L1630 assume !(0 != activate_threads_~tmp___3~0); 1709073#L1630-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1711366#L730 assume !(1 == ~t5_pc~0); 1710455#L730-2 is_transmit5_triggered_~__retres1~5 := 0; 1709251#L741 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1709252#L742 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1709372#L1638 assume !(0 != activate_threads_~tmp___4~0); 1709373#L1638-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1709721#L749 assume !(1 == ~t6_pc~0); 1709260#L749-2 is_transmit6_triggered_~__retres1~6 := 0; 1709261#L760 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1709690#L761 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1709691#L1646 assume !(0 != activate_threads_~tmp___5~0); 1709908#L1646-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1709056#L768 assume !(1 == ~t7_pc~0); 1709057#L768-2 is_transmit7_triggered_~__retres1~7 := 0; 1711055#L779 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1709286#L780 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1709287#L1654 assume !(0 != activate_threads_~tmp___6~0); 1710406#L1654-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1709520#L787 assume !(1 == ~t8_pc~0); 1709521#L787-2 is_transmit8_triggered_~__retres1~8 := 0; 1711134#L798 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1711280#L799 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1711401#L1662 assume !(0 != activate_threads_~tmp___7~0); 1709097#L1662-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1709098#L806 assume !(1 == ~t9_pc~0); 1709888#L806-2 is_transmit9_triggered_~__retres1~9 := 0; 1709132#L817 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1709133#L818 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 1709370#L1670 assume !(0 != activate_threads_~tmp___8~0); 1709371#L1670-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1710804#L825 assume !(1 == ~t10_pc~0); 1710805#L825-2 is_transmit10_triggered_~__retres1~10 := 0; 1710345#L836 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1710346#L837 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 1709461#L1678 assume !(0 != activate_threads_~tmp___9~0); 1709462#L1678-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1710049#L844 assume !(1 == ~t11_pc~0); 1710050#L844-2 is_transmit11_triggered_~__retres1~11 := 0; 1710288#L855 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1710112#L856 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 1710113#L1686 assume !(0 != activate_threads_~tmp___10~0); 1710793#L1686-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1710794#L863 assume !(1 == ~t12_pc~0); 1709235#L863-2 is_transmit12_triggered_~__retres1~12 := 0; 1709236#L874 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1709449#L875 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 1710912#L1694 assume !(0 != activate_threads_~tmp___11~0); 1710913#L1694-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 1710185#L882 assume !(1 == ~t13_pc~0); 1710187#L882-2 is_transmit13_triggered_~__retres1~13 := 0; 1710495#L893 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 1711197#L894 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 1710867#L1702 assume !(0 != activate_threads_~tmp___12~0); 1710481#L1702-2 assume !(1 == ~M_E~0); 1710482#L1434-1 assume !(1 == ~T1_E~0); 1711090#L1439-1 assume !(1 == ~T2_E~0); 1709354#L1444-1 assume !(1 == ~T3_E~0); 1709355#L1449-1 assume !(1 == ~T4_E~0); 1709807#L1454-1 assume !(1 == ~T5_E~0); 1709808#L1459-1 assume !(1 == ~T6_E~0); 1710407#L1464-1 assume !(1 == ~T7_E~0); 1710408#L1469-1 assume !(1 == ~T8_E~0); 1710498#L1474-1 assume !(1 == ~T9_E~0); 1710145#L1479-1 assume !(1 == ~T10_E~0); 1710146#L1484-1 assume !(1 == ~T11_E~0); 1710415#L1489-1 assume !(1 == ~T12_E~0); 1710015#L1494-1 assume !(1 == ~T13_E~0); 1710016#L1499-1 assume !(1 == ~E_M~0); 1710205#L1504-1 assume !(1 == ~E_1~0); 1710206#L1509-1 assume !(1 == ~E_2~0); 1710932#L1514-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1710540#L1519-1 assume !(1 == ~E_4~0); 1710541#L1524-1 assume !(1 == ~E_5~0); 1711281#L1529-1 assume !(1 == ~E_6~0); 1711282#L1534-1 assume !(1 == ~E_7~0); 1709154#L1539-1 assume !(1 == ~E_8~0); 1709155#L1544-1 assume !(1 == ~E_9~0); 1709578#L1549-1 assume !(1 == ~E_10~0); 1711237#L1554-1 assume 1 == ~E_11~0;~E_11~0 := 2; 1711234#L1559-1 assume !(1 == ~E_12~0); 1710983#L1564-1 assume !(1 == ~E_13~0); 1710984#L1935-1 [2021-11-07 07:30:35,340 INFO L793 eck$LassoCheckResult]: Loop: 1710984#L1935-1 assume !false; 1827937#L1936 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_#t~nondet16, eval_~tmp_ndt_7~0, eval_#t~nondet17, eval_~tmp_ndt_8~0, eval_#t~nondet18, eval_~tmp_ndt_9~0, eval_#t~nondet19, eval_~tmp_ndt_10~0, eval_#t~nondet20, eval_~tmp_ndt_11~0, eval_#t~nondet21, eval_~tmp_ndt_12~0, eval_#t~nondet22, eval_~tmp_ndt_13~0, eval_#t~nondet23, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 1827932#L1261 assume !false; 1827930#L1070 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1827909#L987 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1827902#L1059 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1827900#L1060 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1827897#L1074 assume !(0 != eval_~tmp~0); 1827898#L1276 start_simulation_~kernel_st~0 := 2; 1890411#L902-1 start_simulation_~kernel_st~0 := 3; 1890408#L1286-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1890406#L1286-4 assume !(0 == ~T1_E~0); 1890405#L1291-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1890404#L1296-3 assume !(0 == ~T3_E~0); 1890403#L1301-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1890402#L1306-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1890401#L1311-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1890400#L1316-3 assume !(0 == ~T7_E~0); 1890399#L1321-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1890398#L1326-3 assume !(0 == ~T9_E~0); 1890396#L1331-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1890394#L1336-3 assume !(0 == ~T11_E~0); 1890393#L1341-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1890392#L1346-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1890391#L1351-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1890389#L1356-3 assume !(0 == ~E_1~0); 1890388#L1361-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1890387#L1366-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1890386#L1371-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1890385#L1376-3 assume !(0 == ~E_5~0); 1890384#L1381-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1890383#L1386-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1890381#L1391-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1890380#L1396-3 assume !(0 == ~E_9~0); 1890379#L1401-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1890378#L1406-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1890376#L1411-3 assume 0 == ~E_12~0;~E_12~0 := 1; 1890374#L1416-3 assume !(0 == ~E_13~0); 1890372#L1421-3 havoc activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_#t~ret36, activate_threads_#t~ret37, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1890370#L635-45 assume !(1 == ~m_pc~0); 1890368#L635-47 is_master_triggered_~__retres1~0 := 0; 1890366#L646-15 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1890364#L647-15 activate_threads_#t~ret24 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1890362#L1598-45 assume !(0 != activate_threads_~tmp~1); 1890360#L1598-47 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1890358#L654-45 assume 1 == ~t1_pc~0; 1890356#L655-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1890357#L665-15 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1890382#L666-15 activate_threads_#t~ret25 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1890347#L1606-45 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1890345#L1606-47 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1890343#L673-45 assume !(1 == ~t2_pc~0); 1884852#L673-47 is_transmit2_triggered_~__retres1~2 := 0; 1890340#L684-15 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1890338#L685-15 activate_threads_#t~ret26 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1890336#L1614-45 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1890334#L1614-47 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1890332#L692-45 assume 1 == ~t3_pc~0; 1890329#L693-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1890327#L703-15 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1890325#L704-15 activate_threads_#t~ret27 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1890323#L1622-45 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1890321#L1622-47 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1890319#L711-45 assume !(1 == ~t4_pc~0); 1890317#L711-47 is_transmit4_triggered_~__retres1~4 := 0; 1890315#L722-15 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1890313#L723-15 activate_threads_#t~ret28 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1890310#L1630-45 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1890308#L1630-47 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1890306#L730-45 assume !(1 == ~t5_pc~0); 1890303#L730-47 is_transmit5_triggered_~__retres1~5 := 0; 1890301#L741-15 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1890297#L742-15 activate_threads_#t~ret29 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1890295#L1638-45 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1890293#L1638-47 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1890291#L749-45 assume !(1 == ~t6_pc~0); 1876341#L749-47 is_transmit6_triggered_~__retres1~6 := 0; 1897009#L760-15 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1897008#L761-15 activate_threads_#t~ret30 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1890188#L1646-45 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1890097#L1646-47 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1709631#L768-45 assume !(1 == ~t7_pc~0); 1709632#L768-47 is_transmit7_triggered_~__retres1~7 := 0; 1710865#L779-15 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1710637#L780-15 activate_threads_#t~ret31 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1710638#L1654-45 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1710685#L1654-47 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1710686#L787-45 assume !(1 == ~t8_pc~0); 1710899#L787-47 is_transmit8_triggered_~__retres1~8 := 0; 1709782#L798-15 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1709783#L799-15 activate_threads_#t~ret32 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1710202#L1662-45 assume !(0 != activate_threads_~tmp___7~0); 1710203#L1662-47 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1710548#L806-45 assume !(1 == ~t9_pc~0); 1828342#L806-47 is_transmit9_triggered_~__retres1~9 := 0; 1828340#L817-15 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1828338#L818-15 activate_threads_#t~ret33 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 1828336#L1670-45 assume !(0 != activate_threads_~tmp___8~0); 1828334#L1670-47 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1828331#L825-45 assume !(1 == ~t10_pc~0); 1828329#L825-47 is_transmit10_triggered_~__retres1~10 := 0; 1828326#L836-15 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1828324#L837-15 activate_threads_#t~ret34 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 1828322#L1678-45 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 1828320#L1678-47 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1828319#L844-45 assume !(1 == ~t11_pc~0); 1803999#L844-47 is_transmit11_triggered_~__retres1~11 := 0; 1828316#L855-15 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1828314#L856-15 activate_threads_#t~ret35 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 1828312#L1686-45 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 1828310#L1686-47 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1828307#L863-45 assume !(1 == ~t12_pc~0); 1828305#L863-47 is_transmit12_triggered_~__retres1~12 := 0; 1828302#L874-15 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1828300#L875-15 activate_threads_#t~ret36 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret36;havoc activate_threads_#t~ret36; 1828298#L1694-45 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 1828295#L1694-47 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 1828291#L882-45 assume !(1 == ~t13_pc~0); 1828289#L882-47 is_transmit13_triggered_~__retres1~13 := 0; 1828287#L893-15 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 1828285#L894-15 activate_threads_#t~ret37 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret37;havoc activate_threads_#t~ret37; 1828283#L1702-45 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 1828281#L1702-47 assume 1 == ~M_E~0;~M_E~0 := 2; 1828279#L1434-3 assume !(1 == ~T1_E~0); 1828277#L1439-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1828275#L1444-3 assume !(1 == ~T3_E~0); 1828273#L1449-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1828271#L1454-3 assume !(1 == ~T5_E~0); 1828269#L1459-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1828267#L1464-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1828265#L1469-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1828263#L1474-3 assume !(1 == ~T9_E~0); 1828261#L1479-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1828259#L1484-3 assume !(1 == ~T11_E~0); 1828257#L1489-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1828255#L1494-3 assume !(1 == ~T13_E~0); 1828253#L1499-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1828251#L1504-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1828249#L1509-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1828247#L1514-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1828245#L1519-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1828243#L1524-3 assume !(1 == ~E_5~0); 1828241#L1529-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1828239#L1534-3 assume !(1 == ~E_7~0); 1828237#L1539-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1828235#L1544-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1828233#L1549-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1828232#L1554-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1828231#L1559-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1828230#L1564-3 assume !(1 == ~E_13~0); 1828229#L1569-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1828205#L987-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1828198#L1059-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1828196#L1060-1 start_simulation_#t~ret39 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret39;havoc start_simulation_#t~ret39; 1828193#L1954 assume !(0 == start_simulation_~tmp~3); 1828190#L1954-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret38, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1828171#L987-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1828163#L1059-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1828161#L1060-2 stop_simulation_#t~ret38 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret38;havoc stop_simulation_#t~ret38; 1828159#L1909 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1828156#L1916 stop_simulation_#res := stop_simulation_~__retres2~0; 1828154#L1917 start_simulation_#t~ret40 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret40;havoc start_simulation_#t~ret40; 1828152#L1967 assume !(0 != start_simulation_~tmp___0~1); 1710984#L1935-1 [2021-11-07 07:30:35,340 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:30:35,340 INFO L85 PathProgramCache]: Analyzing trace with hash 1583714365, now seen corresponding path program 1 times [2021-11-07 07:30:35,340 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:30:35,340 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2102700997] [2021-11-07 07:30:35,340 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:30:35,341 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:30:35,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:30:35,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:30:35,392 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:30:35,392 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2102700997] [2021-11-07 07:30:35,392 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2102700997] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:30:35,392 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:30:35,392 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 07:30:35,393 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1992943859] [2021-11-07 07:30:35,393 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:30:35,393 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:30:35,394 INFO L85 PathProgramCache]: Analyzing trace with hash -203976742, now seen corresponding path program 1 times [2021-11-07 07:30:35,394 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:30:35,394 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [552970205] [2021-11-07 07:30:35,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:30:35,394 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:30:35,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:30:35,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:30:35,430 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:30:35,430 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [552970205] [2021-11-07 07:30:35,430 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [552970205] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:30:35,430 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:30:35,430 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:30:35,431 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [236931541] [2021-11-07 07:30:35,431 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:30:35,431 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:30:35,431 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:30:35,432 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:30:35,432 INFO L87 Difference]: Start difference. First operand 191402 states and 265906 transitions. cyclomatic complexity: 74508 Second operand has 3 states, 3 states have (on average 52.333333333333336) internal successors, (157), 2 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:30:36,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:30:36,992 INFO L93 Difference]: Finished difference Result 191402 states and 263983 transitions. [2021-11-07 07:30:36,993 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:30:36,993 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191402 states and 263983 transitions. [2021-11-07 07:30:37,951 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 191040