./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.11.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 47ea0209 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58ff9886-207a-4c22-b2c5-4c34ba296e95/bin/uautomizer-AkOaLMaTGY/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58ff9886-207a-4c22-b2c5-4c34ba296e95/bin/uautomizer-AkOaLMaTGY/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58ff9886-207a-4c22-b2c5-4c34ba296e95/bin/uautomizer-AkOaLMaTGY/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58ff9886-207a-4c22-b2c5-4c34ba296e95/bin/uautomizer-AkOaLMaTGY/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.11.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58ff9886-207a-4c22-b2c5-4c34ba296e95/bin/uautomizer-AkOaLMaTGY/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58ff9886-207a-4c22-b2c5-4c34ba296e95/bin/uautomizer-AkOaLMaTGY --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 940a677bfde7dbbc79e036121bd0ec6fd3518c0f58a02d336e5d42fafb098792 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-47ea020 [2021-11-07 07:22:12,909 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-07 07:22:12,912 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-07 07:22:12,958 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-07 07:22:12,959 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-07 07:22:12,961 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-07 07:22:12,963 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-07 07:22:12,966 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-07 07:22:12,968 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-07 07:22:12,969 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-07 07:22:12,971 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-07 07:22:12,973 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-07 07:22:12,973 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-07 07:22:12,975 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-07 07:22:12,977 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-07 07:22:12,979 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-07 07:22:12,980 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-07 07:22:12,981 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-07 07:22:12,984 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-07 07:22:12,987 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-07 07:22:12,990 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-07 07:22:12,992 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-07 07:22:12,994 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-07 07:22:12,995 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-07 07:22:13,000 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-07 07:22:13,000 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-07 07:22:13,001 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-07 07:22:13,002 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-07 07:22:13,003 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-07 07:22:13,004 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-07 07:22:13,005 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-07 07:22:13,006 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-07 07:22:13,007 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-07 07:22:13,009 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-07 07:22:13,010 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-07 07:22:13,011 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-07 07:22:13,012 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-07 07:22:13,012 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-07 07:22:13,013 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-07 07:22:13,014 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-07 07:22:13,015 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-07 07:22:13,016 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58ff9886-207a-4c22-b2c5-4c34ba296e95/bin/uautomizer-AkOaLMaTGY/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-07 07:22:13,049 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-07 07:22:13,050 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-07 07:22:13,050 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-07 07:22:13,051 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-07 07:22:13,052 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-07 07:22:13,052 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-07 07:22:13,053 INFO L138 SettingsManager]: * Use SBE=true [2021-11-07 07:22:13,053 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-07 07:22:13,053 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-07 07:22:13,053 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-07 07:22:13,054 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-07 07:22:13,054 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-07 07:22:13,054 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-07 07:22:13,055 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-07 07:22:13,055 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-07 07:22:13,055 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-07 07:22:13,056 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-07 07:22:13,056 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-07 07:22:13,056 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-07 07:22:13,057 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-07 07:22:13,057 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-07 07:22:13,057 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-07 07:22:13,057 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-07 07:22:13,058 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-07 07:22:13,058 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-07 07:22:13,058 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-07 07:22:13,059 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-07 07:22:13,059 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-07 07:22:13,059 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-07 07:22:13,060 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-07 07:22:13,060 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-07 07:22:13,060 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-07 07:22:13,062 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-07 07:22:13,062 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58ff9886-207a-4c22-b2c5-4c34ba296e95/bin/uautomizer-AkOaLMaTGY/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58ff9886-207a-4c22-b2c5-4c34ba296e95/bin/uautomizer-AkOaLMaTGY Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 940a677bfde7dbbc79e036121bd0ec6fd3518c0f58a02d336e5d42fafb098792 [2021-11-07 07:22:13,367 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-07 07:22:13,400 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-07 07:22:13,403 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-07 07:22:13,405 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-07 07:22:13,406 INFO L275 PluginConnector]: CDTParser initialized [2021-11-07 07:22:13,407 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58ff9886-207a-4c22-b2c5-4c34ba296e95/bin/uautomizer-AkOaLMaTGY/../../sv-benchmarks/c/systemc/transmitter.11.cil.c [2021-11-07 07:22:13,491 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58ff9886-207a-4c22-b2c5-4c34ba296e95/bin/uautomizer-AkOaLMaTGY/data/050924294/c0b9d7aa61824a659b06e92471c957b8/FLAG8a386fa23 [2021-11-07 07:22:14,043 INFO L306 CDTParser]: Found 1 translation units. [2021-11-07 07:22:14,044 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58ff9886-207a-4c22-b2c5-4c34ba296e95/sv-benchmarks/c/systemc/transmitter.11.cil.c [2021-11-07 07:22:14,063 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58ff9886-207a-4c22-b2c5-4c34ba296e95/bin/uautomizer-AkOaLMaTGY/data/050924294/c0b9d7aa61824a659b06e92471c957b8/FLAG8a386fa23 [2021-11-07 07:22:14,366 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58ff9886-207a-4c22-b2c5-4c34ba296e95/bin/uautomizer-AkOaLMaTGY/data/050924294/c0b9d7aa61824a659b06e92471c957b8 [2021-11-07 07:22:14,368 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-07 07:22:14,370 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-07 07:22:14,374 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-07 07:22:14,374 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-07 07:22:14,377 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-07 07:22:14,378 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.11 07:22:14" (1/1) ... [2021-11-07 07:22:14,380 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2f2a6676 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:22:14, skipping insertion in model container [2021-11-07 07:22:14,380 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.11 07:22:14" (1/1) ... [2021-11-07 07:22:14,389 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-07 07:22:14,478 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-07 07:22:14,648 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58ff9886-207a-4c22-b2c5-4c34ba296e95/sv-benchmarks/c/systemc/transmitter.11.cil.c[706,719] [2021-11-07 07:22:14,801 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-07 07:22:14,820 INFO L203 MainTranslator]: Completed pre-run [2021-11-07 07:22:14,844 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58ff9886-207a-4c22-b2c5-4c34ba296e95/sv-benchmarks/c/systemc/transmitter.11.cil.c[706,719] [2021-11-07 07:22:14,931 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-07 07:22:14,974 INFO L208 MainTranslator]: Completed translation [2021-11-07 07:22:14,976 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:22:14 WrapperNode [2021-11-07 07:22:14,976 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-07 07:22:14,978 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-07 07:22:14,978 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-07 07:22:14,978 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-07 07:22:14,989 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:22:14" (1/1) ... [2021-11-07 07:22:15,013 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:22:14" (1/1) ... [2021-11-07 07:22:15,159 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-07 07:22:15,160 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-07 07:22:15,160 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-07 07:22:15,160 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-07 07:22:15,170 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:22:14" (1/1) ... [2021-11-07 07:22:15,171 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:22:14" (1/1) ... [2021-11-07 07:22:15,183 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:22:14" (1/1) ... [2021-11-07 07:22:15,183 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:22:14" (1/1) ... [2021-11-07 07:22:15,240 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:22:14" (1/1) ... [2021-11-07 07:22:15,296 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:22:14" (1/1) ... [2021-11-07 07:22:15,303 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:22:14" (1/1) ... [2021-11-07 07:22:15,331 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-07 07:22:15,332 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-07 07:22:15,332 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-07 07:22:15,332 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-07 07:22:15,336 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:22:14" (1/1) ... [2021-11-07 07:22:15,344 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 07:22:15,357 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58ff9886-207a-4c22-b2c5-4c34ba296e95/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 07:22:15,374 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58ff9886-207a-4c22-b2c5-4c34ba296e95/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 07:22:15,396 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_58ff9886-207a-4c22-b2c5-4c34ba296e95/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-07 07:22:15,433 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-07 07:22:15,434 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-07 07:22:15,434 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-07 07:22:15,434 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-07 07:22:18,036 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-07 07:22:18,037 INFO L299 CfgBuilder]: Removed 463 assume(true) statements. [2021-11-07 07:22:18,041 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.11 07:22:18 BoogieIcfgContainer [2021-11-07 07:22:18,042 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-07 07:22:18,046 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-07 07:22:18,047 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-07 07:22:18,050 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-07 07:22:18,051 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-07 07:22:18,051 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 07.11 07:22:14" (1/3) ... [2021-11-07 07:22:18,053 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@76028ef2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.11 07:22:18, skipping insertion in model container [2021-11-07 07:22:18,053 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-07 07:22:18,053 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 07:22:14" (2/3) ... [2021-11-07 07:22:18,053 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@76028ef2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.11 07:22:18, skipping insertion in model container [2021-11-07 07:22:18,054 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-07 07:22:18,054 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.11 07:22:18" (3/3) ... [2021-11-07 07:22:18,056 INFO L389 chiAutomizerObserver]: Analyzing ICFG transmitter.11.cil.c [2021-11-07 07:22:18,127 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-07 07:22:18,128 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-07 07:22:18,128 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-07 07:22:18,128 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-07 07:22:18,128 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-07 07:22:18,128 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-07 07:22:18,129 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-07 07:22:18,129 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-07 07:22:18,199 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1451 states, 1450 states have (on average 1.516551724137931) internal successors, (2199), 1450 states have internal predecessors, (2199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:18,288 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1302 [2021-11-07 07:22:18,289 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:22:18,289 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:22:18,311 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:18,311 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:18,311 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-07 07:22:18,316 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1451 states, 1450 states have (on average 1.516551724137931) internal successors, (2199), 1450 states have internal predecessors, (2199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:18,379 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1302 [2021-11-07 07:22:18,379 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:22:18,379 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:22:18,387 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:18,388 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:18,400 INFO L791 eck$LassoCheckResult]: Stem: 694#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1325#L-1true havoc main_#res;havoc main_~__retres1~13;havoc main_~__retres1~13;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 704#L1607true havoc start_simulation_#t~ret33, start_simulation_#t~ret34, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1269#L754true assume !(1 == ~m_i~0);~m_st~0 := 2; 858#L761-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 415#L766-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 358#L771-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 200#L776-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 21#L781-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1430#L786-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 44#L791-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 625#L796-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 595#L801-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 634#L806-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1305#L811-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 258#L816-1true assume !(0 == ~M_E~0); 1116#L1090-1true assume !(0 == ~T1_E~0); 1277#L1095-1true assume !(0 == ~T2_E~0); 764#L1100-1true assume !(0 == ~T3_E~0); 790#L1105-1true assume !(0 == ~T4_E~0); 154#L1110-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 377#L1115-1true assume !(0 == ~T6_E~0); 579#L1120-1true assume !(0 == ~T7_E~0); 1313#L1125-1true assume !(0 == ~T8_E~0); 1306#L1130-1true assume !(0 == ~T9_E~0); 788#L1135-1true assume !(0 == ~T10_E~0); 261#L1140-1true assume !(0 == ~T11_E~0); 718#L1145-1true assume !(0 == ~E_1~0); 760#L1150-1true assume 0 == ~E_2~0;~E_2~0 := 1; 365#L1155-1true assume !(0 == ~E_3~0); 1286#L1160-1true assume !(0 == ~E_4~0); 421#L1165-1true assume !(0 == ~E_5~0); 1045#L1170-1true assume !(0 == ~E_6~0); 1226#L1175-1true assume !(0 == ~E_7~0); 468#L1180-1true assume !(0 == ~E_8~0); 875#L1185-1true assume !(0 == ~E_9~0); 259#L1190-1true assume 0 == ~E_10~0;~E_10~0 := 1; 478#L1195-1true assume !(0 == ~E_11~0); 990#L1200-1true havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 372#L525true assume !(1 == ~m_pc~0); 62#L525-2true is_master_triggered_~__retres1~0 := 0; 986#L536true is_master_triggered_#res := is_master_triggered_~__retres1~0; 480#L537true activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 853#L1350true assume !(0 != activate_threads_~tmp~1); 250#L1350-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 516#L544true assume 1 == ~t1_pc~0; 403#L545true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 715#L555true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1434#L556true activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 165#L1358true assume !(0 != activate_threads_~tmp___0~0); 558#L1358-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 981#L563true assume !(1 == ~t2_pc~0); 705#L563-2true is_transmit2_triggered_~__retres1~2 := 0; 72#L574true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 554#L575true activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 297#L1366true assume !(0 != activate_threads_~tmp___1~0); 614#L1366-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 716#L582true assume 1 == ~t3_pc~0; 138#L583true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1187#L593true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1396#L594true activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1057#L1374true assume !(0 != activate_threads_~tmp___2~0); 107#L1374-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1348#L601true assume !(1 == ~t4_pc~0); 808#L601-2true is_transmit4_triggered_~__retres1~4 := 0; 378#L612true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 770#L613true activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 727#L1382true assume !(0 != activate_threads_~tmp___3~0); 1356#L1382-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1159#L620true assume 1 == ~t5_pc~0; 86#L621true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 631#L631true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 576#L632true activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1428#L1390true assume !(0 != activate_threads_~tmp___4~0); 1216#L1390-2true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1318#L639true assume 1 == ~t6_pc~0; 1121#L640true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 317#L650true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1061#L651true activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1212#L1398true assume !(0 != activate_threads_~tmp___5~0); 382#L1398-2true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 920#L658true assume !(1 == ~t7_pc~0); 513#L658-2true is_transmit7_triggered_~__retres1~7 := 0; 1233#L669true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 603#L670true activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 666#L1406true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 255#L1406-2true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 385#L677true assume 1 == ~t8_pc~0; 842#L678true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 145#L688true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1010#L689true activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 295#L1414true assume !(0 != activate_threads_~tmp___7~0); 843#L1414-2true havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 950#L696true assume !(1 == ~t9_pc~0); 566#L696-2true is_transmit9_triggered_~__retres1~9 := 0; 641#L707true is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 734#L708true activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 582#L1422true assume !(0 != activate_threads_~tmp___8~0); 768#L1422-2true havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1098#L715true assume 1 == ~t10_pc~0; 776#L716true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 656#L726true is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 560#L727true activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 745#L1430true assume !(0 != activate_threads_~tmp___9~0); 463#L1430-2true havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 142#L734true assume !(1 == ~t11_pc~0); 422#L734-2true is_transmit11_triggered_~__retres1~11 := 0; 471#L745true is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 484#L746true activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 15#L1438true assume !(0 != activate_threads_~tmp___10~0); 632#L1438-2true assume !(1 == ~M_E~0); 824#L1213-1true assume !(1 == ~T1_E~0); 937#L1218-1true assume !(1 == ~T2_E~0); 33#L1223-1true assume !(1 == ~T3_E~0); 448#L1228-1true assume !(1 == ~T4_E~0); 1217#L1233-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1408#L1238-1true assume !(1 == ~T6_E~0); 726#L1243-1true assume !(1 == ~T7_E~0); 1362#L1248-1true assume !(1 == ~T8_E~0); 774#L1253-1true assume !(1 == ~T9_E~0); 1062#L1258-1true assume !(1 == ~T10_E~0); 752#L1263-1true assume !(1 == ~T11_E~0); 1105#L1268-1true assume !(1 == ~E_1~0); 594#L1273-1true assume 1 == ~E_2~0;~E_2~0 := 2; 1198#L1278-1true assume !(1 == ~E_3~0); 316#L1283-1true assume !(1 == ~E_4~0); 1247#L1288-1true assume !(1 == ~E_5~0); 896#L1293-1true assume !(1 == ~E_6~0); 849#L1298-1true assume !(1 == ~E_7~0); 617#L1303-1true assume !(1 == ~E_8~0); 323#L1308-1true assume !(1 == ~E_9~0); 264#L1313-1true assume 1 == ~E_10~0;~E_10~0 := 2; 1331#L1318-1true assume !(1 == ~E_11~0); 1289#L1644-1true [2021-11-07 07:22:18,404 INFO L793 eck$LassoCheckResult]: Loop: 1289#L1644-1true assume !false; 664#L1645true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_~tmp~0;havoc eval_~tmp~0; 744#L1065true assume false; 845#L1080true start_simulation_~kernel_st~0 := 2; 741#L754-1true start_simulation_~kernel_st~0 := 3; 281#L1090-2true assume 0 == ~M_E~0;~M_E~0 := 1; 1100#L1090-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1334#L1095-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 953#L1100-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1210#L1105-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 197#L1110-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1050#L1115-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 359#L1120-3true assume !(0 == ~T7_E~0); 723#L1125-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1090#L1130-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1244#L1135-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 310#L1140-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 49#L1145-3true assume 0 == ~E_1~0;~E_1~0 := 1; 486#L1150-3true assume 0 == ~E_2~0;~E_2~0 := 1; 108#L1155-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1390#L1160-3true assume !(0 == ~E_4~0); 301#L1165-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1448#L1170-3true assume 0 == ~E_6~0;~E_6~0 := 1; 552#L1175-3true assume 0 == ~E_7~0;~E_7~0 := 1; 252#L1180-3true assume 0 == ~E_8~0;~E_8~0 := 1; 122#L1185-3true assume 0 == ~E_9~0;~E_9~0 := 1; 1249#L1190-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1070#L1195-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1446#L1200-3true havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 437#L525-36true assume 1 == ~m_pc~0; 1076#L526-12true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 171#L536-12true is_master_triggered_#res := is_master_triggered_~__retres1~0; 1321#L537-12true activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 331#L1350-36true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 551#L1350-38true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 283#L544-36true assume 1 == ~t1_pc~0; 771#L545-12true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 646#L555-12true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 217#L556-12true activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1227#L1358-36true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1041#L1358-38true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 886#L563-36true assume !(1 == ~t2_pc~0); 931#L563-38true is_transmit2_triggered_~__retres1~2 := 0; 47#L574-12true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 731#L575-12true activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1225#L1366-36true assume !(0 != activate_threads_~tmp___1~0); 447#L1366-38true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1333#L582-36true assume !(1 == ~t3_pc~0); 910#L582-38true is_transmit3_triggered_~__retres1~3 := 0; 497#L593-12true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1336#L594-12true activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 639#L1374-36true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 470#L1374-38true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 434#L601-36true assume 1 == ~t4_pc~0; 369#L602-12true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1424#L612-12true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1236#L613-12true activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1011#L1382-36true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1151#L1382-38true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 871#L620-36true assume !(1 == ~t5_pc~0); 1421#L620-38true is_transmit5_triggered_~__retres1~5 := 0; 708#L631-12true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 932#L632-12true activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 384#L1390-36true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 177#L1390-38true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 69#L639-36true assume 1 == ~t6_pc~0; 696#L640-12true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 88#L650-12true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 982#L651-12true activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 208#L1398-36true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 581#L1398-38true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1150#L658-36true assume !(1 == ~t7_pc~0); 74#L658-38true is_transmit7_triggered_~__retres1~7 := 0; 983#L669-12true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1022#L670-12true activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 64#L1406-36true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 691#L1406-38true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 907#L677-36true assume !(1 == ~t8_pc~0); 519#L677-38true is_transmit8_triggered_~__retres1~8 := 0; 615#L688-12true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1160#L689-12true activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1148#L1414-36true assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 540#L1414-38true havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1067#L696-36true assume 1 == ~t9_pc~0; 460#L697-12true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 806#L707-12true is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 97#L708-12true activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 984#L1422-36true assume !(0 != activate_threads_~tmp___8~0); 553#L1422-38true havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1222#L715-36true assume !(1 == ~t10_pc~0); 528#L715-38true is_transmit10_triggered_~__retres1~10 := 0; 16#L726-12true is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 125#L727-12true activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 4#L1430-36true assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 1028#L1430-38true havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 202#L734-36true assume 1 == ~t11_pc~0; 778#L735-12true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 212#L745-12true is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 450#L746-12true activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 12#L1438-36true assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 599#L1438-38true assume 1 == ~M_E~0;~M_E~0 := 2; 1073#L1213-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 689#L1218-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 229#L1223-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 732#L1228-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 337#L1233-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1234#L1238-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 495#L1243-3true assume !(1 == ~T7_E~0); 1009#L1248-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1369#L1253-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1018#L1258-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 218#L1263-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 967#L1268-3true assume 1 == ~E_1~0;~E_1~0 := 2; 989#L1273-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1422#L1278-3true assume 1 == ~E_3~0;~E_3~0 := 2; 992#L1283-3true assume !(1 == ~E_4~0); 419#L1288-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1256#L1293-3true assume 1 == ~E_6~0;~E_6~0 := 2; 330#L1298-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1110#L1303-3true assume 1 == ~E_8~0;~E_8~0 := 2; 662#L1308-3true assume 1 == ~E_9~0;~E_9~0 := 2; 328#L1313-3true assume 1 == ~E_10~0;~E_10~0 := 2; 1013#L1318-3true assume 1 == ~E_11~0;~E_11~0 := 2; 219#L1323-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 1397#L829-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 430#L891-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 814#L892-1true start_simulation_#t~ret33 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 1398#L1663true assume !(0 == start_simulation_~tmp~3); 846#L1663-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret32, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 580#L829-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 512#L891-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 682#L892-2true stop_simulation_#t~ret32 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret32;havoc stop_simulation_#t~ret32; 79#L1618true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 257#L1625true stop_simulation_#res := stop_simulation_~__retres2~0; 1270#L1626true start_simulation_#t~ret34 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret34;havoc start_simulation_#t~ret34; 1138#L1676true assume !(0 != start_simulation_~tmp___0~1); 1289#L1644-1true [2021-11-07 07:22:18,413 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:18,413 INFO L85 PathProgramCache]: Analyzing trace with hash 767245565, now seen corresponding path program 1 times [2021-11-07 07:22:18,425 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:18,425 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1863645839] [2021-11-07 07:22:18,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:18,427 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:18,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:18,754 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:18,755 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:18,756 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1863645839] [2021-11-07 07:22:18,758 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1863645839] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:18,758 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:18,758 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:18,762 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [83789493] [2021-11-07 07:22:18,772 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:22:18,776 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:18,777 INFO L85 PathProgramCache]: Analyzing trace with hash 458526836, now seen corresponding path program 1 times [2021-11-07 07:22:18,778 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:18,778 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [202867818] [2021-11-07 07:22:18,779 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:18,779 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:18,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:18,884 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:18,885 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:18,886 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [202867818] [2021-11-07 07:22:18,887 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [202867818] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:18,887 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:18,888 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 07:22:18,888 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [992683739] [2021-11-07 07:22:18,892 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:22:18,901 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:22:18,918 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:22:18,919 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:22:18,925 INFO L87 Difference]: Start difference. First operand has 1451 states, 1450 states have (on average 1.516551724137931) internal successors, (2199), 1450 states have internal predecessors, (2199), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 44.333333333333336) internal successors, (133), 3 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:19,044 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:22:19,044 INFO L93 Difference]: Finished difference Result 1451 states and 2167 transitions. [2021-11-07 07:22:19,044 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:22:19,046 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1451 states and 2167 transitions. [2021-11-07 07:22:19,063 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:19,090 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1451 states to 1446 states and 2162 transitions. [2021-11-07 07:22:19,092 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1446 [2021-11-07 07:22:19,095 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1446 [2021-11-07 07:22:19,096 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1446 states and 2162 transitions. [2021-11-07 07:22:19,112 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:22:19,112 INFO L681 BuchiCegarLoop]: Abstraction has 1446 states and 2162 transitions. [2021-11-07 07:22:19,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1446 states and 2162 transitions. [2021-11-07 07:22:19,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1446 to 1446. [2021-11-07 07:22:19,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1446 states, 1446 states have (on average 1.4951590594744122) internal successors, (2162), 1445 states have internal predecessors, (2162), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:19,227 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1446 states to 1446 states and 2162 transitions. [2021-11-07 07:22:19,228 INFO L704 BuchiCegarLoop]: Abstraction has 1446 states and 2162 transitions. [2021-11-07 07:22:19,228 INFO L587 BuchiCegarLoop]: Abstraction has 1446 states and 2162 transitions. [2021-11-07 07:22:19,229 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-07 07:22:19,229 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1446 states and 2162 transitions. [2021-11-07 07:22:19,244 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:19,244 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:22:19,244 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:22:19,249 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:19,249 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:19,250 INFO L791 eck$LassoCheckResult]: Stem: 4006#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 4007#L-1 havoc main_#res;havoc main_~__retres1~13;havoc main_~__retres1~13;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4016#L1607 havoc start_simulation_#t~ret33, start_simulation_#t~ret34, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4017#L754 assume 1 == ~m_i~0;~m_st~0 := 0; 4145#L761-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3666#L766-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3579#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3309#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2949#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2950#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2998#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2999#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3902#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3903#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 3938#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 3409#L816-1 assume !(0 == ~M_E~0); 3410#L1090-1 assume !(0 == ~T1_E~0); 4292#L1095-1 assume !(0 == ~T2_E~0); 4074#L1100-1 assume !(0 == ~T3_E~0); 4075#L1105-1 assume !(0 == ~T4_E~0); 3229#L1110-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3230#L1115-1 assume !(0 == ~T6_E~0); 3614#L1120-1 assume !(0 == ~T7_E~0); 3882#L1125-1 assume !(0 == ~T8_E~0); 4345#L1130-1 assume !(0 == ~T9_E~0); 4094#L1135-1 assume !(0 == ~T10_E~0); 3414#L1140-1 assume !(0 == ~T11_E~0); 3415#L1145-1 assume !(0 == ~E_1~0); 4030#L1150-1 assume 0 == ~E_2~0;~E_2~0 := 1; 3589#L1155-1 assume !(0 == ~E_3~0); 3590#L1160-1 assume !(0 == ~E_4~0); 3674#L1165-1 assume !(0 == ~E_5~0); 3675#L1170-1 assume !(0 == ~E_6~0); 4264#L1175-1 assume !(0 == ~E_7~0); 3747#L1180-1 assume !(0 == ~E_8~0); 3748#L1185-1 assume !(0 == ~E_9~0); 3411#L1190-1 assume 0 == ~E_10~0;~E_10~0 := 1; 3412#L1195-1 assume !(0 == ~E_11~0); 3761#L1200-1 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3611#L525 assume !(1 == ~m_pc~0); 3037#L525-2 is_master_triggered_~__retres1~0 := 0; 3038#L536 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3765#L537 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3766#L1350 assume !(0 != activate_threads_~tmp~1); 3398#L1350-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3399#L544 assume 1 == ~t1_pc~0; 3650#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3613#L555 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4028#L556 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 3250#L1358 assume !(0 != activate_threads_~tmp___0~0); 3251#L1358-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3854#L563 assume !(1 == ~t2_pc~0); 4018#L563-2 is_transmit2_triggered_~__retres1~2 := 0; 3058#L574 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3059#L575 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 3479#L1366 assume !(0 != activate_threads_~tmp___1~0); 3480#L1366-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3922#L582 assume 1 == ~t3_pc~0; 3194#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3195#L593 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4318#L594 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 4273#L1374 assume !(0 != activate_threads_~tmp___2~0); 3132#L1374-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3133#L601 assume !(1 == ~t4_pc~0); 4045#L601-2 is_transmit4_triggered_~__retres1~4 := 0; 3615#L612 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3616#L613 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 4039#L1382 assume !(0 != activate_threads_~tmp___3~0); 4040#L1382-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4310#L620 assume 1 == ~t5_pc~0; 3091#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3092#L631 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3878#L632 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 3879#L1390 assume !(0 != activate_threads_~tmp___4~0); 4325#L1390-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4326#L639 assume 1 == ~t6_pc~0; 4296#L640 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3515#L650 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3516#L651 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 4276#L1398 assume !(0 != activate_threads_~tmp___5~0); 3623#L1398-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3624#L658 assume !(1 == ~t7_pc~0); 3808#L658-2 is_transmit7_triggered_~__retres1~7 := 0; 3809#L669 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3911#L670 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 3912#L1406 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 3405#L1406-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 3406#L677 assume 1 == ~t8_pc~0; 3628#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 3209#L688 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 3210#L689 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 3473#L1414 assume !(0 != activate_threads_~tmp___7~0); 3474#L1414-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 4133#L696 assume !(1 == ~t9_pc~0); 3866#L696-2 is_transmit9_triggered_~__retres1~9 := 0; 3867#L707 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 3953#L708 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 3886#L1422 assume !(0 != activate_threads_~tmp___8~0); 3887#L1422-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 4078#L715 assume 1 == ~t10_pc~0; 4082#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 3967#L726 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 3856#L727 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 3857#L1430 assume !(0 != activate_threads_~tmp___9~0); 3739#L1430-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 3203#L734 assume !(1 == ~t11_pc~0); 3204#L734-2 is_transmit11_triggered_~__retres1~11 := 0; 3676#L745 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 3752#L746 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 2939#L1438 assume !(0 != activate_threads_~tmp___10~0); 2940#L1438-2 assume !(1 == ~M_E~0); 3937#L1213-1 assume !(1 == ~T1_E~0); 4120#L1218-1 assume !(1 == ~T2_E~0); 2974#L1223-1 assume !(1 == ~T3_E~0); 2975#L1228-1 assume !(1 == ~T4_E~0); 3718#L1233-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4327#L1238-1 assume !(1 == ~T6_E~0); 4037#L1243-1 assume !(1 == ~T7_E~0); 4038#L1248-1 assume !(1 == ~T8_E~0); 4080#L1253-1 assume !(1 == ~T9_E~0); 4081#L1258-1 assume !(1 == ~T10_E~0); 4060#L1263-1 assume !(1 == ~T11_E~0); 4061#L1268-1 assume !(1 == ~E_1~0); 3900#L1273-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3901#L1278-1 assume !(1 == ~E_3~0); 3513#L1283-1 assume !(1 == ~E_4~0); 3514#L1288-1 assume !(1 == ~E_5~0); 4173#L1293-1 assume !(1 == ~E_6~0); 4137#L1298-1 assume !(1 == ~E_7~0); 3925#L1303-1 assume !(1 == ~E_8~0); 3524#L1308-1 assume !(1 == ~E_9~0); 3420#L1313-1 assume 1 == ~E_10~0;~E_10~0 := 2; 3421#L1318-1 assume !(1 == ~E_11~0); 4303#L1644-1 [2021-11-07 07:22:19,251 INFO L793 eck$LassoCheckResult]: Loop: 4303#L1644-1 assume !false; 3978#L1645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_~tmp~0;havoc eval_~tmp~0; 3955#L1065 assume !false; 4053#L902 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 4323#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 3056#L891 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 4237#L892 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 3529#L906 assume !(0 != eval_~tmp~0); 3531#L1080 start_simulation_~kernel_st~0 := 2; 4052#L754-1 start_simulation_~kernel_st~0 := 3; 3447#L1090-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3448#L1090-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4289#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4204#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4205#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3304#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3305#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3580#L1120-3 assume !(0 == ~T7_E~0); 3581#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4035#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4285#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3505#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3012#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3013#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3135#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3136#L1160-3 assume !(0 == ~E_4~0); 3485#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3486#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3846#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3401#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3165#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3166#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4279#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4280#L1200-3 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3703#L525-36 assume 1 == ~m_pc~0; 3704#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3266#L536-12 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3267#L537-12 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3540#L1350-36 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3541#L1350-38 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3450#L544-36 assume 1 == ~t1_pc~0; 3451#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3956#L555-12 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3344#L556-12 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 3345#L1358-36 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4261#L1358-38 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4166#L563-36 assume 1 == ~t2_pc~0; 3248#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3008#L574-12 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3009#L575-12 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 4043#L1366-36 assume !(0 != activate_threads_~tmp___1~0); 3716#L1366-38 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3717#L582-36 assume 1 == ~t3_pc~0; 3571#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3572#L593-12 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3788#L594-12 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 3947#L1374-36 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3751#L1374-38 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3697#L601-36 assume 1 == ~t4_pc~0; 3597#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3599#L612-12 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4331#L613-12 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 4246#L1382-36 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4247#L1382-38 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4155#L620-36 assume 1 == ~t5_pc~0; 3638#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3639#L631-12 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4019#L632-12 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 3625#L1390-36 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3270#L1390-38 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3052#L639-36 assume !(1 == ~t6_pc~0); 3053#L639-38 is_transmit6_triggered_~__retres1~6 := 0; 3089#L650-12 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3090#L651-12 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 3325#L1398-36 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 3326#L1398-38 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3885#L658-36 assume !(1 == ~t7_pc~0); 3063#L658-38 is_transmit7_triggered_~__retres1~7 := 0; 3064#L669-12 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4232#L670-12 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 3039#L1406-36 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 3040#L1406-38 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4003#L677-36 assume 1 == ~t8_pc~0; 4178#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 3812#L688-12 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 3923#L689-12 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 4306#L1414-36 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 3834#L1414-38 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 3835#L696-36 assume 1 == ~t9_pc~0; 3735#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 3736#L707-12 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 3112#L708-12 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 3113#L1422-36 assume !(0 != activate_threads_~tmp___8~0); 3847#L1422-38 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 3848#L715-36 assume 1 == ~t10_pc~0; 3976#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 2937#L726-12 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 2938#L727-12 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 2913#L1430-36 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 2914#L1430-38 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 3313#L734-36 assume 1 == ~t11_pc~0; 3314#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 3018#L745-12 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 3335#L746-12 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 2931#L1438-36 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 2932#L1438-38 assume 1 == ~M_E~0;~M_E~0 := 2; 3906#L1213-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4002#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3364#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3365#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3547#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3548#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3784#L1243-3 assume !(1 == ~T7_E~0); 3785#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4244#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4249#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3346#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3347#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4216#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4234#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4236#L1283-3 assume !(1 == ~E_4~0); 3670#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3671#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3537#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3538#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3977#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3534#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3535#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3348#L1323-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 3349#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 3289#L891-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 3688#L892-1 start_simulation_#t~ret33 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 4113#L1663 assume !(0 == start_simulation_~tmp~3); 3634#L1663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret32, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 3883#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 3130#L891-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 3803#L892-2 stop_simulation_#t~ret32 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret32;havoc stop_simulation_#t~ret32; 3074#L1618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3075#L1625 stop_simulation_#res := stop_simulation_~__retres2~0; 3408#L1626 start_simulation_#t~ret34 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret34;havoc start_simulation_#t~ret34; 4302#L1676 assume !(0 != start_simulation_~tmp___0~1); 4303#L1644-1 [2021-11-07 07:22:19,252 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:19,252 INFO L85 PathProgramCache]: Analyzing trace with hash 92085439, now seen corresponding path program 1 times [2021-11-07 07:22:19,253 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:19,253 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [429915893] [2021-11-07 07:22:19,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:19,254 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:19,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:19,374 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:19,375 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:19,375 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [429915893] [2021-11-07 07:22:19,375 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [429915893] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:19,376 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:19,376 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:19,376 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1303404441] [2021-11-07 07:22:19,377 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:22:19,378 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:19,378 INFO L85 PathProgramCache]: Analyzing trace with hash 1477331187, now seen corresponding path program 1 times [2021-11-07 07:22:19,378 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:19,378 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1480418708] [2021-11-07 07:22:19,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:19,379 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:19,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:19,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:19,584 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:19,584 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1480418708] [2021-11-07 07:22:19,585 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1480418708] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:19,585 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:19,585 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:19,585 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [724047543] [2021-11-07 07:22:19,586 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:22:19,586 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:22:19,587 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:22:19,587 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:22:19,587 INFO L87 Difference]: Start difference. First operand 1446 states and 2162 transitions. cyclomatic complexity: 717 Second operand has 3 states, 3 states have (on average 44.333333333333336) internal successors, (133), 3 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:19,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:22:19,628 INFO L93 Difference]: Finished difference Result 1446 states and 2161 transitions. [2021-11-07 07:22:19,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:22:19,629 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1446 states and 2161 transitions. [2021-11-07 07:22:19,644 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:19,659 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1446 states to 1446 states and 2161 transitions. [2021-11-07 07:22:19,659 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1446 [2021-11-07 07:22:19,662 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1446 [2021-11-07 07:22:19,662 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1446 states and 2161 transitions. [2021-11-07 07:22:19,665 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:22:19,666 INFO L681 BuchiCegarLoop]: Abstraction has 1446 states and 2161 transitions. [2021-11-07 07:22:19,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1446 states and 2161 transitions. [2021-11-07 07:22:19,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1446 to 1446. [2021-11-07 07:22:19,699 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1446 states, 1446 states have (on average 1.4944674965421854) internal successors, (2161), 1445 states have internal predecessors, (2161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:19,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1446 states to 1446 states and 2161 transitions. [2021-11-07 07:22:19,709 INFO L704 BuchiCegarLoop]: Abstraction has 1446 states and 2161 transitions. [2021-11-07 07:22:19,709 INFO L587 BuchiCegarLoop]: Abstraction has 1446 states and 2161 transitions. [2021-11-07 07:22:19,709 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-07 07:22:19,710 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1446 states and 2161 transitions. [2021-11-07 07:22:19,722 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:19,723 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:22:19,723 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:22:19,728 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:19,729 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:19,731 INFO L791 eck$LassoCheckResult]: Stem: 6905#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 6906#L-1 havoc main_#res;havoc main_~__retres1~13;havoc main_~__retres1~13;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 6913#L1607 havoc start_simulation_#t~ret33, start_simulation_#t~ret34, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6914#L754 assume 1 == ~m_i~0;~m_st~0 := 0; 7044#L761-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6565#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6478#L771-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 6208#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5848#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5849#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5897#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5898#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6801#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6802#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 6837#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 6308#L816-1 assume !(0 == ~M_E~0); 6309#L1090-1 assume !(0 == ~T1_E~0); 7191#L1095-1 assume !(0 == ~T2_E~0); 6973#L1100-1 assume !(0 == ~T3_E~0); 6974#L1105-1 assume !(0 == ~T4_E~0); 6127#L1110-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6128#L1115-1 assume !(0 == ~T6_E~0); 6513#L1120-1 assume !(0 == ~T7_E~0); 6781#L1125-1 assume !(0 == ~T8_E~0); 7244#L1130-1 assume !(0 == ~T9_E~0); 6993#L1135-1 assume !(0 == ~T10_E~0); 6313#L1140-1 assume !(0 == ~T11_E~0); 6314#L1145-1 assume !(0 == ~E_1~0); 6929#L1150-1 assume 0 == ~E_2~0;~E_2~0 := 1; 6488#L1155-1 assume !(0 == ~E_3~0); 6489#L1160-1 assume !(0 == ~E_4~0); 6573#L1165-1 assume !(0 == ~E_5~0); 6574#L1170-1 assume !(0 == ~E_6~0); 7163#L1175-1 assume !(0 == ~E_7~0); 6646#L1180-1 assume !(0 == ~E_8~0); 6647#L1185-1 assume !(0 == ~E_9~0); 6310#L1190-1 assume 0 == ~E_10~0;~E_10~0 := 1; 6311#L1195-1 assume !(0 == ~E_11~0); 6660#L1200-1 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6503#L525 assume !(1 == ~m_pc~0); 5936#L525-2 is_master_triggered_~__retres1~0 := 0; 5937#L536 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6664#L537 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6665#L1350 assume !(0 != activate_threads_~tmp~1); 6297#L1350-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6298#L544 assume 1 == ~t1_pc~0; 6549#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6512#L555 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6927#L556 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 6149#L1358 assume !(0 != activate_threads_~tmp___0~0); 6150#L1358-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6753#L563 assume !(1 == ~t2_pc~0); 6915#L563-2 is_transmit2_triggered_~__retres1~2 := 0; 5957#L574 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5958#L575 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 6375#L1366 assume !(0 != activate_threads_~tmp___1~0); 6376#L1366-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6821#L582 assume 1 == ~t3_pc~0; 6091#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6092#L593 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7217#L594 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 7172#L1374 assume !(0 != activate_threads_~tmp___2~0); 6031#L1374-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6032#L601 assume !(1 == ~t4_pc~0); 6944#L601-2 is_transmit4_triggered_~__retres1~4 := 0; 6514#L612 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6515#L613 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 6938#L1382 assume !(0 != activate_threads_~tmp___3~0); 6939#L1382-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7209#L620 assume 1 == ~t5_pc~0; 5986#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5987#L631 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6777#L632 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 6778#L1390 assume !(0 != activate_threads_~tmp___4~0); 7224#L1390-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7225#L639 assume 1 == ~t6_pc~0; 7195#L640 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 6414#L650 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6415#L651 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 7175#L1398 assume !(0 != activate_threads_~tmp___5~0); 6522#L1398-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6523#L658 assume !(1 == ~t7_pc~0); 6705#L658-2 is_transmit7_triggered_~__retres1~7 := 0; 6706#L669 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 6810#L670 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 6811#L1406 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 6304#L1406-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 6305#L677 assume 1 == ~t8_pc~0; 6525#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 6108#L688 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 6109#L689 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 6372#L1414 assume !(0 != activate_threads_~tmp___7~0); 6373#L1414-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 7032#L696 assume !(1 == ~t9_pc~0); 6763#L696-2 is_transmit9_triggered_~__retres1~9 := 0; 6764#L707 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 6849#L708 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 6785#L1422 assume !(0 != activate_threads_~tmp___8~0); 6786#L1422-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 6977#L715 assume 1 == ~t10_pc~0; 6981#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 6866#L726 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 6755#L727 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 6756#L1430 assume !(0 != activate_threads_~tmp___9~0); 6638#L1430-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 6100#L734 assume !(1 == ~t11_pc~0); 6101#L734-2 is_transmit11_triggered_~__retres1~11 := 0; 6575#L745 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 6651#L746 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 5836#L1438 assume !(0 != activate_threads_~tmp___10~0); 5837#L1438-2 assume !(1 == ~M_E~0); 6836#L1213-1 assume !(1 == ~T1_E~0); 7019#L1218-1 assume !(1 == ~T2_E~0); 5873#L1223-1 assume !(1 == ~T3_E~0); 5874#L1228-1 assume !(1 == ~T4_E~0); 6617#L1233-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7226#L1238-1 assume !(1 == ~T6_E~0); 6936#L1243-1 assume !(1 == ~T7_E~0); 6937#L1248-1 assume !(1 == ~T8_E~0); 6979#L1253-1 assume !(1 == ~T9_E~0); 6980#L1258-1 assume !(1 == ~T10_E~0); 6959#L1263-1 assume !(1 == ~T11_E~0); 6960#L1268-1 assume !(1 == ~E_1~0); 6799#L1273-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6800#L1278-1 assume !(1 == ~E_3~0); 6412#L1283-1 assume !(1 == ~E_4~0); 6413#L1288-1 assume !(1 == ~E_5~0); 7072#L1293-1 assume !(1 == ~E_6~0); 7036#L1298-1 assume !(1 == ~E_7~0); 6824#L1303-1 assume !(1 == ~E_8~0); 6423#L1308-1 assume !(1 == ~E_9~0); 6319#L1313-1 assume 1 == ~E_10~0;~E_10~0 := 2; 6320#L1318-1 assume !(1 == ~E_11~0); 7202#L1644-1 [2021-11-07 07:22:19,732 INFO L793 eck$LassoCheckResult]: Loop: 7202#L1644-1 assume !false; 6877#L1645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_~tmp~0;havoc eval_~tmp~0; 6853#L1065 assume !false; 6952#L902 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 7222#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 5955#L891 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 7136#L892 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 6428#L906 assume !(0 != eval_~tmp~0); 6430#L1080 start_simulation_~kernel_st~0 := 2; 6950#L754-1 start_simulation_~kernel_st~0 := 3; 6346#L1090-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6347#L1090-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7188#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7103#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7104#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6203#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6204#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6479#L1120-3 assume !(0 == ~T7_E~0); 6480#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6934#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7184#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6402#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5909#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5910#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6033#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6034#L1160-3 assume !(0 == ~E_4~0); 6384#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6385#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6745#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6300#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6061#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6062#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 7178#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7179#L1200-3 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6602#L525-36 assume 1 == ~m_pc~0; 6603#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 6160#L536-12 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6161#L537-12 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6438#L1350-36 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6439#L1350-38 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6349#L544-36 assume 1 == ~t1_pc~0; 6350#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6855#L555-12 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6243#L556-12 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 6244#L1358-36 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7160#L1358-38 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7065#L563-36 assume 1 == ~t2_pc~0; 6147#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5907#L574-12 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5908#L575-12 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 6942#L1366-36 assume !(0 != activate_threads_~tmp___1~0); 6615#L1366-38 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6616#L582-36 assume 1 == ~t3_pc~0; 6470#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6471#L593-12 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6687#L594-12 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 6846#L1374-36 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6650#L1374-38 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6596#L601-36 assume 1 == ~t4_pc~0; 6496#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6498#L612-12 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7230#L613-12 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 7145#L1382-36 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7146#L1382-38 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7054#L620-36 assume 1 == ~t5_pc~0; 6539#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6540#L631-12 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6918#L632-12 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 6524#L1390-36 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 6169#L1390-38 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5951#L639-36 assume !(1 == ~t6_pc~0); 5952#L639-38 is_transmit6_triggered_~__retres1~6 := 0; 5991#L650-12 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5992#L651-12 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 6226#L1398-36 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 6227#L1398-38 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6784#L658-36 assume 1 == ~t7_pc~0; 6068#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 5963#L669-12 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 7131#L670-12 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 5940#L1406-36 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 5941#L1406-38 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 6902#L677-36 assume 1 == ~t8_pc~0; 7077#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 6711#L688-12 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 6822#L689-12 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 7205#L1414-36 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 6733#L1414-38 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 6734#L696-36 assume 1 == ~t9_pc~0; 6634#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 6635#L707-12 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 6011#L708-12 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 6012#L1422-36 assume !(0 != activate_threads_~tmp___8~0); 6746#L1422-38 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 6747#L715-36 assume 1 == ~t10_pc~0; 6875#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 5838#L726-12 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 5839#L727-12 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 5812#L1430-36 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 5813#L1430-38 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 6212#L734-36 assume 1 == ~t11_pc~0; 6213#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 5917#L745-12 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 6234#L746-12 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 5830#L1438-36 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 5831#L1438-38 assume 1 == ~M_E~0;~M_E~0 := 2; 6805#L1213-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6901#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6263#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6264#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6446#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6447#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6683#L1243-3 assume !(1 == ~T7_E~0); 6684#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7144#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7149#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6245#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 6246#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7115#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7133#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7135#L1283-3 assume !(1 == ~E_4~0); 6569#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6570#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6436#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6437#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6876#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6433#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6434#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 6247#L1323-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 6248#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 6188#L891-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 6587#L892-1 start_simulation_#t~ret33 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 7012#L1663 assume !(0 == start_simulation_~tmp~3); 6533#L1663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret32, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 6782#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 6029#L891-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 6704#L892-2 stop_simulation_#t~ret32 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret32;havoc stop_simulation_#t~ret32; 5973#L1618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5974#L1625 stop_simulation_#res := stop_simulation_~__retres2~0; 6307#L1626 start_simulation_#t~ret34 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret34;havoc start_simulation_#t~ret34; 7201#L1676 assume !(0 != start_simulation_~tmp___0~1); 7202#L1644-1 [2021-11-07 07:22:19,733 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:19,734 INFO L85 PathProgramCache]: Analyzing trace with hash 676857089, now seen corresponding path program 1 times [2021-11-07 07:22:19,734 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:19,734 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2103860826] [2021-11-07 07:22:19,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:19,735 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:19,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:19,833 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:19,833 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:19,834 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2103860826] [2021-11-07 07:22:19,834 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2103860826] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:19,834 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:19,835 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:19,835 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1228208307] [2021-11-07 07:22:19,836 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:22:19,837 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:19,838 INFO L85 PathProgramCache]: Analyzing trace with hash 1099688370, now seen corresponding path program 1 times [2021-11-07 07:22:19,838 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:19,839 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1939833073] [2021-11-07 07:22:19,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:19,839 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:19,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:19,933 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:19,934 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:19,935 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1939833073] [2021-11-07 07:22:19,935 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1939833073] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:19,935 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:19,936 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:19,938 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [984756836] [2021-11-07 07:22:19,939 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:22:19,939 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:22:19,940 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:22:19,940 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:22:19,940 INFO L87 Difference]: Start difference. First operand 1446 states and 2161 transitions. cyclomatic complexity: 716 Second operand has 3 states, 3 states have (on average 44.333333333333336) internal successors, (133), 3 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:19,976 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:22:19,976 INFO L93 Difference]: Finished difference Result 1446 states and 2160 transitions. [2021-11-07 07:22:19,999 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:22:20,000 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1446 states and 2160 transitions. [2021-11-07 07:22:20,015 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:20,029 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1446 states to 1446 states and 2160 transitions. [2021-11-07 07:22:20,030 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1446 [2021-11-07 07:22:20,032 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1446 [2021-11-07 07:22:20,032 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1446 states and 2160 transitions. [2021-11-07 07:22:20,035 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:22:20,035 INFO L681 BuchiCegarLoop]: Abstraction has 1446 states and 2160 transitions. [2021-11-07 07:22:20,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1446 states and 2160 transitions. [2021-11-07 07:22:20,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1446 to 1446. [2021-11-07 07:22:20,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1446 states, 1446 states have (on average 1.4937759336099585) internal successors, (2160), 1445 states have internal predecessors, (2160), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:20,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1446 states to 1446 states and 2160 transitions. [2021-11-07 07:22:20,075 INFO L704 BuchiCegarLoop]: Abstraction has 1446 states and 2160 transitions. [2021-11-07 07:22:20,075 INFO L587 BuchiCegarLoop]: Abstraction has 1446 states and 2160 transitions. [2021-11-07 07:22:20,075 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-07 07:22:20,075 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1446 states and 2160 transitions. [2021-11-07 07:22:20,088 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:20,088 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:22:20,089 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:22:20,100 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:20,100 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:20,101 INFO L791 eck$LassoCheckResult]: Stem: 9804#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 9805#L-1 havoc main_#res;havoc main_~__retres1~13;havoc main_~__retres1~13;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 9814#L1607 havoc start_simulation_#t~ret33, start_simulation_#t~ret34, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9815#L754 assume 1 == ~m_i~0;~m_st~0 := 0; 9943#L761-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9464#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9377#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9107#L776-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8747#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8748#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8796#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8797#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9700#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9701#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9736#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9207#L816-1 assume !(0 == ~M_E~0); 9208#L1090-1 assume !(0 == ~T1_E~0); 10090#L1095-1 assume !(0 == ~T2_E~0); 9872#L1100-1 assume !(0 == ~T3_E~0); 9873#L1105-1 assume !(0 == ~T4_E~0); 9027#L1110-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9028#L1115-1 assume !(0 == ~T6_E~0); 9412#L1120-1 assume !(0 == ~T7_E~0); 9680#L1125-1 assume !(0 == ~T8_E~0); 10143#L1130-1 assume !(0 == ~T9_E~0); 9892#L1135-1 assume !(0 == ~T10_E~0); 9212#L1140-1 assume !(0 == ~T11_E~0); 9213#L1145-1 assume !(0 == ~E_1~0); 9828#L1150-1 assume 0 == ~E_2~0;~E_2~0 := 1; 9387#L1155-1 assume !(0 == ~E_3~0); 9388#L1160-1 assume !(0 == ~E_4~0); 9472#L1165-1 assume !(0 == ~E_5~0); 9473#L1170-1 assume !(0 == ~E_6~0); 10062#L1175-1 assume !(0 == ~E_7~0); 9545#L1180-1 assume !(0 == ~E_8~0); 9546#L1185-1 assume !(0 == ~E_9~0); 9209#L1190-1 assume 0 == ~E_10~0;~E_10~0 := 1; 9210#L1195-1 assume !(0 == ~E_11~0); 9559#L1200-1 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9409#L525 assume !(1 == ~m_pc~0); 8835#L525-2 is_master_triggered_~__retres1~0 := 0; 8836#L536 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9563#L537 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9564#L1350 assume !(0 != activate_threads_~tmp~1); 9196#L1350-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9197#L544 assume 1 == ~t1_pc~0; 9448#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9411#L555 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9826#L556 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 9048#L1358 assume !(0 != activate_threads_~tmp___0~0); 9049#L1358-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9652#L563 assume !(1 == ~t2_pc~0); 9816#L563-2 is_transmit2_triggered_~__retres1~2 := 0; 8856#L574 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8857#L575 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 9274#L1366 assume !(0 != activate_threads_~tmp___1~0); 9275#L1366-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9720#L582 assume 1 == ~t3_pc~0; 8992#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8993#L593 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10116#L594 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 10071#L1374 assume !(0 != activate_threads_~tmp___2~0); 8930#L1374-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8931#L601 assume !(1 == ~t4_pc~0); 9843#L601-2 is_transmit4_triggered_~__retres1~4 := 0; 9413#L612 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9414#L613 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 9837#L1382 assume !(0 != activate_threads_~tmp___3~0); 9838#L1382-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10108#L620 assume 1 == ~t5_pc~0; 8887#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8888#L631 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9676#L632 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 9677#L1390 assume !(0 != activate_threads_~tmp___4~0); 10123#L1390-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10124#L639 assume 1 == ~t6_pc~0; 10094#L640 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 9313#L650 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9314#L651 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 10074#L1398 assume !(0 != activate_threads_~tmp___5~0); 9421#L1398-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9422#L658 assume !(1 == ~t7_pc~0); 9606#L658-2 is_transmit7_triggered_~__retres1~7 := 0; 9607#L669 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 9709#L670 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 9710#L1406 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 9203#L1406-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 9204#L677 assume 1 == ~t8_pc~0; 9426#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 9007#L688 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 9008#L689 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 9271#L1414 assume !(0 != activate_threads_~tmp___7~0); 9272#L1414-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 9931#L696 assume !(1 == ~t9_pc~0); 9664#L696-2 is_transmit9_triggered_~__retres1~9 := 0; 9665#L707 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 9748#L708 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 9684#L1422 assume !(0 != activate_threads_~tmp___8~0); 9685#L1422-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 9876#L715 assume 1 == ~t10_pc~0; 9880#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 9765#L726 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 9654#L727 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 9655#L1430 assume !(0 != activate_threads_~tmp___9~0); 9537#L1430-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 9001#L734 assume !(1 == ~t11_pc~0); 9002#L734-2 is_transmit11_triggered_~__retres1~11 := 0; 9474#L745 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 9550#L746 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 8737#L1438 assume !(0 != activate_threads_~tmp___10~0); 8738#L1438-2 assume !(1 == ~M_E~0); 9735#L1213-1 assume !(1 == ~T1_E~0); 9918#L1218-1 assume !(1 == ~T2_E~0); 8772#L1223-1 assume !(1 == ~T3_E~0); 8773#L1228-1 assume !(1 == ~T4_E~0); 9516#L1233-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10125#L1238-1 assume !(1 == ~T6_E~0); 9835#L1243-1 assume !(1 == ~T7_E~0); 9836#L1248-1 assume !(1 == ~T8_E~0); 9878#L1253-1 assume !(1 == ~T9_E~0); 9879#L1258-1 assume !(1 == ~T10_E~0); 9858#L1263-1 assume !(1 == ~T11_E~0); 9859#L1268-1 assume !(1 == ~E_1~0); 9698#L1273-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9699#L1278-1 assume !(1 == ~E_3~0); 9311#L1283-1 assume !(1 == ~E_4~0); 9312#L1288-1 assume !(1 == ~E_5~0); 9971#L1293-1 assume !(1 == ~E_6~0); 9935#L1298-1 assume !(1 == ~E_7~0); 9723#L1303-1 assume !(1 == ~E_8~0); 9322#L1308-1 assume !(1 == ~E_9~0); 9218#L1313-1 assume 1 == ~E_10~0;~E_10~0 := 2; 9219#L1318-1 assume !(1 == ~E_11~0); 10101#L1644-1 [2021-11-07 07:22:20,101 INFO L793 eck$LassoCheckResult]: Loop: 10101#L1644-1 assume !false; 9776#L1645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_~tmp~0;havoc eval_~tmp~0; 9752#L1065 assume !false; 9851#L902 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 10121#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 8854#L891 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 10035#L892 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 9327#L906 assume !(0 != eval_~tmp~0); 9329#L1080 start_simulation_~kernel_st~0 := 2; 9849#L754-1 start_simulation_~kernel_st~0 := 3; 9245#L1090-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9246#L1090-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10087#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10002#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10003#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9102#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9103#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9378#L1120-3 assume !(0 == ~T7_E~0); 9379#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9833#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10083#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9301#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8810#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8811#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8933#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8934#L1160-3 assume !(0 == ~E_4~0); 9283#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9284#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9644#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9199#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8961#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8962#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 10077#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10078#L1200-3 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9501#L525-36 assume 1 == ~m_pc~0; 9502#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 9064#L536-12 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9065#L537-12 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9338#L1350-36 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 9339#L1350-38 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9248#L544-36 assume 1 == ~t1_pc~0; 9249#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9754#L555-12 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9148#L556-12 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 9149#L1358-36 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10060#L1358-38 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9964#L563-36 assume 1 == ~t2_pc~0; 9046#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8806#L574-12 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8807#L575-12 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 9841#L1366-36 assume !(0 != activate_threads_~tmp___1~0); 9514#L1366-38 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9515#L582-36 assume 1 == ~t3_pc~0; 9369#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9370#L593-12 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9586#L594-12 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 9745#L1374-36 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9549#L1374-38 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9495#L601-36 assume 1 == ~t4_pc~0; 9395#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9397#L612-12 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10129#L613-12 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 10044#L1382-36 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10045#L1382-38 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9953#L620-36 assume 1 == ~t5_pc~0; 9436#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 9437#L631-12 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9817#L632-12 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 9423#L1390-36 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 9068#L1390-38 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8847#L639-36 assume !(1 == ~t6_pc~0); 8848#L639-38 is_transmit6_triggered_~__retres1~6 := 0; 8885#L650-12 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8886#L651-12 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 9121#L1398-36 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 9122#L1398-38 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9683#L658-36 assume 1 == ~t7_pc~0; 8965#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 8859#L669-12 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10030#L670-12 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 8837#L1406-36 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 8838#L1406-38 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 9801#L677-36 assume 1 == ~t8_pc~0; 9976#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 9610#L688-12 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 9721#L689-12 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 10104#L1414-36 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 9632#L1414-38 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 9633#L696-36 assume 1 == ~t9_pc~0; 9533#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 9534#L707-12 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 8907#L708-12 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 8908#L1422-36 assume !(0 != activate_threads_~tmp___8~0); 9645#L1422-38 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 9646#L715-36 assume !(1 == ~t10_pc~0); 9616#L715-38 is_transmit10_triggered_~__retres1~10 := 0; 8735#L726-12 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 8736#L727-12 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 8711#L1430-36 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 8712#L1430-38 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 9111#L734-36 assume 1 == ~t11_pc~0; 9112#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 8816#L745-12 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 9133#L746-12 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 8729#L1438-36 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 8730#L1438-38 assume 1 == ~M_E~0;~M_E~0 := 2; 9704#L1213-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9800#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9162#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9163#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9345#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9346#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9582#L1243-3 assume !(1 == ~T7_E~0); 9583#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10042#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10047#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9142#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9143#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10014#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10032#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10034#L1283-3 assume !(1 == ~E_4~0); 9468#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9469#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9335#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9336#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9775#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9332#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9333#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9144#L1323-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 9145#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 9087#L891-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 9486#L892-1 start_simulation_#t~ret33 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 9911#L1663 assume !(0 == start_simulation_~tmp~3); 9432#L1663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret32, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 9681#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 8928#L891-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 9601#L892-2 stop_simulation_#t~ret32 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret32;havoc stop_simulation_#t~ret32; 8869#L1618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 8870#L1625 stop_simulation_#res := stop_simulation_~__retres2~0; 9206#L1626 start_simulation_#t~ret34 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret34;havoc start_simulation_#t~ret34; 10100#L1676 assume !(0 != start_simulation_~tmp___0~1); 10101#L1644-1 [2021-11-07 07:22:20,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:20,102 INFO L85 PathProgramCache]: Analyzing trace with hash 1111362687, now seen corresponding path program 1 times [2021-11-07 07:22:20,103 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:20,104 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1699087924] [2021-11-07 07:22:20,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:20,105 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:20,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:20,165 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:20,165 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:20,165 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1699087924] [2021-11-07 07:22:20,166 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1699087924] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:20,167 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:20,168 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:20,169 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1554203898] [2021-11-07 07:22:20,169 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:22:20,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:20,170 INFO L85 PathProgramCache]: Analyzing trace with hash -793753805, now seen corresponding path program 1 times [2021-11-07 07:22:20,170 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:20,172 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1543962319] [2021-11-07 07:22:20,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:20,172 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:20,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:20,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:20,252 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:20,257 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1543962319] [2021-11-07 07:22:20,257 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1543962319] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:20,257 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:20,257 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:20,258 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [815118836] [2021-11-07 07:22:20,258 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:22:20,258 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:22:20,259 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:22:20,259 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:22:20,260 INFO L87 Difference]: Start difference. First operand 1446 states and 2160 transitions. cyclomatic complexity: 715 Second operand has 3 states, 3 states have (on average 44.333333333333336) internal successors, (133), 3 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:20,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:22:20,301 INFO L93 Difference]: Finished difference Result 1446 states and 2159 transitions. [2021-11-07 07:22:20,301 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:22:20,301 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1446 states and 2159 transitions. [2021-11-07 07:22:20,317 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:20,332 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1446 states to 1446 states and 2159 transitions. [2021-11-07 07:22:20,332 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1446 [2021-11-07 07:22:20,334 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1446 [2021-11-07 07:22:20,334 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1446 states and 2159 transitions. [2021-11-07 07:22:20,338 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:22:20,338 INFO L681 BuchiCegarLoop]: Abstraction has 1446 states and 2159 transitions. [2021-11-07 07:22:20,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1446 states and 2159 transitions. [2021-11-07 07:22:20,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1446 to 1446. [2021-11-07 07:22:20,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1446 states, 1446 states have (on average 1.4930843706777317) internal successors, (2159), 1445 states have internal predecessors, (2159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:20,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1446 states to 1446 states and 2159 transitions. [2021-11-07 07:22:20,380 INFO L704 BuchiCegarLoop]: Abstraction has 1446 states and 2159 transitions. [2021-11-07 07:22:20,380 INFO L587 BuchiCegarLoop]: Abstraction has 1446 states and 2159 transitions. [2021-11-07 07:22:20,380 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-07 07:22:20,380 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1446 states and 2159 transitions. [2021-11-07 07:22:20,391 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:20,392 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:22:20,392 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:22:20,410 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:20,411 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:20,412 INFO L791 eck$LassoCheckResult]: Stem: 12703#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 12704#L-1 havoc main_#res;havoc main_~__retres1~13;havoc main_~__retres1~13;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 12713#L1607 havoc start_simulation_#t~ret33, start_simulation_#t~ret34, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12714#L754 assume 1 == ~m_i~0;~m_st~0 := 0; 12842#L761-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12363#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12276#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12006#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11646#L781-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11647#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11695#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11696#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12601#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12602#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12642#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12106#L816-1 assume !(0 == ~M_E~0); 12107#L1090-1 assume !(0 == ~T1_E~0); 12989#L1095-1 assume !(0 == ~T2_E~0); 12771#L1100-1 assume !(0 == ~T3_E~0); 12772#L1105-1 assume !(0 == ~T4_E~0); 11926#L1110-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11927#L1115-1 assume !(0 == ~T6_E~0); 12314#L1120-1 assume !(0 == ~T7_E~0); 12579#L1125-1 assume !(0 == ~T8_E~0); 13042#L1130-1 assume !(0 == ~T9_E~0); 12791#L1135-1 assume !(0 == ~T10_E~0); 12113#L1140-1 assume !(0 == ~T11_E~0); 12114#L1145-1 assume !(0 == ~E_1~0); 12727#L1150-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12286#L1155-1 assume !(0 == ~E_3~0); 12287#L1160-1 assume !(0 == ~E_4~0); 12371#L1165-1 assume !(0 == ~E_5~0); 12372#L1170-1 assume !(0 == ~E_6~0); 12961#L1175-1 assume !(0 == ~E_7~0); 12444#L1180-1 assume !(0 == ~E_8~0); 12445#L1185-1 assume !(0 == ~E_9~0); 12108#L1190-1 assume 0 == ~E_10~0;~E_10~0 := 1; 12109#L1195-1 assume !(0 == ~E_11~0); 12458#L1200-1 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12308#L525 assume !(1 == ~m_pc~0); 11734#L525-2 is_master_triggered_~__retres1~0 := 0; 11735#L536 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12462#L537 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 12463#L1350 assume !(0 != activate_threads_~tmp~1); 12096#L1350-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12097#L544 assume 1 == ~t1_pc~0; 12347#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 12310#L555 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12725#L556 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 11947#L1358 assume !(0 != activate_threads_~tmp___0~0); 11948#L1358-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12551#L563 assume !(1 == ~t2_pc~0); 12715#L563-2 is_transmit2_triggered_~__retres1~2 := 0; 11755#L574 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11756#L575 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 12176#L1366 assume !(0 != activate_threads_~tmp___1~0); 12177#L1366-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12619#L582 assume 1 == ~t3_pc~0; 11891#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11892#L593 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13015#L594 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 12971#L1374 assume !(0 != activate_threads_~tmp___2~0); 11829#L1374-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11830#L601 assume !(1 == ~t4_pc~0); 12742#L601-2 is_transmit4_triggered_~__retres1~4 := 0; 12315#L612 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12316#L613 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 12736#L1382 assume !(0 != activate_threads_~tmp___3~0); 12737#L1382-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13007#L620 assume 1 == ~t5_pc~0; 11788#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 11789#L631 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12575#L632 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 12576#L1390 assume !(0 != activate_threads_~tmp___4~0); 13022#L1390-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13023#L639 assume 1 == ~t6_pc~0; 12993#L640 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 12212#L650 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12213#L651 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 12973#L1398 assume !(0 != activate_threads_~tmp___5~0); 12320#L1398-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 12321#L658 assume !(1 == ~t7_pc~0); 12503#L658-2 is_transmit7_triggered_~__retres1~7 := 0; 12504#L669 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12608#L670 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 12609#L1406 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 12102#L1406-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 12103#L677 assume 1 == ~t8_pc~0; 12323#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 11906#L688 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 11907#L689 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 12170#L1414 assume !(0 != activate_threads_~tmp___7~0); 12171#L1414-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 12830#L696 assume !(1 == ~t9_pc~0); 12561#L696-2 is_transmit9_triggered_~__retres1~9 := 0; 12562#L707 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 12647#L708 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 12583#L1422 assume !(0 != activate_threads_~tmp___8~0); 12584#L1422-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 12775#L715 assume 1 == ~t10_pc~0; 12779#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 12664#L726 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 12553#L727 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 12554#L1430 assume !(0 != activate_threads_~tmp___9~0); 12436#L1430-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 11898#L734 assume !(1 == ~t11_pc~0); 11899#L734-2 is_transmit11_triggered_~__retres1~11 := 0; 12373#L745 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 12449#L746 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 11634#L1438 assume !(0 != activate_threads_~tmp___10~0); 11635#L1438-2 assume !(1 == ~M_E~0); 12634#L1213-1 assume !(1 == ~T1_E~0); 12817#L1218-1 assume !(1 == ~T2_E~0); 11671#L1223-1 assume !(1 == ~T3_E~0); 11672#L1228-1 assume !(1 == ~T4_E~0); 12415#L1233-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13024#L1238-1 assume !(1 == ~T6_E~0); 12734#L1243-1 assume !(1 == ~T7_E~0); 12735#L1248-1 assume !(1 == ~T8_E~0); 12777#L1253-1 assume !(1 == ~T9_E~0); 12778#L1258-1 assume !(1 == ~T10_E~0); 12757#L1263-1 assume !(1 == ~T11_E~0); 12758#L1268-1 assume !(1 == ~E_1~0); 12597#L1273-1 assume 1 == ~E_2~0;~E_2~0 := 2; 12598#L1278-1 assume !(1 == ~E_3~0); 12210#L1283-1 assume !(1 == ~E_4~0); 12211#L1288-1 assume !(1 == ~E_5~0); 12870#L1293-1 assume !(1 == ~E_6~0); 12834#L1298-1 assume !(1 == ~E_7~0); 12622#L1303-1 assume !(1 == ~E_8~0); 12221#L1308-1 assume !(1 == ~E_9~0); 12117#L1313-1 assume 1 == ~E_10~0;~E_10~0 := 2; 12118#L1318-1 assume !(1 == ~E_11~0); 13000#L1644-1 [2021-11-07 07:22:20,412 INFO L793 eck$LassoCheckResult]: Loop: 13000#L1644-1 assume !false; 12675#L1645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_~tmp~0;havoc eval_~tmp~0; 12651#L1065 assume !false; 12750#L902 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 13020#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 11753#L891 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 12934#L892 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 12226#L906 assume !(0 != eval_~tmp~0); 12228#L1080 start_simulation_~kernel_st~0 := 2; 12748#L754-1 start_simulation_~kernel_st~0 := 3; 12144#L1090-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12145#L1090-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12986#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12901#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12902#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12001#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12002#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12277#L1120-3 assume !(0 == ~T7_E~0); 12278#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12732#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12982#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12200#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 11707#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11708#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11831#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11832#L1160-3 assume !(0 == ~E_4~0); 12182#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12183#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12543#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12098#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 11859#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11860#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12976#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12977#L1200-3 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12400#L525-36 assume 1 == ~m_pc~0; 12401#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 11958#L536-12 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11959#L537-12 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 12236#L1350-36 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12237#L1350-38 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12147#L544-36 assume 1 == ~t1_pc~0; 12148#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 12653#L555-12 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12041#L556-12 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 12042#L1358-36 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12958#L1358-38 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12863#L563-36 assume 1 == ~t2_pc~0; 11945#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 11705#L574-12 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11706#L575-12 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 12740#L1366-36 assume !(0 != activate_threads_~tmp___1~0); 12413#L1366-38 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12414#L582-36 assume 1 == ~t3_pc~0; 12268#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 12269#L593-12 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12485#L594-12 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 12644#L1374-36 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12448#L1374-38 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12394#L601-36 assume 1 == ~t4_pc~0; 12294#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12296#L612-12 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13028#L613-12 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 12943#L1382-36 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12944#L1382-38 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12852#L620-36 assume 1 == ~t5_pc~0; 12337#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 12338#L631-12 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12716#L632-12 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 12322#L1390-36 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 11967#L1390-38 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11749#L639-36 assume !(1 == ~t6_pc~0); 11750#L639-38 is_transmit6_triggered_~__retres1~6 := 0; 11786#L650-12 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11787#L651-12 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 12024#L1398-36 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 12025#L1398-38 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 12582#L658-36 assume !(1 == ~t7_pc~0); 11760#L658-38 is_transmit7_triggered_~__retres1~7 := 0; 11761#L669-12 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12929#L670-12 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 11738#L1406-36 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 11739#L1406-38 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 12700#L677-36 assume 1 == ~t8_pc~0; 12875#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 12509#L688-12 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 12620#L689-12 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 13003#L1414-36 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 12531#L1414-38 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 12532#L696-36 assume 1 == ~t9_pc~0; 12432#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 12433#L707-12 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 11809#L708-12 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 11810#L1422-36 assume !(0 != activate_threads_~tmp___8~0); 12544#L1422-38 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 12545#L715-36 assume 1 == ~t10_pc~0; 12673#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 11636#L726-12 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 11637#L727-12 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 11610#L1430-36 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 11611#L1430-38 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 12010#L734-36 assume !(1 == ~t11_pc~0); 11714#L734-38 is_transmit11_triggered_~__retres1~11 := 0; 11715#L745-12 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 12032#L746-12 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 11628#L1438-36 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 11629#L1438-38 assume 1 == ~M_E~0;~M_E~0 := 2; 12603#L1213-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12699#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12061#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12062#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12244#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12245#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12481#L1243-3 assume !(1 == ~T7_E~0); 12482#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12942#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12947#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12043#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12044#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12913#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12931#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12933#L1283-3 assume !(1 == ~E_4~0); 12367#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12368#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12234#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12235#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12674#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12231#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12232#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12045#L1323-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 12046#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 11986#L891-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 12385#L892-1 start_simulation_#t~ret33 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 12810#L1663 assume !(0 == start_simulation_~tmp~3); 12331#L1663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret32, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 12580#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 11827#L891-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 12502#L892-2 stop_simulation_#t~ret32 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret32;havoc stop_simulation_#t~ret32; 11771#L1618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11772#L1625 stop_simulation_#res := stop_simulation_~__retres2~0; 12105#L1626 start_simulation_#t~ret34 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret34;havoc start_simulation_#t~ret34; 12999#L1676 assume !(0 != start_simulation_~tmp___0~1); 13000#L1644-1 [2021-11-07 07:22:20,413 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:20,413 INFO L85 PathProgramCache]: Analyzing trace with hash 1541020993, now seen corresponding path program 1 times [2021-11-07 07:22:20,414 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:20,414 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1660902284] [2021-11-07 07:22:20,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:20,414 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:20,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:20,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:20,462 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:20,463 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1660902284] [2021-11-07 07:22:20,463 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1660902284] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:20,463 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:20,463 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:20,464 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2049500156] [2021-11-07 07:22:20,464 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:22:20,465 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:20,465 INFO L85 PathProgramCache]: Analyzing trace with hash 992156468, now seen corresponding path program 1 times [2021-11-07 07:22:20,465 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:20,465 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [439355061] [2021-11-07 07:22:20,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:20,466 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:20,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:20,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:20,530 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:20,531 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [439355061] [2021-11-07 07:22:20,531 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [439355061] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:20,531 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:20,531 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:20,532 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [439975851] [2021-11-07 07:22:20,532 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:22:20,532 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:22:20,533 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:22:20,533 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:22:20,533 INFO L87 Difference]: Start difference. First operand 1446 states and 2159 transitions. cyclomatic complexity: 714 Second operand has 3 states, 3 states have (on average 44.333333333333336) internal successors, (133), 3 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:20,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:22:20,563 INFO L93 Difference]: Finished difference Result 1446 states and 2158 transitions. [2021-11-07 07:22:20,564 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:22:20,564 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1446 states and 2158 transitions. [2021-11-07 07:22:20,577 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:20,589 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1446 states to 1446 states and 2158 transitions. [2021-11-07 07:22:20,589 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1446 [2021-11-07 07:22:20,591 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1446 [2021-11-07 07:22:20,591 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1446 states and 2158 transitions. [2021-11-07 07:22:20,593 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:22:20,594 INFO L681 BuchiCegarLoop]: Abstraction has 1446 states and 2158 transitions. [2021-11-07 07:22:20,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1446 states and 2158 transitions. [2021-11-07 07:22:20,618 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1446 to 1446. [2021-11-07 07:22:20,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1446 states, 1446 states have (on average 1.4923928077455049) internal successors, (2158), 1445 states have internal predecessors, (2158), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:20,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1446 states to 1446 states and 2158 transitions. [2021-11-07 07:22:20,630 INFO L704 BuchiCegarLoop]: Abstraction has 1446 states and 2158 transitions. [2021-11-07 07:22:20,631 INFO L587 BuchiCegarLoop]: Abstraction has 1446 states and 2158 transitions. [2021-11-07 07:22:20,631 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-07 07:22:20,631 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1446 states and 2158 transitions. [2021-11-07 07:22:20,640 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:20,641 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:22:20,641 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:22:20,643 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:20,644 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:20,644 INFO L791 eck$LassoCheckResult]: Stem: 15602#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 15603#L-1 havoc main_#res;havoc main_~__retres1~13;havoc main_~__retres1~13;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 15610#L1607 havoc start_simulation_#t~ret33, start_simulation_#t~ret34, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15611#L754 assume 1 == ~m_i~0;~m_st~0 := 0; 15741#L761-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15262#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15175#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14905#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14545#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14546#L786-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14594#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14595#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15498#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15499#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15534#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 15005#L816-1 assume !(0 == ~M_E~0); 15006#L1090-1 assume !(0 == ~T1_E~0); 15888#L1095-1 assume !(0 == ~T2_E~0); 15670#L1100-1 assume !(0 == ~T3_E~0); 15671#L1105-1 assume !(0 == ~T4_E~0); 14824#L1110-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14825#L1115-1 assume !(0 == ~T6_E~0); 15210#L1120-1 assume !(0 == ~T7_E~0); 15478#L1125-1 assume !(0 == ~T8_E~0); 15941#L1130-1 assume !(0 == ~T9_E~0); 15690#L1135-1 assume !(0 == ~T10_E~0); 15010#L1140-1 assume !(0 == ~T11_E~0); 15011#L1145-1 assume !(0 == ~E_1~0); 15626#L1150-1 assume 0 == ~E_2~0;~E_2~0 := 1; 15185#L1155-1 assume !(0 == ~E_3~0); 15186#L1160-1 assume !(0 == ~E_4~0); 15270#L1165-1 assume !(0 == ~E_5~0); 15271#L1170-1 assume !(0 == ~E_6~0); 15860#L1175-1 assume !(0 == ~E_7~0); 15343#L1180-1 assume !(0 == ~E_8~0); 15344#L1185-1 assume !(0 == ~E_9~0); 15007#L1190-1 assume 0 == ~E_10~0;~E_10~0 := 1; 15008#L1195-1 assume !(0 == ~E_11~0); 15357#L1200-1 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15200#L525 assume !(1 == ~m_pc~0); 14633#L525-2 is_master_triggered_~__retres1~0 := 0; 14634#L536 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15361#L537 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 15362#L1350 assume !(0 != activate_threads_~tmp~1); 14994#L1350-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14995#L544 assume 1 == ~t1_pc~0; 15246#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 15209#L555 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15624#L556 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 14846#L1358 assume !(0 != activate_threads_~tmp___0~0); 14847#L1358-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15450#L563 assume !(1 == ~t2_pc~0); 15612#L563-2 is_transmit2_triggered_~__retres1~2 := 0; 14654#L574 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14655#L575 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 15072#L1366 assume !(0 != activate_threads_~tmp___1~0); 15073#L1366-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15518#L582 assume 1 == ~t3_pc~0; 14788#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 14789#L593 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15914#L594 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 15869#L1374 assume !(0 != activate_threads_~tmp___2~0); 14728#L1374-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14729#L601 assume !(1 == ~t4_pc~0); 15641#L601-2 is_transmit4_triggered_~__retres1~4 := 0; 15211#L612 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15212#L613 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 15635#L1382 assume !(0 != activate_threads_~tmp___3~0); 15636#L1382-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15906#L620 assume 1 == ~t5_pc~0; 14683#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 14684#L631 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15474#L632 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 15475#L1390 assume !(0 != activate_threads_~tmp___4~0); 15921#L1390-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 15922#L639 assume 1 == ~t6_pc~0; 15892#L640 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 15111#L650 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 15112#L651 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 15872#L1398 assume !(0 != activate_threads_~tmp___5~0); 15219#L1398-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 15220#L658 assume !(1 == ~t7_pc~0); 15402#L658-2 is_transmit7_triggered_~__retres1~7 := 0; 15403#L669 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 15507#L670 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 15508#L1406 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 15001#L1406-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 15002#L677 assume 1 == ~t8_pc~0; 15222#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 14805#L688 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 14806#L689 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 15069#L1414 assume !(0 != activate_threads_~tmp___7~0); 15070#L1414-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 15729#L696 assume !(1 == ~t9_pc~0); 15460#L696-2 is_transmit9_triggered_~__retres1~9 := 0; 15461#L707 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 15546#L708 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 15482#L1422 assume !(0 != activate_threads_~tmp___8~0); 15483#L1422-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 15674#L715 assume 1 == ~t10_pc~0; 15678#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 15563#L726 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 15452#L727 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 15453#L1430 assume !(0 != activate_threads_~tmp___9~0); 15335#L1430-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 14797#L734 assume !(1 == ~t11_pc~0); 14798#L734-2 is_transmit11_triggered_~__retres1~11 := 0; 15272#L745 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 15348#L746 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 14533#L1438 assume !(0 != activate_threads_~tmp___10~0); 14534#L1438-2 assume !(1 == ~M_E~0); 15533#L1213-1 assume !(1 == ~T1_E~0); 15716#L1218-1 assume !(1 == ~T2_E~0); 14570#L1223-1 assume !(1 == ~T3_E~0); 14571#L1228-1 assume !(1 == ~T4_E~0); 15314#L1233-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15923#L1238-1 assume !(1 == ~T6_E~0); 15633#L1243-1 assume !(1 == ~T7_E~0); 15634#L1248-1 assume !(1 == ~T8_E~0); 15676#L1253-1 assume !(1 == ~T9_E~0); 15677#L1258-1 assume !(1 == ~T10_E~0); 15656#L1263-1 assume !(1 == ~T11_E~0); 15657#L1268-1 assume !(1 == ~E_1~0); 15496#L1273-1 assume 1 == ~E_2~0;~E_2~0 := 2; 15497#L1278-1 assume !(1 == ~E_3~0); 15109#L1283-1 assume !(1 == ~E_4~0); 15110#L1288-1 assume !(1 == ~E_5~0); 15769#L1293-1 assume !(1 == ~E_6~0); 15733#L1298-1 assume !(1 == ~E_7~0); 15521#L1303-1 assume !(1 == ~E_8~0); 15120#L1308-1 assume !(1 == ~E_9~0); 15016#L1313-1 assume 1 == ~E_10~0;~E_10~0 := 2; 15017#L1318-1 assume !(1 == ~E_11~0); 15899#L1644-1 [2021-11-07 07:22:20,645 INFO L793 eck$LassoCheckResult]: Loop: 15899#L1644-1 assume !false; 15574#L1645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_~tmp~0;havoc eval_~tmp~0; 15550#L1065 assume !false; 15649#L902 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 15919#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 14652#L891 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 15833#L892 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 15125#L906 assume !(0 != eval_~tmp~0); 15127#L1080 start_simulation_~kernel_st~0 := 2; 15647#L754-1 start_simulation_~kernel_st~0 := 3; 15043#L1090-2 assume 0 == ~M_E~0;~M_E~0 := 1; 15044#L1090-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15885#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15800#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15801#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14900#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14901#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15176#L1120-3 assume !(0 == ~T7_E~0); 15177#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15631#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 15881#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15099#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 14606#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14607#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14731#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14732#L1160-3 assume !(0 == ~E_4~0); 15081#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15082#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15442#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14997#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 14758#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 14759#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15875#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 15876#L1200-3 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15299#L525-36 assume 1 == ~m_pc~0; 15300#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 14857#L536-12 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14858#L537-12 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 15135#L1350-36 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 15136#L1350-38 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15046#L544-36 assume 1 == ~t1_pc~0; 15047#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 15552#L555-12 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14946#L556-12 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 14947#L1358-36 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15857#L1358-38 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15762#L563-36 assume 1 == ~t2_pc~0; 14844#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 14604#L574-12 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14605#L575-12 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 15639#L1366-36 assume !(0 != activate_threads_~tmp___1~0); 15312#L1366-38 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15313#L582-36 assume !(1 == ~t3_pc~0); 15169#L582-38 is_transmit3_triggered_~__retres1~3 := 0; 15168#L593-12 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15384#L594-12 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 15543#L1374-36 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 15347#L1374-38 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15293#L601-36 assume 1 == ~t4_pc~0; 15193#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 15195#L612-12 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15927#L613-12 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 15842#L1382-36 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 15843#L1382-38 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15751#L620-36 assume 1 == ~t5_pc~0; 15236#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 15237#L631-12 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15617#L632-12 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 15221#L1390-36 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 14866#L1390-38 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 14648#L639-36 assume !(1 == ~t6_pc~0); 14649#L639-38 is_transmit6_triggered_~__retres1~6 := 0; 14688#L650-12 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 14689#L651-12 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 14923#L1398-36 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 14924#L1398-38 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 15481#L658-36 assume !(1 == ~t7_pc~0); 14659#L658-38 is_transmit7_triggered_~__retres1~7 := 0; 14660#L669-12 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 15828#L670-12 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 14637#L1406-36 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 14638#L1406-38 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 15599#L677-36 assume 1 == ~t8_pc~0; 15774#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 15408#L688-12 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 15519#L689-12 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 15902#L1414-36 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 15430#L1414-38 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 15431#L696-36 assume 1 == ~t9_pc~0; 15331#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 15332#L707-12 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 14708#L708-12 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 14709#L1422-36 assume !(0 != activate_threads_~tmp___8~0); 15443#L1422-38 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 15444#L715-36 assume 1 == ~t10_pc~0; 15573#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 14535#L726-12 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 14536#L727-12 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 14511#L1430-36 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 14512#L1430-38 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 14906#L734-36 assume !(1 == ~t11_pc~0); 14610#L734-38 is_transmit11_triggered_~__retres1~11 := 0; 14611#L745-12 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 14931#L746-12 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 14527#L1438-36 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 14528#L1438-38 assume 1 == ~M_E~0;~M_E~0 := 2; 15502#L1213-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15598#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14960#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14961#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15143#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15144#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15380#L1243-3 assume !(1 == ~T7_E~0); 15381#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15840#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15845#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14940#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 14941#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15812#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15830#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15831#L1283-3 assume !(1 == ~E_4~0); 15266#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15267#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15132#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15133#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15572#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15130#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15131#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 14942#L1323-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 14943#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 14885#L891-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 15284#L892-1 start_simulation_#t~ret33 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 15709#L1663 assume !(0 == start_simulation_~tmp~3); 15230#L1663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret32, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 15479#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 14726#L891-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 15399#L892-2 stop_simulation_#t~ret32 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret32;havoc stop_simulation_#t~ret32; 14667#L1618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 14668#L1625 stop_simulation_#res := stop_simulation_~__retres2~0; 15004#L1626 start_simulation_#t~ret34 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret34;havoc start_simulation_#t~ret34; 15898#L1676 assume !(0 != start_simulation_~tmp___0~1); 15899#L1644-1 [2021-11-07 07:22:20,645 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:20,645 INFO L85 PathProgramCache]: Analyzing trace with hash -2047349697, now seen corresponding path program 1 times [2021-11-07 07:22:20,646 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:20,646 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [854142045] [2021-11-07 07:22:20,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:20,647 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:20,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:20,688 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:20,688 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:20,688 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [854142045] [2021-11-07 07:22:20,689 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [854142045] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:20,689 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:20,689 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:20,689 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2030203664] [2021-11-07 07:22:20,690 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:22:20,691 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:20,691 INFO L85 PathProgramCache]: Analyzing trace with hash -394524811, now seen corresponding path program 1 times [2021-11-07 07:22:20,692 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:20,692 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [272043021] [2021-11-07 07:22:20,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:20,692 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:20,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:20,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:20,740 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:20,745 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [272043021] [2021-11-07 07:22:20,745 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [272043021] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:20,746 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:20,746 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:20,746 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1073885546] [2021-11-07 07:22:20,747 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:22:20,750 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:22:20,750 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:22:20,751 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:22:20,751 INFO L87 Difference]: Start difference. First operand 1446 states and 2158 transitions. cyclomatic complexity: 713 Second operand has 3 states, 3 states have (on average 44.333333333333336) internal successors, (133), 3 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:20,809 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:22:20,810 INFO L93 Difference]: Finished difference Result 1446 states and 2157 transitions. [2021-11-07 07:22:20,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:22:20,811 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1446 states and 2157 transitions. [2021-11-07 07:22:20,828 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:20,842 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1446 states to 1446 states and 2157 transitions. [2021-11-07 07:22:20,849 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1446 [2021-11-07 07:22:20,851 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1446 [2021-11-07 07:22:20,851 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1446 states and 2157 transitions. [2021-11-07 07:22:20,854 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:22:20,854 INFO L681 BuchiCegarLoop]: Abstraction has 1446 states and 2157 transitions. [2021-11-07 07:22:20,858 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1446 states and 2157 transitions. [2021-11-07 07:22:20,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1446 to 1446. [2021-11-07 07:22:20,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1446 states, 1446 states have (on average 1.491701244813278) internal successors, (2157), 1445 states have internal predecessors, (2157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:20,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1446 states to 1446 states and 2157 transitions. [2021-11-07 07:22:20,903 INFO L704 BuchiCegarLoop]: Abstraction has 1446 states and 2157 transitions. [2021-11-07 07:22:20,903 INFO L587 BuchiCegarLoop]: Abstraction has 1446 states and 2157 transitions. [2021-11-07 07:22:20,903 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-07 07:22:20,903 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1446 states and 2157 transitions. [2021-11-07 07:22:20,913 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:20,914 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:22:20,914 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:22:20,917 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:20,918 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:20,918 INFO L791 eck$LassoCheckResult]: Stem: 18501#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 18502#L-1 havoc main_#res;havoc main_~__retres1~13;havoc main_~__retres1~13;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 18511#L1607 havoc start_simulation_#t~ret33, start_simulation_#t~ret34, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 18512#L754 assume 1 == ~m_i~0;~m_st~0 := 0; 18640#L761-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18161#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18074#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17804#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17444#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17445#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17493#L791-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17494#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 18398#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18399#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18436#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17904#L816-1 assume !(0 == ~M_E~0); 17905#L1090-1 assume !(0 == ~T1_E~0); 18787#L1095-1 assume !(0 == ~T2_E~0); 18569#L1100-1 assume !(0 == ~T3_E~0); 18570#L1105-1 assume !(0 == ~T4_E~0); 17724#L1110-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17725#L1115-1 assume !(0 == ~T6_E~0); 18109#L1120-1 assume !(0 == ~T7_E~0); 18377#L1125-1 assume !(0 == ~T8_E~0); 18840#L1130-1 assume !(0 == ~T9_E~0); 18589#L1135-1 assume !(0 == ~T10_E~0); 17909#L1140-1 assume !(0 == ~T11_E~0); 17910#L1145-1 assume !(0 == ~E_1~0); 18525#L1150-1 assume 0 == ~E_2~0;~E_2~0 := 1; 18084#L1155-1 assume !(0 == ~E_3~0); 18085#L1160-1 assume !(0 == ~E_4~0); 18169#L1165-1 assume !(0 == ~E_5~0); 18170#L1170-1 assume !(0 == ~E_6~0); 18759#L1175-1 assume !(0 == ~E_7~0); 18242#L1180-1 assume !(0 == ~E_8~0); 18243#L1185-1 assume !(0 == ~E_9~0); 17906#L1190-1 assume 0 == ~E_10~0;~E_10~0 := 1; 17907#L1195-1 assume !(0 == ~E_11~0); 18256#L1200-1 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18106#L525 assume !(1 == ~m_pc~0); 17532#L525-2 is_master_triggered_~__retres1~0 := 0; 17533#L536 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18260#L537 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 18261#L1350 assume !(0 != activate_threads_~tmp~1); 17893#L1350-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17894#L544 assume 1 == ~t1_pc~0; 18145#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 18108#L555 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18523#L556 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 17745#L1358 assume !(0 != activate_threads_~tmp___0~0); 17746#L1358-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18349#L563 assume !(1 == ~t2_pc~0); 18513#L563-2 is_transmit2_triggered_~__retres1~2 := 0; 17553#L574 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17554#L575 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 17974#L1366 assume !(0 != activate_threads_~tmp___1~0); 17975#L1366-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18417#L582 assume 1 == ~t3_pc~0; 17689#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 17690#L593 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18813#L594 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 18768#L1374 assume !(0 != activate_threads_~tmp___2~0); 17627#L1374-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 17628#L601 assume !(1 == ~t4_pc~0); 18540#L601-2 is_transmit4_triggered_~__retres1~4 := 0; 18110#L612 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18111#L613 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 18534#L1382 assume !(0 != activate_threads_~tmp___3~0); 18535#L1382-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 18805#L620 assume 1 == ~t5_pc~0; 17586#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 17587#L631 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 18373#L632 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 18374#L1390 assume !(0 != activate_threads_~tmp___4~0); 18820#L1390-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 18821#L639 assume 1 == ~t6_pc~0; 18791#L640 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 18010#L650 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 18011#L651 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 18771#L1398 assume !(0 != activate_threads_~tmp___5~0); 18118#L1398-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 18119#L658 assume !(1 == ~t7_pc~0); 18303#L658-2 is_transmit7_triggered_~__retres1~7 := 0; 18304#L669 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 18406#L670 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 18407#L1406 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 17900#L1406-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 17901#L677 assume 1 == ~t8_pc~0; 18123#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 17704#L688 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 17705#L689 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 17968#L1414 assume !(0 != activate_threads_~tmp___7~0); 17969#L1414-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 18628#L696 assume !(1 == ~t9_pc~0); 18361#L696-2 is_transmit9_triggered_~__retres1~9 := 0; 18362#L707 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 18448#L708 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 18383#L1422 assume !(0 != activate_threads_~tmp___8~0); 18384#L1422-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 18573#L715 assume 1 == ~t10_pc~0; 18577#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 18462#L726 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 18351#L727 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 18352#L1430 assume !(0 != activate_threads_~tmp___9~0); 18234#L1430-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 17698#L734 assume !(1 == ~t11_pc~0); 17699#L734-2 is_transmit11_triggered_~__retres1~11 := 0; 18171#L745 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 18247#L746 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 17434#L1438 assume !(0 != activate_threads_~tmp___10~0); 17435#L1438-2 assume !(1 == ~M_E~0); 18432#L1213-1 assume !(1 == ~T1_E~0); 18615#L1218-1 assume !(1 == ~T2_E~0); 17469#L1223-1 assume !(1 == ~T3_E~0); 17470#L1228-1 assume !(1 == ~T4_E~0); 18213#L1233-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18822#L1238-1 assume !(1 == ~T6_E~0); 18532#L1243-1 assume !(1 == ~T7_E~0); 18533#L1248-1 assume !(1 == ~T8_E~0); 18575#L1253-1 assume !(1 == ~T9_E~0); 18576#L1258-1 assume !(1 == ~T10_E~0); 18555#L1263-1 assume !(1 == ~T11_E~0); 18556#L1268-1 assume !(1 == ~E_1~0); 18395#L1273-1 assume 1 == ~E_2~0;~E_2~0 := 2; 18396#L1278-1 assume !(1 == ~E_3~0); 18008#L1283-1 assume !(1 == ~E_4~0); 18009#L1288-1 assume !(1 == ~E_5~0); 18668#L1293-1 assume !(1 == ~E_6~0); 18632#L1298-1 assume !(1 == ~E_7~0); 18420#L1303-1 assume !(1 == ~E_8~0); 18019#L1308-1 assume !(1 == ~E_9~0); 17915#L1313-1 assume 1 == ~E_10~0;~E_10~0 := 2; 17916#L1318-1 assume !(1 == ~E_11~0); 18798#L1644-1 [2021-11-07 07:22:20,919 INFO L793 eck$LassoCheckResult]: Loop: 18798#L1644-1 assume !false; 18473#L1645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_~tmp~0;havoc eval_~tmp~0; 18450#L1065 assume !false; 18548#L902 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 18818#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 17551#L891 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 18732#L892 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 18024#L906 assume !(0 != eval_~tmp~0); 18026#L1080 start_simulation_~kernel_st~0 := 2; 18547#L754-1 start_simulation_~kernel_st~0 := 3; 17945#L1090-2 assume 0 == ~M_E~0;~M_E~0 := 1; 17946#L1090-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18784#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18699#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18700#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17799#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17800#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18075#L1120-3 assume !(0 == ~T7_E~0); 18076#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18530#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18780#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 18000#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 17507#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17508#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17630#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17631#L1160-3 assume !(0 == ~E_4~0); 17980#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17981#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18341#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17896#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17657#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17658#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 18774#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18775#L1200-3 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18193#L525-36 assume 1 == ~m_pc~0; 18194#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 17756#L536-12 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17757#L537-12 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 18034#L1350-36 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 18035#L1350-38 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17942#L544-36 assume 1 == ~t1_pc~0; 17943#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 18451#L555-12 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17839#L556-12 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 17840#L1358-36 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 18756#L1358-38 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18661#L563-36 assume !(1 == ~t2_pc~0); 17744#L563-38 is_transmit2_triggered_~__retres1~2 := 0; 17503#L574-12 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17504#L575-12 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 18538#L1366-36 assume !(0 != activate_threads_~tmp___1~0); 18211#L1366-38 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18212#L582-36 assume 1 == ~t3_pc~0; 18066#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 18067#L593-12 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18283#L594-12 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 18442#L1374-36 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 18246#L1374-38 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18192#L601-36 assume 1 == ~t4_pc~0; 18092#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 18094#L612-12 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18826#L613-12 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 18741#L1382-36 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 18742#L1382-38 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 18650#L620-36 assume 1 == ~t5_pc~0; 18133#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 18134#L631-12 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 18514#L632-12 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 18120#L1390-36 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 17765#L1390-38 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 17547#L639-36 assume !(1 == ~t6_pc~0); 17548#L639-38 is_transmit6_triggered_~__retres1~6 := 0; 17584#L650-12 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 17585#L651-12 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 17820#L1398-36 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 17821#L1398-38 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 18380#L658-36 assume 1 == ~t7_pc~0; 17664#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 17559#L669-12 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 18727#L670-12 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 17534#L1406-36 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 17535#L1406-38 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 18498#L677-36 assume 1 == ~t8_pc~0; 18673#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 18307#L688-12 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 18418#L689-12 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 18801#L1414-36 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 18329#L1414-38 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 18330#L696-36 assume 1 == ~t9_pc~0; 18230#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 18231#L707-12 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 17607#L708-12 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 17608#L1422-36 assume !(0 != activate_threads_~tmp___8~0); 18342#L1422-38 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 18343#L715-36 assume 1 == ~t10_pc~0; 18471#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 17432#L726-12 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 17433#L727-12 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 17408#L1430-36 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 17409#L1430-38 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 17808#L734-36 assume 1 == ~t11_pc~0; 17809#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 17513#L745-12 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 17830#L746-12 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 17426#L1438-36 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 17427#L1438-38 assume 1 == ~M_E~0;~M_E~0 := 2; 18401#L1213-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18497#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17859#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17860#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18042#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18043#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18279#L1243-3 assume !(1 == ~T7_E~0); 18280#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 18739#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18744#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17841#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17842#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18711#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18729#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18731#L1283-3 assume !(1 == ~E_4~0); 18165#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18166#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18032#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18033#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18472#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 18029#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 18030#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17843#L1323-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 17844#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 17784#L891-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 18183#L892-1 start_simulation_#t~ret33 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 18608#L1663 assume !(0 == start_simulation_~tmp~3); 18129#L1663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret32, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 18378#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 17625#L891-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 18298#L892-2 stop_simulation_#t~ret32 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret32;havoc stop_simulation_#t~ret32; 17569#L1618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 17570#L1625 stop_simulation_#res := stop_simulation_~__retres2~0; 17903#L1626 start_simulation_#t~ret34 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret34;havoc start_simulation_#t~ret34; 18797#L1676 assume !(0 != start_simulation_~tmp___0~1); 18798#L1644-1 [2021-11-07 07:22:20,920 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:20,920 INFO L85 PathProgramCache]: Analyzing trace with hash 1300579713, now seen corresponding path program 1 times [2021-11-07 07:22:20,921 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:20,921 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1256781244] [2021-11-07 07:22:20,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:20,921 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:20,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:20,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:20,966 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:20,966 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1256781244] [2021-11-07 07:22:20,967 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1256781244] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:20,967 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:20,967 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:20,967 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [292296395] [2021-11-07 07:22:20,968 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:22:20,969 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:20,969 INFO L85 PathProgramCache]: Analyzing trace with hash 972611891, now seen corresponding path program 1 times [2021-11-07 07:22:20,969 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:20,970 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [556348619] [2021-11-07 07:22:20,970 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:20,970 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:21,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:21,043 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:21,044 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:21,044 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [556348619] [2021-11-07 07:22:21,044 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [556348619] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:21,045 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:21,045 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:21,045 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1541231063] [2021-11-07 07:22:21,046 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:22:21,046 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:22:21,047 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:22:21,047 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:22:21,047 INFO L87 Difference]: Start difference. First operand 1446 states and 2157 transitions. cyclomatic complexity: 712 Second operand has 3 states, 3 states have (on average 44.333333333333336) internal successors, (133), 3 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:21,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:22:21,090 INFO L93 Difference]: Finished difference Result 1446 states and 2156 transitions. [2021-11-07 07:22:21,091 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:22:21,091 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1446 states and 2156 transitions. [2021-11-07 07:22:21,109 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:21,124 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1446 states to 1446 states and 2156 transitions. [2021-11-07 07:22:21,125 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1446 [2021-11-07 07:22:21,127 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1446 [2021-11-07 07:22:21,127 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1446 states and 2156 transitions. [2021-11-07 07:22:21,131 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:22:21,131 INFO L681 BuchiCegarLoop]: Abstraction has 1446 states and 2156 transitions. [2021-11-07 07:22:21,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1446 states and 2156 transitions. [2021-11-07 07:22:21,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1446 to 1446. [2021-11-07 07:22:21,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1446 states, 1446 states have (on average 1.4910096818810512) internal successors, (2156), 1445 states have internal predecessors, (2156), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:21,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1446 states to 1446 states and 2156 transitions. [2021-11-07 07:22:21,180 INFO L704 BuchiCegarLoop]: Abstraction has 1446 states and 2156 transitions. [2021-11-07 07:22:21,180 INFO L587 BuchiCegarLoop]: Abstraction has 1446 states and 2156 transitions. [2021-11-07 07:22:21,181 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-07 07:22:21,181 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1446 states and 2156 transitions. [2021-11-07 07:22:21,191 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:21,191 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:22:21,191 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:22:21,195 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:21,195 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:21,196 INFO L791 eck$LassoCheckResult]: Stem: 21400#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 21401#L-1 havoc main_#res;havoc main_~__retres1~13;havoc main_~__retres1~13;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 21408#L1607 havoc start_simulation_#t~ret33, start_simulation_#t~ret34, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 21409#L754 assume 1 == ~m_i~0;~m_st~0 := 0; 21539#L761-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21060#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20973#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20703#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20343#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20344#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20392#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 20393#L796-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21296#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21297#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21332#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20803#L816-1 assume !(0 == ~M_E~0); 20804#L1090-1 assume !(0 == ~T1_E~0); 21686#L1095-1 assume !(0 == ~T2_E~0); 21468#L1100-1 assume !(0 == ~T3_E~0); 21469#L1105-1 assume !(0 == ~T4_E~0); 20622#L1110-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20623#L1115-1 assume !(0 == ~T6_E~0); 21008#L1120-1 assume !(0 == ~T7_E~0); 21276#L1125-1 assume !(0 == ~T8_E~0); 21739#L1130-1 assume !(0 == ~T9_E~0); 21488#L1135-1 assume !(0 == ~T10_E~0); 20808#L1140-1 assume !(0 == ~T11_E~0); 20809#L1145-1 assume !(0 == ~E_1~0); 21424#L1150-1 assume 0 == ~E_2~0;~E_2~0 := 1; 20983#L1155-1 assume !(0 == ~E_3~0); 20984#L1160-1 assume !(0 == ~E_4~0); 21068#L1165-1 assume !(0 == ~E_5~0); 21069#L1170-1 assume !(0 == ~E_6~0); 21658#L1175-1 assume !(0 == ~E_7~0); 21141#L1180-1 assume !(0 == ~E_8~0); 21142#L1185-1 assume !(0 == ~E_9~0); 20805#L1190-1 assume 0 == ~E_10~0;~E_10~0 := 1; 20806#L1195-1 assume !(0 == ~E_11~0); 21155#L1200-1 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20998#L525 assume !(1 == ~m_pc~0); 20431#L525-2 is_master_triggered_~__retres1~0 := 0; 20432#L536 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21159#L537 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 21160#L1350 assume !(0 != activate_threads_~tmp~1); 20792#L1350-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20793#L544 assume 1 == ~t1_pc~0; 21044#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 21007#L555 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21422#L556 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 20644#L1358 assume !(0 != activate_threads_~tmp___0~0); 20645#L1358-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21248#L563 assume !(1 == ~t2_pc~0); 21410#L563-2 is_transmit2_triggered_~__retres1~2 := 0; 20452#L574 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20453#L575 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 20870#L1366 assume !(0 != activate_threads_~tmp___1~0); 20871#L1366-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21316#L582 assume 1 == ~t3_pc~0; 20586#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 20587#L593 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21712#L594 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 21667#L1374 assume !(0 != activate_threads_~tmp___2~0); 20526#L1374-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20527#L601 assume !(1 == ~t4_pc~0); 21439#L601-2 is_transmit4_triggered_~__retres1~4 := 0; 21009#L612 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21010#L613 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 21433#L1382 assume !(0 != activate_threads_~tmp___3~0); 21434#L1382-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 21704#L620 assume 1 == ~t5_pc~0; 20481#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 20482#L631 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 21272#L632 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 21273#L1390 assume !(0 != activate_threads_~tmp___4~0); 21719#L1390-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 21720#L639 assume 1 == ~t6_pc~0; 21690#L640 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 20909#L650 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 20910#L651 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 21670#L1398 assume !(0 != activate_threads_~tmp___5~0); 21017#L1398-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 21018#L658 assume !(1 == ~t7_pc~0); 21200#L658-2 is_transmit7_triggered_~__retres1~7 := 0; 21201#L669 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 21305#L670 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 21306#L1406 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 20799#L1406-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 20800#L677 assume 1 == ~t8_pc~0; 21020#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 20603#L688 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 20604#L689 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 20867#L1414 assume !(0 != activate_threads_~tmp___7~0); 20868#L1414-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 21527#L696 assume !(1 == ~t9_pc~0); 21258#L696-2 is_transmit9_triggered_~__retres1~9 := 0; 21259#L707 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 21344#L708 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 21280#L1422 assume !(0 != activate_threads_~tmp___8~0); 21281#L1422-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 21472#L715 assume 1 == ~t10_pc~0; 21476#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 21361#L726 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 21250#L727 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 21251#L1430 assume !(0 != activate_threads_~tmp___9~0); 21133#L1430-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 20595#L734 assume !(1 == ~t11_pc~0); 20596#L734-2 is_transmit11_triggered_~__retres1~11 := 0; 21070#L745 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 21146#L746 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 20331#L1438 assume !(0 != activate_threads_~tmp___10~0); 20332#L1438-2 assume !(1 == ~M_E~0); 21331#L1213-1 assume !(1 == ~T1_E~0); 21514#L1218-1 assume !(1 == ~T2_E~0); 20368#L1223-1 assume !(1 == ~T3_E~0); 20369#L1228-1 assume !(1 == ~T4_E~0); 21112#L1233-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21721#L1238-1 assume !(1 == ~T6_E~0); 21431#L1243-1 assume !(1 == ~T7_E~0); 21432#L1248-1 assume !(1 == ~T8_E~0); 21474#L1253-1 assume !(1 == ~T9_E~0); 21475#L1258-1 assume !(1 == ~T10_E~0); 21454#L1263-1 assume !(1 == ~T11_E~0); 21455#L1268-1 assume !(1 == ~E_1~0); 21294#L1273-1 assume 1 == ~E_2~0;~E_2~0 := 2; 21295#L1278-1 assume !(1 == ~E_3~0); 20907#L1283-1 assume !(1 == ~E_4~0); 20908#L1288-1 assume !(1 == ~E_5~0); 21567#L1293-1 assume !(1 == ~E_6~0); 21531#L1298-1 assume !(1 == ~E_7~0); 21319#L1303-1 assume !(1 == ~E_8~0); 20918#L1308-1 assume !(1 == ~E_9~0); 20814#L1313-1 assume 1 == ~E_10~0;~E_10~0 := 2; 20815#L1318-1 assume !(1 == ~E_11~0); 21697#L1644-1 [2021-11-07 07:22:21,197 INFO L793 eck$LassoCheckResult]: Loop: 21697#L1644-1 assume !false; 21372#L1645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_~tmp~0;havoc eval_~tmp~0; 21348#L1065 assume !false; 21447#L902 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 21717#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 20450#L891 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 21631#L892 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 20923#L906 assume !(0 != eval_~tmp~0); 20925#L1080 start_simulation_~kernel_st~0 := 2; 21445#L754-1 start_simulation_~kernel_st~0 := 3; 20841#L1090-2 assume 0 == ~M_E~0;~M_E~0 := 1; 20842#L1090-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21683#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21598#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21599#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20698#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20699#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20974#L1120-3 assume !(0 == ~T7_E~0); 20975#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21429#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21679#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 20897#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20404#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 20405#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20528#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20529#L1160-3 assume !(0 == ~E_4~0); 20879#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20880#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21240#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20795#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20556#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 20557#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21673#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 21674#L1200-3 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21097#L525-36 assume 1 == ~m_pc~0; 21098#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 20655#L536-12 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20656#L537-12 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 20933#L1350-36 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 20934#L1350-38 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20844#L544-36 assume 1 == ~t1_pc~0; 20845#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 21350#L555-12 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20738#L556-12 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 20739#L1358-36 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 21655#L1358-38 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21560#L563-36 assume 1 == ~t2_pc~0; 20642#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 20402#L574-12 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20403#L575-12 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 21437#L1366-36 assume !(0 != activate_threads_~tmp___1~0); 21110#L1366-38 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21111#L582-36 assume 1 == ~t3_pc~0; 20965#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 20966#L593-12 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21182#L594-12 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 21341#L1374-36 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 21145#L1374-38 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21091#L601-36 assume !(1 == ~t4_pc~0); 20992#L601-38 is_transmit4_triggered_~__retres1~4 := 0; 20993#L612-12 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21725#L613-12 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 21640#L1382-36 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 21641#L1382-38 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 21549#L620-36 assume 1 == ~t5_pc~0; 21034#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 21035#L631-12 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 21413#L632-12 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 21019#L1390-36 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 20664#L1390-38 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 20446#L639-36 assume 1 == ~t6_pc~0; 20448#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 20486#L650-12 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 20487#L651-12 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 20721#L1398-36 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 20722#L1398-38 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 21279#L658-36 assume 1 == ~t7_pc~0; 20563#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 20458#L669-12 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 21626#L670-12 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 20435#L1406-36 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 20436#L1406-38 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 21397#L677-36 assume 1 == ~t8_pc~0; 21572#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 21206#L688-12 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 21317#L689-12 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 21700#L1414-36 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 21228#L1414-38 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 21229#L696-36 assume 1 == ~t9_pc~0; 21129#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 21130#L707-12 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 20506#L708-12 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 20507#L1422-36 assume !(0 != activate_threads_~tmp___8~0); 21241#L1422-38 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 21242#L715-36 assume 1 == ~t10_pc~0; 21370#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 20333#L726-12 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 20334#L727-12 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 20307#L1430-36 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 20308#L1430-38 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 20707#L734-36 assume 1 == ~t11_pc~0; 20708#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 20412#L745-12 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 20729#L746-12 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 20325#L1438-36 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 20326#L1438-38 assume 1 == ~M_E~0;~M_E~0 := 2; 21300#L1213-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21396#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20758#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20759#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20941#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20942#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21178#L1243-3 assume !(1 == ~T7_E~0); 21179#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21639#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21644#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 20740#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20741#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21610#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21628#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21630#L1283-3 assume !(1 == ~E_4~0); 21064#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21065#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20931#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20932#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21371#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20928#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20929#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 20742#L1323-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 20743#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 20683#L891-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 21082#L892-1 start_simulation_#t~ret33 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 21507#L1663 assume !(0 == start_simulation_~tmp~3); 21028#L1663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret32, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 21277#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 20524#L891-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 21199#L892-2 stop_simulation_#t~ret32 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret32;havoc stop_simulation_#t~ret32; 20468#L1618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 20469#L1625 stop_simulation_#res := stop_simulation_~__retres2~0; 20802#L1626 start_simulation_#t~ret34 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret34;havoc start_simulation_#t~ret34; 21696#L1676 assume !(0 != start_simulation_~tmp___0~1); 21697#L1644-1 [2021-11-07 07:22:21,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:21,198 INFO L85 PathProgramCache]: Analyzing trace with hash 438746111, now seen corresponding path program 1 times [2021-11-07 07:22:21,198 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:21,198 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [187908802] [2021-11-07 07:22:21,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:21,199 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:21,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:21,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:21,239 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:21,239 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [187908802] [2021-11-07 07:22:21,239 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [187908802] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:21,240 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:21,240 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:21,240 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1759701706] [2021-11-07 07:22:21,241 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:22:21,241 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:21,241 INFO L85 PathProgramCache]: Analyzing trace with hash 1654861874, now seen corresponding path program 1 times [2021-11-07 07:22:21,242 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:21,242 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2116912255] [2021-11-07 07:22:21,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:21,243 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:21,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:21,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:21,309 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:21,311 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2116912255] [2021-11-07 07:22:21,313 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2116912255] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:21,314 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:21,314 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-07 07:22:21,314 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1990079707] [2021-11-07 07:22:21,315 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:22:21,315 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:22:21,315 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:22:21,316 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:22:21,316 INFO L87 Difference]: Start difference. First operand 1446 states and 2156 transitions. cyclomatic complexity: 711 Second operand has 3 states, 3 states have (on average 44.333333333333336) internal successors, (133), 3 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:21,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:22:21,351 INFO L93 Difference]: Finished difference Result 1446 states and 2155 transitions. [2021-11-07 07:22:21,352 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:22:21,352 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1446 states and 2155 transitions. [2021-11-07 07:22:21,364 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:21,379 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1446 states to 1446 states and 2155 transitions. [2021-11-07 07:22:21,379 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1446 [2021-11-07 07:22:21,381 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1446 [2021-11-07 07:22:21,381 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1446 states and 2155 transitions. [2021-11-07 07:22:21,384 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:22:21,385 INFO L681 BuchiCegarLoop]: Abstraction has 1446 states and 2155 transitions. [2021-11-07 07:22:21,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1446 states and 2155 transitions. [2021-11-07 07:22:21,414 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1446 to 1446. [2021-11-07 07:22:21,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1446 states, 1446 states have (on average 1.4903181189488244) internal successors, (2155), 1445 states have internal predecessors, (2155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:21,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1446 states to 1446 states and 2155 transitions. [2021-11-07 07:22:21,429 INFO L704 BuchiCegarLoop]: Abstraction has 1446 states and 2155 transitions. [2021-11-07 07:22:21,429 INFO L587 BuchiCegarLoop]: Abstraction has 1446 states and 2155 transitions. [2021-11-07 07:22:21,430 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-07 07:22:21,430 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1446 states and 2155 transitions. [2021-11-07 07:22:21,439 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:21,439 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:22:21,439 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:22:21,442 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:21,443 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:21,443 INFO L791 eck$LassoCheckResult]: Stem: 24301#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 24302#L-1 havoc main_#res;havoc main_~__retres1~13;havoc main_~__retres1~13;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 24311#L1607 havoc start_simulation_#t~ret33, start_simulation_#t~ret34, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 24312#L754 assume 1 == ~m_i~0;~m_st~0 := 0; 24440#L761-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23961#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23874#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23604#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23244#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23245#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23293#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 23294#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24197#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24198#L806-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 24233#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 23704#L816-1 assume !(0 == ~M_E~0); 23705#L1090-1 assume !(0 == ~T1_E~0); 24587#L1095-1 assume !(0 == ~T2_E~0); 24369#L1100-1 assume !(0 == ~T3_E~0); 24370#L1105-1 assume !(0 == ~T4_E~0); 23524#L1110-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23525#L1115-1 assume !(0 == ~T6_E~0); 23909#L1120-1 assume !(0 == ~T7_E~0); 24177#L1125-1 assume !(0 == ~T8_E~0); 24640#L1130-1 assume !(0 == ~T9_E~0); 24389#L1135-1 assume !(0 == ~T10_E~0); 23709#L1140-1 assume !(0 == ~T11_E~0); 23710#L1145-1 assume !(0 == ~E_1~0); 24325#L1150-1 assume 0 == ~E_2~0;~E_2~0 := 1; 23884#L1155-1 assume !(0 == ~E_3~0); 23885#L1160-1 assume !(0 == ~E_4~0); 23969#L1165-1 assume !(0 == ~E_5~0); 23970#L1170-1 assume !(0 == ~E_6~0); 24559#L1175-1 assume !(0 == ~E_7~0); 24042#L1180-1 assume !(0 == ~E_8~0); 24043#L1185-1 assume !(0 == ~E_9~0); 23706#L1190-1 assume 0 == ~E_10~0;~E_10~0 := 1; 23707#L1195-1 assume !(0 == ~E_11~0); 24056#L1200-1 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23906#L525 assume !(1 == ~m_pc~0); 23332#L525-2 is_master_triggered_~__retres1~0 := 0; 23333#L536 is_master_triggered_#res := is_master_triggered_~__retres1~0; 24060#L537 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 24061#L1350 assume !(0 != activate_threads_~tmp~1); 23693#L1350-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23694#L544 assume 1 == ~t1_pc~0; 23945#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 23908#L555 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 24323#L556 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 23545#L1358 assume !(0 != activate_threads_~tmp___0~0); 23546#L1358-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 24149#L563 assume !(1 == ~t2_pc~0); 24313#L563-2 is_transmit2_triggered_~__retres1~2 := 0; 23353#L574 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23354#L575 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 23771#L1366 assume !(0 != activate_threads_~tmp___1~0); 23772#L1366-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 24217#L582 assume 1 == ~t3_pc~0; 23489#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 23490#L593 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 24613#L594 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 24568#L1374 assume !(0 != activate_threads_~tmp___2~0); 23427#L1374-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 23428#L601 assume !(1 == ~t4_pc~0); 24340#L601-2 is_transmit4_triggered_~__retres1~4 := 0; 23910#L612 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 23911#L613 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 24334#L1382 assume !(0 != activate_threads_~tmp___3~0); 24335#L1382-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 24605#L620 assume 1 == ~t5_pc~0; 23384#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 23385#L631 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 24173#L632 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 24174#L1390 assume !(0 != activate_threads_~tmp___4~0); 24620#L1390-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 24621#L639 assume 1 == ~t6_pc~0; 24591#L640 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 23810#L650 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 23811#L651 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 24571#L1398 assume !(0 != activate_threads_~tmp___5~0); 23918#L1398-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 23919#L658 assume !(1 == ~t7_pc~0); 24103#L658-2 is_transmit7_triggered_~__retres1~7 := 0; 24104#L669 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 24206#L670 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 24207#L1406 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 23700#L1406-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 23701#L677 assume 1 == ~t8_pc~0; 23923#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 23504#L688 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 23505#L689 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 23768#L1414 assume !(0 != activate_threads_~tmp___7~0); 23769#L1414-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 24428#L696 assume !(1 == ~t9_pc~0); 24161#L696-2 is_transmit9_triggered_~__retres1~9 := 0; 24162#L707 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 24245#L708 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 24181#L1422 assume !(0 != activate_threads_~tmp___8~0); 24182#L1422-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 24373#L715 assume 1 == ~t10_pc~0; 24377#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 24262#L726 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 24151#L727 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 24152#L1430 assume !(0 != activate_threads_~tmp___9~0); 24034#L1430-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 23498#L734 assume !(1 == ~t11_pc~0); 23499#L734-2 is_transmit11_triggered_~__retres1~11 := 0; 23971#L745 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 24047#L746 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 23234#L1438 assume !(0 != activate_threads_~tmp___10~0); 23235#L1438-2 assume !(1 == ~M_E~0); 24232#L1213-1 assume !(1 == ~T1_E~0); 24415#L1218-1 assume !(1 == ~T2_E~0); 23269#L1223-1 assume !(1 == ~T3_E~0); 23270#L1228-1 assume !(1 == ~T4_E~0); 24013#L1233-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24622#L1238-1 assume !(1 == ~T6_E~0); 24332#L1243-1 assume !(1 == ~T7_E~0); 24333#L1248-1 assume !(1 == ~T8_E~0); 24375#L1253-1 assume !(1 == ~T9_E~0); 24376#L1258-1 assume !(1 == ~T10_E~0); 24355#L1263-1 assume !(1 == ~T11_E~0); 24356#L1268-1 assume !(1 == ~E_1~0); 24195#L1273-1 assume 1 == ~E_2~0;~E_2~0 := 2; 24196#L1278-1 assume !(1 == ~E_3~0); 23808#L1283-1 assume !(1 == ~E_4~0); 23809#L1288-1 assume !(1 == ~E_5~0); 24468#L1293-1 assume !(1 == ~E_6~0); 24432#L1298-1 assume !(1 == ~E_7~0); 24220#L1303-1 assume !(1 == ~E_8~0); 23819#L1308-1 assume !(1 == ~E_9~0); 23715#L1313-1 assume 1 == ~E_10~0;~E_10~0 := 2; 23716#L1318-1 assume !(1 == ~E_11~0); 24598#L1644-1 [2021-11-07 07:22:21,444 INFO L793 eck$LassoCheckResult]: Loop: 24598#L1644-1 assume !false; 24273#L1645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_~tmp~0;havoc eval_~tmp~0; 24250#L1065 assume !false; 24348#L902 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 24618#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 23351#L891 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 24532#L892 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 23824#L906 assume !(0 != eval_~tmp~0); 23826#L1080 start_simulation_~kernel_st~0 := 2; 24347#L754-1 start_simulation_~kernel_st~0 := 3; 23742#L1090-2 assume 0 == ~M_E~0;~M_E~0 := 1; 23743#L1090-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24584#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24499#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24500#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23599#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23600#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23875#L1120-3 assume !(0 == ~T7_E~0); 23876#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24330#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 24580#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 23800#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 23307#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23308#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23430#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23431#L1160-3 assume !(0 == ~E_4~0); 23780#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23781#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24141#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23696#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23458#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23459#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24574#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24575#L1200-3 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23998#L525-36 assume !(1 == ~m_pc~0); 24000#L525-38 is_master_triggered_~__retres1~0 := 0; 23561#L536-12 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23562#L537-12 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 23835#L1350-36 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 23836#L1350-38 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23745#L544-36 assume 1 == ~t1_pc~0; 23746#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 24251#L555-12 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23645#L556-12 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 23646#L1358-36 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 24557#L1358-38 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 24461#L563-36 assume 1 == ~t2_pc~0; 23543#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 23303#L574-12 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23304#L575-12 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 24338#L1366-36 assume !(0 != activate_threads_~tmp___1~0); 24011#L1366-38 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 24012#L582-36 assume 1 == ~t3_pc~0; 23866#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 23867#L593-12 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 24083#L594-12 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 24242#L1374-36 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 24046#L1374-38 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 23989#L601-36 assume 1 == ~t4_pc~0; 23892#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 23894#L612-12 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 24626#L613-12 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 24541#L1382-36 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 24542#L1382-38 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 24448#L620-36 assume 1 == ~t5_pc~0; 23933#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 23934#L631-12 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 24314#L632-12 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 23920#L1390-36 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 23565#L1390-38 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 23347#L639-36 assume !(1 == ~t6_pc~0); 23348#L639-38 is_transmit6_triggered_~__retres1~6 := 0; 23382#L650-12 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 23383#L651-12 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 23620#L1398-36 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 23621#L1398-38 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 24180#L658-36 assume 1 == ~t7_pc~0; 23462#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 23359#L669-12 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 24527#L670-12 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 23334#L1406-36 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 23335#L1406-38 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 24298#L677-36 assume 1 == ~t8_pc~0; 24473#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 24107#L688-12 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 24218#L689-12 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 24601#L1414-36 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 24129#L1414-38 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 24130#L696-36 assume !(1 == ~t9_pc~0); 24032#L696-38 is_transmit9_triggered_~__retres1~9 := 0; 24031#L707-12 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 23404#L708-12 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 23405#L1422-36 assume !(0 != activate_threads_~tmp___8~0); 24142#L1422-38 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 24143#L715-36 assume !(1 == ~t10_pc~0); 24113#L715-38 is_transmit10_triggered_~__retres1~10 := 0; 23232#L726-12 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 23233#L727-12 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 23208#L1430-36 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 23209#L1430-38 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 23608#L734-36 assume !(1 == ~t11_pc~0); 23312#L734-38 is_transmit11_triggered_~__retres1~11 := 0; 23313#L745-12 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 23630#L746-12 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 23226#L1438-36 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 23227#L1438-38 assume 1 == ~M_E~0;~M_E~0 := 2; 24201#L1213-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24297#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23659#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23660#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23842#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23843#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24079#L1243-3 assume !(1 == ~T7_E~0); 24080#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24539#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24544#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 23639#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 23640#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24511#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 24529#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 24531#L1283-3 assume !(1 == ~E_4~0); 23965#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23966#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23832#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 23833#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24272#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 23829#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 23830#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 23641#L1323-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 23642#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 23584#L891-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 23983#L892-1 start_simulation_#t~ret33 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 24408#L1663 assume !(0 == start_simulation_~tmp~3); 23929#L1663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret32, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 24178#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 23425#L891-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 24098#L892-2 stop_simulation_#t~ret32 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret32;havoc stop_simulation_#t~ret32; 23366#L1618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 23367#L1625 stop_simulation_#res := stop_simulation_~__retres2~0; 23703#L1626 start_simulation_#t~ret34 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret34;havoc start_simulation_#t~ret34; 24597#L1676 assume !(0 != start_simulation_~tmp___0~1); 24598#L1644-1 [2021-11-07 07:22:21,445 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:21,445 INFO L85 PathProgramCache]: Analyzing trace with hash -1805812287, now seen corresponding path program 1 times [2021-11-07 07:22:21,445 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:21,445 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1137750494] [2021-11-07 07:22:21,446 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:21,446 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:21,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:21,484 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:21,484 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:21,487 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1137750494] [2021-11-07 07:22:21,487 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1137750494] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:21,487 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:21,488 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:21,488 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1534236101] [2021-11-07 07:22:21,489 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:22:21,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:21,489 INFO L85 PathProgramCache]: Analyzing trace with hash -181645258, now seen corresponding path program 1 times [2021-11-07 07:22:21,490 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:21,490 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [185051994] [2021-11-07 07:22:21,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:21,490 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:21,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:21,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:21,546 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:21,546 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [185051994] [2021-11-07 07:22:21,546 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [185051994] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:21,546 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:21,547 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:21,547 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [904056638] [2021-11-07 07:22:21,547 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:22:21,548 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:22:21,548 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:22:21,548 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:22:21,549 INFO L87 Difference]: Start difference. First operand 1446 states and 2155 transitions. cyclomatic complexity: 710 Second operand has 3 states, 3 states have (on average 44.333333333333336) internal successors, (133), 3 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:21,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:22:21,626 INFO L93 Difference]: Finished difference Result 1446 states and 2154 transitions. [2021-11-07 07:22:21,627 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:22:21,627 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1446 states and 2154 transitions. [2021-11-07 07:22:21,638 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:21,652 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1446 states to 1446 states and 2154 transitions. [2021-11-07 07:22:21,652 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1446 [2021-11-07 07:22:21,654 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1446 [2021-11-07 07:22:21,654 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1446 states and 2154 transitions. [2021-11-07 07:22:21,657 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:22:21,657 INFO L681 BuchiCegarLoop]: Abstraction has 1446 states and 2154 transitions. [2021-11-07 07:22:21,661 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1446 states and 2154 transitions. [2021-11-07 07:22:21,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1446 to 1446. [2021-11-07 07:22:21,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1446 states, 1446 states have (on average 1.4896265560165975) internal successors, (2154), 1445 states have internal predecessors, (2154), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:21,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1446 states to 1446 states and 2154 transitions. [2021-11-07 07:22:21,697 INFO L704 BuchiCegarLoop]: Abstraction has 1446 states and 2154 transitions. [2021-11-07 07:22:21,697 INFO L587 BuchiCegarLoop]: Abstraction has 1446 states and 2154 transitions. [2021-11-07 07:22:21,698 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-07 07:22:21,698 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1446 states and 2154 transitions. [2021-11-07 07:22:21,705 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:21,706 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:22:21,706 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:22:21,709 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:21,709 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:21,709 INFO L791 eck$LassoCheckResult]: Stem: 27200#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 27201#L-1 havoc main_#res;havoc main_~__retres1~13;havoc main_~__retres1~13;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 27208#L1607 havoc start_simulation_#t~ret33, start_simulation_#t~ret34, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 27209#L754 assume 1 == ~m_i~0;~m_st~0 := 0; 27339#L761-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26860#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26773#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26503#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26143#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26144#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26192#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26193#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27096#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27097#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 27132#L811-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 26603#L816-1 assume !(0 == ~M_E~0); 26604#L1090-1 assume !(0 == ~T1_E~0); 27486#L1095-1 assume !(0 == ~T2_E~0); 27268#L1100-1 assume !(0 == ~T3_E~0); 27269#L1105-1 assume !(0 == ~T4_E~0); 26422#L1110-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26423#L1115-1 assume !(0 == ~T6_E~0); 26808#L1120-1 assume !(0 == ~T7_E~0); 27076#L1125-1 assume !(0 == ~T8_E~0); 27539#L1130-1 assume !(0 == ~T9_E~0); 27288#L1135-1 assume !(0 == ~T10_E~0); 26608#L1140-1 assume !(0 == ~T11_E~0); 26609#L1145-1 assume !(0 == ~E_1~0); 27224#L1150-1 assume 0 == ~E_2~0;~E_2~0 := 1; 26783#L1155-1 assume !(0 == ~E_3~0); 26784#L1160-1 assume !(0 == ~E_4~0); 26868#L1165-1 assume !(0 == ~E_5~0); 26869#L1170-1 assume !(0 == ~E_6~0); 27458#L1175-1 assume !(0 == ~E_7~0); 26941#L1180-1 assume !(0 == ~E_8~0); 26942#L1185-1 assume !(0 == ~E_9~0); 26605#L1190-1 assume 0 == ~E_10~0;~E_10~0 := 1; 26606#L1195-1 assume !(0 == ~E_11~0); 26955#L1200-1 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 26798#L525 assume !(1 == ~m_pc~0); 26231#L525-2 is_master_triggered_~__retres1~0 := 0; 26232#L536 is_master_triggered_#res := is_master_triggered_~__retres1~0; 26959#L537 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 26960#L1350 assume !(0 != activate_threads_~tmp~1); 26592#L1350-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26593#L544 assume 1 == ~t1_pc~0; 26844#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 26807#L555 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27222#L556 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 26444#L1358 assume !(0 != activate_threads_~tmp___0~0); 26445#L1358-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27048#L563 assume !(1 == ~t2_pc~0); 27210#L563-2 is_transmit2_triggered_~__retres1~2 := 0; 26252#L574 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26253#L575 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 26670#L1366 assume !(0 != activate_threads_~tmp___1~0); 26671#L1366-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27116#L582 assume 1 == ~t3_pc~0; 26386#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 26387#L593 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27512#L594 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 27467#L1374 assume !(0 != activate_threads_~tmp___2~0); 26326#L1374-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 26327#L601 assume !(1 == ~t4_pc~0); 27239#L601-2 is_transmit4_triggered_~__retres1~4 := 0; 26809#L612 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 26810#L613 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 27233#L1382 assume !(0 != activate_threads_~tmp___3~0); 27234#L1382-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 27504#L620 assume 1 == ~t5_pc~0; 26281#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 26282#L631 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 27072#L632 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 27073#L1390 assume !(0 != activate_threads_~tmp___4~0); 27519#L1390-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 27520#L639 assume 1 == ~t6_pc~0; 27490#L640 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 26709#L650 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 26710#L651 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 27470#L1398 assume !(0 != activate_threads_~tmp___5~0); 26817#L1398-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 26818#L658 assume !(1 == ~t7_pc~0); 27000#L658-2 is_transmit7_triggered_~__retres1~7 := 0; 27001#L669 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 27105#L670 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 27106#L1406 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 26599#L1406-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 26600#L677 assume 1 == ~t8_pc~0; 26820#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 26403#L688 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 26404#L689 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 26667#L1414 assume !(0 != activate_threads_~tmp___7~0); 26668#L1414-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 27327#L696 assume !(1 == ~t9_pc~0); 27058#L696-2 is_transmit9_triggered_~__retres1~9 := 0; 27059#L707 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 27144#L708 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 27080#L1422 assume !(0 != activate_threads_~tmp___8~0); 27081#L1422-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 27272#L715 assume 1 == ~t10_pc~0; 27276#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 27161#L726 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 27050#L727 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 27051#L1430 assume !(0 != activate_threads_~tmp___9~0); 26933#L1430-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 26395#L734 assume !(1 == ~t11_pc~0); 26396#L734-2 is_transmit11_triggered_~__retres1~11 := 0; 26870#L745 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 26946#L746 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 26131#L1438 assume !(0 != activate_threads_~tmp___10~0); 26132#L1438-2 assume !(1 == ~M_E~0); 27131#L1213-1 assume !(1 == ~T1_E~0); 27314#L1218-1 assume !(1 == ~T2_E~0); 26168#L1223-1 assume !(1 == ~T3_E~0); 26169#L1228-1 assume !(1 == ~T4_E~0); 26912#L1233-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27521#L1238-1 assume !(1 == ~T6_E~0); 27231#L1243-1 assume !(1 == ~T7_E~0); 27232#L1248-1 assume !(1 == ~T8_E~0); 27274#L1253-1 assume !(1 == ~T9_E~0); 27275#L1258-1 assume !(1 == ~T10_E~0); 27254#L1263-1 assume !(1 == ~T11_E~0); 27255#L1268-1 assume !(1 == ~E_1~0); 27094#L1273-1 assume 1 == ~E_2~0;~E_2~0 := 2; 27095#L1278-1 assume !(1 == ~E_3~0); 26707#L1283-1 assume !(1 == ~E_4~0); 26708#L1288-1 assume !(1 == ~E_5~0); 27367#L1293-1 assume !(1 == ~E_6~0); 27331#L1298-1 assume !(1 == ~E_7~0); 27119#L1303-1 assume !(1 == ~E_8~0); 26718#L1308-1 assume !(1 == ~E_9~0); 26614#L1313-1 assume 1 == ~E_10~0;~E_10~0 := 2; 26615#L1318-1 assume !(1 == ~E_11~0); 27497#L1644-1 [2021-11-07 07:22:21,710 INFO L793 eck$LassoCheckResult]: Loop: 27497#L1644-1 assume !false; 27172#L1645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_~tmp~0;havoc eval_~tmp~0; 27148#L1065 assume !false; 27247#L902 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 27517#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 26250#L891 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 27431#L892 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 26723#L906 assume !(0 != eval_~tmp~0); 26725#L1080 start_simulation_~kernel_st~0 := 2; 27245#L754-1 start_simulation_~kernel_st~0 := 3; 26641#L1090-2 assume 0 == ~M_E~0;~M_E~0 := 1; 26642#L1090-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 27483#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27398#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27399#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26498#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26499#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26774#L1120-3 assume !(0 == ~T7_E~0); 26775#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 27229#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 27479#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26697#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26204#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26205#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26328#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26329#L1160-3 assume !(0 == ~E_4~0); 26679#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26680#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27040#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 26595#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 26356#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 26357#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 27473#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 27474#L1200-3 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 26897#L525-36 assume 1 == ~m_pc~0; 26898#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 26455#L536-12 is_master_triggered_#res := is_master_triggered_~__retres1~0; 26456#L537-12 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 26733#L1350-36 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 26734#L1350-38 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26644#L544-36 assume 1 == ~t1_pc~0; 26645#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 27150#L555-12 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26538#L556-12 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 26539#L1358-36 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 27455#L1358-38 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27360#L563-36 assume 1 == ~t2_pc~0; 26442#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 26202#L574-12 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26203#L575-12 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 27237#L1366-36 assume !(0 != activate_threads_~tmp___1~0); 26910#L1366-38 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 26911#L582-36 assume 1 == ~t3_pc~0; 26765#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 26766#L593-12 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 26982#L594-12 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 27141#L1374-36 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 26945#L1374-38 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 26891#L601-36 assume 1 == ~t4_pc~0; 26791#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 26793#L612-12 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 27525#L613-12 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 27440#L1382-36 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 27441#L1382-38 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 27349#L620-36 assume 1 == ~t5_pc~0; 26834#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 26835#L631-12 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 27213#L632-12 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 26819#L1390-36 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 26464#L1390-38 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 26246#L639-36 assume !(1 == ~t6_pc~0); 26247#L639-38 is_transmit6_triggered_~__retres1~6 := 0; 26286#L650-12 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 26287#L651-12 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 26521#L1398-36 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 26522#L1398-38 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 27079#L658-36 assume !(1 == ~t7_pc~0); 26257#L658-38 is_transmit7_triggered_~__retres1~7 := 0; 26258#L669-12 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 27426#L670-12 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 26235#L1406-36 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 26236#L1406-38 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 27197#L677-36 assume 1 == ~t8_pc~0; 27372#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 27006#L688-12 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 27117#L689-12 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 27500#L1414-36 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 27028#L1414-38 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 27029#L696-36 assume 1 == ~t9_pc~0; 26929#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 26930#L707-12 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 26306#L708-12 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 26307#L1422-36 assume !(0 != activate_threads_~tmp___8~0); 27041#L1422-38 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 27042#L715-36 assume 1 == ~t10_pc~0; 27170#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 26133#L726-12 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 26134#L727-12 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 26107#L1430-36 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 26108#L1430-38 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 26507#L734-36 assume !(1 == ~t11_pc~0); 26211#L734-38 is_transmit11_triggered_~__retres1~11 := 0; 26212#L745-12 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 26529#L746-12 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 26125#L1438-36 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 26126#L1438-38 assume 1 == ~M_E~0;~M_E~0 := 2; 27100#L1213-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27196#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26558#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26559#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26741#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26742#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26978#L1243-3 assume !(1 == ~T7_E~0); 26979#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 27439#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 27444#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26540#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 26541#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27410#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27428#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27430#L1283-3 assume !(1 == ~E_4~0); 26864#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26865#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26731#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26732#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27171#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 26728#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26729#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 26542#L1323-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 26543#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 26483#L891-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 26882#L892-1 start_simulation_#t~ret33 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 27307#L1663 assume !(0 == start_simulation_~tmp~3); 26828#L1663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret32, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 27077#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 26324#L891-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 26999#L892-2 stop_simulation_#t~ret32 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret32;havoc stop_simulation_#t~ret32; 26268#L1618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 26269#L1625 stop_simulation_#res := stop_simulation_~__retres2~0; 26602#L1626 start_simulation_#t~ret34 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret34;havoc start_simulation_#t~ret34; 27496#L1676 assume !(0 != start_simulation_~tmp___0~1); 27497#L1644-1 [2021-11-07 07:22:21,711 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:21,711 INFO L85 PathProgramCache]: Analyzing trace with hash -713177085, now seen corresponding path program 1 times [2021-11-07 07:22:21,711 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:21,712 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1314637594] [2021-11-07 07:22:21,712 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:21,712 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:21,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:21,747 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:21,747 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:21,747 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1314637594] [2021-11-07 07:22:21,748 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1314637594] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:21,748 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:21,748 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:21,748 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1420812791] [2021-11-07 07:22:21,749 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:22:21,749 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:21,750 INFO L85 PathProgramCache]: Analyzing trace with hash 992156468, now seen corresponding path program 2 times [2021-11-07 07:22:21,750 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:21,750 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [719542052] [2021-11-07 07:22:21,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:21,751 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:21,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:21,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:21,807 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:21,808 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [719542052] [2021-11-07 07:22:21,808 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [719542052] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:21,808 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:21,808 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:21,808 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1758030382] [2021-11-07 07:22:21,809 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:22:21,809 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:22:21,810 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:22:21,810 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:22:21,811 INFO L87 Difference]: Start difference. First operand 1446 states and 2154 transitions. cyclomatic complexity: 709 Second operand has 3 states, 3 states have (on average 44.333333333333336) internal successors, (133), 3 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:21,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:22:21,846 INFO L93 Difference]: Finished difference Result 1446 states and 2153 transitions. [2021-11-07 07:22:21,846 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:22:21,846 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1446 states and 2153 transitions. [2021-11-07 07:22:21,858 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:21,873 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1446 states to 1446 states and 2153 transitions. [2021-11-07 07:22:21,873 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1446 [2021-11-07 07:22:21,875 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1446 [2021-11-07 07:22:21,875 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1446 states and 2153 transitions. [2021-11-07 07:22:21,878 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:22:21,878 INFO L681 BuchiCegarLoop]: Abstraction has 1446 states and 2153 transitions. [2021-11-07 07:22:21,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1446 states and 2153 transitions. [2021-11-07 07:22:21,907 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1446 to 1446. [2021-11-07 07:22:21,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1446 states, 1446 states have (on average 1.4889349930843707) internal successors, (2153), 1445 states have internal predecessors, (2153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:21,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1446 states to 1446 states and 2153 transitions. [2021-11-07 07:22:21,928 INFO L704 BuchiCegarLoop]: Abstraction has 1446 states and 2153 transitions. [2021-11-07 07:22:21,928 INFO L587 BuchiCegarLoop]: Abstraction has 1446 states and 2153 transitions. [2021-11-07 07:22:21,928 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-07 07:22:21,929 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1446 states and 2153 transitions. [2021-11-07 07:22:21,936 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:21,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:22:21,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:22:21,940 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:21,940 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:21,940 INFO L791 eck$LassoCheckResult]: Stem: 30099#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 30100#L-1 havoc main_#res;havoc main_~__retres1~13;havoc main_~__retres1~13;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 30109#L1607 havoc start_simulation_#t~ret33, start_simulation_#t~ret34, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 30110#L754 assume 1 == ~m_i~0;~m_st~0 := 0; 30238#L761-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29759#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29672#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29402#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29042#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29043#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29091#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29092#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 29995#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29996#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 30031#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 29502#L816-1 assume !(0 == ~M_E~0); 29503#L1090-1 assume !(0 == ~T1_E~0); 30385#L1095-1 assume !(0 == ~T2_E~0); 30167#L1100-1 assume !(0 == ~T3_E~0); 30168#L1105-1 assume !(0 == ~T4_E~0); 29321#L1110-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29322#L1115-1 assume !(0 == ~T6_E~0); 29707#L1120-1 assume !(0 == ~T7_E~0); 29975#L1125-1 assume !(0 == ~T8_E~0); 30438#L1130-1 assume !(0 == ~T9_E~0); 30187#L1135-1 assume !(0 == ~T10_E~0); 29507#L1140-1 assume !(0 == ~T11_E~0); 29508#L1145-1 assume !(0 == ~E_1~0); 30123#L1150-1 assume 0 == ~E_2~0;~E_2~0 := 1; 29682#L1155-1 assume !(0 == ~E_3~0); 29683#L1160-1 assume !(0 == ~E_4~0); 29767#L1165-1 assume !(0 == ~E_5~0); 29768#L1170-1 assume !(0 == ~E_6~0); 30357#L1175-1 assume !(0 == ~E_7~0); 29840#L1180-1 assume !(0 == ~E_8~0); 29841#L1185-1 assume !(0 == ~E_9~0); 29504#L1190-1 assume 0 == ~E_10~0;~E_10~0 := 1; 29505#L1195-1 assume !(0 == ~E_11~0); 29854#L1200-1 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 29701#L525 assume !(1 == ~m_pc~0); 29130#L525-2 is_master_triggered_~__retres1~0 := 0; 29131#L536 is_master_triggered_#res := is_master_triggered_~__retres1~0; 29858#L537 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 29859#L1350 assume !(0 != activate_threads_~tmp~1); 29491#L1350-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 29492#L544 assume 1 == ~t1_pc~0; 29743#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 29706#L555 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30121#L556 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 29343#L1358 assume !(0 != activate_threads_~tmp___0~0); 29344#L1358-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 29947#L563 assume !(1 == ~t2_pc~0); 30111#L563-2 is_transmit2_triggered_~__retres1~2 := 0; 29151#L574 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29152#L575 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 29569#L1366 assume !(0 != activate_threads_~tmp___1~0); 29570#L1366-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30015#L582 assume 1 == ~t3_pc~0; 29287#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 29288#L593 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30411#L594 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 30366#L1374 assume !(0 != activate_threads_~tmp___2~0); 29225#L1374-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 29226#L601 assume !(1 == ~t4_pc~0); 30138#L601-2 is_transmit4_triggered_~__retres1~4 := 0; 29708#L612 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 29709#L613 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 30132#L1382 assume !(0 != activate_threads_~tmp___3~0); 30133#L1382-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 30403#L620 assume 1 == ~t5_pc~0; 29180#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 29181#L631 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 29971#L632 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 29972#L1390 assume !(0 != activate_threads_~tmp___4~0); 30418#L1390-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 30419#L639 assume 1 == ~t6_pc~0; 30389#L640 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 29608#L650 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 29609#L651 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 30369#L1398 assume !(0 != activate_threads_~tmp___5~0); 29716#L1398-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 29717#L658 assume !(1 == ~t7_pc~0); 29899#L658-2 is_transmit7_triggered_~__retres1~7 := 0; 29900#L669 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 30004#L670 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 30005#L1406 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 29498#L1406-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 29499#L677 assume 1 == ~t8_pc~0; 29719#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 29302#L688 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 29303#L689 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 29566#L1414 assume !(0 != activate_threads_~tmp___7~0); 29567#L1414-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 30226#L696 assume !(1 == ~t9_pc~0); 29958#L696-2 is_transmit9_triggered_~__retres1~9 := 0; 29959#L707 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 30043#L708 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 29979#L1422 assume !(0 != activate_threads_~tmp___8~0); 29980#L1422-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 30171#L715 assume 1 == ~t10_pc~0; 30175#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 30060#L726 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 29949#L727 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 29950#L1430 assume !(0 != activate_threads_~tmp___9~0); 29832#L1430-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 29294#L734 assume !(1 == ~t11_pc~0); 29295#L734-2 is_transmit11_triggered_~__retres1~11 := 0; 29769#L745 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 29845#L746 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 29032#L1438 assume !(0 != activate_threads_~tmp___10~0); 29033#L1438-2 assume !(1 == ~M_E~0); 30030#L1213-1 assume !(1 == ~T1_E~0); 30213#L1218-1 assume !(1 == ~T2_E~0); 29067#L1223-1 assume !(1 == ~T3_E~0); 29068#L1228-1 assume !(1 == ~T4_E~0); 29811#L1233-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30420#L1238-1 assume !(1 == ~T6_E~0); 30130#L1243-1 assume !(1 == ~T7_E~0); 30131#L1248-1 assume !(1 == ~T8_E~0); 30173#L1253-1 assume !(1 == ~T9_E~0); 30174#L1258-1 assume !(1 == ~T10_E~0); 30153#L1263-1 assume !(1 == ~T11_E~0); 30154#L1268-1 assume !(1 == ~E_1~0); 29993#L1273-1 assume 1 == ~E_2~0;~E_2~0 := 2; 29994#L1278-1 assume !(1 == ~E_3~0); 29606#L1283-1 assume !(1 == ~E_4~0); 29607#L1288-1 assume !(1 == ~E_5~0); 30266#L1293-1 assume !(1 == ~E_6~0); 30230#L1298-1 assume !(1 == ~E_7~0); 30018#L1303-1 assume !(1 == ~E_8~0); 29617#L1308-1 assume !(1 == ~E_9~0); 29513#L1313-1 assume 1 == ~E_10~0;~E_10~0 := 2; 29514#L1318-1 assume !(1 == ~E_11~0); 30396#L1644-1 [2021-11-07 07:22:21,941 INFO L793 eck$LassoCheckResult]: Loop: 30396#L1644-1 assume !false; 30071#L1645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_~tmp~0;havoc eval_~tmp~0; 30047#L1065 assume !false; 30146#L902 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 30416#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 29149#L891 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 30330#L892 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 29622#L906 assume !(0 != eval_~tmp~0); 29624#L1080 start_simulation_~kernel_st~0 := 2; 30144#L754-1 start_simulation_~kernel_st~0 := 3; 29540#L1090-2 assume 0 == ~M_E~0;~M_E~0 := 1; 29541#L1090-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 30382#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30297#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 30298#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29397#L1110-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29398#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29673#L1120-3 assume !(0 == ~T7_E~0); 29674#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 30128#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30378#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29596#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 29105#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29106#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29228#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29229#L1160-3 assume !(0 == ~E_4~0); 29578#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29579#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29939#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29494#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29256#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29257#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 30372#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 30373#L1200-3 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 29796#L525-36 assume 1 == ~m_pc~0; 29797#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 29356#L536-12 is_master_triggered_#res := is_master_triggered_~__retres1~0; 29357#L537-12 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 29632#L1350-36 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 29633#L1350-38 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 29543#L544-36 assume 1 == ~t1_pc~0; 29544#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 30049#L555-12 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 29443#L556-12 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 29444#L1358-36 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 30355#L1358-38 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30259#L563-36 assume 1 == ~t2_pc~0; 29341#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 29101#L574-12 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29102#L575-12 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 30136#L1366-36 assume !(0 != activate_threads_~tmp___1~0); 29809#L1366-38 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 29810#L582-36 assume 1 == ~t3_pc~0; 29664#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 29665#L593-12 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 29881#L594-12 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 30040#L1374-36 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 29844#L1374-38 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 29790#L601-36 assume 1 == ~t4_pc~0; 29690#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 29692#L612-12 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 30424#L613-12 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 30339#L1382-36 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 30340#L1382-38 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 30248#L620-36 assume 1 == ~t5_pc~0; 29734#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 29735#L631-12 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 30114#L632-12 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 29718#L1390-36 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 29363#L1390-38 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 29145#L639-36 assume !(1 == ~t6_pc~0); 29146#L639-38 is_transmit6_triggered_~__retres1~6 := 0; 29185#L650-12 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 29186#L651-12 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 29420#L1398-36 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 29421#L1398-38 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 29978#L658-36 assume !(1 == ~t7_pc~0); 29156#L658-38 is_transmit7_triggered_~__retres1~7 := 0; 29157#L669-12 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 30325#L670-12 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 29132#L1406-36 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 29133#L1406-38 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 30096#L677-36 assume 1 == ~t8_pc~0; 30270#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 29904#L688-12 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 30016#L689-12 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 30399#L1414-36 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 29927#L1414-38 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 29928#L696-36 assume 1 == ~t9_pc~0; 29828#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 29829#L707-12 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 29202#L708-12 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 29203#L1422-36 assume !(0 != activate_threads_~tmp___8~0); 29940#L1422-38 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 29941#L715-36 assume 1 == ~t10_pc~0; 30069#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 29030#L726-12 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 29031#L727-12 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 29006#L1430-36 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 29007#L1430-38 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 29406#L734-36 assume !(1 == ~t11_pc~0); 29110#L734-38 is_transmit11_triggered_~__retres1~11 := 0; 29111#L745-12 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 29428#L746-12 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 29024#L1438-36 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 29025#L1438-38 assume 1 == ~M_E~0;~M_E~0 := 2; 29999#L1213-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30095#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29457#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29458#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29640#L1233-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29641#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29877#L1243-3 assume !(1 == ~T7_E~0); 29878#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 30337#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30342#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29437#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29438#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30309#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30327#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30329#L1283-3 assume !(1 == ~E_4~0); 29763#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29764#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29629#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29630#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 30070#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29627#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29628#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29439#L1323-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 29440#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 29382#L891-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 29781#L892-1 start_simulation_#t~ret33 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 30206#L1663 assume !(0 == start_simulation_~tmp~3); 29727#L1663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret32, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 29976#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 29223#L891-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 29896#L892-2 stop_simulation_#t~ret32 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret32;havoc stop_simulation_#t~ret32; 29164#L1618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 29165#L1625 stop_simulation_#res := stop_simulation_~__retres2~0; 29501#L1626 start_simulation_#t~ret34 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret34;havoc start_simulation_#t~ret34; 30395#L1676 assume !(0 != start_simulation_~tmp___0~1); 30396#L1644-1 [2021-11-07 07:22:21,941 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:21,942 INFO L85 PathProgramCache]: Analyzing trace with hash 568995201, now seen corresponding path program 1 times [2021-11-07 07:22:21,942 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:21,942 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [325028064] [2021-11-07 07:22:21,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:21,942 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:21,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:21,990 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:21,990 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:21,990 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [325028064] [2021-11-07 07:22:21,990 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [325028064] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:21,990 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:21,991 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 07:22:21,991 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1509674678] [2021-11-07 07:22:21,991 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:22:21,992 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:21,992 INFO L85 PathProgramCache]: Analyzing trace with hash 992156468, now seen corresponding path program 3 times [2021-11-07 07:22:21,992 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:21,992 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [583071727] [2021-11-07 07:22:21,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:21,993 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:22,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:22,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:22,062 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:22,062 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [583071727] [2021-11-07 07:22:22,062 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [583071727] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:22,062 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:22,063 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:22,063 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2055671453] [2021-11-07 07:22:22,063 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:22:22,064 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:22:22,064 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:22:22,064 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:22:22,065 INFO L87 Difference]: Start difference. First operand 1446 states and 2153 transitions. cyclomatic complexity: 708 Second operand has 3 states, 3 states have (on average 44.333333333333336) internal successors, (133), 2 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:22,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:22:22,107 INFO L93 Difference]: Finished difference Result 1446 states and 2148 transitions. [2021-11-07 07:22:22,107 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:22:22,107 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1446 states and 2148 transitions. [2021-11-07 07:22:22,118 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:22,131 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1446 states to 1446 states and 2148 transitions. [2021-11-07 07:22:22,131 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1446 [2021-11-07 07:22:22,133 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1446 [2021-11-07 07:22:22,133 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1446 states and 2148 transitions. [2021-11-07 07:22:22,136 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:22:22,137 INFO L681 BuchiCegarLoop]: Abstraction has 1446 states and 2148 transitions. [2021-11-07 07:22:22,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1446 states and 2148 transitions. [2021-11-07 07:22:22,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1446 to 1446. [2021-11-07 07:22:22,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1446 states, 1446 states have (on average 1.4854771784232366) internal successors, (2148), 1445 states have internal predecessors, (2148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:22,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1446 states to 1446 states and 2148 transitions. [2021-11-07 07:22:22,174 INFO L704 BuchiCegarLoop]: Abstraction has 1446 states and 2148 transitions. [2021-11-07 07:22:22,174 INFO L587 BuchiCegarLoop]: Abstraction has 1446 states and 2148 transitions. [2021-11-07 07:22:22,174 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-07 07:22:22,175 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1446 states and 2148 transitions. [2021-11-07 07:22:22,182 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:22,182 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:22:22,182 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:22:22,185 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:22,185 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:22,185 INFO L791 eck$LassoCheckResult]: Stem: 32998#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 32999#L-1 havoc main_#res;havoc main_~__retres1~13;havoc main_~__retres1~13;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 33008#L1607 havoc start_simulation_#t~ret33, start_simulation_#t~ret34, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 33009#L754 assume 1 == ~m_i~0;~m_st~0 := 0; 33137#L761-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32658#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32571#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32301#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31941#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31942#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 31990#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 31991#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32896#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 32897#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 32937#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 32401#L816-1 assume !(0 == ~M_E~0); 32402#L1090-1 assume !(0 == ~T1_E~0); 33284#L1095-1 assume !(0 == ~T2_E~0); 33066#L1100-1 assume !(0 == ~T3_E~0); 33067#L1105-1 assume !(0 == ~T4_E~0); 32221#L1110-1 assume !(0 == ~T5_E~0); 32222#L1115-1 assume !(0 == ~T6_E~0); 32609#L1120-1 assume !(0 == ~T7_E~0); 32874#L1125-1 assume !(0 == ~T8_E~0); 33337#L1130-1 assume !(0 == ~T9_E~0); 33086#L1135-1 assume !(0 == ~T10_E~0); 32408#L1140-1 assume !(0 == ~T11_E~0); 32409#L1145-1 assume !(0 == ~E_1~0); 33022#L1150-1 assume 0 == ~E_2~0;~E_2~0 := 1; 32581#L1155-1 assume !(0 == ~E_3~0); 32582#L1160-1 assume !(0 == ~E_4~0); 32666#L1165-1 assume !(0 == ~E_5~0); 32667#L1170-1 assume !(0 == ~E_6~0); 33256#L1175-1 assume !(0 == ~E_7~0); 32739#L1180-1 assume !(0 == ~E_8~0); 32740#L1185-1 assume !(0 == ~E_9~0); 32403#L1190-1 assume 0 == ~E_10~0;~E_10~0 := 1; 32404#L1195-1 assume !(0 == ~E_11~0); 32753#L1200-1 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 32603#L525 assume !(1 == ~m_pc~0); 32029#L525-2 is_master_triggered_~__retres1~0 := 0; 32030#L536 is_master_triggered_#res := is_master_triggered_~__retres1~0; 32757#L537 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 32758#L1350 assume !(0 != activate_threads_~tmp~1); 32391#L1350-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32392#L544 assume 1 == ~t1_pc~0; 32642#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 32605#L555 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 33020#L556 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 32242#L1358 assume !(0 != activate_threads_~tmp___0~0); 32243#L1358-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 32846#L563 assume !(1 == ~t2_pc~0); 33010#L563-2 is_transmit2_triggered_~__retres1~2 := 0; 32050#L574 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 32051#L575 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 32471#L1366 assume !(0 != activate_threads_~tmp___1~0); 32472#L1366-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 32914#L582 assume 1 == ~t3_pc~0; 32186#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 32187#L593 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 33310#L594 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 33265#L1374 assume !(0 != activate_threads_~tmp___2~0); 32124#L1374-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32125#L601 assume !(1 == ~t4_pc~0); 33037#L601-2 is_transmit4_triggered_~__retres1~4 := 0; 32610#L612 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 32611#L613 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 33031#L1382 assume !(0 != activate_threads_~tmp___3~0); 33032#L1382-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 33302#L620 assume 1 == ~t5_pc~0; 32083#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 32084#L631 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 32870#L632 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 32871#L1390 assume !(0 != activate_threads_~tmp___4~0); 33317#L1390-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 33318#L639 assume 1 == ~t6_pc~0; 33288#L640 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 32507#L650 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 32508#L651 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 33268#L1398 assume !(0 != activate_threads_~tmp___5~0); 32615#L1398-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 32616#L658 assume !(1 == ~t7_pc~0); 32800#L658-2 is_transmit7_triggered_~__retres1~7 := 0; 32801#L669 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 32903#L670 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 32904#L1406 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 32397#L1406-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 32398#L677 assume 1 == ~t8_pc~0; 32620#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 32204#L688 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 32205#L689 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 32465#L1414 assume !(0 != activate_threads_~tmp___7~0); 32466#L1414-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 33125#L696 assume !(1 == ~t9_pc~0); 32859#L696-2 is_transmit9_triggered_~__retres1~9 := 0; 32860#L707 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 32945#L708 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 32880#L1422 assume !(0 != activate_threads_~tmp___8~0); 32881#L1422-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 33070#L715 assume 1 == ~t10_pc~0; 33074#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 32959#L726 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 32848#L727 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 32849#L1430 assume !(0 != activate_threads_~tmp___9~0); 32731#L1430-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 32195#L734 assume !(1 == ~t11_pc~0); 32196#L734-2 is_transmit11_triggered_~__retres1~11 := 0; 32668#L745 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 32744#L746 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 31931#L1438 assume !(0 != activate_threads_~tmp___10~0); 31932#L1438-2 assume !(1 == ~M_E~0); 32929#L1213-1 assume !(1 == ~T1_E~0); 33112#L1218-1 assume !(1 == ~T2_E~0); 31966#L1223-1 assume !(1 == ~T3_E~0); 31967#L1228-1 assume !(1 == ~T4_E~0); 32710#L1233-1 assume !(1 == ~T5_E~0); 33319#L1238-1 assume !(1 == ~T6_E~0); 33029#L1243-1 assume !(1 == ~T7_E~0); 33030#L1248-1 assume !(1 == ~T8_E~0); 33072#L1253-1 assume !(1 == ~T9_E~0); 33073#L1258-1 assume !(1 == ~T10_E~0); 33052#L1263-1 assume !(1 == ~T11_E~0); 33053#L1268-1 assume !(1 == ~E_1~0); 32892#L1273-1 assume 1 == ~E_2~0;~E_2~0 := 2; 32893#L1278-1 assume !(1 == ~E_3~0); 32505#L1283-1 assume !(1 == ~E_4~0); 32506#L1288-1 assume !(1 == ~E_5~0); 33165#L1293-1 assume !(1 == ~E_6~0); 33129#L1298-1 assume !(1 == ~E_7~0); 32917#L1303-1 assume !(1 == ~E_8~0); 32516#L1308-1 assume !(1 == ~E_9~0); 32414#L1313-1 assume 1 == ~E_10~0;~E_10~0 := 2; 32415#L1318-1 assume !(1 == ~E_11~0); 33295#L1644-1 [2021-11-07 07:22:22,186 INFO L793 eck$LassoCheckResult]: Loop: 33295#L1644-1 assume !false; 32970#L1645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_~tmp~0;havoc eval_~tmp~0; 32946#L1065 assume !false; 33045#L902 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 33315#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 32048#L891 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 33229#L892 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 32521#L906 assume !(0 != eval_~tmp~0); 32523#L1080 start_simulation_~kernel_st~0 := 2; 33044#L754-1 start_simulation_~kernel_st~0 := 3; 32443#L1090-2 assume 0 == ~M_E~0;~M_E~0 := 1; 32444#L1090-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33281#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33196#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33197#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32296#L1110-3 assume !(0 == ~T5_E~0); 32297#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32572#L1120-3 assume !(0 == ~T7_E~0); 32573#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33027#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 33277#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32495#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32002#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32003#L1150-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32126#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32127#L1160-3 assume !(0 == ~E_4~0); 32477#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32478#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32838#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 32393#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 32154#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32155#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 33271#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 33272#L1200-3 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 32692#L525-36 assume 1 == ~m_pc~0; 32693#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 32253#L536-12 is_master_triggered_#res := is_master_triggered_~__retres1~0; 32254#L537-12 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 32531#L1350-36 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 32532#L1350-38 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32440#L544-36 assume 1 == ~t1_pc~0; 32441#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 32948#L555-12 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 32336#L556-12 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 32337#L1358-36 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 33253#L1358-38 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 33158#L563-36 assume 1 == ~t2_pc~0; 32240#L564-12 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 32000#L574-12 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 32001#L575-12 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 33035#L1366-36 assume !(0 != activate_threads_~tmp___1~0); 32708#L1366-38 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 32709#L582-36 assume 1 == ~t3_pc~0; 32563#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 32564#L593-12 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 32780#L594-12 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 32939#L1374-36 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 32743#L1374-38 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32689#L601-36 assume 1 == ~t4_pc~0; 32589#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 32591#L612-12 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 33323#L613-12 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 33238#L1382-36 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 33239#L1382-38 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 33147#L620-36 assume 1 == ~t5_pc~0; 32632#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 32633#L631-12 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 33011#L632-12 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 32617#L1390-36 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 32262#L1390-38 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 32044#L639-36 assume !(1 == ~t6_pc~0); 32045#L639-38 is_transmit6_triggered_~__retres1~6 := 0; 32081#L650-12 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 32082#L651-12 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 32317#L1398-36 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 32318#L1398-38 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 32877#L658-36 assume 1 == ~t7_pc~0; 32161#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 32056#L669-12 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 33224#L670-12 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 32033#L1406-36 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 32034#L1406-38 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 32995#L677-36 assume 1 == ~t8_pc~0; 33170#L678-12 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 32804#L688-12 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 32915#L689-12 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 33298#L1414-36 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 32826#L1414-38 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 32827#L696-36 assume 1 == ~t9_pc~0; 32727#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 32728#L707-12 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 32104#L708-12 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 32105#L1422-36 assume !(0 != activate_threads_~tmp___8~0); 32839#L1422-38 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 32840#L715-36 assume 1 == ~t10_pc~0; 32968#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 31929#L726-12 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 31930#L727-12 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 31905#L1430-36 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 31906#L1430-38 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 32305#L734-36 assume 1 == ~t11_pc~0; 32306#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 32010#L745-12 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 32327#L746-12 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 31923#L1438-36 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 31924#L1438-38 assume 1 == ~M_E~0;~M_E~0 := 2; 32898#L1213-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32994#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32356#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32357#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32539#L1233-3 assume !(1 == ~T5_E~0); 32540#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32776#L1243-3 assume !(1 == ~T7_E~0); 32777#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33236#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33242#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32338#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32339#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33208#L1273-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33226#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33228#L1283-3 assume !(1 == ~E_4~0); 32662#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32663#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32529#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32530#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32969#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32526#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32527#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32340#L1323-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 32341#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 32281#L891-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 32680#L892-1 start_simulation_#t~ret33 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 33105#L1663 assume !(0 == start_simulation_~tmp~3); 32626#L1663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret32, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 32875#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 32122#L891-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 32795#L892-2 stop_simulation_#t~ret32 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret32;havoc stop_simulation_#t~ret32; 32066#L1618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 32067#L1625 stop_simulation_#res := stop_simulation_~__retres2~0; 32400#L1626 start_simulation_#t~ret34 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret34;havoc start_simulation_#t~ret34; 33294#L1676 assume !(0 != start_simulation_~tmp___0~1); 33295#L1644-1 [2021-11-07 07:22:22,186 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:22,187 INFO L85 PathProgramCache]: Analyzing trace with hash 301995457, now seen corresponding path program 1 times [2021-11-07 07:22:22,187 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:22,187 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1147981091] [2021-11-07 07:22:22,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:22,187 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:22,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:22,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:22,224 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:22,224 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1147981091] [2021-11-07 07:22:22,224 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1147981091] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:22,224 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:22,224 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 07:22:22,226 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [481378102] [2021-11-07 07:22:22,226 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:22:22,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:22,227 INFO L85 PathProgramCache]: Analyzing trace with hash 1371629938, now seen corresponding path program 1 times [2021-11-07 07:22:22,227 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:22,227 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [702146849] [2021-11-07 07:22:22,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:22,228 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:22,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:22,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:22,268 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:22,268 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [702146849] [2021-11-07 07:22:22,269 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [702146849] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:22,269 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:22,269 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:22,269 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [822434601] [2021-11-07 07:22:22,270 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:22:22,270 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:22:22,271 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:22:22,271 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:22:22,271 INFO L87 Difference]: Start difference. First operand 1446 states and 2148 transitions. cyclomatic complexity: 703 Second operand has 3 states, 3 states have (on average 44.333333333333336) internal successors, (133), 2 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:22,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:22:22,396 INFO L93 Difference]: Finished difference Result 1446 states and 2130 transitions. [2021-11-07 07:22:22,397 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:22:22,398 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1446 states and 2130 transitions. [2021-11-07 07:22:22,408 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:22,420 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1446 states to 1446 states and 2130 transitions. [2021-11-07 07:22:22,420 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1446 [2021-11-07 07:22:22,422 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1446 [2021-11-07 07:22:22,422 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1446 states and 2130 transitions. [2021-11-07 07:22:22,425 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:22:22,425 INFO L681 BuchiCegarLoop]: Abstraction has 1446 states and 2130 transitions. [2021-11-07 07:22:22,429 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1446 states and 2130 transitions. [2021-11-07 07:22:22,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1446 to 1446. [2021-11-07 07:22:22,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1446 states, 1446 states have (on average 1.4730290456431536) internal successors, (2130), 1445 states have internal predecessors, (2130), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:22,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1446 states to 1446 states and 2130 transitions. [2021-11-07 07:22:22,464 INFO L704 BuchiCegarLoop]: Abstraction has 1446 states and 2130 transitions. [2021-11-07 07:22:22,464 INFO L587 BuchiCegarLoop]: Abstraction has 1446 states and 2130 transitions. [2021-11-07 07:22:22,464 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-07 07:22:22,464 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1446 states and 2130 transitions. [2021-11-07 07:22:22,472 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:22,472 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:22:22,473 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:22:22,476 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:22,476 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:22,476 INFO L791 eck$LassoCheckResult]: Stem: 35895#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 35896#L-1 havoc main_#res;havoc main_~__retres1~13;havoc main_~__retres1~13;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 35904#L1607 havoc start_simulation_#t~ret33, start_simulation_#t~ret34, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 35905#L754 assume 1 == ~m_i~0;~m_st~0 := 0; 36035#L761-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35555#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35468#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35199#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34840#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34841#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34889#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34890#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35791#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35792#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 35827#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 35299#L816-1 assume !(0 == ~M_E~0); 35300#L1090-1 assume !(0 == ~T1_E~0); 36183#L1095-1 assume !(0 == ~T2_E~0); 35964#L1100-1 assume !(0 == ~T3_E~0); 35965#L1105-1 assume !(0 == ~T4_E~0); 35117#L1110-1 assume !(0 == ~T5_E~0); 35118#L1115-1 assume !(0 == ~T6_E~0); 35503#L1120-1 assume !(0 == ~T7_E~0); 35771#L1125-1 assume !(0 == ~T8_E~0); 36236#L1130-1 assume !(0 == ~T9_E~0); 35984#L1135-1 assume !(0 == ~T10_E~0); 35304#L1140-1 assume !(0 == ~T11_E~0); 35305#L1145-1 assume !(0 == ~E_1~0); 35920#L1150-1 assume !(0 == ~E_2~0); 35478#L1155-1 assume !(0 == ~E_3~0); 35479#L1160-1 assume !(0 == ~E_4~0); 35563#L1165-1 assume !(0 == ~E_5~0); 35564#L1170-1 assume !(0 == ~E_6~0); 36155#L1175-1 assume !(0 == ~E_7~0); 35636#L1180-1 assume !(0 == ~E_8~0); 35637#L1185-1 assume !(0 == ~E_9~0); 35301#L1190-1 assume 0 == ~E_10~0;~E_10~0 := 1; 35302#L1195-1 assume !(0 == ~E_11~0); 35650#L1200-1 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35493#L525 assume !(1 == ~m_pc~0); 34928#L525-2 is_master_triggered_~__retres1~0 := 0; 34929#L536 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35654#L537 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 35655#L1350 assume !(0 != activate_threads_~tmp~1); 35288#L1350-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 35289#L544 assume 1 == ~t1_pc~0; 35539#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 35502#L555 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35918#L556 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 35139#L1358 assume !(0 != activate_threads_~tmp___0~0); 35140#L1358-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 35743#L563 assume !(1 == ~t2_pc~0); 35906#L563-2 is_transmit2_triggered_~__retres1~2 := 0; 34949#L574 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 34950#L575 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 35365#L1366 assume !(0 != activate_threads_~tmp___1~0); 35366#L1366-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 35811#L582 assume 1 == ~t3_pc~0; 35082#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 35083#L593 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 36209#L594 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 36164#L1374 assume !(0 != activate_threads_~tmp___2~0); 35022#L1374-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 35023#L601 assume !(1 == ~t4_pc~0); 35935#L601-2 is_transmit4_triggered_~__retres1~4 := 0; 35504#L612 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 35505#L613 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 35929#L1382 assume !(0 != activate_threads_~tmp___3~0); 35930#L1382-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36201#L620 assume 1 == ~t5_pc~0; 34978#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 34979#L631 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 35767#L632 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 35768#L1390 assume !(0 != activate_threads_~tmp___4~0); 36216#L1390-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 36217#L639 assume 1 == ~t6_pc~0; 36187#L640 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 35404#L650 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 35405#L651 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 36167#L1398 assume !(0 != activate_threads_~tmp___5~0); 35512#L1398-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 35513#L658 assume !(1 == ~t7_pc~0); 35695#L658-2 is_transmit7_triggered_~__retres1~7 := 0; 35696#L669 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 35800#L670 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 35801#L1406 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 35295#L1406-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 35296#L677 assume 1 == ~t8_pc~0; 35515#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 35099#L688 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 35100#L689 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 35362#L1414 assume !(0 != activate_threads_~tmp___7~0); 35363#L1414-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 36023#L696 assume !(1 == ~t9_pc~0); 35753#L696-2 is_transmit9_triggered_~__retres1~9 := 0; 35754#L707 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 35838#L708 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 35775#L1422 assume !(0 != activate_threads_~tmp___8~0); 35776#L1422-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 35968#L715 assume 1 == ~t10_pc~0; 35972#L716 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 35856#L726 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 35745#L727 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 35746#L1430 assume !(0 != activate_threads_~tmp___9~0); 35628#L1430-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 35091#L734 assume !(1 == ~t11_pc~0); 35092#L734-2 is_transmit11_triggered_~__retres1~11 := 0; 35565#L745 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 35641#L746 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 34828#L1438 assume !(0 != activate_threads_~tmp___10~0); 34829#L1438-2 assume !(1 == ~M_E~0); 35826#L1213-1 assume !(1 == ~T1_E~0); 36010#L1218-1 assume !(1 == ~T2_E~0); 34865#L1223-1 assume !(1 == ~T3_E~0); 34866#L1228-1 assume !(1 == ~T4_E~0); 35607#L1233-1 assume !(1 == ~T5_E~0); 36218#L1238-1 assume !(1 == ~T6_E~0); 35927#L1243-1 assume !(1 == ~T7_E~0); 35928#L1248-1 assume !(1 == ~T8_E~0); 35970#L1253-1 assume !(1 == ~T9_E~0); 35971#L1258-1 assume !(1 == ~T10_E~0); 35950#L1263-1 assume !(1 == ~T11_E~0); 35951#L1268-1 assume !(1 == ~E_1~0); 35789#L1273-1 assume !(1 == ~E_2~0); 35790#L1278-1 assume !(1 == ~E_3~0); 35402#L1283-1 assume !(1 == ~E_4~0); 35403#L1288-1 assume !(1 == ~E_5~0); 36064#L1293-1 assume !(1 == ~E_6~0); 36027#L1298-1 assume !(1 == ~E_7~0); 35814#L1303-1 assume !(1 == ~E_8~0); 35413#L1308-1 assume !(1 == ~E_9~0); 35310#L1313-1 assume 1 == ~E_10~0;~E_10~0 := 2; 35311#L1318-1 assume !(1 == ~E_11~0); 36194#L1644-1 [2021-11-07 07:22:22,477 INFO L793 eck$LassoCheckResult]: Loop: 36194#L1644-1 assume !false; 35867#L1645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_~tmp~0;havoc eval_~tmp~0; 35842#L1065 assume !false; 35943#L902 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 36214#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 34947#L891 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 36128#L892 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 35418#L906 assume !(0 != eval_~tmp~0); 35420#L1080 start_simulation_~kernel_st~0 := 2; 35941#L754-1 start_simulation_~kernel_st~0 := 3; 35337#L1090-2 assume 0 == ~M_E~0;~M_E~0 := 1; 35338#L1090-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36180#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 36095#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 36096#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35194#L1110-3 assume !(0 == ~T5_E~0); 35195#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35469#L1120-3 assume !(0 == ~T7_E~0); 35470#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 35925#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36176#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 35392#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 34901#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34902#L1150-3 assume !(0 == ~E_2~0); 35024#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35025#L1160-3 assume !(0 == ~E_4~0); 35374#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35375#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35735#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 35291#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35052#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35053#L1190-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36170#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 36171#L1200-3 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35592#L525-36 assume 1 == ~m_pc~0; 35593#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 35151#L536-12 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35152#L537-12 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 35428#L1350-36 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 35429#L1350-38 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 35340#L544-36 assume 1 == ~t1_pc~0; 35341#L545-12 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 35844#L555-12 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35234#L556-12 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 35235#L1358-36 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 36152#L1358-38 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36057#L563-36 assume !(1 == ~t2_pc~0); 35138#L563-38 is_transmit2_triggered_~__retres1~2 := 0; 34899#L574-12 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 34900#L575-12 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 35933#L1366-36 assume !(0 != activate_threads_~tmp___1~0); 35605#L1366-38 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 35606#L582-36 assume 1 == ~t3_pc~0; 35460#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 35461#L593-12 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 35677#L594-12 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 35835#L1374-36 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 35640#L1374-38 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 35586#L601-36 assume 1 == ~t4_pc~0; 35486#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 35488#L612-12 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 36222#L613-12 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 36137#L1382-36 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 36138#L1382-38 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36045#L620-36 assume 1 == ~t5_pc~0; 35529#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 35530#L631-12 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 35909#L632-12 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 35514#L1390-36 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 35160#L1390-38 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 34943#L639-36 assume !(1 == ~t6_pc~0); 34944#L639-38 is_transmit6_triggered_~__retres1~6 := 0; 34983#L650-12 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 34984#L651-12 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 35217#L1398-36 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 35218#L1398-38 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 35774#L658-36 assume 1 == ~t7_pc~0; 35059#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 34955#L669-12 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 36123#L670-12 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 34932#L1406-36 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 34933#L1406-38 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 35892#L677-36 assume !(1 == ~t8_pc~0); 35700#L677-38 is_transmit8_triggered_~__retres1~8 := 0; 35701#L688-12 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 35812#L689-12 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 36197#L1414-36 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 35723#L1414-38 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 35724#L696-36 assume 1 == ~t9_pc~0; 35624#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 35625#L707-12 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 35002#L708-12 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 35003#L1422-36 assume !(0 != activate_threads_~tmp___8~0); 35736#L1422-38 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 35737#L715-36 assume 1 == ~t10_pc~0; 35865#L716-12 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 34830#L726-12 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 34831#L727-12 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 34804#L1430-36 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 34805#L1430-38 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 35203#L734-36 assume 1 == ~t11_pc~0; 35204#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 34909#L745-12 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 35225#L746-12 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 34822#L1438-36 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 34823#L1438-38 assume 1 == ~M_E~0;~M_E~0 := 2; 35795#L1213-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35891#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35254#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35255#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35436#L1233-3 assume !(1 == ~T5_E~0); 35437#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35673#L1243-3 assume !(1 == ~T7_E~0); 35674#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36136#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 36141#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 35236#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35237#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36107#L1273-3 assume !(1 == ~E_2~0); 36125#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36127#L1283-3 assume !(1 == ~E_4~0); 35559#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35560#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35426#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35427#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35866#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35423#L1313-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35424#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35238#L1323-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 35239#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 35179#L891-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 35577#L892-1 start_simulation_#t~ret33 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 36003#L1663 assume !(0 == start_simulation_~tmp~3); 35523#L1663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret32, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 35772#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 35020#L891-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 35694#L892-2 stop_simulation_#t~ret32 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret32;havoc stop_simulation_#t~ret32; 34965#L1618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 34966#L1625 stop_simulation_#res := stop_simulation_~__retres2~0; 35298#L1626 start_simulation_#t~ret34 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret34;havoc start_simulation_#t~ret34; 36193#L1676 assume !(0 != start_simulation_~tmp___0~1); 36194#L1644-1 [2021-11-07 07:22:22,478 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:22,478 INFO L85 PathProgramCache]: Analyzing trace with hash 27409921, now seen corresponding path program 1 times [2021-11-07 07:22:22,479 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:22,481 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1090021133] [2021-11-07 07:22:22,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:22,482 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:22,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:22,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:22,528 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:22,528 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1090021133] [2021-11-07 07:22:22,528 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1090021133] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:22,529 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:22,529 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 07:22:22,529 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1394830550] [2021-11-07 07:22:22,531 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:22:22,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:22,531 INFO L85 PathProgramCache]: Analyzing trace with hash 860275892, now seen corresponding path program 1 times [2021-11-07 07:22:22,532 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:22,532 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1814789883] [2021-11-07 07:22:22,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:22,532 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:22,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:22,577 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:22,577 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:22,578 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1814789883] [2021-11-07 07:22:22,578 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1814789883] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:22,578 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:22,578 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:22,579 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1822934944] [2021-11-07 07:22:22,580 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:22:22,580 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:22:22,580 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:22:22,581 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:22:22,581 INFO L87 Difference]: Start difference. First operand 1446 states and 2130 transitions. cyclomatic complexity: 685 Second operand has 3 states, 3 states have (on average 44.333333333333336) internal successors, (133), 2 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:22,659 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:22:22,659 INFO L93 Difference]: Finished difference Result 1446 states and 2112 transitions. [2021-11-07 07:22:22,659 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:22:22,660 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1446 states and 2112 transitions. [2021-11-07 07:22:22,669 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:22,691 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1446 states to 1446 states and 2112 transitions. [2021-11-07 07:22:22,691 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1446 [2021-11-07 07:22:22,693 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1446 [2021-11-07 07:22:22,693 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1446 states and 2112 transitions. [2021-11-07 07:22:22,697 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:22:22,697 INFO L681 BuchiCegarLoop]: Abstraction has 1446 states and 2112 transitions. [2021-11-07 07:22:22,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1446 states and 2112 transitions. [2021-11-07 07:22:22,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1446 to 1446. [2021-11-07 07:22:22,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1446 states, 1446 states have (on average 1.4605809128630705) internal successors, (2112), 1445 states have internal predecessors, (2112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:22,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1446 states to 1446 states and 2112 transitions. [2021-11-07 07:22:22,735 INFO L704 BuchiCegarLoop]: Abstraction has 1446 states and 2112 transitions. [2021-11-07 07:22:22,735 INFO L587 BuchiCegarLoop]: Abstraction has 1446 states and 2112 transitions. [2021-11-07 07:22:22,735 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-07 07:22:22,736 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1446 states and 2112 transitions. [2021-11-07 07:22:22,743 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1301 [2021-11-07 07:22:22,743 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:22:22,743 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:22:22,746 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:22,747 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:22,747 INFO L791 eck$LassoCheckResult]: Stem: 38792#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 38793#L-1 havoc main_#res;havoc main_~__retres1~13;havoc main_~__retres1~13;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 38803#L1607 havoc start_simulation_#t~ret33, start_simulation_#t~ret34, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 38804#L754 assume 1 == ~m_i~0;~m_st~0 := 0; 38933#L761-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38452#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38366#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38097#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 37739#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 37740#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37788#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37789#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38687#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38688#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 38724#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 38197#L816-1 assume !(0 == ~M_E~0); 38198#L1090-1 assume !(0 == ~T1_E~0); 39082#L1095-1 assume !(0 == ~T2_E~0); 38861#L1100-1 assume !(0 == ~T3_E~0); 38862#L1105-1 assume !(0 == ~T4_E~0); 38017#L1110-1 assume !(0 == ~T5_E~0); 38018#L1115-1 assume !(0 == ~T6_E~0); 38400#L1120-1 assume !(0 == ~T7_E~0); 38667#L1125-1 assume !(0 == ~T8_E~0); 39135#L1130-1 assume !(0 == ~T9_E~0); 38881#L1135-1 assume !(0 == ~T10_E~0); 38202#L1140-1 assume !(0 == ~T11_E~0); 38203#L1145-1 assume !(0 == ~E_1~0); 38817#L1150-1 assume !(0 == ~E_2~0); 38376#L1155-1 assume !(0 == ~E_3~0); 38377#L1160-1 assume !(0 == ~E_4~0); 38460#L1165-1 assume !(0 == ~E_5~0); 38461#L1170-1 assume !(0 == ~E_6~0); 39054#L1175-1 assume !(0 == ~E_7~0); 38533#L1180-1 assume !(0 == ~E_8~0); 38534#L1185-1 assume !(0 == ~E_9~0); 38199#L1190-1 assume !(0 == ~E_10~0); 38200#L1195-1 assume !(0 == ~E_11~0); 38547#L1200-1 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 38397#L525 assume !(1 == ~m_pc~0); 37827#L525-2 is_master_triggered_~__retres1~0 := 0; 37828#L536 is_master_triggered_#res := is_master_triggered_~__retres1~0; 38551#L537 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 38552#L1350 assume !(0 != activate_threads_~tmp~1); 38186#L1350-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 38187#L544 assume 1 == ~t1_pc~0; 38436#L545 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 38399#L555 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 38815#L556 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 38038#L1358 assume !(0 != activate_threads_~tmp___0~0); 38039#L1358-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 38640#L563 assume !(1 == ~t2_pc~0); 38805#L563-2 is_transmit2_triggered_~__retres1~2 := 0; 37848#L574 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 37849#L575 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 38263#L1366 assume !(0 != activate_threads_~tmp___1~0); 38264#L1366-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 38707#L582 assume 1 == ~t3_pc~0; 37983#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 37984#L593 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 39108#L594 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 39063#L1374 assume !(0 != activate_threads_~tmp___2~0); 37921#L1374-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 37922#L601 assume !(1 == ~t4_pc~0); 38832#L601-2 is_transmit4_triggered_~__retres1~4 := 0; 38401#L612 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 38402#L613 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 38826#L1382 assume !(0 != activate_threads_~tmp___3~0); 38827#L1382-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 39100#L620 assume 1 == ~t5_pc~0; 37881#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 37882#L631 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 38663#L632 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 38664#L1390 assume !(0 != activate_threads_~tmp___4~0); 39115#L1390-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 39116#L639 assume 1 == ~t6_pc~0; 39086#L640 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 38302#L650 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 38303#L651 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 39066#L1398 assume !(0 != activate_threads_~tmp___5~0); 38409#L1398-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 38410#L658 assume !(1 == ~t7_pc~0); 38594#L658-2 is_transmit7_triggered_~__retres1~7 := 0; 38595#L669 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 38696#L670 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 38697#L1406 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 38193#L1406-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 38194#L677 assume 1 == ~t8_pc~0; 38414#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 37998#L688 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 37999#L689 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 38260#L1414 assume !(0 != activate_threads_~tmp___7~0); 38261#L1414-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 38921#L696 assume !(1 == ~t9_pc~0); 38651#L696-2 is_transmit9_triggered_~__retres1~9 := 0; 38652#L707 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 38738#L708 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 38671#L1422 assume !(0 != activate_threads_~tmp___8~0); 38672#L1422-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 38865#L715 assume !(1 == ~t10_pc~0); 38870#L715-2 is_transmit10_triggered_~__retres1~10 := 0; 38753#L726 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 38642#L727 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 38643#L1430 assume !(0 != activate_threads_~tmp___9~0); 38525#L1430-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 37992#L734 assume !(1 == ~t11_pc~0); 37993#L734-2 is_transmit11_triggered_~__retres1~11 := 0; 38462#L745 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 38538#L746 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 37729#L1438 assume !(0 != activate_threads_~tmp___10~0); 37730#L1438-2 assume !(1 == ~M_E~0); 38723#L1213-1 assume !(1 == ~T1_E~0); 38907#L1218-1 assume !(1 == ~T2_E~0); 37764#L1223-1 assume !(1 == ~T3_E~0); 37765#L1228-1 assume !(1 == ~T4_E~0); 38504#L1233-1 assume !(1 == ~T5_E~0); 39117#L1238-1 assume !(1 == ~T6_E~0); 38824#L1243-1 assume !(1 == ~T7_E~0); 38825#L1248-1 assume !(1 == ~T8_E~0); 38867#L1253-1 assume !(1 == ~T9_E~0); 38868#L1258-1 assume !(1 == ~T10_E~0); 38847#L1263-1 assume !(1 == ~T11_E~0); 38848#L1268-1 assume !(1 == ~E_1~0); 38685#L1273-1 assume !(1 == ~E_2~0); 38686#L1278-1 assume !(1 == ~E_3~0); 38300#L1283-1 assume !(1 == ~E_4~0); 38301#L1288-1 assume !(1 == ~E_5~0); 38962#L1293-1 assume !(1 == ~E_6~0); 38925#L1298-1 assume !(1 == ~E_7~0); 38710#L1303-1 assume !(1 == ~E_8~0); 38311#L1308-1 assume !(1 == ~E_9~0); 38208#L1313-1 assume !(1 == ~E_10~0); 38209#L1318-1 assume !(1 == ~E_11~0); 39093#L1644-1 [2021-11-07 07:22:22,748 INFO L793 eck$LassoCheckResult]: Loop: 39093#L1644-1 assume !false; 38764#L1645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_~tmp~0;havoc eval_~tmp~0; 38740#L1065 assume !false; 38840#L902 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 39113#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 37846#L891 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 39026#L892 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 38316#L906 assume !(0 != eval_~tmp~0); 38318#L1080 start_simulation_~kernel_st~0 := 2; 38839#L754-1 start_simulation_~kernel_st~0 := 3; 38235#L1090-2 assume 0 == ~M_E~0;~M_E~0 := 1; 38236#L1090-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39079#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38993#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38994#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38092#L1110-3 assume !(0 == ~T5_E~0); 38093#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38367#L1120-3 assume !(0 == ~T7_E~0); 38368#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 38822#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 39075#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 38292#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37802#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37803#L1150-3 assume !(0 == ~E_2~0); 37924#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37925#L1160-3 assume !(0 == ~E_4~0); 38272#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38273#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38632#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 38189#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37954#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 37955#L1190-3 assume !(0 == ~E_10~0); 39069#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39070#L1200-3 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 38489#L525-36 assume 1 == ~m_pc~0; 38490#L526-12 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 38054#L536-12 is_master_triggered_#res := is_master_triggered_~__retres1~0; 38055#L537-12 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 38327#L1350-36 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 38328#L1350-38 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 38238#L544-36 assume !(1 == ~t1_pc~0); 38240#L544-38 is_transmit1_triggered_~__retres1~1 := 0; 38741#L555-12 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 38132#L556-12 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 38133#L1358-36 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 39051#L1358-38 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 38955#L563-36 assume !(1 == ~t2_pc~0); 38037#L563-38 is_transmit2_triggered_~__retres1~2 := 0; 37798#L574-12 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 37799#L575-12 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 38830#L1366-36 assume !(0 != activate_threads_~tmp___1~0); 38502#L1366-38 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 38503#L582-36 assume 1 == ~t3_pc~0; 38358#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 38359#L593-12 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 38574#L594-12 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 38732#L1374-36 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 38537#L1374-38 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 38480#L601-36 assume 1 == ~t4_pc~0; 38384#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 38386#L612-12 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 39121#L613-12 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 39035#L1382-36 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 39036#L1382-38 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 38943#L620-36 assume 1 == ~t5_pc~0; 38424#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 38425#L631-12 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 38806#L632-12 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 38411#L1390-36 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 38058#L1390-38 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 37842#L639-36 assume !(1 == ~t6_pc~0); 37843#L639-38 is_transmit6_triggered_~__retres1~6 := 0; 37879#L650-12 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 37880#L651-12 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 38113#L1398-36 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 38114#L1398-38 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 38670#L658-36 assume 1 == ~t7_pc~0; 37956#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 37854#L669-12 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 39021#L670-12 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 37829#L1406-36 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 37830#L1406-38 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 38789#L677-36 assume !(1 == ~t8_pc~0); 38597#L677-38 is_transmit8_triggered_~__retres1~8 := 0; 38598#L688-12 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 38708#L689-12 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 39096#L1414-36 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 38620#L1414-38 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 38621#L696-36 assume 1 == ~t9_pc~0; 38521#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 38522#L707-12 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 37901#L708-12 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 37902#L1422-36 assume !(0 != activate_threads_~tmp___8~0); 38633#L1422-38 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 38634#L715-36 assume !(1 == ~t10_pc~0); 38604#L715-38 is_transmit10_triggered_~__retres1~10 := 0; 37727#L726-12 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 37728#L727-12 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 37703#L1430-36 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 37704#L1430-38 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 38101#L734-36 assume 1 == ~t11_pc~0; 38102#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 37808#L745-12 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 38123#L746-12 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 37721#L1438-36 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 37722#L1438-38 assume 1 == ~M_E~0;~M_E~0 := 2; 38691#L1213-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38788#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38152#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38153#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38334#L1233-3 assume !(1 == ~T5_E~0); 38335#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38570#L1243-3 assume !(1 == ~T7_E~0); 38571#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 39033#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 39039#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38134#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 38135#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 39005#L1273-3 assume !(1 == ~E_2~0); 39023#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 39025#L1283-3 assume !(1 == ~E_4~0); 38456#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38457#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38324#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38325#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38763#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 38321#L1313-3 assume !(1 == ~E_10~0); 38322#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 38136#L1323-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 38137#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 38077#L891-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 38474#L892-1 start_simulation_#t~ret33 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 38900#L1663 assume !(0 == start_simulation_~tmp~3); 38420#L1663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret32, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 38668#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 37919#L891-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 38589#L892-2 stop_simulation_#t~ret32 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret32;havoc stop_simulation_#t~ret32; 37864#L1618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 37865#L1625 stop_simulation_#res := stop_simulation_~__retres2~0; 38196#L1626 start_simulation_#t~ret34 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret34;havoc start_simulation_#t~ret34; 39092#L1676 assume !(0 != start_simulation_~tmp___0~1); 39093#L1644-1 [2021-11-07 07:22:22,749 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:22,749 INFO L85 PathProgramCache]: Analyzing trace with hash -169184, now seen corresponding path program 1 times [2021-11-07 07:22:22,749 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:22,750 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [97030388] [2021-11-07 07:22:22,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:22,750 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:22,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:22,803 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:22,803 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:22,804 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [97030388] [2021-11-07 07:22:22,804 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [97030388] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:22,804 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:22,804 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:22,804 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [929538992] [2021-11-07 07:22:22,805 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:22:22,805 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:22,805 INFO L85 PathProgramCache]: Analyzing trace with hash -1179405130, now seen corresponding path program 1 times [2021-11-07 07:22:22,806 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:22,806 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [817207270] [2021-11-07 07:22:22,806 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:22,806 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:22,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:22,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:22,849 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:22,849 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [817207270] [2021-11-07 07:22:22,849 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [817207270] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:22,849 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:22,849 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:22,849 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [943043622] [2021-11-07 07:22:22,850 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:22:22,850 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:22:22,851 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-07 07:22:22,851 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-07 07:22:22,851 INFO L87 Difference]: Start difference. First operand 1446 states and 2112 transitions. cyclomatic complexity: 667 Second operand has 4 states, 4 states have (on average 33.25) internal successors, (133), 3 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:23,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:22:23,203 INFO L93 Difference]: Finished difference Result 3915 states and 5642 transitions. [2021-11-07 07:22:23,203 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 07:22:23,203 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3915 states and 5642 transitions. [2021-11-07 07:22:23,226 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3680 [2021-11-07 07:22:23,282 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3915 states to 3915 states and 5642 transitions. [2021-11-07 07:22:23,282 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3915 [2021-11-07 07:22:23,286 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3915 [2021-11-07 07:22:23,286 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3915 states and 5642 transitions. [2021-11-07 07:22:23,292 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:22:23,293 INFO L681 BuchiCegarLoop]: Abstraction has 3915 states and 5642 transitions. [2021-11-07 07:22:23,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3915 states and 5642 transitions. [2021-11-07 07:22:23,364 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3915 to 3751. [2021-11-07 07:22:23,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3751 states, 3751 states have (on average 1.4441482271394295) internal successors, (5417), 3750 states have internal predecessors, (5417), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:23,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3751 states to 3751 states and 5417 transitions. [2021-11-07 07:22:23,403 INFO L704 BuchiCegarLoop]: Abstraction has 3751 states and 5417 transitions. [2021-11-07 07:22:23,403 INFO L587 BuchiCegarLoop]: Abstraction has 3751 states and 5417 transitions. [2021-11-07 07:22:23,404 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-07 07:22:23,404 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3751 states and 5417 transitions. [2021-11-07 07:22:23,422 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3603 [2021-11-07 07:22:23,423 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:22:23,423 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:22:23,426 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:23,426 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:23,428 INFO L791 eck$LassoCheckResult]: Stem: 44176#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 44177#L-1 havoc main_#res;havoc main_~__retres1~13;havoc main_~__retres1~13;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 44187#L1607 havoc start_simulation_#t~ret33, start_simulation_#t~ret34, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 44188#L754 assume 1 == ~m_i~0;~m_st~0 := 0; 44328#L761-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 43827#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 43738#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 43468#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 43110#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 43111#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 43159#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 43160#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 44067#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 44068#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 44104#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 43571#L816-1 assume !(0 == ~M_E~0); 43572#L1090-1 assume !(0 == ~T1_E~0); 44494#L1095-1 assume !(0 == ~T2_E~0); 44249#L1100-1 assume !(0 == ~T3_E~0); 44250#L1105-1 assume !(0 == ~T4_E~0); 43388#L1110-1 assume !(0 == ~T5_E~0); 43389#L1115-1 assume !(0 == ~T6_E~0); 43777#L1120-1 assume !(0 == ~T7_E~0); 44047#L1125-1 assume !(0 == ~T8_E~0); 44566#L1130-1 assume !(0 == ~T9_E~0); 44272#L1135-1 assume !(0 == ~T10_E~0); 43576#L1140-1 assume !(0 == ~T11_E~0); 43577#L1145-1 assume !(0 == ~E_1~0); 44202#L1150-1 assume !(0 == ~E_2~0); 43749#L1155-1 assume !(0 == ~E_3~0); 43750#L1160-1 assume !(0 == ~E_4~0); 43835#L1165-1 assume !(0 == ~E_5~0); 43836#L1170-1 assume !(0 == ~E_6~0); 44457#L1175-1 assume !(0 == ~E_7~0); 43908#L1180-1 assume !(0 == ~E_8~0); 43909#L1185-1 assume !(0 == ~E_9~0); 43573#L1190-1 assume !(0 == ~E_10~0); 43574#L1195-1 assume !(0 == ~E_11~0); 43922#L1200-1 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 43772#L525 assume !(1 == ~m_pc~0); 43198#L525-2 is_master_triggered_~__retres1~0 := 0; 43199#L536 is_master_triggered_#res := is_master_triggered_~__retres1~0; 43926#L537 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 43927#L1350 assume !(0 != activate_threads_~tmp~1); 43561#L1350-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 43562#L544 assume !(1 == ~t1_pc~0); 43773#L544-2 is_transmit1_triggered_~__retres1~1 := 0; 43774#L555 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 44200#L556 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 43408#L1358 assume !(0 != activate_threads_~tmp___0~0); 43409#L1358-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 44018#L563 assume !(1 == ~t2_pc~0); 44189#L563-2 is_transmit2_triggered_~__retres1~2 := 0; 43219#L574 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43220#L575 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 43637#L1366 assume !(0 != activate_threads_~tmp___1~0); 43638#L1366-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 44087#L582 assume 1 == ~t3_pc~0; 43354#L583 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 43355#L593 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 44526#L594 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 44468#L1374 assume !(0 != activate_threads_~tmp___2~0); 43292#L1374-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 43293#L601 assume !(1 == ~t4_pc~0); 44218#L601-2 is_transmit4_triggered_~__retres1~4 := 0; 43778#L612 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 43779#L613 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 44212#L1382 assume !(0 != activate_threads_~tmp___3~0); 44213#L1382-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 44518#L620 assume 1 == ~t5_pc~0; 43250#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 43251#L631 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 44043#L632 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 44044#L1390 assume !(0 != activate_threads_~tmp___4~0); 44539#L1390-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 44540#L639 assume 1 == ~t6_pc~0; 44498#L640 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 43674#L650 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 43675#L651 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 44470#L1398 assume !(0 != activate_threads_~tmp___5~0); 43783#L1398-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 43784#L658 assume !(1 == ~t7_pc~0); 43969#L658-2 is_transmit7_triggered_~__retres1~7 := 0; 43970#L669 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 44076#L670 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 44077#L1406 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 43567#L1406-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 43568#L677 assume 1 == ~t8_pc~0; 43789#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 43372#L688 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 43373#L689 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 43634#L1414 assume !(0 != activate_threads_~tmp___7~0); 43635#L1414-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 44313#L696 assume !(1 == ~t9_pc~0); 44030#L696-2 is_transmit9_triggered_~__retres1~9 := 0; 44031#L707 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 44115#L708 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 44051#L1422 assume !(0 != activate_threads_~tmp___8~0); 44052#L1422-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 44253#L715 assume !(1 == ~t10_pc~0); 44261#L715-2 is_transmit10_triggered_~__retres1~10 := 0; 44133#L726 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 44020#L727 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 44021#L1430 assume !(0 != activate_threads_~tmp___9~0); 43899#L1430-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 43363#L734 assume !(1 == ~t11_pc~0); 43364#L734-2 is_transmit11_triggered_~__retres1~11 := 0; 43839#L745 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 43913#L746 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 43100#L1438 assume !(0 != activate_threads_~tmp___10~0); 43101#L1438-2 assume !(1 == ~M_E~0); 44103#L1213-1 assume !(1 == ~T1_E~0); 44299#L1218-1 assume !(1 == ~T2_E~0); 43135#L1223-1 assume !(1 == ~T3_E~0); 43136#L1228-1 assume !(1 == ~T4_E~0); 43878#L1233-1 assume !(1 == ~T5_E~0); 44541#L1238-1 assume !(1 == ~T6_E~0); 44210#L1243-1 assume !(1 == ~T7_E~0); 44211#L1248-1 assume !(1 == ~T8_E~0); 44258#L1253-1 assume !(1 == ~T9_E~0); 44259#L1258-1 assume !(1 == ~T10_E~0); 44235#L1263-1 assume !(1 == ~T11_E~0); 44236#L1268-1 assume !(1 == ~E_1~0); 44065#L1273-1 assume !(1 == ~E_2~0); 44066#L1278-1 assume !(1 == ~E_3~0); 43672#L1283-1 assume !(1 == ~E_4~0); 43673#L1288-1 assume !(1 == ~E_5~0); 44359#L1293-1 assume !(1 == ~E_6~0); 44317#L1298-1 assume !(1 == ~E_7~0); 44090#L1303-1 assume !(1 == ~E_8~0); 43683#L1308-1 assume !(1 == ~E_9~0); 43584#L1313-1 assume !(1 == ~E_10~0); 43585#L1318-1 assume !(1 == ~E_11~0); 44570#L1644-1 [2021-11-07 07:22:23,428 INFO L793 eck$LassoCheckResult]: Loop: 44570#L1644-1 assume !false; 46139#L1645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_~tmp~0;havoc eval_~tmp~0; 44226#L1065 assume !false; 44227#L902 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 44537#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 43217#L891 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 44427#L892 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 43688#L906 assume !(0 != eval_~tmp~0); 43690#L1080 start_simulation_~kernel_st~0 := 2; 44225#L754-1 start_simulation_~kernel_st~0 := 3; 43609#L1090-2 assume 0 == ~M_E~0;~M_E~0 := 1; 43610#L1090-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44491#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44394#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 44395#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43463#L1110-3 assume !(0 == ~T5_E~0); 43464#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 43739#L1120-3 assume !(0 == ~T7_E~0); 43740#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 44207#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 44487#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 43665#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43173#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43174#L1150-3 assume !(0 == ~E_2~0); 43294#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 43295#L1160-3 assume !(0 == ~E_4~0); 43646#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 43647#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44010#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 43563#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 43323#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 43324#L1190-3 assume !(0 == ~E_10~0); 44473#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 44474#L1200-3 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 43862#L525-36 assume !(1 == ~m_pc~0); 43863#L525-38 is_master_triggered_~__retres1~0 := 0; 43422#L536-12 is_master_triggered_#res := is_master_triggered_~__retres1~0; 43423#L537-12 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 43699#L1350-36 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 43700#L1350-38 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 43611#L544-36 assume !(1 == ~t1_pc~0); 43612#L544-38 is_transmit1_triggered_~__retres1~1 := 0; 44121#L555-12 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 43503#L556-12 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 43504#L1358-36 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 44454#L1358-38 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 44350#L563-36 assume !(1 == ~t2_pc~0); 43407#L563-38 is_transmit2_triggered_~__retres1~2 := 0; 43166#L574-12 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43167#L575-12 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 44216#L1366-36 assume !(0 != activate_threads_~tmp___1~0); 43876#L1366-38 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 43877#L582-36 assume 1 == ~t3_pc~0; 43730#L583-12 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 43731#L593-12 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 43949#L594-12 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 44112#L1374-36 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 43912#L1374-38 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 43855#L601-36 assume !(1 == ~t4_pc~0); 43760#L601-38 is_transmit4_triggered_~__retres1~4 := 0; 43761#L612-12 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 44545#L613-12 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 44436#L1382-36 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 44437#L1382-38 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 44336#L620-36 assume 1 == ~t5_pc~0; 43799#L621-12 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 43800#L631-12 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 44190#L632-12 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 43786#L1390-36 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 43428#L1390-38 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 43210#L639-36 assume !(1 == ~t6_pc~0); 43211#L639-38 is_transmit6_triggered_~__retres1~6 := 0; 43248#L650-12 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 43249#L651-12 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 43482#L1398-36 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 43483#L1398-38 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 44050#L658-36 assume !(1 == ~t7_pc~0); 43224#L658-38 is_transmit7_triggered_~__retres1~7 := 0; 43225#L669-12 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 44422#L670-12 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 43200#L1406-36 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 43201#L1406-38 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 44173#L677-36 assume !(1 == ~t8_pc~0); 43972#L677-38 is_transmit8_triggered_~__retres1~8 := 0; 43973#L688-12 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 44088#L689-12 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 44511#L1414-36 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 43997#L1414-38 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 43998#L696-36 assume 1 == ~t9_pc~0; 43895#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 43896#L707-12 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 43269#L708-12 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 43270#L1422-36 assume !(0 != activate_threads_~tmp___8~0); 44011#L1422-38 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 44012#L715-36 assume !(1 == ~t10_pc~0); 43980#L715-38 is_transmit10_triggered_~__retres1~10 := 0; 43098#L726-12 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 43099#L727-12 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 43074#L1430-36 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 43075#L1430-38 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 43472#L734-36 assume 1 == ~t11_pc~0; 43473#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 43179#L745-12 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 43494#L746-12 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 43092#L1438-36 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 43093#L1438-38 assume 1 == ~M_E~0;~M_E~0 := 2; 44071#L1213-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44172#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 43524#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 43525#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 43706#L1233-3 assume !(1 == ~T5_E~0); 43707#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 43945#L1243-3 assume !(1 == ~T7_E~0); 43946#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 44435#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 44441#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43505#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 43506#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44406#L1273-3 assume !(1 == ~E_2~0); 44424#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44426#L1283-3 assume !(1 == ~E_4~0); 43831#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 43832#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 43696#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 43697#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 44142#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 43693#L1313-3 assume !(1 == ~E_10~0); 43694#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 43507#L1323-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 43508#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 43447#L891-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 43849#L892-1 start_simulation_#t~ret33 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 44292#L1663 assume !(0 == start_simulation_~tmp~3); 44581#L1663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret32, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 46156#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 46151#L891-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 46150#L892-2 stop_simulation_#t~ret32 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret32;havoc stop_simulation_#t~ret32; 46149#L1618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 46148#L1625 stop_simulation_#res := stop_simulation_~__retres2~0; 46147#L1626 start_simulation_#t~ret34 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret34;havoc start_simulation_#t~ret34; 46146#L1676 assume !(0 != start_simulation_~tmp___0~1); 44570#L1644-1 [2021-11-07 07:22:23,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:23,430 INFO L85 PathProgramCache]: Analyzing trace with hash 1202025151, now seen corresponding path program 1 times [2021-11-07 07:22:23,431 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:23,431 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192820693] [2021-11-07 07:22:23,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:23,431 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:23,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:23,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:23,481 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:23,481 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1192820693] [2021-11-07 07:22:23,482 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1192820693] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:23,482 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:23,482 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:23,482 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1035553824] [2021-11-07 07:22:23,483 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:22:23,483 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:23,483 INFO L85 PathProgramCache]: Analyzing trace with hash -830848263, now seen corresponding path program 1 times [2021-11-07 07:22:23,483 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:23,484 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1014876399] [2021-11-07 07:22:23,484 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:23,484 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:23,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:23,528 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:23,528 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:23,529 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1014876399] [2021-11-07 07:22:23,529 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1014876399] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:23,529 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:23,529 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-07 07:22:23,529 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1595149405] [2021-11-07 07:22:23,530 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:22:23,530 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:22:23,531 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-07 07:22:23,531 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-07 07:22:23,532 INFO L87 Difference]: Start difference. First operand 3751 states and 5417 transitions. cyclomatic complexity: 1668 Second operand has 4 states, 4 states have (on average 33.25) internal successors, (133), 3 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:23,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:22:23,935 INFO L93 Difference]: Finished difference Result 10556 states and 15102 transitions. [2021-11-07 07:22:23,935 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 07:22:23,935 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10556 states and 15102 transitions. [2021-11-07 07:22:24,111 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10212 [2021-11-07 07:22:24,167 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10556 states to 10556 states and 15102 transitions. [2021-11-07 07:22:24,167 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10556 [2021-11-07 07:22:24,180 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10556 [2021-11-07 07:22:24,181 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10556 states and 15102 transitions. [2021-11-07 07:22:24,200 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:22:24,201 INFO L681 BuchiCegarLoop]: Abstraction has 10556 states and 15102 transitions. [2021-11-07 07:22:24,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10556 states and 15102 transitions. [2021-11-07 07:22:24,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10556 to 10180. [2021-11-07 07:22:24,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10180 states, 10180 states have (on average 1.4333005893909627) internal successors, (14591), 10179 states have internal predecessors, (14591), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:24,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10180 states to 10180 states and 14591 transitions. [2021-11-07 07:22:24,496 INFO L704 BuchiCegarLoop]: Abstraction has 10180 states and 14591 transitions. [2021-11-07 07:22:24,496 INFO L587 BuchiCegarLoop]: Abstraction has 10180 states and 14591 transitions. [2021-11-07 07:22:24,497 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-07 07:22:24,497 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10180 states and 14591 transitions. [2021-11-07 07:22:24,553 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10023 [2021-11-07 07:22:24,553 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:22:24,553 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:22:24,557 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:24,557 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:24,557 INFO L791 eck$LassoCheckResult]: Stem: 58545#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 58546#L-1 havoc main_#res;havoc main_~__retres1~13;havoc main_~__retres1~13;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 58558#L1607 havoc start_simulation_#t~ret33, start_simulation_#t~ret34, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 58559#L754 assume 1 == ~m_i~0;~m_st~0 := 0; 58724#L761-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 58157#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 58066#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 57784#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 57429#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 57430#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 57478#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 57479#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 58424#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 58425#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 58472#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 57892#L816-1 assume !(0 == ~M_E~0); 57893#L1090-1 assume !(0 == ~T1_E~0); 58948#L1095-1 assume !(0 == ~T2_E~0); 58623#L1100-1 assume !(0 == ~T3_E~0); 58624#L1105-1 assume !(0 == ~T4_E~0); 57704#L1110-1 assume !(0 == ~T5_E~0); 57705#L1115-1 assume !(0 == ~T6_E~0); 58103#L1120-1 assume !(0 == ~T7_E~0); 58396#L1125-1 assume !(0 == ~T8_E~0); 59073#L1130-1 assume !(0 == ~T9_E~0); 58649#L1135-1 assume !(0 == ~T10_E~0); 57899#L1140-1 assume !(0 == ~T11_E~0); 57900#L1145-1 assume !(0 == ~E_1~0); 58574#L1150-1 assume !(0 == ~E_2~0); 58076#L1155-1 assume !(0 == ~E_3~0); 58077#L1160-1 assume !(0 == ~E_4~0); 58166#L1165-1 assume !(0 == ~E_5~0); 58167#L1170-1 assume !(0 == ~E_6~0); 58898#L1175-1 assume !(0 == ~E_7~0); 58246#L1180-1 assume !(0 == ~E_8~0); 58247#L1185-1 assume !(0 == ~E_9~0); 57894#L1190-1 assume !(0 == ~E_10~0); 57895#L1195-1 assume !(0 == ~E_11~0); 58260#L1200-1 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 58098#L525 assume !(1 == ~m_pc~0); 57516#L525-2 is_master_triggered_~__retres1~0 := 0; 57517#L536 is_master_triggered_#res := is_master_triggered_~__retres1~0; 58264#L537 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 58265#L1350 assume !(0 != activate_threads_~tmp~1); 57881#L1350-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 57882#L544 assume !(1 == ~t1_pc~0); 58099#L544-2 is_transmit1_triggered_~__retres1~1 := 0; 58100#L555 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 58571#L556 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 57724#L1358 assume !(0 != activate_threads_~tmp___0~0); 57725#L1358-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 58366#L563 assume !(1 == ~t2_pc~0); 58560#L563-2 is_transmit2_triggered_~__retres1~2 := 0; 57537#L574 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 57538#L575 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 57960#L1366 assume !(0 != activate_threads_~tmp___1~0); 57961#L1366-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 58445#L582 assume !(1 == ~t3_pc~0); 58572#L582-2 is_transmit3_triggered_~__retres1~3 := 0; 58997#L593 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 58998#L594 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 58911#L1374 assume !(0 != activate_threads_~tmp___2~0); 57610#L1374-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 57611#L601 assume !(1 == ~t4_pc~0); 58590#L601-2 is_transmit4_triggered_~__retres1~4 := 0; 58104#L612 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 58105#L613 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 58584#L1382 assume !(0 != activate_threads_~tmp___3~0); 58585#L1382-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 58987#L620 assume 1 == ~t5_pc~0; 57570#L621 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 57571#L631 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 58392#L632 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 58393#L1390 assume !(0 != activate_threads_~tmp___4~0); 59025#L1390-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 59026#L639 assume 1 == ~t6_pc~0; 58955#L640 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 57998#L650 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 57999#L651 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 58915#L1398 assume !(0 != activate_threads_~tmp___5~0); 58109#L1398-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 58110#L658 assume !(1 == ~t7_pc~0); 58310#L658-2 is_transmit7_triggered_~__retres1~7 := 0; 58311#L669 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 58431#L670 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 58432#L1406 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 57887#L1406-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 57888#L677 assume 1 == ~t8_pc~0; 58115#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 57689#L688 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 57690#L689 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 57957#L1414 assume !(0 != activate_threads_~tmp___7~0); 57958#L1414-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 58705#L696 assume !(1 == ~t9_pc~0); 58380#L696-2 is_transmit9_triggered_~__retres1~9 := 0; 58381#L707 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 58477#L708 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 58404#L1422 assume !(0 != activate_threads_~tmp___8~0); 58405#L1422-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 58627#L715 assume !(1 == ~t10_pc~0); 58635#L715-2 is_transmit10_triggered_~__retres1~10 := 0; 58498#L726 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 58368#L727 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 58369#L1430 assume !(0 != activate_threads_~tmp___9~0); 58237#L1430-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 57678#L734 assume !(1 == ~t11_pc~0); 57679#L734-2 is_transmit11_triggered_~__retres1~11 := 0; 58170#L745 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 58251#L746 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 57419#L1438 assume !(0 != activate_threads_~tmp___10~0); 57420#L1438-2 assume !(1 == ~M_E~0); 58466#L1213-1 assume !(1 == ~T1_E~0); 58686#L1218-1 assume !(1 == ~T2_E~0); 57454#L1223-1 assume !(1 == ~T3_E~0); 57455#L1228-1 assume !(1 == ~T4_E~0); 58214#L1233-1 assume !(1 == ~T5_E~0); 59027#L1238-1 assume !(1 == ~T6_E~0); 58582#L1243-1 assume !(1 == ~T7_E~0); 58583#L1248-1 assume !(1 == ~T8_E~0); 58632#L1253-1 assume !(1 == ~T9_E~0); 58633#L1258-1 assume !(1 == ~T10_E~0); 58609#L1263-1 assume !(1 == ~T11_E~0); 58610#L1268-1 assume !(1 == ~E_1~0); 58418#L1273-1 assume !(1 == ~E_2~0); 58419#L1278-1 assume !(1 == ~E_3~0); 57996#L1283-1 assume !(1 == ~E_4~0); 57997#L1288-1 assume !(1 == ~E_5~0); 58766#L1293-1 assume !(1 == ~E_6~0); 58714#L1298-1 assume !(1 == ~E_7~0); 58448#L1303-1 assume !(1 == ~E_8~0); 58007#L1308-1 assume !(1 == ~E_9~0); 57905#L1313-1 assume !(1 == ~E_10~0); 57906#L1318-1 assume !(1 == ~E_11~0); 59084#L1644-1 [2021-11-07 07:22:24,558 INFO L793 eck$LassoCheckResult]: Loop: 59084#L1644-1 assume !false; 58511#L1645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_~tmp~0;havoc eval_~tmp~0; 58484#L1065 assume !false; 59022#L902 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 59023#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 66650#L891 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 58916#L892 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 58012#L906 assume !(0 != eval_~tmp~0); 58014#L1080 start_simulation_~kernel_st~0 := 2; 67417#L754-1 start_simulation_~kernel_st~0 := 3; 67416#L1090-2 assume 0 == ~M_E~0;~M_E~0 := 1; 67415#L1090-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 67414#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 67413#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 67412#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 67411#L1110-3 assume !(0 == ~T5_E~0); 67410#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 67409#L1120-3 assume !(0 == ~T7_E~0); 67408#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 67407#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 67406#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 67405#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 67404#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 67403#L1150-3 assume !(0 == ~E_2~0); 67402#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 67401#L1160-3 assume !(0 == ~E_4~0); 67400#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 67399#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 67398#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 67397#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 67396#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 67395#L1190-3 assume !(0 == ~E_10~0); 67394#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 67393#L1200-3 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 67392#L525-36 assume !(1 == ~m_pc~0); 67391#L525-38 is_master_triggered_~__retres1~0 := 0; 67390#L536-12 is_master_triggered_#res := is_master_triggered_~__retres1~0; 67389#L537-12 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 67388#L1350-36 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 67387#L1350-38 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 67386#L544-36 assume !(1 == ~t1_pc~0); 67385#L544-38 is_transmit1_triggered_~__retres1~1 := 0; 67384#L555-12 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 67383#L556-12 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 67382#L1358-36 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 67381#L1358-38 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 67380#L563-36 assume !(1 == ~t2_pc~0); 67378#L563-38 is_transmit2_triggered_~__retres1~2 := 0; 67377#L574-12 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 67376#L575-12 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 67375#L1366-36 assume !(0 != activate_threads_~tmp___1~0); 67374#L1366-38 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 67373#L582-36 assume !(1 == ~t3_pc~0); 67372#L582-38 is_transmit3_triggered_~__retres1~3 := 0; 67371#L593-12 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 67370#L594-12 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 67369#L1374-36 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 67368#L1374-38 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 67367#L601-36 assume !(1 == ~t4_pc~0); 67365#L601-38 is_transmit4_triggered_~__retres1~4 := 0; 67364#L612-12 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 67363#L613-12 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 67362#L1382-36 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 67361#L1382-38 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 67360#L620-36 assume !(1 == ~t5_pc~0); 67359#L620-38 is_transmit5_triggered_~__retres1~5 := 0; 67357#L631-12 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 67356#L632-12 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 67355#L1390-36 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 67354#L1390-38 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 67353#L639-36 assume !(1 == ~t6_pc~0); 67351#L639-38 is_transmit6_triggered_~__retres1~6 := 0; 67350#L650-12 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 67349#L651-12 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 67348#L1398-36 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 67347#L1398-38 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 67346#L658-36 assume !(1 == ~t7_pc~0); 67345#L658-38 is_transmit7_triggered_~__retres1~7 := 0; 67343#L669-12 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 67342#L670-12 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 67341#L1406-36 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 67340#L1406-38 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 67339#L677-36 assume !(1 == ~t8_pc~0); 67337#L677-38 is_transmit8_triggered_~__retres1~8 := 0; 67336#L688-12 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 67335#L689-12 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 67334#L1414-36 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 67333#L1414-38 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 67332#L696-36 assume !(1 == ~t9_pc~0); 67331#L696-38 is_transmit9_triggered_~__retres1~9 := 0; 67329#L707-12 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 67328#L708-12 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 67327#L1422-36 assume !(0 != activate_threads_~tmp___8~0); 67326#L1422-38 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 67325#L715-36 assume !(1 == ~t10_pc~0); 67323#L715-38 is_transmit10_triggered_~__retres1~10 := 0; 67322#L726-12 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 67321#L727-12 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 67320#L1430-36 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 67319#L1430-38 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 67318#L734-36 assume !(1 == ~t11_pc~0); 67317#L734-38 is_transmit11_triggered_~__retres1~11 := 0; 67315#L745-12 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 67314#L746-12 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 67313#L1438-36 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 67312#L1438-38 assume 1 == ~M_E~0;~M_E~0 := 2; 67311#L1213-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 67310#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 67309#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 67308#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 67307#L1233-3 assume !(1 == ~T5_E~0); 67306#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 67305#L1243-3 assume !(1 == ~T7_E~0); 67304#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 67303#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 67302#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 67301#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 67300#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 67299#L1273-3 assume !(1 == ~E_2~0); 67298#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 67297#L1283-3 assume !(1 == ~E_4~0); 67296#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 67295#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 67294#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 67293#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 67292#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 67291#L1313-3 assume !(1 == ~E_10~0); 67290#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 67289#L1323-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 67277#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 67276#L891-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 67275#L892-1 start_simulation_#t~ret33 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 59115#L1663 assume !(0 == start_simulation_~tmp~3); 58123#L1663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret32, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 58708#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 66749#L891-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 66748#L892-2 stop_simulation_#t~ret32 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret32;havoc stop_simulation_#t~ret32; 66747#L1618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 66746#L1625 stop_simulation_#res := stop_simulation_~__retres2~0; 66745#L1626 start_simulation_#t~ret34 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret34;havoc start_simulation_#t~ret34; 66744#L1676 assume !(0 != start_simulation_~tmp___0~1); 59084#L1644-1 [2021-11-07 07:22:24,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:24,559 INFO L85 PathProgramCache]: Analyzing trace with hash 1281143006, now seen corresponding path program 1 times [2021-11-07 07:22:24,559 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:24,559 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2114444884] [2021-11-07 07:22:24,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:24,560 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:24,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:24,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:24,613 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:24,613 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2114444884] [2021-11-07 07:22:24,614 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2114444884] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:24,614 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:24,614 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:24,614 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1509277923] [2021-11-07 07:22:24,615 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:22:24,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:24,615 INFO L85 PathProgramCache]: Analyzing trace with hash -523829251, now seen corresponding path program 1 times [2021-11-07 07:22:24,615 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:24,616 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1434179266] [2021-11-07 07:22:24,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:24,616 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:24,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:24,668 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:24,669 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:24,669 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1434179266] [2021-11-07 07:22:24,669 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1434179266] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:24,669 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:24,669 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-07 07:22:24,669 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1890548762] [2021-11-07 07:22:24,670 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:22:24,670 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:22:24,671 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-07 07:22:24,671 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-07 07:22:24,671 INFO L87 Difference]: Start difference. First operand 10180 states and 14591 transitions. cyclomatic complexity: 4415 Second operand has 4 states, 4 states have (on average 33.25) internal successors, (133), 3 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:25,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:22:25,117 INFO L93 Difference]: Finished difference Result 28956 states and 41191 transitions. [2021-11-07 07:22:25,118 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 07:22:25,118 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28956 states and 41191 transitions. [2021-11-07 07:22:25,425 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 28386 [2021-11-07 07:22:25,558 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28956 states to 28956 states and 41191 transitions. [2021-11-07 07:22:25,558 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28956 [2021-11-07 07:22:25,595 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28956 [2021-11-07 07:22:25,596 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28956 states and 41191 transitions. [2021-11-07 07:22:25,627 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:22:25,628 INFO L681 BuchiCegarLoop]: Abstraction has 28956 states and 41191 transitions. [2021-11-07 07:22:25,652 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28956 states and 41191 transitions. [2021-11-07 07:22:26,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28956 to 28121. [2021-11-07 07:22:26,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28121 states, 28121 states have (on average 1.4248070836741225) internal successors, (40067), 28120 states have internal predecessors, (40067), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:26,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28121 states to 28121 states and 40067 transitions. [2021-11-07 07:22:26,448 INFO L704 BuchiCegarLoop]: Abstraction has 28121 states and 40067 transitions. [2021-11-07 07:22:26,448 INFO L587 BuchiCegarLoop]: Abstraction has 28121 states and 40067 transitions. [2021-11-07 07:22:26,448 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-07 07:22:26,448 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28121 states and 40067 transitions. [2021-11-07 07:22:26,821 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 27945 [2021-11-07 07:22:26,835 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:22:26,836 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:22:26,839 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:26,840 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:26,840 INFO L791 eck$LassoCheckResult]: Stem: 97673#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 97674#L-1 havoc main_#res;havoc main_~__retres1~13;havoc main_~__retres1~13;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 97684#L1607 havoc start_simulation_#t~ret33, start_simulation_#t~ret34, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 97685#L754 assume 1 == ~m_i~0;~m_st~0 := 0; 97842#L761-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 97298#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 97208#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96932#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 96577#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 96578#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 96626#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 96627#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 97557#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 97558#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 97597#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 97038#L816-1 assume !(0 == ~M_E~0); 97039#L1090-1 assume !(0 == ~T1_E~0); 98052#L1095-1 assume !(0 == ~T2_E~0); 97753#L1100-1 assume !(0 == ~T3_E~0); 97754#L1105-1 assume !(0 == ~T4_E~0); 96848#L1110-1 assume !(0 == ~T5_E~0); 96849#L1115-1 assume !(0 == ~T6_E~0); 97244#L1120-1 assume !(0 == ~T7_E~0); 97532#L1125-1 assume !(0 == ~T8_E~0); 98169#L1130-1 assume !(0 == ~T9_E~0); 97776#L1135-1 assume !(0 == ~T10_E~0); 97043#L1140-1 assume !(0 == ~T11_E~0); 97044#L1145-1 assume !(0 == ~E_1~0); 97704#L1150-1 assume !(0 == ~E_2~0); 97219#L1155-1 assume !(0 == ~E_3~0); 97220#L1160-1 assume !(0 == ~E_4~0); 97306#L1165-1 assume !(0 == ~E_5~0); 97307#L1170-1 assume !(0 == ~E_6~0); 98004#L1175-1 assume !(0 == ~E_7~0); 97385#L1180-1 assume !(0 == ~E_8~0); 97386#L1185-1 assume !(0 == ~E_9~0); 97040#L1190-1 assume !(0 == ~E_10~0); 97041#L1195-1 assume !(0 == ~E_11~0); 97400#L1200-1 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 97235#L525 assume !(1 == ~m_pc~0); 96663#L525-2 is_master_triggered_~__retres1~0 := 0; 96664#L536 is_master_triggered_#res := is_master_triggered_~__retres1~0; 97404#L537 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 97405#L1350 assume !(0 != activate_threads_~tmp~1); 97026#L1350-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 97027#L544 assume !(1 == ~t1_pc~0); 97242#L544-2 is_transmit1_triggered_~__retres1~1 := 0; 97243#L555 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 97700#L556 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 96871#L1358 assume !(0 != activate_threads_~tmp___0~0); 96872#L1358-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 97504#L563 assume !(1 == ~t2_pc~0); 97686#L563-2 is_transmit2_triggered_~__retres1~2 := 0; 96687#L574 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 96688#L575 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 97104#L1366 assume !(0 != activate_threads_~tmp___1~0); 97105#L1366-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 97577#L582 assume !(1 == ~t3_pc~0); 97701#L582-2 is_transmit3_triggered_~__retres1~3 := 0; 98094#L593 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 98095#L594 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 98015#L1374 assume !(0 != activate_threads_~tmp___2~0); 96756#L1374-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 96757#L601 assume !(1 == ~t4_pc~0); 97721#L601-2 is_transmit4_triggered_~__retres1~4 := 0; 97245#L612 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 97246#L613 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 97714#L1382 assume !(0 != activate_threads_~tmp___3~0); 97715#L1382-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 98083#L620 assume !(1 == ~t5_pc~0); 97548#L620-2 is_transmit5_triggered_~__retres1~5 := 0; 97549#L631 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 97528#L632 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 97529#L1390 assume !(0 != activate_threads_~tmp___4~0); 98117#L1390-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 98118#L639 assume 1 == ~t6_pc~0; 98058#L640 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 97142#L650 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 97143#L651 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 98020#L1398 assume !(0 != activate_threads_~tmp___5~0); 97252#L1398-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 97253#L658 assume !(1 == ~t7_pc~0); 97451#L658-2 is_transmit7_triggered_~__retres1~7 := 0; 97452#L669 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 97566#L670 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 97567#L1406 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 97034#L1406-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 97035#L677 assume 1 == ~t8_pc~0; 97257#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 96830#L688 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 96831#L689 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 97101#L1414 assume !(0 != activate_threads_~tmp___7~0); 97102#L1414-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 97825#L696 assume !(1 == ~t9_pc~0); 97514#L696-2 is_transmit9_triggered_~__retres1~9 := 0; 97515#L707 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 97608#L708 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 97537#L1422 assume !(0 != activate_threads_~tmp___8~0); 97538#L1422-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 97757#L715 assume !(1 == ~t10_pc~0); 97765#L715-2 is_transmit10_triggered_~__retres1~10 := 0; 97628#L726 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 97506#L727 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 97507#L1430 assume !(0 != activate_threads_~tmp___9~0); 97376#L1430-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 96822#L734 assume !(1 == ~t11_pc~0); 96823#L734-2 is_transmit11_triggered_~__retres1~11 := 0; 97308#L745 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 97391#L746 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 96565#L1438 assume !(0 != activate_threads_~tmp___10~0); 96566#L1438-2 assume !(1 == ~M_E~0); 97596#L1213-1 assume !(1 == ~T1_E~0); 97806#L1218-1 assume !(1 == ~T2_E~0); 96602#L1223-1 assume !(1 == ~T3_E~0); 96603#L1228-1 assume !(1 == ~T4_E~0); 97354#L1233-1 assume !(1 == ~T5_E~0); 98119#L1238-1 assume !(1 == ~T6_E~0); 97712#L1243-1 assume !(1 == ~T7_E~0); 97713#L1248-1 assume !(1 == ~T8_E~0); 97762#L1253-1 assume !(1 == ~T9_E~0); 97763#L1258-1 assume !(1 == ~T10_E~0); 97739#L1263-1 assume !(1 == ~T11_E~0); 97740#L1268-1 assume !(1 == ~E_1~0); 97555#L1273-1 assume !(1 == ~E_2~0); 97556#L1278-1 assume !(1 == ~E_3~0); 97140#L1283-1 assume !(1 == ~E_4~0); 97141#L1288-1 assume !(1 == ~E_5~0); 97880#L1293-1 assume !(1 == ~E_6~0); 97831#L1298-1 assume !(1 == ~E_7~0); 97581#L1303-1 assume !(1 == ~E_8~0); 97151#L1308-1 assume !(1 == ~E_9~0); 97049#L1313-1 assume !(1 == ~E_10~0); 97050#L1318-1 assume !(1 == ~E_11~0); 98067#L1644-1 [2021-11-07 07:22:26,841 INFO L793 eck$LassoCheckResult]: Loop: 98067#L1644-1 assume !false; 98163#L1645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_~tmp~0;havoc eval_~tmp~0; 123135#L1065 assume !false; 98114#L902 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 98115#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 96682#L891 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 97964#L892 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 97156#L906 assume !(0 != eval_~tmp~0); 97158#L1080 start_simulation_~kernel_st~0 := 2; 124243#L754-1 start_simulation_~kernel_st~0 := 3; 124242#L1090-2 assume 0 == ~M_E~0;~M_E~0 := 1; 124241#L1090-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 124240#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 124239#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 124238#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 124237#L1110-3 assume !(0 == ~T5_E~0); 124236#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 124235#L1120-3 assume !(0 == ~T7_E~0); 124234#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 124233#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 124232#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 124231#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 124230#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 124229#L1150-3 assume !(0 == ~E_2~0); 124228#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 124227#L1160-3 assume !(0 == ~E_4~0); 124226#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 124225#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 124224#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 124223#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 124222#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 124221#L1190-3 assume !(0 == ~E_10~0); 124220#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 124219#L1200-3 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 124218#L525-36 assume !(1 == ~m_pc~0); 124217#L525-38 is_master_triggered_~__retres1~0 := 0; 124216#L536-12 is_master_triggered_#res := is_master_triggered_~__retres1~0; 124215#L537-12 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 124214#L1350-36 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 124213#L1350-38 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 124212#L544-36 assume !(1 == ~t1_pc~0); 124211#L544-38 is_transmit1_triggered_~__retres1~1 := 0; 124210#L555-12 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 124209#L556-12 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 124208#L1358-36 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 124207#L1358-38 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 124206#L563-36 assume !(1 == ~t2_pc~0); 124204#L563-38 is_transmit2_triggered_~__retres1~2 := 0; 124203#L574-12 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 124202#L575-12 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 124201#L1366-36 assume !(0 != activate_threads_~tmp___1~0); 124200#L1366-38 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 124199#L582-36 assume !(1 == ~t3_pc~0); 124198#L582-38 is_transmit3_triggered_~__retres1~3 := 0; 124197#L593-12 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 124196#L594-12 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 124195#L1374-36 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 124194#L1374-38 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 124193#L601-36 assume 1 == ~t4_pc~0; 124192#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 124190#L612-12 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 124189#L613-12 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 124188#L1382-36 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 124187#L1382-38 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 124186#L620-36 assume !(1 == ~t5_pc~0); 124185#L620-38 is_transmit5_triggered_~__retres1~5 := 0; 124184#L631-12 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 124183#L632-12 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 124182#L1390-36 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 124181#L1390-38 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 124180#L639-36 assume 1 == ~t6_pc~0; 124179#L640-12 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 124177#L650-12 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 124176#L651-12 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 124175#L1398-36 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 124174#L1398-38 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 124173#L658-36 assume 1 == ~t7_pc~0; 124171#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 124169#L669-12 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 124168#L670-12 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 124167#L1406-36 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 124166#L1406-38 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 124165#L677-36 assume !(1 == ~t8_pc~0); 124163#L677-38 is_transmit8_triggered_~__retres1~8 := 0; 97578#L688-12 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 97579#L689-12 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 98075#L1414-36 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 97479#L1414-38 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 97480#L696-36 assume 1 == ~t9_pc~0; 97372#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 97373#L707-12 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 96736#L708-12 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 96737#L1422-36 assume !(0 != activate_threads_~tmp___8~0); 123779#L1422-38 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 123580#L715-36 assume !(1 == ~t10_pc~0); 123578#L715-38 is_transmit10_triggered_~__retres1~10 := 0; 123576#L726-12 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 123574#L727-12 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 123561#L1430-36 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 123104#L1430-38 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 123103#L734-36 assume 1 == ~t11_pc~0; 123101#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 123100#L745-12 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 123099#L746-12 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 123098#L1438-36 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 123096#L1438-38 assume 1 == ~M_E~0;~M_E~0 := 2; 123094#L1213-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 123092#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 123090#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 123088#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 123086#L1233-3 assume !(1 == ~T5_E~0); 123084#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 123082#L1243-3 assume !(1 == ~T7_E~0); 123080#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 123078#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 123075#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 123073#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 123071#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 123069#L1273-3 assume !(1 == ~E_2~0); 123067#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 123065#L1283-3 assume !(1 == ~E_4~0); 123063#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 123061#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 123059#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 123057#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 123055#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 123054#L1313-3 assume !(1 == ~E_10~0); 97976#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 96971#L1323-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 96972#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 96911#L891-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 97320#L892-1 start_simulation_#t~ret33 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 97798#L1663 assume !(0 == start_simulation_~tmp~3); 97266#L1663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret32, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 97533#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 96754#L891-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 97450#L892-2 stop_simulation_#t~ret32 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret32;havoc stop_simulation_#t~ret32; 96702#L1618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 96703#L1625 stop_simulation_#res := stop_simulation_~__retres2~0; 97037#L1626 start_simulation_#t~ret34 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret34;havoc start_simulation_#t~ret34; 98066#L1676 assume !(0 != start_simulation_~tmp___0~1); 98067#L1644-1 [2021-11-07 07:22:26,842 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:26,842 INFO L85 PathProgramCache]: Analyzing trace with hash 1986061693, now seen corresponding path program 1 times [2021-11-07 07:22:26,842 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:26,843 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2142894994] [2021-11-07 07:22:26,843 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:26,843 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:26,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:26,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:26,927 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:26,927 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2142894994] [2021-11-07 07:22:26,927 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2142894994] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:26,928 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:26,928 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:26,928 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [743643524] [2021-11-07 07:22:26,929 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:22:26,929 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:26,929 INFO L85 PathProgramCache]: Analyzing trace with hash -1082017224, now seen corresponding path program 1 times [2021-11-07 07:22:26,930 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:26,930 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [651398683] [2021-11-07 07:22:26,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:26,930 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:26,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:27,037 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:27,037 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:27,038 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [651398683] [2021-11-07 07:22:27,038 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [651398683] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:27,038 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:27,038 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:27,039 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1459755150] [2021-11-07 07:22:27,039 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:22:27,039 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:22:27,040 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-07 07:22:27,040 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-07 07:22:27,040 INFO L87 Difference]: Start difference. First operand 28121 states and 40067 transitions. cyclomatic complexity: 11954 Second operand has 4 states, 4 states have (on average 33.25) internal successors, (133), 3 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:28,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:22:28,013 INFO L93 Difference]: Finished difference Result 80130 states and 113457 transitions. [2021-11-07 07:22:28,024 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 07:22:28,024 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 80130 states and 113457 transitions. [2021-11-07 07:22:28,600 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 79085 [2021-11-07 07:22:28,982 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 80130 states to 80130 states and 113457 transitions. [2021-11-07 07:22:28,982 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 80130 [2021-11-07 07:22:29,161 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 80130 [2021-11-07 07:22:29,162 INFO L73 IsDeterministic]: Start isDeterministic. Operand 80130 states and 113457 transitions. [2021-11-07 07:22:29,369 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:22:29,369 INFO L681 BuchiCegarLoop]: Abstraction has 80130 states and 113457 transitions. [2021-11-07 07:22:29,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80130 states and 113457 transitions. [2021-11-07 07:22:30,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80130 to 78166. [2021-11-07 07:22:30,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78166 states, 78166 states have (on average 1.417892689916332) internal successors, (110831), 78165 states have internal predecessors, (110831), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:31,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78166 states to 78166 states and 110831 transitions. [2021-11-07 07:22:31,151 INFO L704 BuchiCegarLoop]: Abstraction has 78166 states and 110831 transitions. [2021-11-07 07:22:31,151 INFO L587 BuchiCegarLoop]: Abstraction has 78166 states and 110831 transitions. [2021-11-07 07:22:31,151 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-07 07:22:31,151 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78166 states and 110831 transitions. [2021-11-07 07:22:31,598 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 77951 [2021-11-07 07:22:31,598 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:22:31,598 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:22:31,602 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:31,602 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:31,603 INFO L791 eck$LassoCheckResult]: Stem: 205955#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 205956#L-1 havoc main_#res;havoc main_~__retres1~13;havoc main_~__retres1~13;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 205972#L1607 havoc start_simulation_#t~ret33, start_simulation_#t~ret34, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 205973#L754 assume 1 == ~m_i~0;~m_st~0 := 0; 206142#L761-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 205568#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 205474#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 205194#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 204838#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 204839#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 204887#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 204888#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 205831#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 205832#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 205879#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 205302#L816-1 assume !(0 == ~M_E~0); 205303#L1090-1 assume !(0 == ~T1_E~0); 206367#L1095-1 assume !(0 == ~T2_E~0); 206047#L1100-1 assume !(0 == ~T3_E~0); 206048#L1105-1 assume !(0 == ~T4_E~0); 205111#L1110-1 assume !(0 == ~T5_E~0); 205112#L1115-1 assume !(0 == ~T6_E~0); 205512#L1120-1 assume !(0 == ~T7_E~0); 205803#L1125-1 assume !(0 == ~T8_E~0); 206501#L1130-1 assume !(0 == ~T9_E~0); 206071#L1135-1 assume !(0 == ~T10_E~0); 205309#L1140-1 assume !(0 == ~T11_E~0); 205310#L1145-1 assume !(0 == ~E_1~0); 205990#L1150-1 assume !(0 == ~E_2~0); 205485#L1155-1 assume !(0 == ~E_3~0); 205486#L1160-1 assume !(0 == ~E_4~0); 205577#L1165-1 assume !(0 == ~E_5~0); 205578#L1170-1 assume !(0 == ~E_6~0); 206315#L1175-1 assume !(0 == ~E_7~0); 205654#L1180-1 assume !(0 == ~E_8~0); 205655#L1185-1 assume !(0 == ~E_9~0); 205304#L1190-1 assume !(0 == ~E_10~0); 205305#L1195-1 assume !(0 == ~E_11~0); 205668#L1200-1 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 205507#L525 assume !(1 == ~m_pc~0); 204924#L525-2 is_master_triggered_~__retres1~0 := 0; 204925#L536 is_master_triggered_#res := is_master_triggered_~__retres1~0; 205672#L537 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 205673#L1350 assume !(0 != activate_threads_~tmp~1); 205292#L1350-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 205293#L544 assume !(1 == ~t1_pc~0); 205508#L544-2 is_transmit1_triggered_~__retres1~1 := 0; 205509#L555 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 205987#L556 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 205133#L1358 assume !(0 != activate_threads_~tmp___0~0); 205134#L1358-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 205773#L563 assume !(1 == ~t2_pc~0); 205974#L563-2 is_transmit2_triggered_~__retres1~2 := 0; 204947#L574 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 204948#L575 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 205371#L1366 assume !(0 != activate_threads_~tmp___1~0); 205372#L1366-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 205853#L582 assume !(1 == ~t3_pc~0); 205988#L582-2 is_transmit3_triggered_~__retres1~3 := 0; 206422#L593 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 206423#L594 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 206328#L1374 assume !(0 != activate_threads_~tmp___2~0); 205016#L1374-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 205017#L601 assume !(1 == ~t4_pc~0); 206010#L601-2 is_transmit4_triggered_~__retres1~4 := 0; 205513#L612 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 205514#L613 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 206002#L1382 assume !(0 != activate_threads_~tmp___3~0); 206003#L1382-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 206408#L620 assume !(1 == ~t5_pc~0); 205823#L620-2 is_transmit5_triggered_~__retres1~5 := 0; 205824#L631 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 205799#L632 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 205800#L1390 assume !(0 != activate_threads_~tmp___4~0); 206442#L1390-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 206443#L639 assume !(1 == ~t6_pc~0); 205801#L639-2 is_transmit6_triggered_~__retres1~6 := 0; 205406#L650 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 205407#L651 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 206330#L1398 assume !(0 != activate_threads_~tmp___5~0); 205518#L1398-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 205519#L658 assume !(1 == ~t7_pc~0); 205718#L658-2 is_transmit7_triggered_~__retres1~7 := 0; 205719#L669 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 205839#L670 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 205840#L1406 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 205298#L1406-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 205299#L677 assume 1 == ~t8_pc~0; 205524#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 205096#L688 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 205097#L689 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 205365#L1414 assume !(0 != activate_threads_~tmp___7~0); 205366#L1414-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 206123#L696 assume !(1 == ~t9_pc~0); 205787#L696-2 is_transmit9_triggered_~__retres1~9 := 0; 205788#L707 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 205887#L708 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 205812#L1422 assume !(0 != activate_threads_~tmp___8~0); 205813#L1422-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 206052#L715 assume !(1 == ~t10_pc~0); 206059#L715-2 is_transmit10_triggered_~__retres1~10 := 0; 205904#L726 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 205776#L727 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 205777#L1430 assume !(0 != activate_threads_~tmp___9~0); 205645#L1430-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 205085#L734 assume !(1 == ~t11_pc~0); 205086#L734-2 is_transmit11_triggered_~__retres1~11 := 0; 205581#L745 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 205659#L746 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 204828#L1438 assume !(0 != activate_threads_~tmp___10~0); 204829#L1438-2 assume !(1 == ~M_E~0); 205871#L1213-1 assume !(1 == ~T1_E~0); 206103#L1218-1 assume !(1 == ~T2_E~0); 204863#L1223-1 assume !(1 == ~T3_E~0); 204864#L1228-1 assume !(1 == ~T4_E~0); 205622#L1233-1 assume !(1 == ~T5_E~0); 206444#L1238-1 assume !(1 == ~T6_E~0); 206000#L1243-1 assume !(1 == ~T7_E~0); 206001#L1248-1 assume !(1 == ~T8_E~0); 206056#L1253-1 assume !(1 == ~T9_E~0); 206057#L1258-1 assume !(1 == ~T10_E~0); 206031#L1263-1 assume !(1 == ~T11_E~0); 206032#L1268-1 assume !(1 == ~E_1~0); 205827#L1273-1 assume !(1 == ~E_2~0); 205828#L1278-1 assume !(1 == ~E_3~0); 205404#L1283-1 assume !(1 == ~E_4~0); 205405#L1288-1 assume !(1 == ~E_5~0); 206189#L1293-1 assume !(1 == ~E_6~0); 206133#L1298-1 assume !(1 == ~E_7~0); 205857#L1303-1 assume !(1 == ~E_8~0); 205416#L1308-1 assume !(1 == ~E_9~0); 205315#L1313-1 assume !(1 == ~E_10~0); 205316#L1318-1 assume !(1 == ~E_11~0); 206511#L1644-1 [2021-11-07 07:22:31,603 INFO L793 eck$LassoCheckResult]: Loop: 206511#L1644-1 assume !false; 272022#L1645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_~tmp~0;havoc eval_~tmp~0; 272014#L1065 assume !false; 272007#L902 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 271941#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 271926#L891 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 271922#L892 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 271915#L906 assume !(0 != eval_~tmp~0); 271916#L1080 start_simulation_~kernel_st~0 := 2; 273597#L754-1 start_simulation_~kernel_st~0 := 3; 273595#L1090-2 assume 0 == ~M_E~0;~M_E~0 := 1; 273592#L1090-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 273590#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 273588#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 273586#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 273584#L1110-3 assume !(0 == ~T5_E~0); 273581#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 273579#L1120-3 assume !(0 == ~T7_E~0); 273577#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 273575#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 273573#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 273571#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 273569#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 273567#L1150-3 assume !(0 == ~E_2~0); 273565#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 273563#L1160-3 assume !(0 == ~E_4~0); 273561#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 273559#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 273557#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 273554#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 273552#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 273550#L1190-3 assume !(0 == ~E_10~0); 273548#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 273546#L1200-3 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 273544#L525-36 assume !(1 == ~m_pc~0); 273542#L525-38 is_master_triggered_~__retres1~0 := 0; 273540#L536-12 is_master_triggered_#res := is_master_triggered_~__retres1~0; 273538#L537-12 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 273536#L1350-36 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 273534#L1350-38 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 273532#L544-36 assume !(1 == ~t1_pc~0); 273530#L544-38 is_transmit1_triggered_~__retres1~1 := 0; 273527#L555-12 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 273524#L556-12 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 273521#L1358-36 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 273518#L1358-38 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 273515#L563-36 assume !(1 == ~t2_pc~0); 273510#L563-38 is_transmit2_triggered_~__retres1~2 := 0; 273507#L574-12 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 273502#L575-12 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 273498#L1366-36 assume !(0 != activate_threads_~tmp___1~0); 273494#L1366-38 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 273490#L582-36 assume !(1 == ~t3_pc~0); 273485#L582-38 is_transmit3_triggered_~__retres1~3 := 0; 273480#L593-12 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 273476#L594-12 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 273472#L1374-36 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 273468#L1374-38 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 273464#L601-36 assume !(1 == ~t4_pc~0); 273458#L601-38 is_transmit4_triggered_~__retres1~4 := 0; 273453#L612-12 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 273447#L613-12 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 273442#L1382-36 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 273437#L1382-38 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 273431#L620-36 assume !(1 == ~t5_pc~0); 273426#L620-38 is_transmit5_triggered_~__retres1~5 := 0; 273421#L631-12 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 273415#L632-12 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 273410#L1390-36 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 273406#L1390-38 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 273402#L639-36 assume !(1 == ~t6_pc~0); 273398#L639-38 is_transmit6_triggered_~__retres1~6 := 0; 273393#L650-12 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 273389#L651-12 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 273384#L1398-36 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 273380#L1398-38 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 273376#L658-36 assume !(1 == ~t7_pc~0); 273372#L658-38 is_transmit7_triggered_~__retres1~7 := 0; 273366#L669-12 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 273361#L670-12 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 273356#L1406-36 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 273351#L1406-38 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 273346#L677-36 assume !(1 == ~t8_pc~0); 273340#L677-38 is_transmit8_triggered_~__retres1~8 := 0; 273335#L688-12 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 273327#L689-12 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 273322#L1414-36 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 273317#L1414-38 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 273312#L696-36 assume 1 == ~t9_pc~0; 273306#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 273300#L707-12 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 273294#L708-12 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 273288#L1422-36 assume !(0 != activate_threads_~tmp___8~0); 273283#L1422-38 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 273278#L715-36 assume !(1 == ~t10_pc~0); 273275#L715-38 is_transmit10_triggered_~__retres1~10 := 0; 273273#L726-12 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 273271#L727-12 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 273269#L1430-36 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 273267#L1430-38 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 273265#L734-36 assume 1 == ~t11_pc~0; 273262#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 273260#L745-12 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 273257#L746-12 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 273255#L1438-36 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 273253#L1438-38 assume 1 == ~M_E~0;~M_E~0 := 2; 273251#L1213-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 273249#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 273247#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 273246#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 273243#L1233-3 assume !(1 == ~T5_E~0); 273241#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 273239#L1243-3 assume !(1 == ~T7_E~0); 273237#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 273235#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 273233#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 273230#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 273228#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 273226#L1273-3 assume !(1 == ~E_2~0); 273224#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 273222#L1283-3 assume !(1 == ~E_4~0); 273219#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 273217#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 273215#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 273213#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 273211#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 273209#L1313-3 assume !(1 == ~E_10~0); 273207#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 273206#L1323-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 273143#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 273137#L891-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 273130#L892-1 start_simulation_#t~ret33 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 273122#L1663 assume !(0 == start_simulation_~tmp~3); 273119#L1663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret32, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 273103#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 273095#L891-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 273090#L892-2 stop_simulation_#t~ret32 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret32;havoc stop_simulation_#t~ret32; 273086#L1618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 273081#L1625 stop_simulation_#res := stop_simulation_~__retres2~0; 273077#L1626 start_simulation_#t~ret34 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret34;havoc start_simulation_#t~ret34; 272162#L1676 assume !(0 != start_simulation_~tmp___0~1); 206511#L1644-1 [2021-11-07 07:22:31,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:31,604 INFO L85 PathProgramCache]: Analyzing trace with hash 844414300, now seen corresponding path program 1 times [2021-11-07 07:22:31,605 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:31,605 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2039527888] [2021-11-07 07:22:31,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:31,606 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:31,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:31,671 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:31,672 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:31,672 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2039527888] [2021-11-07 07:22:31,672 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2039527888] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:31,673 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:31,673 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-07 07:22:31,673 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1792805547] [2021-11-07 07:22:31,674 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:22:31,674 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:31,675 INFO L85 PathProgramCache]: Analyzing trace with hash 235123963, now seen corresponding path program 1 times [2021-11-07 07:22:31,675 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:31,675 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1974811504] [2021-11-07 07:22:31,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:31,676 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:31,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:31,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:31,746 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:31,746 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1974811504] [2021-11-07 07:22:31,747 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1974811504] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:31,747 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:31,747 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-07 07:22:31,748 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [566718961] [2021-11-07 07:22:31,748 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:22:31,749 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:22:31,749 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-07 07:22:31,750 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-07 07:22:31,750 INFO L87 Difference]: Start difference. First operand 78166 states and 110831 transitions. cyclomatic complexity: 32681 Second operand has 5 states, 5 states have (on average 26.6) internal successors, (133), 5 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:33,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:22:33,088 INFO L93 Difference]: Finished difference Result 192104 states and 275074 transitions. [2021-11-07 07:22:33,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-07 07:22:33,089 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 192104 states and 275074 transitions. [2021-11-07 07:22:34,371 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 191649 [2021-11-07 07:22:35,452 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 192104 states to 192104 states and 275074 transitions. [2021-11-07 07:22:35,452 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 192104 [2021-11-07 07:22:35,563 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 192104 [2021-11-07 07:22:35,564 INFO L73 IsDeterministic]: Start isDeterministic. Operand 192104 states and 275074 transitions. [2021-11-07 07:22:35,713 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:22:35,713 INFO L681 BuchiCegarLoop]: Abstraction has 192104 states and 275074 transitions. [2021-11-07 07:22:35,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 192104 states and 275074 transitions. [2021-11-07 07:22:37,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 192104 to 80485. [2021-11-07 07:22:37,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80485 states, 80485 states have (on average 1.4058520221159223) internal successors, (113150), 80484 states have internal predecessors, (113150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:37,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80485 states to 80485 states and 113150 transitions. [2021-11-07 07:22:37,487 INFO L704 BuchiCegarLoop]: Abstraction has 80485 states and 113150 transitions. [2021-11-07 07:22:37,487 INFO L587 BuchiCegarLoop]: Abstraction has 80485 states and 113150 transitions. [2021-11-07 07:22:37,487 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-07 07:22:37,488 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80485 states and 113150 transitions. [2021-11-07 07:22:37,708 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 80267 [2021-11-07 07:22:37,709 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:22:37,709 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:22:37,711 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:37,712 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:37,712 INFO L791 eck$LassoCheckResult]: Stem: 476223#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 476224#L-1 havoc main_#res;havoc main_~__retres1~13;havoc main_~__retres1~13;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 476236#L1607 havoc start_simulation_#t~ret33, start_simulation_#t~ret34, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 476237#L754 assume 1 == ~m_i~0;~m_st~0 := 0; 476393#L761-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 475848#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 475757#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 475479#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 475123#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 475124#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 475172#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 475173#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 476107#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 476108#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 476150#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 475586#L816-1 assume !(0 == ~M_E~0); 475587#L1090-1 assume !(0 == ~T1_E~0); 476613#L1095-1 assume !(0 == ~T2_E~0); 476306#L1100-1 assume !(0 == ~T3_E~0); 476307#L1105-1 assume !(0 == ~T4_E~0); 475394#L1110-1 assume !(0 == ~T5_E~0); 475395#L1115-1 assume !(0 == ~T6_E~0); 475793#L1120-1 assume !(0 == ~T7_E~0); 476081#L1125-1 assume !(0 == ~T8_E~0); 476727#L1130-1 assume !(0 == ~T9_E~0); 476330#L1135-1 assume !(0 == ~T10_E~0); 475591#L1140-1 assume !(0 == ~T11_E~0); 475592#L1145-1 assume !(0 == ~E_1~0); 476255#L1150-1 assume !(0 == ~E_2~0); 475768#L1155-1 assume !(0 == ~E_3~0); 475769#L1160-1 assume !(0 == ~E_4~0); 475856#L1165-1 assume !(0 == ~E_5~0); 475857#L1170-1 assume !(0 == ~E_6~0); 476558#L1175-1 assume !(0 == ~E_7~0); 475935#L1180-1 assume !(0 == ~E_8~0); 475936#L1185-1 assume !(0 == ~E_9~0); 475588#L1190-1 assume !(0 == ~E_10~0); 475589#L1195-1 assume !(0 == ~E_11~0); 475949#L1200-1 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 475784#L525 assume !(1 == ~m_pc~0); 475209#L525-2 is_master_triggered_~__retres1~0 := 0; 475210#L536 is_master_triggered_#res := is_master_triggered_~__retres1~0; 475953#L537 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 475954#L1350 assume !(0 != activate_threads_~tmp~1); 475575#L1350-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 475576#L544 assume !(1 == ~t1_pc~0); 475791#L544-2 is_transmit1_triggered_~__retres1~1 := 0; 475792#L555 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 476252#L556 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 475416#L1358 assume !(0 != activate_threads_~tmp___0~0); 475417#L1358-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 476050#L563 assume !(1 == ~t2_pc~0); 476238#L563-2 is_transmit2_triggered_~__retres1~2 := 0; 475232#L574 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 475233#L575 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 475653#L1366 assume !(0 != activate_threads_~tmp___1~0); 475654#L1366-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 476128#L582 assume !(1 == ~t3_pc~0); 476253#L582-2 is_transmit3_triggered_~__retres1~3 := 0; 476667#L593 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 476668#L594 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 476571#L1374 assume !(0 != activate_threads_~tmp___2~0); 475301#L1374-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 475302#L601 assume !(1 == ~t4_pc~0); 476274#L601-2 is_transmit4_triggered_~__retres1~4 := 0; 475794#L612 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 475795#L613 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 476266#L1382 assume !(0 != activate_threads_~tmp___3~0); 476267#L1382-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 476651#L620 assume !(1 == ~t5_pc~0); 476097#L620-2 is_transmit5_triggered_~__retres1~5 := 0; 476098#L631 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 476077#L632 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 476078#L1390 assume !(0 != activate_threads_~tmp___4~0); 476685#L1390-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 476686#L639 assume !(1 == ~t6_pc~0); 476076#L639-2 is_transmit6_triggered_~__retres1~6 := 0; 475691#L650 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 475692#L651 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 476574#L1398 assume !(0 != activate_threads_~tmp___5~0); 475802#L1398-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 475803#L658 assume !(1 == ~t7_pc~0); 475999#L658-2 is_transmit7_triggered_~__retres1~7 := 0; 476000#L669 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 476694#L670 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 476193#L1406 assume !(0 != activate_threads_~tmp___6~0); 475582#L1406-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 475583#L677 assume 1 == ~t8_pc~0; 475807#L678 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 475376#L688 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 475377#L689 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 475650#L1414 assume !(0 != activate_threads_~tmp___7~0); 475651#L1414-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 476377#L696 assume !(1 == ~t9_pc~0); 476061#L696-2 is_transmit9_triggered_~__retres1~9 := 0; 476062#L707 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 476160#L708 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 476086#L1422 assume !(0 != activate_threads_~tmp___8~0); 476087#L1422-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 476310#L715 assume !(1 == ~t10_pc~0); 476318#L715-2 is_transmit10_triggered_~__retres1~10 := 0; 476179#L726 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 476052#L727 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 476053#L1430 assume !(0 != activate_threads_~tmp___9~0); 475926#L1430-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 475368#L734 assume !(1 == ~t11_pc~0); 475369#L734-2 is_transmit11_triggered_~__retres1~11 := 0; 475858#L745 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 475940#L746 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 475111#L1438 assume !(0 != activate_threads_~tmp___10~0); 475112#L1438-2 assume !(1 == ~M_E~0); 476148#L1213-1 assume !(1 == ~T1_E~0); 476359#L1218-1 assume !(1 == ~T2_E~0); 475148#L1223-1 assume !(1 == ~T3_E~0); 475149#L1228-1 assume !(1 == ~T4_E~0); 475904#L1233-1 assume !(1 == ~T5_E~0); 476687#L1238-1 assume !(1 == ~T6_E~0); 476264#L1243-1 assume !(1 == ~T7_E~0); 476265#L1248-1 assume !(1 == ~T8_E~0); 476315#L1253-1 assume !(1 == ~T9_E~0); 476316#L1258-1 assume !(1 == ~T10_E~0); 476290#L1263-1 assume !(1 == ~T11_E~0); 476291#L1268-1 assume !(1 == ~E_1~0); 476105#L1273-1 assume !(1 == ~E_2~0); 476106#L1278-1 assume !(1 == ~E_3~0); 475689#L1283-1 assume !(1 == ~E_4~0); 475690#L1288-1 assume !(1 == ~E_5~0); 476436#L1293-1 assume !(1 == ~E_6~0); 476382#L1298-1 assume !(1 == ~E_7~0); 476131#L1303-1 assume !(1 == ~E_8~0); 475700#L1308-1 assume !(1 == ~E_9~0); 475597#L1313-1 assume !(1 == ~E_10~0); 475598#L1318-1 assume !(1 == ~E_11~0); 476733#L1644-1 [2021-11-07 07:22:37,713 INFO L793 eck$LassoCheckResult]: Loop: 476733#L1644-1 assume !false; 528863#L1645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_~tmp~0;havoc eval_~tmp~0; 528856#L1065 assume !false; 528850#L902 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 528049#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 528034#L891 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 528030#L892 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 528025#L906 assume !(0 != eval_~tmp~0); 528026#L1080 start_simulation_~kernel_st~0 := 2; 530147#L754-1 start_simulation_~kernel_st~0 := 3; 530145#L1090-2 assume 0 == ~M_E~0;~M_E~0 := 1; 530143#L1090-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 530140#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 530138#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 530136#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 530134#L1110-3 assume !(0 == ~T5_E~0); 530132#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 530130#L1120-3 assume !(0 == ~T7_E~0); 530127#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 530125#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 530123#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 530121#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 530119#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 530117#L1150-3 assume !(0 == ~E_2~0); 530114#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 530112#L1160-3 assume !(0 == ~E_4~0); 530110#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 530108#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 530104#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 530102#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 530101#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 530100#L1190-3 assume !(0 == ~E_10~0); 530099#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 530098#L1200-3 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 530097#L525-36 assume !(1 == ~m_pc~0); 530096#L525-38 is_master_triggered_~__retres1~0 := 0; 530095#L536-12 is_master_triggered_#res := is_master_triggered_~__retres1~0; 530094#L537-12 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 530093#L1350-36 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 530092#L1350-38 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 530091#L544-36 assume !(1 == ~t1_pc~0); 530090#L544-38 is_transmit1_triggered_~__retres1~1 := 0; 530089#L555-12 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 530088#L556-12 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 530087#L1358-36 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 530086#L1358-38 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 530085#L563-36 assume !(1 == ~t2_pc~0); 530083#L563-38 is_transmit2_triggered_~__retres1~2 := 0; 530082#L574-12 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 530081#L575-12 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 530080#L1366-36 assume !(0 != activate_threads_~tmp___1~0); 530079#L1366-38 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 530078#L582-36 assume !(1 == ~t3_pc~0); 530077#L582-38 is_transmit3_triggered_~__retres1~3 := 0; 530076#L593-12 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 530075#L594-12 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 530074#L1374-36 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 530073#L1374-38 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 530072#L601-36 assume !(1 == ~t4_pc~0); 530070#L601-38 is_transmit4_triggered_~__retres1~4 := 0; 530069#L612-12 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 530068#L613-12 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 530067#L1382-36 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 530066#L1382-38 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 530065#L620-36 assume !(1 == ~t5_pc~0); 530064#L620-38 is_transmit5_triggered_~__retres1~5 := 0; 530063#L631-12 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 530062#L632-12 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 530061#L1390-36 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 530060#L1390-38 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 530059#L639-36 assume !(1 == ~t6_pc~0); 530058#L639-38 is_transmit6_triggered_~__retres1~6 := 0; 530057#L650-12 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 530056#L651-12 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 530055#L1398-36 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 530054#L1398-38 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 530053#L658-36 assume 1 == ~t7_pc~0; 530051#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 530049#L669-12 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 530047#L670-12 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 530045#L1406-36 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 530043#L1406-38 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 530041#L677-36 assume !(1 == ~t8_pc~0); 530038#L677-38 is_transmit8_triggered_~__retres1~8 := 0; 530036#L688-12 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 530035#L689-12 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 530032#L1414-36 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 530030#L1414-38 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 529896#L696-36 assume 1 == ~t9_pc~0; 529878#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 529876#L707-12 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 529874#L708-12 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 529872#L1422-36 assume !(0 != activate_threads_~tmp___8~0); 529870#L1422-38 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 529868#L715-36 assume !(1 == ~t10_pc~0); 529864#L715-38 is_transmit10_triggered_~__retres1~10 := 0; 529862#L726-12 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 529860#L727-12 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 529858#L1430-36 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 529857#L1430-38 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 529853#L734-36 assume 1 == ~t11_pc~0; 529850#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 529849#L745-12 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 529848#L746-12 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 529847#L1438-36 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 529846#L1438-38 assume 1 == ~M_E~0;~M_E~0 := 2; 529842#L1213-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 529785#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 529779#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 529718#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 529709#L1233-3 assume !(1 == ~T5_E~0); 529701#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 529695#L1243-3 assume !(1 == ~T7_E~0); 529691#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 529633#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 529627#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 529620#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 529613#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 529606#L1273-3 assume !(1 == ~E_2~0); 529545#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 529539#L1283-3 assume !(1 == ~E_4~0); 529532#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 529525#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 529517#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 529511#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 529505#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 529499#L1313-3 assume !(1 == ~E_10~0); 529493#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 529485#L1323-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 529362#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 529355#L891-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 529343#L892-1 start_simulation_#t~ret33 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 529333#L1663 assume !(0 == start_simulation_~tmp~3); 529327#L1663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret32, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 529193#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 529186#L891-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 529184#L892-2 stop_simulation_#t~ret32 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret32;havoc stop_simulation_#t~ret32; 529182#L1618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 529003#L1625 stop_simulation_#res := stop_simulation_~__retres2~0; 529002#L1626 start_simulation_#t~ret34 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret34;havoc start_simulation_#t~ret34; 528992#L1676 assume !(0 != start_simulation_~tmp___0~1); 476733#L1644-1 [2021-11-07 07:22:37,713 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:37,714 INFO L85 PathProgramCache]: Analyzing trace with hash -1511390950, now seen corresponding path program 1 times [2021-11-07 07:22:37,714 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:37,714 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1486370142] [2021-11-07 07:22:37,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:37,715 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:37,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:37,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:37,766 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:37,766 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1486370142] [2021-11-07 07:22:37,766 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1486370142] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:37,766 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:37,767 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:37,767 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [97761445] [2021-11-07 07:22:37,767 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:22:37,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:37,768 INFO L85 PathProgramCache]: Analyzing trace with hash -142518854, now seen corresponding path program 1 times [2021-11-07 07:22:37,768 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:37,769 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1410080946] [2021-11-07 07:22:37,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:37,769 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:37,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:37,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:37,818 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:37,818 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1410080946] [2021-11-07 07:22:37,818 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1410080946] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:37,818 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:37,818 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-07 07:22:37,819 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [209525142] [2021-11-07 07:22:37,819 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:22:37,819 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:22:37,820 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-07 07:22:37,820 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-07 07:22:37,821 INFO L87 Difference]: Start difference. First operand 80485 states and 113150 transitions. cyclomatic complexity: 32681 Second operand has 4 states, 4 states have (on average 33.25) internal successors, (133), 3 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:39,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:22:39,458 INFO L93 Difference]: Finished difference Result 228038 states and 318982 transitions. [2021-11-07 07:22:39,458 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 07:22:39,458 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 228038 states and 318982 transitions. [2021-11-07 07:22:41,291 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 225923 [2021-11-07 07:22:42,529 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 228038 states to 228038 states and 318982 transitions. [2021-11-07 07:22:42,530 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 228038 [2021-11-07 07:22:42,623 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 228038 [2021-11-07 07:22:42,623 INFO L73 IsDeterministic]: Start isDeterministic. Operand 228038 states and 318982 transitions. [2021-11-07 07:22:42,714 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:22:42,714 INFO L681 BuchiCegarLoop]: Abstraction has 228038 states and 318982 transitions. [2021-11-07 07:22:42,830 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228038 states and 318982 transitions. [2021-11-07 07:22:44,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228038 to 223952. [2021-11-07 07:22:45,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 223952 states, 223952 states have (on average 1.4004786740015718) internal successors, (313640), 223951 states have internal predecessors, (313640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:46,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 223952 states to 223952 states and 313640 transitions. [2021-11-07 07:22:46,806 INFO L704 BuchiCegarLoop]: Abstraction has 223952 states and 313640 transitions. [2021-11-07 07:22:46,806 INFO L587 BuchiCegarLoop]: Abstraction has 223952 states and 313640 transitions. [2021-11-07 07:22:46,806 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-07 07:22:46,806 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 223952 states and 313640 transitions. [2021-11-07 07:22:47,394 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 223655 [2021-11-07 07:22:47,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:22:47,394 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:22:47,397 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:47,398 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:22:47,398 INFO L791 eck$LassoCheckResult]: Stem: 784765#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 784766#L-1 havoc main_#res;havoc main_~__retres1~13;havoc main_~__retres1~13;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 784779#L1607 havoc start_simulation_#t~ret33, start_simulation_#t~ret34, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 784780#L754 assume 1 == ~m_i~0;~m_st~0 := 0; 784935#L761-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 784386#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 784294#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 784013#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 783658#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 783659#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 783707#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 783708#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 784645#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 784646#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 784683#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 784120#L816-1 assume !(0 == ~M_E~0); 784121#L1090-1 assume !(0 == ~T1_E~0); 785156#L1095-1 assume !(0 == ~T2_E~0); 784849#L1100-1 assume !(0 == ~T3_E~0); 784850#L1105-1 assume !(0 == ~T4_E~0); 783930#L1110-1 assume !(0 == ~T5_E~0); 783931#L1115-1 assume !(0 == ~T6_E~0); 784331#L1120-1 assume !(0 == ~T7_E~0); 784620#L1125-1 assume !(0 == ~T8_E~0); 785270#L1130-1 assume !(0 == ~T9_E~0); 784873#L1135-1 assume !(0 == ~T10_E~0); 784126#L1140-1 assume !(0 == ~T11_E~0); 784127#L1145-1 assume !(0 == ~E_1~0); 784797#L1150-1 assume !(0 == ~E_2~0); 784306#L1155-1 assume !(0 == ~E_3~0); 784307#L1160-1 assume !(0 == ~E_4~0); 784394#L1165-1 assume !(0 == ~E_5~0); 784395#L1170-1 assume !(0 == ~E_6~0); 785103#L1175-1 assume !(0 == ~E_7~0); 784470#L1180-1 assume !(0 == ~E_8~0); 784471#L1185-1 assume !(0 == ~E_9~0); 784122#L1190-1 assume !(0 == ~E_10~0); 784123#L1195-1 assume !(0 == ~E_11~0); 784484#L1200-1 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 784322#L525 assume !(1 == ~m_pc~0); 783744#L525-2 is_master_triggered_~__retres1~0 := 0; 783745#L536 is_master_triggered_#res := is_master_triggered_~__retres1~0; 784487#L537 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 784488#L1350 assume !(0 != activate_threads_~tmp~1); 784108#L1350-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 784109#L544 assume !(1 == ~t1_pc~0); 784329#L544-2 is_transmit1_triggered_~__retres1~1 := 0; 784330#L555 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 784794#L556 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 783951#L1358 assume !(0 != activate_threads_~tmp___0~0); 783952#L1358-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 784591#L563 assume !(1 == ~t2_pc~0); 784781#L563-2 is_transmit2_triggered_~__retres1~2 := 0; 783767#L574 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 783768#L575 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 784190#L1366 assume !(0 != activate_threads_~tmp___1~0); 784191#L1366-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 784665#L582 assume !(1 == ~t3_pc~0); 784795#L582-2 is_transmit3_triggered_~__retres1~3 := 0; 785211#L593 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 785212#L594 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 785113#L1374 assume !(0 != activate_threads_~tmp___2~0); 783837#L1374-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 783838#L601 assume !(1 == ~t4_pc~0); 784818#L601-2 is_transmit4_triggered_~__retres1~4 := 0; 784332#L612 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 784333#L613 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 784811#L1382 assume !(0 != activate_threads_~tmp___3~0); 784812#L1382-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 785196#L620 assume !(1 == ~t5_pc~0); 784635#L620-2 is_transmit5_triggered_~__retres1~5 := 0; 784636#L631 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 784615#L632 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 784616#L1390 assume !(0 != activate_threads_~tmp___4~0); 785228#L1390-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 785229#L639 assume !(1 == ~t6_pc~0); 784617#L639-2 is_transmit6_triggered_~__retres1~6 := 0; 784228#L650 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 784229#L651 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 785119#L1398 assume !(0 != activate_threads_~tmp___5~0); 784339#L1398-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 784340#L658 assume !(1 == ~t7_pc~0); 784531#L658-2 is_transmit7_triggered_~__retres1~7 := 0; 784532#L669 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 785239#L670 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 784729#L1406 assume !(0 != activate_threads_~tmp___6~0); 784115#L1406-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 784116#L677 assume !(1 == ~t8_pc~0); 784140#L677-2 is_transmit8_triggered_~__retres1~8 := 0; 783912#L688 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 783913#L689 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 784187#L1414 assume !(0 != activate_threads_~tmp___7~0); 784188#L1414-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 784919#L696 assume !(1 == ~t9_pc~0); 784601#L696-2 is_transmit9_triggered_~__retres1~9 := 0; 784602#L707 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 784694#L708 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 784624#L1422 assume !(0 != activate_threads_~tmp___8~0); 784625#L1422-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 784853#L715 assume !(1 == ~t10_pc~0); 784861#L715-2 is_transmit10_triggered_~__retres1~10 := 0; 784715#L726 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 784593#L727 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 784594#L1430 assume !(0 != activate_threads_~tmp___9~0); 784461#L1430-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 783904#L734 assume !(1 == ~t11_pc~0); 783905#L734-2 is_transmit11_triggered_~__retres1~11 := 0; 784396#L745 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 784475#L746 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 783646#L1438 assume !(0 != activate_threads_~tmp___10~0); 783647#L1438-2 assume !(1 == ~M_E~0); 784682#L1213-1 assume !(1 == ~T1_E~0); 784901#L1218-1 assume !(1 == ~T2_E~0); 783683#L1223-1 assume !(1 == ~T3_E~0); 783684#L1228-1 assume !(1 == ~T4_E~0); 784439#L1233-1 assume !(1 == ~T5_E~0); 785230#L1238-1 assume !(1 == ~T6_E~0); 784809#L1243-1 assume !(1 == ~T7_E~0); 784810#L1248-1 assume !(1 == ~T8_E~0); 784858#L1253-1 assume !(1 == ~T9_E~0); 784859#L1258-1 assume !(1 == ~T10_E~0); 784833#L1263-1 assume !(1 == ~T11_E~0); 784834#L1268-1 assume !(1 == ~E_1~0); 784643#L1273-1 assume !(1 == ~E_2~0); 784644#L1278-1 assume !(1 == ~E_3~0); 784226#L1283-1 assume !(1 == ~E_4~0); 784227#L1288-1 assume !(1 == ~E_5~0); 784977#L1293-1 assume !(1 == ~E_6~0); 784924#L1298-1 assume !(1 == ~E_7~0); 784668#L1303-1 assume !(1 == ~E_8~0); 784237#L1308-1 assume !(1 == ~E_9~0); 784132#L1313-1 assume !(1 == ~E_10~0); 784133#L1318-1 assume !(1 == ~E_11~0); 785281#L1644-1 [2021-11-07 07:22:47,399 INFO L793 eck$LassoCheckResult]: Loop: 785281#L1644-1 assume !false; 941278#L1645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_~tmp~0;havoc eval_~tmp~0; 941275#L1065 assume !false; 941272#L902 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 941263#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 941252#L891 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 941249#L892 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 941244#L906 assume !(0 != eval_~tmp~0); 941245#L1080 start_simulation_~kernel_st~0 := 2; 942479#L754-1 start_simulation_~kernel_st~0 := 3; 942478#L1090-2 assume 0 == ~M_E~0;~M_E~0 := 1; 942477#L1090-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 942476#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 942475#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 942474#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 942473#L1110-3 assume !(0 == ~T5_E~0); 942472#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 942471#L1120-3 assume !(0 == ~T7_E~0); 942470#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 942469#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 942468#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 942467#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 942466#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 942465#L1150-3 assume !(0 == ~E_2~0); 942464#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 942463#L1160-3 assume !(0 == ~E_4~0); 942462#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 942461#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 942460#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 942459#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 942458#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 942457#L1190-3 assume !(0 == ~E_10~0); 942456#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 942455#L1200-3 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 942454#L525-36 assume !(1 == ~m_pc~0); 942453#L525-38 is_master_triggered_~__retres1~0 := 0; 942452#L536-12 is_master_triggered_#res := is_master_triggered_~__retres1~0; 942451#L537-12 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 942450#L1350-36 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 942449#L1350-38 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 942448#L544-36 assume !(1 == ~t1_pc~0); 942447#L544-38 is_transmit1_triggered_~__retres1~1 := 0; 942446#L555-12 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 942445#L556-12 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 942444#L1358-36 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 942443#L1358-38 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 942442#L563-36 assume !(1 == ~t2_pc~0); 942440#L563-38 is_transmit2_triggered_~__retres1~2 := 0; 942439#L574-12 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 942438#L575-12 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 942437#L1366-36 assume !(0 != activate_threads_~tmp___1~0); 942436#L1366-38 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 942435#L582-36 assume !(1 == ~t3_pc~0); 942434#L582-38 is_transmit3_triggered_~__retres1~3 := 0; 942433#L593-12 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 942432#L594-12 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 942431#L1374-36 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 942430#L1374-38 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 942429#L601-36 assume 1 == ~t4_pc~0; 942428#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 942426#L612-12 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 942425#L613-12 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 942424#L1382-36 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 942423#L1382-38 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 942422#L620-36 assume !(1 == ~t5_pc~0); 942421#L620-38 is_transmit5_triggered_~__retres1~5 := 0; 942420#L631-12 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 942419#L632-12 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 942418#L1390-36 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 942417#L1390-38 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 942416#L639-36 assume !(1 == ~t6_pc~0); 942415#L639-38 is_transmit6_triggered_~__retres1~6 := 0; 942413#L650-12 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 942411#L651-12 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 942409#L1398-36 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 942407#L1398-38 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 942405#L658-36 assume 1 == ~t7_pc~0; 942402#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 942399#L669-12 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 942396#L670-12 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 942393#L1406-36 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 942391#L1406-38 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 942389#L677-36 assume !(1 == ~t8_pc~0); 942387#L677-38 is_transmit8_triggered_~__retres1~8 := 0; 942385#L688-12 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 942383#L689-12 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 942381#L1414-36 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 942379#L1414-38 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 942377#L696-36 assume 1 == ~t9_pc~0; 942374#L697-12 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 942372#L707-12 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 942370#L708-12 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 942368#L1422-36 assume !(0 != activate_threads_~tmp___8~0); 942366#L1422-38 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 942364#L715-36 assume !(1 == ~t10_pc~0); 942361#L715-38 is_transmit10_triggered_~__retres1~10 := 0; 942358#L726-12 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 942355#L727-12 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 942352#L1430-36 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 942349#L1430-38 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 942346#L734-36 assume 1 == ~t11_pc~0; 942342#L735-12 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 942339#L745-12 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 942336#L746-12 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 942333#L1438-36 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 942330#L1438-38 assume 1 == ~M_E~0;~M_E~0 := 2; 942327#L1213-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 942324#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 942320#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 942316#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 942313#L1233-3 assume !(1 == ~T5_E~0); 942310#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 942307#L1243-3 assume !(1 == ~T7_E~0); 942304#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 942301#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 942298#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 942295#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 942292#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 942289#L1273-3 assume !(1 == ~E_2~0); 942285#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 942281#L1283-3 assume !(1 == ~E_4~0); 942276#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 942271#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 942267#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 942262#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 942258#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 942254#L1313-3 assume !(1 == ~E_10~0); 942248#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 941679#L1323-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 941500#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 941489#L891-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 941482#L892-1 start_simulation_#t~ret33 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 941475#L1663 assume !(0 == start_simulation_~tmp~3); 941473#L1663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret32, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 941349#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 941338#L891-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 941328#L892-2 stop_simulation_#t~ret32 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret32;havoc stop_simulation_#t~ret32; 941322#L1618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 941312#L1625 stop_simulation_#res := stop_simulation_~__retres2~0; 941303#L1626 start_simulation_#t~ret34 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret34;havoc start_simulation_#t~ret34; 941294#L1676 assume !(0 != start_simulation_~tmp___0~1); 785281#L1644-1 [2021-11-07 07:22:47,399 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:47,400 INFO L85 PathProgramCache]: Analyzing trace with hash 1475571577, now seen corresponding path program 1 times [2021-11-07 07:22:47,400 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:47,400 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [633989403] [2021-11-07 07:22:47,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:47,400 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:47,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:22:47,416 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-07 07:22:47,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-07 07:22:47,527 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-07 07:22:47,528 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:22:47,528 INFO L85 PathProgramCache]: Analyzing trace with hash 1257628857, now seen corresponding path program 1 times [2021-11-07 07:22:47,529 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:22:47,529 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2013475322] [2021-11-07 07:22:47,529 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:22:47,529 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:22:47,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:22:47,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:22:47,573 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:22:47,573 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2013475322] [2021-11-07 07:22:47,573 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2013475322] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:22:47,573 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:22:47,574 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 07:22:47,574 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1075699942] [2021-11-07 07:22:47,574 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:22:47,575 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:22:47,575 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:22:47,575 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:22:47,576 INFO L87 Difference]: Start difference. First operand 223952 states and 313640 transitions. cyclomatic complexity: 89720 Second operand has 3 states, 3 states have (on average 47.0) internal successors, (141), 3 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:22:49,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:22:49,949 INFO L93 Difference]: Finished difference Result 421466 states and 584679 transitions. [2021-11-07 07:22:49,950 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:22:49,950 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 421466 states and 584679 transitions. [2021-11-07 07:22:53,293 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 420910 [2021-11-07 07:22:54,311 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 421466 states to 421466 states and 584679 transitions. [2021-11-07 07:22:54,311 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 421466 [2021-11-07 07:22:54,481 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 421466 [2021-11-07 07:22:54,481 INFO L73 IsDeterministic]: Start isDeterministic. Operand 421466 states and 584679 transitions. [2021-11-07 07:22:54,640 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 07:22:54,640 INFO L681 BuchiCegarLoop]: Abstraction has 421466 states and 584679 transitions. [2021-11-07 07:22:54,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 421466 states and 584679 transitions. [2021-11-07 07:22:59,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 421466 to 421385. [2021-11-07 07:22:59,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 421385 states, 421385 states have (on average 1.3873251302253284) internal successors, (584598), 421384 states have internal predecessors, (584598), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:23:01,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 421385 states to 421385 states and 584598 transitions. [2021-11-07 07:23:01,905 INFO L704 BuchiCegarLoop]: Abstraction has 421385 states and 584598 transitions. [2021-11-07 07:23:01,905 INFO L587 BuchiCegarLoop]: Abstraction has 421385 states and 584598 transitions. [2021-11-07 07:23:01,905 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-07 07:23:01,905 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 421385 states and 584598 transitions. [2021-11-07 07:23:03,224 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 420829 [2021-11-07 07:23:03,224 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 07:23:03,224 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 07:23:03,227 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:23:03,228 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 07:23:03,228 INFO L791 eck$LassoCheckResult]: Stem: 1430210#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2; 1430211#L-1 havoc main_#res;havoc main_~__retres1~13;havoc main_~__retres1~13;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1430225#L1607 havoc start_simulation_#t~ret33, start_simulation_#t~ret34, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1430226#L754 assume 1 == ~m_i~0;~m_st~0 := 0; 1430391#L761-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1429809#L766-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1429721#L771-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1429437#L776-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1429082#L781-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1429083#L786-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1429130#L791-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1429131#L796-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1430080#L801-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1430081#L806-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1430128#L811-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1429546#L816-1 assume !(0 == ~M_E~0); 1429547#L1090-1 assume !(0 == ~T1_E~0); 1430639#L1095-1 assume !(0 == ~T2_E~0); 1430295#L1100-1 assume !(0 == ~T3_E~0); 1430296#L1105-1 assume !(0 == ~T4_E~0); 1429354#L1110-1 assume !(0 == ~T5_E~0); 1429355#L1115-1 assume !(0 == ~T6_E~0); 1429759#L1120-1 assume !(0 == ~T7_E~0); 1430052#L1125-1 assume !(0 == ~T8_E~0); 1430780#L1130-1 assume !(0 == ~T9_E~0); 1430323#L1135-1 assume !(0 == ~T10_E~0); 1429554#L1140-1 assume !(0 == ~T11_E~0); 1429555#L1145-1 assume !(0 == ~E_1~0); 1430242#L1150-1 assume !(0 == ~E_2~0); 1429733#L1155-1 assume !(0 == ~E_3~0); 1429734#L1160-1 assume 0 == ~E_4~0;~E_4~0 := 1; 1430769#L1165-1 assume !(0 == ~E_5~0); 1430583#L1170-1 assume !(0 == ~E_6~0); 1430584#L1175-1 assume !(0 == ~E_7~0); 1430924#L1180-1 assume !(0 == ~E_8~0); 1430923#L1185-1 assume !(0 == ~E_9~0); 1430922#L1190-1 assume !(0 == ~E_10~0); 1430921#L1195-1 assume !(0 == ~E_11~0); 1430920#L1200-1 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1429754#L525 assume !(1 == ~m_pc~0); 1429167#L525-2 is_master_triggered_~__retres1~0 := 0; 1429168#L536 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1429913#L537 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1429914#L1350 assume !(0 != activate_threads_~tmp~1); 1429535#L1350-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1429536#L544 assume !(1 == ~t1_pc~0); 1429755#L544-2 is_transmit1_triggered_~__retres1~1 := 0; 1429756#L555 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1430239#L556 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1430861#L1358 assume !(0 != activate_threads_~tmp___0~0); 1430018#L1358-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1430019#L563 assume !(1 == ~t2_pc~0); 1430266#L563-2 is_transmit2_triggered_~__retres1~2 := 0; 1429190#L574 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1429191#L575 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1429618#L1366 assume !(0 != activate_threads_~tmp___1~0); 1429619#L1366-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1430908#L582 assume !(1 == ~t3_pc~0); 1430781#L582-2 is_transmit3_triggered_~__retres1~3 := 0; 1430782#L593 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1430832#L594 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1430833#L1374 assume !(0 != activate_threads_~tmp___2~0); 1430907#L1374-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1430804#L601 assume !(1 == ~t4_pc~0); 1430342#L601-2 is_transmit4_triggered_~__retres1~4 := 0; 1429760#L612 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1429761#L613 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1430255#L1382 assume !(0 != activate_threads_~tmp___3~0); 1430256#L1382-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1430680#L620 assume !(1 == ~t5_pc~0); 1430681#L620-2 is_transmit5_triggered_~__retres1~5 := 0; 1430118#L631 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1430119#L632 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1430856#L1390 assume !(0 != activate_threads_~tmp___4~0); 1430857#L1390-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1430787#L639 assume !(1 == ~t6_pc~0); 1430788#L639-2 is_transmit6_triggered_~__retres1~6 := 0; 1429652#L650 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1429653#L651 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1430715#L1398 assume !(0 != activate_threads_~tmp___5~0); 1429766#L1398-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1429767#L658 assume !(1 == ~t7_pc~0); 1430471#L658-2 is_transmit7_triggered_~__retres1~7 := 0; 1430899#L669 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1430897#L670 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1430894#L1406 assume !(0 != activate_threads_~tmp___6~0); 1430893#L1406-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1430892#L677 assume !(1 == ~t8_pc~0); 1429568#L677-2 is_transmit8_triggered_~__retres1~8 := 0; 1429569#L688 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1430891#L689 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1429611#L1414 assume !(0 != activate_threads_~tmp___7~0); 1429612#L1414-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1430374#L696 assume !(1 == ~t9_pc~0); 1430498#L696-2 is_transmit9_triggered_~__retres1~9 := 0; 1430137#L707 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1430138#L708 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1430262#L1422 assume !(0 != activate_threads_~tmp___8~0); 1430887#L1422-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1430629#L715 assume !(1 == ~t10_pc~0); 1430310#L715-2 is_transmit10_triggered_~__retres1~10 := 0; 1430885#L726 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1430021#L727 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1430022#L1430 assume !(0 != activate_threads_~tmp___9~0); 1429885#L1430-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1429329#L734 assume !(1 == ~t11_pc~0); 1429330#L734-2 is_transmit11_triggered_~__retres1~11 := 0; 1429822#L745 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1429900#L746 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1429072#L1438 assume !(0 != activate_threads_~tmp___10~0); 1429073#L1438-2 assume !(1 == ~M_E~0); 1430876#L1213-1 assume !(1 == ~T1_E~0); 1430875#L1218-1 assume !(1 == ~T2_E~0); 1430874#L1223-1 assume !(1 == ~T3_E~0); 1430873#L1228-1 assume !(1 == ~T4_E~0); 1430719#L1233-1 assume !(1 == ~T5_E~0); 1430720#L1238-1 assume !(1 == ~T6_E~0); 1430872#L1243-1 assume !(1 == ~T7_E~0); 1430811#L1248-1 assume !(1 == ~T8_E~0); 1430306#L1253-1 assume !(1 == ~T9_E~0); 1430307#L1258-1 assume !(1 == ~T10_E~0); 1430280#L1263-1 assume !(1 == ~T11_E~0); 1430281#L1268-1 assume !(1 == ~E_1~0); 1430075#L1273-1 assume !(1 == ~E_2~0); 1430076#L1278-1 assume !(1 == ~E_3~0); 1429650#L1283-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1429651#L1288-1 assume !(1 == ~E_5~0); 1430438#L1293-1 assume !(1 == ~E_6~0); 1430382#L1298-1 assume !(1 == ~E_7~0); 1430104#L1303-1 assume !(1 == ~E_8~0); 1429661#L1308-1 assume !(1 == ~E_9~0); 1429560#L1313-1 assume !(1 == ~E_10~0); 1429561#L1318-1 assume !(1 == ~E_11~0); 1430662#L1644-1 [2021-11-07 07:23:03,229 INFO L793 eck$LassoCheckResult]: Loop: 1430662#L1644-1 assume !false; 1430770#L1645 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_~tmp~0;havoc eval_~tmp~0; 1843624#L1065 assume !false; 1843623#L902 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 1842832#L829 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 1804133#L891 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 1737542#L892 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 1737540#L906 assume !(0 != eval_~tmp~0); 1737541#L1080 start_simulation_~kernel_st~0 := 2; 1849641#L754-1 start_simulation_~kernel_st~0 := 3; 1849639#L1090-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1849637#L1090-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1849636#L1095-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1849635#L1100-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1849634#L1105-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1849633#L1110-3 assume !(0 == ~T5_E~0); 1849632#L1115-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1849630#L1120-3 assume !(0 == ~T7_E~0); 1849628#L1125-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1849626#L1130-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1849624#L1135-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1849622#L1140-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1849620#L1145-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1849618#L1150-3 assume !(0 == ~E_2~0); 1849616#L1155-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1849614#L1160-3 assume !(0 == ~E_4~0); 1849612#L1165-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1849610#L1170-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1849608#L1175-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1849606#L1180-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1849604#L1185-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1849602#L1190-3 assume !(0 == ~E_10~0); 1849600#L1195-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1849598#L1200-3 havoc activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1849597#L525-36 assume !(1 == ~m_pc~0); 1849595#L525-38 is_master_triggered_~__retres1~0 := 0; 1849593#L536-12 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1849591#L537-12 activate_threads_#t~ret20 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1849589#L1350-36 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1849587#L1350-38 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1849585#L544-36 assume !(1 == ~t1_pc~0); 1849583#L544-38 is_transmit1_triggered_~__retres1~1 := 0; 1849581#L555-12 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1849579#L556-12 activate_threads_#t~ret21 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1849577#L1358-36 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1849575#L1358-38 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1849573#L563-36 assume !(1 == ~t2_pc~0); 1849570#L563-38 is_transmit2_triggered_~__retres1~2 := 0; 1849568#L574-12 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1849566#L575-12 activate_threads_#t~ret22 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1849564#L1366-36 assume !(0 != activate_threads_~tmp___1~0); 1849562#L1366-38 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1849560#L582-36 assume !(1 == ~t3_pc~0); 1849558#L582-38 is_transmit3_triggered_~__retres1~3 := 0; 1849555#L593-12 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1849553#L594-12 activate_threads_#t~ret23 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1849551#L1374-36 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1829793#L1374-38 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1829686#L601-36 assume 1 == ~t4_pc~0; 1829685#L602-12 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1829556#L612-12 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1829555#L613-12 activate_threads_#t~ret24 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1829554#L1382-36 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1829553#L1382-38 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1829552#L620-36 assume !(1 == ~t5_pc~0); 1829551#L620-38 is_transmit5_triggered_~__retres1~5 := 0; 1829550#L631-12 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1829548#L632-12 activate_threads_#t~ret25 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1829547#L1390-36 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1829546#L1390-38 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1829545#L639-36 assume !(1 == ~t6_pc~0); 1829543#L639-38 is_transmit6_triggered_~__retres1~6 := 0; 1829541#L650-12 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1829539#L651-12 activate_threads_#t~ret26 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1829537#L1398-36 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1829535#L1398-38 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1829533#L658-36 assume 1 == ~t7_pc~0; 1829531#L659-12 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 1829532#L669-12 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1829549#L670-12 activate_threads_#t~ret27 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1829522#L1406-36 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1829520#L1406-38 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1829518#L677-36 assume !(1 == ~t8_pc~0); 1829516#L677-38 is_transmit8_triggered_~__retres1~8 := 0; 1829514#L688-12 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1829512#L689-12 activate_threads_#t~ret28 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1829510#L1414-36 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 1829507#L1414-38 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1829505#L696-36 assume !(1 == ~t9_pc~0); 1829503#L696-38 is_transmit9_triggered_~__retres1~9 := 0; 1829500#L707-12 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1829498#L708-12 activate_threads_#t~ret29 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1829496#L1422-36 assume !(0 != activate_threads_~tmp___8~0); 1829494#L1422-38 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1829492#L715-36 assume !(1 == ~t10_pc~0); 1829489#L715-38 is_transmit10_triggered_~__retres1~10 := 0; 1829487#L726-12 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1829485#L727-12 activate_threads_#t~ret30 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1829483#L1430-36 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 1829481#L1430-38 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1829479#L734-36 assume !(1 == ~t11_pc~0); 1829477#L734-38 is_transmit11_triggered_~__retres1~11 := 0; 1829474#L745-12 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1829473#L746-12 activate_threads_#t~ret31 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1829471#L1438-36 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 1829469#L1438-38 assume 1 == ~M_E~0;~M_E~0 := 2; 1829467#L1213-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1829465#L1218-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1829462#L1223-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1829460#L1228-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1829458#L1233-3 assume !(1 == ~T5_E~0); 1829456#L1238-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1829454#L1243-3 assume !(1 == ~T7_E~0); 1829452#L1248-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1829450#L1253-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1829448#L1258-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1829446#L1263-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1829444#L1268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1829442#L1273-3 assume !(1 == ~E_2~0); 1829440#L1278-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1829437#L1283-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1829434#L1288-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1829432#L1293-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1829430#L1298-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1829428#L1303-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1829427#L1308-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1829425#L1313-3 assume !(1 == ~E_10~0); 1829423#L1318-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1429477#L1323-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 1429478#L829-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 1429414#L891-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 1429832#L892-1 start_simulation_#t~ret33 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret33;havoc start_simulation_#t~ret33; 1430348#L1663 assume !(0 == start_simulation_~tmp~3); 1430835#L1663-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret32, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~12;havoc exists_runnable_thread_~__retres1~12; 1849985#L829-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12 := 1; 1849979#L891-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~12; 1849977#L892-2 stop_simulation_#t~ret32 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret32;havoc stop_simulation_#t~ret32; 1849976#L1618 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1849974#L1625 stop_simulation_#res := stop_simulation_~__retres2~0; 1848809#L1626 start_simulation_#t~ret34 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret34;havoc start_simulation_#t~ret34; 1430661#L1676 assume !(0 != start_simulation_~tmp___0~1); 1430662#L1644-1 [2021-11-07 07:23:03,230 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:23:03,230 INFO L85 PathProgramCache]: Analyzing trace with hash 23344953, now seen corresponding path program 1 times [2021-11-07 07:23:03,230 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:23:03,230 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021458540] [2021-11-07 07:23:03,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:23:03,231 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:23:03,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:23:03,265 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:23:03,266 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:23:03,266 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1021458540] [2021-11-07 07:23:03,266 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1021458540] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:23:03,266 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:23:03,266 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 07:23:03,267 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1727707527] [2021-11-07 07:23:03,267 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 07:23:03,268 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 07:23:03,268 INFO L85 PathProgramCache]: Analyzing trace with hash 75973817, now seen corresponding path program 1 times [2021-11-07 07:23:03,268 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 07:23:03,268 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [549597918] [2021-11-07 07:23:03,268 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 07:23:03,269 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 07:23:03,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 07:23:03,313 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 07:23:03,314 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 07:23:03,314 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [549597918] [2021-11-07 07:23:03,314 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [549597918] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 07:23:03,314 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 07:23:03,315 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-07 07:23:03,315 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [74713007] [2021-11-07 07:23:03,315 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 07:23:03,316 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 07:23:03,316 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 07:23:03,316 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 07:23:03,317 INFO L87 Difference]: Start difference. First operand 421385 states and 584598 transitions. cyclomatic complexity: 163245 Second operand has 3 states, 3 states have (on average 44.333333333333336) internal successors, (133), 2 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 07:23:05,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 07:23:05,366 INFO L93 Difference]: Finished difference Result 223952 states and 310770 transitions. [2021-11-07 07:23:05,367 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 07:23:05,367 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 223952 states and 310770 transitions. [2021-11-07 07:23:06,306 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 223655