./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.13.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 47ea0209 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0907b326-10ea-41c4-98bf-47b04eb55339/bin/uautomizer-AkOaLMaTGY/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0907b326-10ea-41c4-98bf-47b04eb55339/bin/uautomizer-AkOaLMaTGY/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0907b326-10ea-41c4-98bf-47b04eb55339/bin/uautomizer-AkOaLMaTGY/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0907b326-10ea-41c4-98bf-47b04eb55339/bin/uautomizer-AkOaLMaTGY/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.13.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0907b326-10ea-41c4-98bf-47b04eb55339/bin/uautomizer-AkOaLMaTGY/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0907b326-10ea-41c4-98bf-47b04eb55339/bin/uautomizer-AkOaLMaTGY --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 5975f0f3825b3a6653676f33bd69d14e1e58fcf0306bfb5508ab91dc8951d6c4 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-47ea020 [2021-11-07 08:01:34,371 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-07 08:01:34,373 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-07 08:01:34,408 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-07 08:01:34,409 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-07 08:01:34,410 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-07 08:01:34,412 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-07 08:01:34,415 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-07 08:01:34,417 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-07 08:01:34,418 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-07 08:01:34,419 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-07 08:01:34,421 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-07 08:01:34,422 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-07 08:01:34,423 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-07 08:01:34,425 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-07 08:01:34,427 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-07 08:01:34,428 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-07 08:01:34,429 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-07 08:01:34,432 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-07 08:01:34,435 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-07 08:01:34,438 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-07 08:01:34,440 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-07 08:01:34,441 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-07 08:01:34,443 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-07 08:01:34,447 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-07 08:01:34,447 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-07 08:01:34,448 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-07 08:01:34,449 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-07 08:01:34,450 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-07 08:01:34,451 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-07 08:01:34,452 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-07 08:01:34,453 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-07 08:01:34,454 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-07 08:01:34,455 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-07 08:01:34,456 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-07 08:01:34,457 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-07 08:01:34,458 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-07 08:01:34,459 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-07 08:01:34,459 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-07 08:01:34,460 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-07 08:01:34,461 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-07 08:01:34,463 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0907b326-10ea-41c4-98bf-47b04eb55339/bin/uautomizer-AkOaLMaTGY/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-07 08:01:34,490 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-07 08:01:34,491 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-07 08:01:34,491 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-07 08:01:34,492 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-07 08:01:34,493 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-07 08:01:34,493 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-07 08:01:34,493 INFO L138 SettingsManager]: * Use SBE=true [2021-11-07 08:01:34,494 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-07 08:01:34,494 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-07 08:01:34,494 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-07 08:01:34,495 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-07 08:01:34,495 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-07 08:01:34,495 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-07 08:01:34,495 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-07 08:01:34,496 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-07 08:01:34,496 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-07 08:01:34,496 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-07 08:01:34,497 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-07 08:01:34,497 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-07 08:01:34,497 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-07 08:01:34,497 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-07 08:01:34,498 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-07 08:01:34,498 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-07 08:01:34,498 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-07 08:01:34,498 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-07 08:01:34,499 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-07 08:01:34,499 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-07 08:01:34,499 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-07 08:01:34,499 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-07 08:01:34,500 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-07 08:01:34,500 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-07 08:01:34,500 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-07 08:01:34,501 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-07 08:01:34,502 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0907b326-10ea-41c4-98bf-47b04eb55339/bin/uautomizer-AkOaLMaTGY/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0907b326-10ea-41c4-98bf-47b04eb55339/bin/uautomizer-AkOaLMaTGY Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 5975f0f3825b3a6653676f33bd69d14e1e58fcf0306bfb5508ab91dc8951d6c4 [2021-11-07 08:01:34,769 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-07 08:01:34,792 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-07 08:01:34,795 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-07 08:01:34,796 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-07 08:01:34,797 INFO L275 PluginConnector]: CDTParser initialized [2021-11-07 08:01:34,798 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0907b326-10ea-41c4-98bf-47b04eb55339/bin/uautomizer-AkOaLMaTGY/../../sv-benchmarks/c/systemc/transmitter.13.cil.c [2021-11-07 08:01:34,881 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0907b326-10ea-41c4-98bf-47b04eb55339/bin/uautomizer-AkOaLMaTGY/data/1d153db06/063c25959ef542839af3b95c56eaf514/FLAGb78c5bd32 [2021-11-07 08:01:35,532 INFO L306 CDTParser]: Found 1 translation units. [2021-11-07 08:01:35,535 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0907b326-10ea-41c4-98bf-47b04eb55339/sv-benchmarks/c/systemc/transmitter.13.cil.c [2021-11-07 08:01:35,559 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0907b326-10ea-41c4-98bf-47b04eb55339/bin/uautomizer-AkOaLMaTGY/data/1d153db06/063c25959ef542839af3b95c56eaf514/FLAGb78c5bd32 [2021-11-07 08:01:35,803 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0907b326-10ea-41c4-98bf-47b04eb55339/bin/uautomizer-AkOaLMaTGY/data/1d153db06/063c25959ef542839af3b95c56eaf514 [2021-11-07 08:01:35,810 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-07 08:01:35,812 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-07 08:01:35,814 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-07 08:01:35,814 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-07 08:01:35,818 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-07 08:01:35,819 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.11 08:01:35" (1/1) ... [2021-11-07 08:01:35,820 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@11fe3bc8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:01:35, skipping insertion in model container [2021-11-07 08:01:35,820 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.11 08:01:35" (1/1) ... [2021-11-07 08:01:35,828 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-07 08:01:35,892 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-07 08:01:36,118 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0907b326-10ea-41c4-98bf-47b04eb55339/sv-benchmarks/c/systemc/transmitter.13.cil.c[706,719] [2021-11-07 08:01:36,315 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-07 08:01:36,330 INFO L203 MainTranslator]: Completed pre-run [2021-11-07 08:01:36,352 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0907b326-10ea-41c4-98bf-47b04eb55339/sv-benchmarks/c/systemc/transmitter.13.cil.c[706,719] [2021-11-07 08:01:36,499 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-07 08:01:36,541 INFO L208 MainTranslator]: Completed translation [2021-11-07 08:01:36,543 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:01:36 WrapperNode [2021-11-07 08:01:36,543 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-07 08:01:36,546 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-07 08:01:36,546 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-07 08:01:36,546 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-07 08:01:36,555 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:01:36" (1/1) ... [2021-11-07 08:01:36,588 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:01:36" (1/1) ... [2021-11-07 08:01:36,770 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-07 08:01:36,781 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-07 08:01:36,781 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-07 08:01:36,781 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-07 08:01:36,792 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:01:36" (1/1) ... [2021-11-07 08:01:36,792 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:01:36" (1/1) ... [2021-11-07 08:01:36,809 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:01:36" (1/1) ... [2021-11-07 08:01:36,810 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:01:36" (1/1) ... [2021-11-07 08:01:36,890 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:01:36" (1/1) ... [2021-11-07 08:01:36,951 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:01:36" (1/1) ... [2021-11-07 08:01:36,963 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:01:36" (1/1) ... [2021-11-07 08:01:36,984 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-07 08:01:36,985 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-07 08:01:36,986 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-07 08:01:36,986 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-07 08:01:36,988 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:01:36" (1/1) ... [2021-11-07 08:01:36,998 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-07 08:01:37,012 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0907b326-10ea-41c4-98bf-47b04eb55339/bin/uautomizer-AkOaLMaTGY/z3 [2021-11-07 08:01:37,033 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0907b326-10ea-41c4-98bf-47b04eb55339/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-07 08:01:37,053 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_0907b326-10ea-41c4-98bf-47b04eb55339/bin/uautomizer-AkOaLMaTGY/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-07 08:01:37,093 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-07 08:01:37,094 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-07 08:01:37,094 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-07 08:01:37,094 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-07 08:01:40,159 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-07 08:01:40,160 INFO L299 CfgBuilder]: Removed 589 assume(true) statements. [2021-11-07 08:01:40,165 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.11 08:01:40 BoogieIcfgContainer [2021-11-07 08:01:40,166 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-07 08:01:40,169 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-07 08:01:40,170 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-07 08:01:40,174 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-07 08:01:40,175 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-07 08:01:40,175 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 07.11 08:01:35" (1/3) ... [2021-11-07 08:01:40,177 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@b7198ef and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.11 08:01:40, skipping insertion in model container [2021-11-07 08:01:40,177 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-07 08:01:40,177 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.11 08:01:36" (2/3) ... [2021-11-07 08:01:40,178 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@b7198ef and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 07.11 08:01:40, skipping insertion in model container [2021-11-07 08:01:40,178 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-07 08:01:40,178 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.11 08:01:40" (3/3) ... [2021-11-07 08:01:40,180 INFO L389 chiAutomizerObserver]: Analyzing ICFG transmitter.13.cil.c [2021-11-07 08:01:40,243 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-07 08:01:40,243 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-07 08:01:40,243 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-07 08:01:40,244 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-07 08:01:40,244 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-07 08:01:40,244 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-07 08:01:40,244 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-07 08:01:40,244 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-07 08:01:40,313 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1885 states, 1884 states have (on average 1.5079617834394905) internal successors, (2841), 1884 states have internal predecessors, (2841), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:40,440 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1712 [2021-11-07 08:01:40,443 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:40,443 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:40,463 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:40,464 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:40,464 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-07 08:01:40,469 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1885 states, 1884 states have (on average 1.5079617834394905) internal successors, (2841), 1884 states have internal predecessors, (2841), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:40,524 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1712 [2021-11-07 08:01:40,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:40,525 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:40,532 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:40,533 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:40,544 INFO L791 eck$LassoCheckResult]: Stem: 457#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1803#L-1true havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 351#L1855true havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 201#L874true assume !(1 == ~m_i~0);~m_st~0 := 2; 769#L881-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1388#L886-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 272#L891-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1379#L896-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 541#L901-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 435#L906-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 787#L911-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 308#L916-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 550#L921-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 676#L926-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 795#L931-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 824#L936-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 910#L941-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 315#L946-1true assume !(0 == ~M_E~0); 673#L1258-1true assume !(0 == ~T1_E~0); 486#L1263-1true assume !(0 == ~T2_E~0); 702#L1268-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1343#L1273-1true assume !(0 == ~T4_E~0); 1722#L1278-1true assume !(0 == ~T5_E~0); 1138#L1283-1true assume !(0 == ~T6_E~0); 1752#L1288-1true assume !(0 == ~T7_E~0); 1545#L1293-1true assume !(0 == ~T8_E~0); 1516#L1298-1true assume !(0 == ~T9_E~0); 1361#L1303-1true assume !(0 == ~T10_E~0); 215#L1308-1true assume 0 == ~T11_E~0;~T11_E~0 := 1; 186#L1313-1true assume !(0 == ~T12_E~0); 1807#L1318-1true assume !(0 == ~T13_E~0); 189#L1323-1true assume !(0 == ~E_1~0); 277#L1328-1true assume !(0 == ~E_2~0); 1761#L1333-1true assume !(0 == ~E_3~0); 963#L1338-1true assume !(0 == ~E_4~0); 1098#L1343-1true assume !(0 == ~E_5~0); 1626#L1348-1true assume 0 == ~E_6~0;~E_6~0 := 1; 1643#L1353-1true assume !(0 == ~E_7~0); 718#L1358-1true assume !(0 == ~E_8~0); 989#L1363-1true assume !(0 == ~E_9~0); 1050#L1368-1true assume !(0 == ~E_10~0); 106#L1373-1true assume !(0 == ~E_11~0); 485#L1378-1true assume !(0 == ~E_12~0); 250#L1383-1true assume !(0 == ~E_13~0); 1087#L1388-1true havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 721#L607true assume 1 == ~m_pc~0; 999#L608true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1094#L618true is_master_triggered_#res := is_master_triggered_~__retres1~0; 1603#L619true activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 659#L1560true assume !(0 != activate_threads_~tmp~1); 1699#L1560-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 196#L626true assume 1 == ~t1_pc~0; 1697#L627true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 338#L637true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 437#L638true activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1872#L1568true assume !(0 != activate_threads_~tmp___0~0); 147#L1568-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1314#L645true assume !(1 == ~t2_pc~0); 183#L645-2true is_transmit2_triggered_~__retres1~2 := 0; 1280#L656true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 577#L657true activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1864#L1576true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 644#L1576-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1680#L664true assume 1 == ~t3_pc~0; 1609#L665true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 67#L675true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1112#L676true activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 415#L1584true assume !(0 != activate_threads_~tmp___2~0); 1397#L1584-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1604#L683true assume !(1 == ~t4_pc~0); 976#L683-2true is_transmit4_triggered_~__retres1~4 := 0; 777#L694true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 802#L695true activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1670#L1592true assume !(0 != activate_threads_~tmp___3~0); 921#L1592-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 607#L702true assume 1 == ~t5_pc~0; 1660#L703true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 915#L713true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1321#L714true activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1369#L1600true assume !(0 != activate_threads_~tmp___4~0); 1218#L1600-2true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 91#L721true assume !(1 == ~t6_pc~0); 78#L721-2true is_transmit6_triggered_~__retres1~6 := 0; 161#L732true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 552#L733true activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 419#L1608true assume !(0 != activate_threads_~tmp___5~0); 1501#L1608-2true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 857#L740true assume 1 == ~t7_pc~0; 117#L741true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 21#L751true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 748#L752true activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 16#L1616true assume !(0 != activate_threads_~tmp___6~0); 753#L1616-2true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 383#L759true assume !(1 == ~t8_pc~0); 1351#L759-2true is_transmit8_triggered_~__retres1~8 := 0; 1811#L770true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 913#L771true activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1070#L1624true assume !(0 != activate_threads_~tmp___7~0); 1646#L1624-2true havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1544#L778true assume 1 == ~t9_pc~0; 1319#L779true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 1253#L789true is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 74#L790true activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 36#L1632true assume !(0 != activate_threads_~tmp___8~0); 725#L1632-2true havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 203#L797true assume 1 == ~t10_pc~0; 1570#L798true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 1285#L808true is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1164#L809true activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 484#L1640true assume !(0 != activate_threads_~tmp___9~0); 689#L1640-2true havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1368#L816true assume !(1 == ~t11_pc~0); 198#L816-2true is_transmit11_triggered_~__retres1~11 := 0; 581#L827true is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 459#L828true activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 424#L1648true assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 1488#L1648-2true havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 794#L835true assume 1 == ~t12_pc~0; 698#L836true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 151#L846true is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 222#L847true activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 1755#L1656true assume !(0 != activate_threads_~tmp___11~0); 523#L1656-2true havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 1420#L854true assume !(1 == ~t13_pc~0); 309#L854-2true is_transmit13_triggered_~__retres1~13 := 0; 335#L865true is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 1068#L866true activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 160#L1664true assume !(0 != activate_threads_~tmp___12~0); 1211#L1664-2true assume !(1 == ~M_E~0); 634#L1401-1true assume !(1 == ~T1_E~0); 1221#L1406-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 848#L1411-1true assume !(1 == ~T3_E~0); 1588#L1416-1true assume !(1 == ~T4_E~0); 588#L1421-1true assume !(1 == ~T5_E~0); 307#L1426-1true assume !(1 == ~T6_E~0); 1004#L1431-1true assume !(1 == ~T7_E~0); 76#L1436-1true assume !(1 == ~T8_E~0); 736#L1441-1true assume !(1 == ~T9_E~0); 479#L1446-1true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1744#L1451-1true assume !(1 == ~T11_E~0); 1093#L1456-1true assume !(1 == ~T12_E~0); 735#L1461-1true assume !(1 == ~T13_E~0); 433#L1466-1true assume !(1 == ~E_1~0); 1739#L1471-1true assume !(1 == ~E_2~0); 1069#L1476-1true assume !(1 == ~E_3~0); 1293#L1481-1true assume !(1 == ~E_4~0); 1569#L1486-1true assume 1 == ~E_5~0;~E_5~0 := 2; 225#L1491-1true assume !(1 == ~E_6~0); 42#L1496-1true assume !(1 == ~E_7~0); 747#L1501-1true assume !(1 == ~E_8~0); 477#L1506-1true assume !(1 == ~E_9~0); 1027#L1511-1true assume !(1 == ~E_10~0); 450#L1516-1true assume !(1 == ~E_11~0); 14#L1521-1true assume !(1 == ~E_12~0); 41#L1526-1true assume 1 == ~E_13~0;~E_13~0 := 2; 46#L1892-1true [2021-11-07 08:01:40,548 INFO L793 eck$LassoCheckResult]: Loop: 46#L1892-1true assume !false; 1834#L1893true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 1490#L1233true assume !true; 82#L1248true start_simulation_~kernel_st~0 := 2; 796#L874-1true start_simulation_~kernel_st~0 := 3; 1377#L1258-2true assume 0 == ~M_E~0;~M_E~0 := 1; 712#L1258-4true assume !(0 == ~T1_E~0); 154#L1263-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1580#L1268-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1595#L1273-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1870#L1278-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1597#L1283-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 267#L1288-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1760#L1293-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1153#L1298-3true assume !(0 == ~T9_E~0); 1669#L1303-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1405#L1308-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1152#L1313-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 650#L1318-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 155#L1323-3true assume 0 == ~E_1~0;~E_1~0 := 1; 1281#L1328-3true assume 0 == ~E_2~0;~E_2~0 := 1; 1648#L1333-3true assume 0 == ~E_3~0;~E_3~0 := 1; 229#L1338-3true assume !(0 == ~E_4~0); 1044#L1343-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1517#L1348-3true assume 0 == ~E_6~0;~E_6~0 := 1; 1290#L1353-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1330#L1358-3true assume 0 == ~E_8~0;~E_8~0 := 1; 619#L1363-3true assume 0 == ~E_9~0;~E_9~0 := 1; 339#L1368-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1850#L1373-3true assume 0 == ~E_11~0;~E_11~0 := 1; 874#L1378-3true assume !(0 == ~E_12~0); 1437#L1383-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1085#L1388-3true havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1738#L607-42true assume !(1 == ~m_pc~0); 901#L607-44true is_master_triggered_~__retres1~0 := 0; 506#L618-14true is_master_triggered_#res := is_master_triggered_~__retres1~0; 1062#L619-14true activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 348#L1560-42true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 690#L1560-44true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1200#L626-42true assume !(1 == ~t1_pc~0); 408#L626-44true is_transmit1_triggered_~__retres1~1 := 0; 1448#L637-14true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 593#L638-14true activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1116#L1568-42true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 171#L1568-44true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1550#L645-42true assume 1 == ~t2_pc~0; 1393#L646-14true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1671#L656-14true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1233#L657-14true activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 279#L1576-42true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 24#L1576-44true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1637#L664-42true assume !(1 == ~t3_pc~0); 297#L664-44true is_transmit3_triggered_~__retres1~3 := 0; 1600#L675-14true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1451#L676-14true activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 823#L1584-42true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1005#L1584-44true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1759#L683-42true assume !(1 == ~t4_pc~0); 723#L683-44true is_transmit4_triggered_~__retres1~4 := 0; 831#L694-14true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1740#L695-14true activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1389#L1592-42true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1868#L1592-44true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1147#L702-42true assume 1 == ~t5_pc~0; 638#L703-14true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 583#L713-14true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1708#L714-14true activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1267#L1600-42true assume !(0 != activate_threads_~tmp___4~0); 33#L1600-44true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 115#L721-42true assume 1 == ~t6_pc~0; 124#L722-14true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 366#L732-14true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1596#L733-14true activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1564#L1608-42true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 466#L1608-44true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 377#L740-42true assume 1 == ~t7_pc~0; 1297#L741-14true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 555#L751-14true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 554#L752-14true activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 455#L1616-42true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 642#L1616-44true havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1861#L759-42true assume 1 == ~t8_pc~0; 536#L760-14true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 489#L770-14true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 665#L771-14true activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 543#L1624-42true assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 609#L1624-44true havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1158#L778-42true assume 1 == ~t9_pc~0; 497#L779-14true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 800#L789-14true is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1723#L790-14true activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 724#L1632-42true assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 1589#L1632-44true havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 772#L797-42true assume !(1 == ~t10_pc~0); 1034#L797-44true is_transmit10_triggered_~__retres1~10 := 0; 927#L808-14true is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1353#L809-14true activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1843#L1640-42true assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 801#L1640-44true havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1684#L816-42true assume !(1 == ~t11_pc~0); 346#L816-44true is_transmit11_triggered_~__retres1~11 := 0; 1819#L827-14true is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 287#L828-14true activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 482#L1648-42true assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 329#L1648-44true havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 580#L835-42true assume !(1 == ~t12_pc~0); 503#L835-44true is_transmit12_triggered_~__retres1~12 := 0; 1224#L846-14true is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 316#L847-14true activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 1806#L1656-42true assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 1217#L1656-44true havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 939#L854-42true assume 1 == ~t13_pc~0; 1753#L855-14true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 478#L865-14true is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 87#L866-14true activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 511#L1664-42true assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 432#L1664-44true assume !(1 == ~M_E~0); 1822#L1401-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 204#L1406-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 136#L1411-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1655#L1416-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 461#L1421-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1041#L1426-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 228#L1431-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 295#L1436-3true assume !(1 == ~T8_E~0); 17#L1441-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1130#L1446-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1121#L1451-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 517#L1456-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 311#L1461-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 1587#L1466-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1786#L1471-3true assume 1 == ~E_2~0;~E_2~0 := 2; 280#L1476-3true assume !(1 == ~E_3~0); 1662#L1481-3true assume 1 == ~E_4~0;~E_4~0 := 2; 510#L1486-3true assume 1 == ~E_5~0;~E_5~0 := 2; 294#L1491-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1458#L1496-3true assume 1 == ~E_7~0;~E_7~0 := 2; 540#L1501-3true assume 1 == ~E_8~0;~E_8~0 := 2; 1571#L1506-3true assume 1 == ~E_9~0;~E_9~0 := 2; 871#L1511-3true assume 1 == ~E_10~0;~E_10~0 := 2; 864#L1516-3true assume !(1 == ~E_11~0); 1693#L1521-3true assume 1 == ~E_12~0;~E_12~0 := 2; 622#L1526-3true assume 1 == ~E_13~0;~E_13~0 := 2; 959#L1531-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1810#L959-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1847#L1031-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 751#L1032-1true start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 490#L1911true assume !(0 == start_simulation_~tmp~3); 281#L1911-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 896#L959-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1014#L1031-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 833#L1032-2true stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 108#L1866true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 516#L1873true stop_simulation_#res := stop_simulation_~__retres2~0; 224#L1874true start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 1326#L1924true assume !(0 != start_simulation_~tmp___0~1); 46#L1892-1true [2021-11-07 08:01:40,556 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:40,556 INFO L85 PathProgramCache]: Analyzing trace with hash -57869955, now seen corresponding path program 1 times [2021-11-07 08:01:40,577 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:40,578 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2024686016] [2021-11-07 08:01:40,578 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:40,580 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:40,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:41,013 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:41,013 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:41,014 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2024686016] [2021-11-07 08:01:41,016 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2024686016] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:41,016 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:41,017 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:41,019 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [961513357] [2021-11-07 08:01:41,028 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:41,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:41,033 INFO L85 PathProgramCache]: Analyzing trace with hash -1156735866, now seen corresponding path program 1 times [2021-11-07 08:01:41,033 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:41,034 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1742251833] [2021-11-07 08:01:41,034 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:41,035 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:41,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:41,144 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:41,144 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:41,145 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1742251833] [2021-11-07 08:01:41,145 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1742251833] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:41,146 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:41,146 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 08:01:41,146 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1127814774] [2021-11-07 08:01:41,148 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:01:41,150 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:41,181 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 08:01:41,182 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 08:01:41,190 INFO L87 Difference]: Start difference. First operand has 1885 states, 1884 states have (on average 1.5079617834394905) internal successors, (2841), 1884 states have internal predecessors, (2841), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 51.666666666666664) internal successors, (155), 3 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:41,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:41,331 INFO L93 Difference]: Finished difference Result 1885 states and 2805 transitions. [2021-11-07 08:01:41,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 08:01:41,334 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1885 states and 2805 transitions. [2021-11-07 08:01:41,363 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:41,393 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1885 states to 1880 states and 2800 transitions. [2021-11-07 08:01:41,394 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1880 [2021-11-07 08:01:41,398 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1880 [2021-11-07 08:01:41,399 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1880 states and 2800 transitions. [2021-11-07 08:01:41,409 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:41,410 INFO L681 BuchiCegarLoop]: Abstraction has 1880 states and 2800 transitions. [2021-11-07 08:01:41,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1880 states and 2800 transitions. [2021-11-07 08:01:41,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1880 to 1880. [2021-11-07 08:01:41,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1880 states, 1880 states have (on average 1.4893617021276595) internal successors, (2800), 1879 states have internal predecessors, (2800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:41,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1880 states to 1880 states and 2800 transitions. [2021-11-07 08:01:41,534 INFO L704 BuchiCegarLoop]: Abstraction has 1880 states and 2800 transitions. [2021-11-07 08:01:41,534 INFO L587 BuchiCegarLoop]: Abstraction has 1880 states and 2800 transitions. [2021-11-07 08:01:41,534 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-07 08:01:41,534 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1880 states and 2800 transitions. [2021-11-07 08:01:41,551 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:41,552 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:41,552 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:41,558 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:41,559 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:41,560 INFO L791 eck$LassoCheckResult]: Stem: 4630#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 4631#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 4458#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4175#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 4176#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5060#L886-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4311#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4312#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4754#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4592#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4593#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4381#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4382#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4764#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4940#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5094#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5130#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4392#L946-1 assume !(0 == ~M_E~0); 4393#L1258-1 assume !(0 == ~T1_E~0); 4673#L1263-1 assume !(0 == ~T2_E~0); 4674#L1268-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4974#L1273-1 assume !(0 == ~T4_E~0); 5517#L1278-1 assume !(0 == ~T5_E~0); 5383#L1283-1 assume !(0 == ~T6_E~0); 5384#L1288-1 assume !(0 == ~T7_E~0); 5613#L1293-1 assume !(0 == ~T8_E~0); 5601#L1298-1 assume !(0 == ~T9_E~0); 5529#L1303-1 assume !(0 == ~T10_E~0); 4204#L1308-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4146#L1313-1 assume !(0 == ~T12_E~0); 4147#L1318-1 assume !(0 == ~T13_E~0); 4153#L1323-1 assume !(0 == ~E_1~0); 4154#L1328-1 assume !(0 == ~E_2~0); 4321#L1333-1 assume !(0 == ~E_3~0); 5261#L1338-1 assume !(0 == ~E_4~0); 5262#L1343-1 assume !(0 == ~E_5~0); 5357#L1348-1 assume 0 == ~E_6~0;~E_6~0 := 1; 5635#L1353-1 assume !(0 == ~E_7~0); 4993#L1358-1 assume !(0 == ~E_8~0); 4994#L1363-1 assume !(0 == ~E_9~0); 5277#L1368-1 assume !(0 == ~E_10~0); 3985#L1373-1 assume !(0 == ~E_11~0); 3986#L1378-1 assume !(0 == ~E_12~0); 4270#L1383-1 assume !(0 == ~E_13~0); 4271#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5000#L607 assume 1 == ~m_pc~0; 5001#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4344#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5355#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 4919#L1560 assume !(0 != activate_threads_~tmp~1); 4920#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4166#L626 assume 1 == ~t1_pc~0; 4167#L627 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4434#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4435#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 4596#L1568 assume !(0 != activate_threads_~tmp___0~0); 4066#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4067#L645 assume !(1 == ~t2_pc~0); 4139#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 4140#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4803#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 4804#L1576 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4895#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4896#L664 assume 1 == ~t3_pc~0; 5634#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3910#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3911#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 4563#L1584 assume !(0 != activate_threads_~tmp___2~0); 4564#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5544#L683 assume !(1 == ~t4_pc~0); 5116#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 5068#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5069#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 5103#L1592 assume !(0 != activate_threads_~tmp___3~0); 5223#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4844#L702 assume 1 == ~t5_pc~0; 4845#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4773#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5218#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 5504#L1600 assume !(0 != activate_threads_~tmp___4~0); 5447#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3958#L721 assume !(1 == ~t6_pc~0); 3932#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 3933#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4093#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 4570#L1608 assume !(0 != activate_threads_~tmp___5~0); 4571#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5161#L740 assume 1 == ~t7_pc~0; 4006#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 3818#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3819#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 3808#L1616 assume !(0 != activate_threads_~tmp___6~0); 3809#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4509#L759 assume !(1 == ~t8_pc~0); 4510#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 4539#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5216#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 5217#L1624 assume !(0 != activate_threads_~tmp___7~0); 5342#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 5612#L778 assume 1 == ~t9_pc~0; 5501#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 3984#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 3925#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 3852#L1632 assume !(0 != activate_threads_~tmp___8~0); 3853#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 4179#L797 assume 1 == ~t10_pc~0; 4180#L798 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 4298#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 5406#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 4671#L1640 assume !(0 != activate_threads_~tmp___9~0); 4672#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 4958#L816 assume !(1 == ~t11_pc~0); 3892#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 3891#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 4634#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 4577#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 4578#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 5093#L835 assume 1 == ~t12_pc~0; 4971#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 4051#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 4073#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 4214#L1656 assume !(0 != activate_threads_~tmp___11~0); 4727#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 4728#L854 assume !(1 == ~t13_pc~0); 4383#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 4384#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 4430#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 4091#L1664 assume !(0 != activate_threads_~tmp___12~0); 4092#L1664-2 assume !(1 == ~M_E~0); 4881#L1401-1 assume !(1 == ~T1_E~0); 4882#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5150#L1411-1 assume !(1 == ~T3_E~0); 5151#L1416-1 assume !(1 == ~T4_E~0); 4819#L1421-1 assume !(1 == ~T5_E~0); 4379#L1426-1 assume !(1 == ~T6_E~0); 4380#L1431-1 assume !(1 == ~T7_E~0); 3928#L1436-1 assume !(1 == ~T8_E~0); 3929#L1441-1 assume !(1 == ~T9_E~0); 4664#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4665#L1451-1 assume !(1 == ~T11_E~0); 5354#L1456-1 assume !(1 == ~T12_E~0); 5018#L1461-1 assume !(1 == ~T13_E~0); 4587#L1466-1 assume !(1 == ~E_1~0); 4588#L1471-1 assume !(1 == ~E_2~0); 5340#L1476-1 assume !(1 == ~E_3~0); 5341#L1481-1 assume !(1 == ~E_4~0); 5484#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 4219#L1491-1 assume !(1 == ~E_6~0); 3860#L1496-1 assume !(1 == ~E_7~0); 3861#L1501-1 assume !(1 == ~E_8~0); 4662#L1506-1 assume !(1 == ~E_9~0); 4663#L1511-1 assume !(1 == ~E_10~0); 4619#L1516-1 assume !(1 == ~E_11~0); 3804#L1521-1 assume !(1 == ~E_12~0); 3805#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 3859#L1892-1 [2021-11-07 08:01:41,561 INFO L793 eck$LassoCheckResult]: Loop: 3859#L1892-1 assume !false; 3868#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 3980#L1233 assume !false; 5574#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 4922#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 4901#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 5061#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 3904#L1046 assume !(0 != eval_~tmp~0); 3906#L1248 start_simulation_~kernel_st~0 := 2; 3940#L874-1 start_simulation_~kernel_st~0 := 3; 5095#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4988#L1258-4 assume !(0 == ~T1_E~0); 4079#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4080#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5626#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5632#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5633#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4303#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4304#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5396#L1298-3 assume !(0 == ~T9_E~0); 5397#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5550#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 5395#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4906#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4081#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4082#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5476#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4224#L1338-3 assume !(0 == ~E_4~0); 4225#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5315#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5481#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5482#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4860#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4436#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4437#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5177#L1378-3 assume !(0 == ~E_12~0); 5178#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5351#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5352#L607-42 assume 1 == ~m_pc~0; 4976#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4706#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4707#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 4450#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4451#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4959#L626-42 assume 1 == ~t1_pc~0; 4533#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4534#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4826#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 4827#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4115#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4116#L645-42 assume 1 == ~t2_pc~0; 5543#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5295#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5453#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 4324#L1576-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3830#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3831#L664-42 assume !(1 == ~t3_pc~0); 4359#L664-44 is_transmit3_triggered_~__retres1~3 := 0; 4360#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5577#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 5128#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5129#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5288#L683-42 assume 1 == ~t4_pc~0; 5641#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5004#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5135#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 5539#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5540#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5390#L702-42 assume 1 == ~t5_pc~0; 4888#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4526#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4810#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 5468#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 3846#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3847#L721-42 assume 1 == ~t6_pc~0; 4001#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 4021#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4481#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 5618#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 4646#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4499#L740-42 assume 1 == ~t7_pc~0; 4500#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 4239#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4767#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 4626#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 4627#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4894#L759-42 assume 1 == ~t8_pc~0; 4746#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 4679#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 4680#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 4757#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 4758#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 4849#L778-42 assume 1 == ~t9_pc~0; 4690#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 4692#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 5100#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 5005#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 5006#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 5063#L797-42 assume 1 == ~t10_pc~0; 4244#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 4245#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 5228#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 5525#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 5101#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 5102#L816-42 assume 1 == ~t11_pc~0; 3794#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 3795#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 4339#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 4340#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 4418#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 4419#L835-42 assume 1 == ~t12_pc~0; 4807#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 4702#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 4394#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 4395#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 5446#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 5240#L854-42 assume !(1 == ~t13_pc~0); 4337#L854-44 is_transmit13_triggered_~__retres1~13 := 0; 4338#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 3948#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 3949#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 4585#L1664-44 assume !(1 == ~M_E~0); 4586#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4182#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4046#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4047#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4637#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4638#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4222#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4223#L1436-3 assume !(1 == ~T8_E~0); 3810#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3811#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5374#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4718#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4386#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4387#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5629#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4325#L1476-3 assume !(1 == ~E_3~0); 4326#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4712#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4354#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4355#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4752#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4753#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5174#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5165#L1516-3 assume !(1 == ~E_11~0); 5166#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4864#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4865#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 5257#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 4158#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 5036#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 4681#L1911 assume !(0 == start_simulation_~tmp~3); 3903#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 4327#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 4282#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 5138#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 3989#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3990#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 4217#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 4218#L1924 assume !(0 != start_simulation_~tmp___0~1); 3859#L1892-1 [2021-11-07 08:01:41,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:41,563 INFO L85 PathProgramCache]: Analyzing trace with hash -1952203841, now seen corresponding path program 1 times [2021-11-07 08:01:41,563 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:41,564 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1406026163] [2021-11-07 08:01:41,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:41,564 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:41,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:41,658 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:41,662 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:41,664 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1406026163] [2021-11-07 08:01:41,664 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1406026163] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:41,664 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:41,665 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:41,665 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1302008363] [2021-11-07 08:01:41,666 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:41,668 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:41,669 INFO L85 PathProgramCache]: Analyzing trace with hash -1926629057, now seen corresponding path program 1 times [2021-11-07 08:01:41,670 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:41,670 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1799731666] [2021-11-07 08:01:41,671 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:41,672 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:41,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:41,833 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:41,834 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:41,838 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1799731666] [2021-11-07 08:01:41,838 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1799731666] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:41,839 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:41,839 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:41,839 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [922248017] [2021-11-07 08:01:41,840 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:01:41,840 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:41,841 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 08:01:41,841 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 08:01:41,842 INFO L87 Difference]: Start difference. First operand 1880 states and 2800 transitions. cyclomatic complexity: 921 Second operand has 3 states, 3 states have (on average 51.666666666666664) internal successors, (155), 3 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:41,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:41,900 INFO L93 Difference]: Finished difference Result 1880 states and 2799 transitions. [2021-11-07 08:01:41,900 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 08:01:41,901 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1880 states and 2799 transitions. [2021-11-07 08:01:41,923 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:41,946 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1880 states to 1880 states and 2799 transitions. [2021-11-07 08:01:41,946 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1880 [2021-11-07 08:01:41,949 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1880 [2021-11-07 08:01:41,949 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1880 states and 2799 transitions. [2021-11-07 08:01:41,953 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:41,954 INFO L681 BuchiCegarLoop]: Abstraction has 1880 states and 2799 transitions. [2021-11-07 08:01:41,959 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1880 states and 2799 transitions. [2021-11-07 08:01:41,996 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1880 to 1880. [2021-11-07 08:01:42,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1880 states, 1880 states have (on average 1.4888297872340426) internal successors, (2799), 1879 states have internal predecessors, (2799), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:42,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1880 states to 1880 states and 2799 transitions. [2021-11-07 08:01:42,079 INFO L704 BuchiCegarLoop]: Abstraction has 1880 states and 2799 transitions. [2021-11-07 08:01:42,079 INFO L587 BuchiCegarLoop]: Abstraction has 1880 states and 2799 transitions. [2021-11-07 08:01:42,079 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-07 08:01:42,079 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1880 states and 2799 transitions. [2021-11-07 08:01:42,094 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:42,095 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:42,095 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:42,098 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:42,099 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:42,101 INFO L791 eck$LassoCheckResult]: Stem: 8397#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 8398#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 8225#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7942#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 7943#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8827#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8078#L891-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 8079#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8521#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8359#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8360#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8148#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8149#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8531#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8707#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 8861#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 8897#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 8159#L946-1 assume !(0 == ~M_E~0); 8160#L1258-1 assume !(0 == ~T1_E~0); 8440#L1263-1 assume !(0 == ~T2_E~0); 8441#L1268-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8741#L1273-1 assume !(0 == ~T4_E~0); 9284#L1278-1 assume !(0 == ~T5_E~0); 9150#L1283-1 assume !(0 == ~T6_E~0); 9151#L1288-1 assume !(0 == ~T7_E~0); 9380#L1293-1 assume !(0 == ~T8_E~0); 9368#L1298-1 assume !(0 == ~T9_E~0); 9296#L1303-1 assume !(0 == ~T10_E~0); 7971#L1308-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 7913#L1313-1 assume !(0 == ~T12_E~0); 7914#L1318-1 assume !(0 == ~T13_E~0); 7920#L1323-1 assume !(0 == ~E_1~0); 7921#L1328-1 assume !(0 == ~E_2~0); 8088#L1333-1 assume !(0 == ~E_3~0); 9028#L1338-1 assume !(0 == ~E_4~0); 9029#L1343-1 assume !(0 == ~E_5~0); 9124#L1348-1 assume 0 == ~E_6~0;~E_6~0 := 1; 9402#L1353-1 assume !(0 == ~E_7~0); 8760#L1358-1 assume !(0 == ~E_8~0); 8761#L1363-1 assume !(0 == ~E_9~0); 9044#L1368-1 assume !(0 == ~E_10~0); 7752#L1373-1 assume !(0 == ~E_11~0); 7753#L1378-1 assume !(0 == ~E_12~0); 8037#L1383-1 assume !(0 == ~E_13~0); 8038#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8767#L607 assume 1 == ~m_pc~0; 8768#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 8111#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9122#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 8686#L1560 assume !(0 != activate_threads_~tmp~1); 8687#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7933#L626 assume 1 == ~t1_pc~0; 7934#L627 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8201#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8202#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 8363#L1568 assume !(0 != activate_threads_~tmp___0~0); 7833#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7834#L645 assume !(1 == ~t2_pc~0); 7906#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 7907#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8570#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 8571#L1576 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8662#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8663#L664 assume 1 == ~t3_pc~0; 9401#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7677#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7678#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 8330#L1584 assume !(0 != activate_threads_~tmp___2~0); 8331#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9311#L683 assume !(1 == ~t4_pc~0); 8883#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 8835#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8836#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 8870#L1592 assume !(0 != activate_threads_~tmp___3~0); 8990#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8611#L702 assume 1 == ~t5_pc~0; 8612#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8540#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8985#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 9271#L1600 assume !(0 != activate_threads_~tmp___4~0); 9214#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7725#L721 assume !(1 == ~t6_pc~0); 7699#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 7700#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7860#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 8337#L1608 assume !(0 != activate_threads_~tmp___5~0); 8338#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8928#L740 assume 1 == ~t7_pc~0; 7773#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 7585#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 7586#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 7575#L1616 assume !(0 != activate_threads_~tmp___6~0); 7576#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 8276#L759 assume !(1 == ~t8_pc~0); 8277#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 8306#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 8983#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 8984#L1624 assume !(0 != activate_threads_~tmp___7~0); 9109#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 9379#L778 assume 1 == ~t9_pc~0; 9268#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 7751#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 7692#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 7619#L1632 assume !(0 != activate_threads_~tmp___8~0); 7620#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 7946#L797 assume 1 == ~t10_pc~0; 7947#L798 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 8065#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 9173#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 8438#L1640 assume !(0 != activate_threads_~tmp___9~0); 8439#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 8725#L816 assume !(1 == ~t11_pc~0); 7659#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 7658#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 8401#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 8344#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 8345#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 8860#L835 assume 1 == ~t12_pc~0; 8738#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 7818#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 7840#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 7981#L1656 assume !(0 != activate_threads_~tmp___11~0); 8494#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 8495#L854 assume !(1 == ~t13_pc~0); 8150#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 8151#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 8197#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 7858#L1664 assume !(0 != activate_threads_~tmp___12~0); 7859#L1664-2 assume !(1 == ~M_E~0); 8648#L1401-1 assume !(1 == ~T1_E~0); 8649#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8917#L1411-1 assume !(1 == ~T3_E~0); 8918#L1416-1 assume !(1 == ~T4_E~0); 8586#L1421-1 assume !(1 == ~T5_E~0); 8146#L1426-1 assume !(1 == ~T6_E~0); 8147#L1431-1 assume !(1 == ~T7_E~0); 7695#L1436-1 assume !(1 == ~T8_E~0); 7696#L1441-1 assume !(1 == ~T9_E~0); 8431#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8432#L1451-1 assume !(1 == ~T11_E~0); 9121#L1456-1 assume !(1 == ~T12_E~0); 8785#L1461-1 assume !(1 == ~T13_E~0); 8354#L1466-1 assume !(1 == ~E_1~0); 8355#L1471-1 assume !(1 == ~E_2~0); 9107#L1476-1 assume !(1 == ~E_3~0); 9108#L1481-1 assume !(1 == ~E_4~0); 9251#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 7986#L1491-1 assume !(1 == ~E_6~0); 7627#L1496-1 assume !(1 == ~E_7~0); 7628#L1501-1 assume !(1 == ~E_8~0); 8429#L1506-1 assume !(1 == ~E_9~0); 8430#L1511-1 assume !(1 == ~E_10~0); 8386#L1516-1 assume !(1 == ~E_11~0); 7571#L1521-1 assume !(1 == ~E_12~0); 7572#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 7626#L1892-1 [2021-11-07 08:01:42,101 INFO L793 eck$LassoCheckResult]: Loop: 7626#L1892-1 assume !false; 7635#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 7747#L1233 assume !false; 9341#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 8689#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 8668#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 8828#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 7671#L1046 assume !(0 != eval_~tmp~0); 7673#L1248 start_simulation_~kernel_st~0 := 2; 7707#L874-1 start_simulation_~kernel_st~0 := 3; 8862#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 8755#L1258-4 assume !(0 == ~T1_E~0); 7846#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7847#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9393#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9399#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9400#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8070#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8071#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9163#L1298-3 assume !(0 == ~T9_E~0); 9164#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9317#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 9162#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8673#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 7848#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7849#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9243#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7991#L1338-3 assume !(0 == ~E_4~0); 7992#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9082#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9248#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9249#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8627#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8203#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8204#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 8944#L1378-3 assume !(0 == ~E_12~0); 8945#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9118#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9119#L607-42 assume 1 == ~m_pc~0; 8743#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 8473#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8474#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 8217#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8218#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8726#L626-42 assume 1 == ~t1_pc~0; 8300#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8301#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8593#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 8594#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7882#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7883#L645-42 assume !(1 == ~t2_pc~0); 9061#L645-44 is_transmit2_triggered_~__retres1~2 := 0; 9062#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9220#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 8091#L1576-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7597#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7598#L664-42 assume 1 == ~t3_pc~0; 8390#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8127#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9344#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 8895#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8896#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9055#L683-42 assume 1 == ~t4_pc~0; 9408#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8771#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8902#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 9306#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 9307#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9157#L702-42 assume !(1 == ~t5_pc~0); 8292#L702-44 is_transmit5_triggered_~__retres1~5 := 0; 8293#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8577#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 9235#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 7613#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7614#L721-42 assume 1 == ~t6_pc~0; 7768#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7788#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8248#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 9385#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 8413#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8266#L740-42 assume !(1 == ~t7_pc~0); 8005#L740-44 is_transmit7_triggered_~__retres1~7 := 0; 8006#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8534#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 8393#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 8394#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 8661#L759-42 assume 1 == ~t8_pc~0; 8513#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 8446#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 8447#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 8524#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 8525#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 8616#L778-42 assume 1 == ~t9_pc~0; 8457#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 8459#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 8867#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 8772#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 8773#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 8830#L797-42 assume 1 == ~t10_pc~0; 8011#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 8012#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 8995#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 9292#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 8868#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 8869#L816-42 assume 1 == ~t11_pc~0; 7561#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 7562#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 8106#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 8107#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 8185#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 8186#L835-42 assume !(1 == ~t12_pc~0); 8468#L835-44 is_transmit12_triggered_~__retres1~12 := 0; 8469#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 8161#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 8162#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 9213#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 9007#L854-42 assume 1 == ~t13_pc~0; 9008#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 8105#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 7715#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 7716#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 8352#L1664-44 assume !(1 == ~M_E~0); 8353#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7949#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7813#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7814#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8404#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8405#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7989#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7990#L1436-3 assume !(1 == ~T8_E~0); 7577#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7578#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9141#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8485#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8153#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 8154#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9396#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8092#L1476-3 assume !(1 == ~E_3~0); 8093#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8479#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8121#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8122#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8519#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8520#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 8941#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 8932#L1516-3 assume !(1 == ~E_11~0); 8933#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8631#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 8632#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 9024#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 7925#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 8803#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 8448#L1911 assume !(0 == start_simulation_~tmp~3); 7670#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 8094#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 8049#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 8905#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 7756#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7757#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 7984#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 7985#L1924 assume !(0 != start_simulation_~tmp___0~1); 7626#L1892-1 [2021-11-07 08:01:42,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:42,102 INFO L85 PathProgramCache]: Analyzing trace with hash -1029036415, now seen corresponding path program 1 times [2021-11-07 08:01:42,102 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:42,103 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1707654286] [2021-11-07 08:01:42,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:42,103 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:42,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:42,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:42,206 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:42,206 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1707654286] [2021-11-07 08:01:42,206 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1707654286] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:42,206 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:42,207 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:42,207 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1856718871] [2021-11-07 08:01:42,207 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:42,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:42,208 INFO L85 PathProgramCache]: Analyzing trace with hash -139194175, now seen corresponding path program 1 times [2021-11-07 08:01:42,208 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:42,209 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1218481303] [2021-11-07 08:01:42,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:42,209 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:42,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:42,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:42,304 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:42,305 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1218481303] [2021-11-07 08:01:42,305 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1218481303] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:42,305 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:42,307 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:42,310 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1752297967] [2021-11-07 08:01:42,310 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:01:42,311 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:42,311 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 08:01:42,312 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 08:01:42,312 INFO L87 Difference]: Start difference. First operand 1880 states and 2799 transitions. cyclomatic complexity: 920 Second operand has 3 states, 3 states have (on average 51.666666666666664) internal successors, (155), 3 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:42,363 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:42,363 INFO L93 Difference]: Finished difference Result 1880 states and 2798 transitions. [2021-11-07 08:01:42,363 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 08:01:42,364 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1880 states and 2798 transitions. [2021-11-07 08:01:42,385 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:42,407 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1880 states to 1880 states and 2798 transitions. [2021-11-07 08:01:42,407 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1880 [2021-11-07 08:01:42,410 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1880 [2021-11-07 08:01:42,410 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1880 states and 2798 transitions. [2021-11-07 08:01:42,414 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:42,414 INFO L681 BuchiCegarLoop]: Abstraction has 1880 states and 2798 transitions. [2021-11-07 08:01:42,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1880 states and 2798 transitions. [2021-11-07 08:01:42,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1880 to 1880. [2021-11-07 08:01:42,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1880 states, 1880 states have (on average 1.4882978723404254) internal successors, (2798), 1879 states have internal predecessors, (2798), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:42,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1880 states to 1880 states and 2798 transitions. [2021-11-07 08:01:42,468 INFO L704 BuchiCegarLoop]: Abstraction has 1880 states and 2798 transitions. [2021-11-07 08:01:42,468 INFO L587 BuchiCegarLoop]: Abstraction has 1880 states and 2798 transitions. [2021-11-07 08:01:42,468 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-07 08:01:42,468 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1880 states and 2798 transitions. [2021-11-07 08:01:42,482 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:42,483 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:42,483 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:42,486 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:42,487 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:42,487 INFO L791 eck$LassoCheckResult]: Stem: 12164#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 12165#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 11992#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 11709#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 11710#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12594#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11845#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11846#L896-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 12288#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 12126#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12127#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11915#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11916#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12298#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12474#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12628#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 12664#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 11926#L946-1 assume !(0 == ~M_E~0); 11927#L1258-1 assume !(0 == ~T1_E~0); 12207#L1263-1 assume !(0 == ~T2_E~0); 12208#L1268-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12508#L1273-1 assume !(0 == ~T4_E~0); 13051#L1278-1 assume !(0 == ~T5_E~0); 12917#L1283-1 assume !(0 == ~T6_E~0); 12918#L1288-1 assume !(0 == ~T7_E~0); 13147#L1293-1 assume !(0 == ~T8_E~0); 13135#L1298-1 assume !(0 == ~T9_E~0); 13063#L1303-1 assume !(0 == ~T10_E~0); 11738#L1308-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 11680#L1313-1 assume !(0 == ~T12_E~0); 11681#L1318-1 assume !(0 == ~T13_E~0); 11687#L1323-1 assume !(0 == ~E_1~0); 11688#L1328-1 assume !(0 == ~E_2~0); 11855#L1333-1 assume !(0 == ~E_3~0); 12795#L1338-1 assume !(0 == ~E_4~0); 12796#L1343-1 assume !(0 == ~E_5~0); 12891#L1348-1 assume 0 == ~E_6~0;~E_6~0 := 1; 13169#L1353-1 assume !(0 == ~E_7~0); 12527#L1358-1 assume !(0 == ~E_8~0); 12528#L1363-1 assume !(0 == ~E_9~0); 12811#L1368-1 assume !(0 == ~E_10~0); 11519#L1373-1 assume !(0 == ~E_11~0); 11520#L1378-1 assume !(0 == ~E_12~0); 11804#L1383-1 assume !(0 == ~E_13~0); 11805#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12534#L607 assume 1 == ~m_pc~0; 12535#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 11878#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12889#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 12453#L1560 assume !(0 != activate_threads_~tmp~1); 12454#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11700#L626 assume 1 == ~t1_pc~0; 11701#L627 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 11968#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11969#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 12130#L1568 assume !(0 != activate_threads_~tmp___0~0); 11600#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11601#L645 assume !(1 == ~t2_pc~0); 11673#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 11674#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12337#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 12338#L1576 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 12429#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12430#L664 assume 1 == ~t3_pc~0; 13168#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11444#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11445#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 12097#L1584 assume !(0 != activate_threads_~tmp___2~0); 12098#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13078#L683 assume !(1 == ~t4_pc~0); 12650#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 12602#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12603#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 12637#L1592 assume !(0 != activate_threads_~tmp___3~0); 12757#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12378#L702 assume 1 == ~t5_pc~0; 12379#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 12307#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12752#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 13038#L1600 assume !(0 != activate_threads_~tmp___4~0); 12981#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11492#L721 assume !(1 == ~t6_pc~0); 11466#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 11467#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11627#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 12104#L1608 assume !(0 != activate_threads_~tmp___5~0); 12105#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 12695#L740 assume 1 == ~t7_pc~0; 11540#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 11352#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 11353#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 11342#L1616 assume !(0 != activate_threads_~tmp___6~0); 11343#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 12043#L759 assume !(1 == ~t8_pc~0); 12044#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 12073#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 12750#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 12751#L1624 assume !(0 != activate_threads_~tmp___7~0); 12876#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 13146#L778 assume 1 == ~t9_pc~0; 13035#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 11518#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 11459#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 11386#L1632 assume !(0 != activate_threads_~tmp___8~0); 11387#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 11713#L797 assume 1 == ~t10_pc~0; 11714#L798 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 11832#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 12940#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 12205#L1640 assume !(0 != activate_threads_~tmp___9~0); 12206#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 12492#L816 assume !(1 == ~t11_pc~0); 11426#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 11425#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 12168#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 12111#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 12112#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 12627#L835 assume 1 == ~t12_pc~0; 12505#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 11585#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 11607#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 11748#L1656 assume !(0 != activate_threads_~tmp___11~0); 12261#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 12262#L854 assume !(1 == ~t13_pc~0); 11917#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 11918#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 11964#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 11625#L1664 assume !(0 != activate_threads_~tmp___12~0); 11626#L1664-2 assume !(1 == ~M_E~0); 12415#L1401-1 assume !(1 == ~T1_E~0); 12416#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12684#L1411-1 assume !(1 == ~T3_E~0); 12685#L1416-1 assume !(1 == ~T4_E~0); 12353#L1421-1 assume !(1 == ~T5_E~0); 11913#L1426-1 assume !(1 == ~T6_E~0); 11914#L1431-1 assume !(1 == ~T7_E~0); 11462#L1436-1 assume !(1 == ~T8_E~0); 11463#L1441-1 assume !(1 == ~T9_E~0); 12198#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12199#L1451-1 assume !(1 == ~T11_E~0); 12888#L1456-1 assume !(1 == ~T12_E~0); 12552#L1461-1 assume !(1 == ~T13_E~0); 12121#L1466-1 assume !(1 == ~E_1~0); 12122#L1471-1 assume !(1 == ~E_2~0); 12874#L1476-1 assume !(1 == ~E_3~0); 12875#L1481-1 assume !(1 == ~E_4~0); 13018#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 11753#L1491-1 assume !(1 == ~E_6~0); 11394#L1496-1 assume !(1 == ~E_7~0); 11395#L1501-1 assume !(1 == ~E_8~0); 12196#L1506-1 assume !(1 == ~E_9~0); 12197#L1511-1 assume !(1 == ~E_10~0); 12153#L1516-1 assume !(1 == ~E_11~0); 11338#L1521-1 assume !(1 == ~E_12~0); 11339#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 11393#L1892-1 [2021-11-07 08:01:42,488 INFO L793 eck$LassoCheckResult]: Loop: 11393#L1892-1 assume !false; 11402#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 11514#L1233 assume !false; 13108#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 12456#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 12435#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 12595#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 11438#L1046 assume !(0 != eval_~tmp~0); 11440#L1248 start_simulation_~kernel_st~0 := 2; 11474#L874-1 start_simulation_~kernel_st~0 := 3; 12629#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12522#L1258-4 assume !(0 == ~T1_E~0); 11613#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11614#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13160#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13166#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13167#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11837#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11838#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12930#L1298-3 assume !(0 == ~T9_E~0); 12931#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13084#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12929#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 12440#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 11615#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11616#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13010#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11758#L1338-3 assume !(0 == ~E_4~0); 11759#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12849#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13015#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13016#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12394#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11970#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11971#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12711#L1378-3 assume !(0 == ~E_12~0); 12712#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 12885#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12886#L607-42 assume 1 == ~m_pc~0; 12510#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 12240#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12241#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 11984#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 11985#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12493#L626-42 assume 1 == ~t1_pc~0; 12067#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 12068#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12360#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 12361#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11649#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11650#L645-42 assume 1 == ~t2_pc~0; 13077#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 12829#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12987#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 11858#L1576-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 11364#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11365#L664-42 assume !(1 == ~t3_pc~0); 11893#L664-44 is_transmit3_triggered_~__retres1~3 := 0; 11894#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13111#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 12662#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12663#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12822#L683-42 assume 1 == ~t4_pc~0; 13175#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12538#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12669#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 13073#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 13074#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12924#L702-42 assume 1 == ~t5_pc~0; 12422#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 12060#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12344#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 13002#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 11380#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11381#L721-42 assume !(1 == ~t6_pc~0); 11536#L721-44 is_transmit6_triggered_~__retres1~6 := 0; 11555#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12015#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 13152#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 12180#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 12033#L740-42 assume 1 == ~t7_pc~0; 12034#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 11773#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12301#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 12160#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 12161#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 12428#L759-42 assume 1 == ~t8_pc~0; 12280#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 12213#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 12214#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 12291#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 12292#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 12383#L778-42 assume 1 == ~t9_pc~0; 12224#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 12226#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 12634#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 12539#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 12540#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 12597#L797-42 assume 1 == ~t10_pc~0; 11778#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 11779#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 12762#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 13059#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 12635#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 12636#L816-42 assume 1 == ~t11_pc~0; 11328#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 11329#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 11873#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 11874#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 11952#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 11953#L835-42 assume 1 == ~t12_pc~0; 12341#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 12236#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 11928#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 11929#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 12980#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 12774#L854-42 assume 1 == ~t13_pc~0; 12775#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 11872#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 11482#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 11483#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 12119#L1664-44 assume !(1 == ~M_E~0); 12120#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11716#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11580#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11581#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12171#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12172#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11756#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11757#L1436-3 assume !(1 == ~T8_E~0); 11344#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11345#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12908#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12252#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11920#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 11921#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13163#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11859#L1476-3 assume !(1 == ~E_3~0); 11860#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12246#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11888#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11889#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12286#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12287#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12708#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12699#L1516-3 assume !(1 == ~E_11~0); 12700#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12398#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 12399#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 12791#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 11692#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 12570#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 12215#L1911 assume !(0 == start_simulation_~tmp~3); 11437#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 11861#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 11816#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 12672#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 11523#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11524#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 11751#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 11752#L1924 assume !(0 != start_simulation_~tmp___0~1); 11393#L1892-1 [2021-11-07 08:01:42,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:42,489 INFO L85 PathProgramCache]: Analyzing trace with hash -1414898817, now seen corresponding path program 1 times [2021-11-07 08:01:42,489 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:42,490 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [381337735] [2021-11-07 08:01:42,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:42,490 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:42,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:42,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:42,545 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:42,545 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [381337735] [2021-11-07 08:01:42,545 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [381337735] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:42,546 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:42,546 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:42,546 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [994205424] [2021-11-07 08:01:42,547 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:42,547 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:42,547 INFO L85 PathProgramCache]: Analyzing trace with hash 1756575743, now seen corresponding path program 1 times [2021-11-07 08:01:42,548 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:42,548 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [454514282] [2021-11-07 08:01:42,548 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:42,549 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:42,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:42,608 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:42,609 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:42,609 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [454514282] [2021-11-07 08:01:42,609 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [454514282] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:42,609 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:42,610 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:42,610 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [259234815] [2021-11-07 08:01:42,611 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:01:42,611 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:42,611 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 08:01:42,612 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 08:01:42,612 INFO L87 Difference]: Start difference. First operand 1880 states and 2798 transitions. cyclomatic complexity: 919 Second operand has 3 states, 3 states have (on average 51.666666666666664) internal successors, (155), 3 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:42,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:42,660 INFO L93 Difference]: Finished difference Result 1880 states and 2797 transitions. [2021-11-07 08:01:42,661 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 08:01:42,661 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1880 states and 2797 transitions. [2021-11-07 08:01:42,681 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:42,703 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1880 states to 1880 states and 2797 transitions. [2021-11-07 08:01:42,703 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1880 [2021-11-07 08:01:42,706 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1880 [2021-11-07 08:01:42,706 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1880 states and 2797 transitions. [2021-11-07 08:01:42,710 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:42,711 INFO L681 BuchiCegarLoop]: Abstraction has 1880 states and 2797 transitions. [2021-11-07 08:01:42,715 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1880 states and 2797 transitions. [2021-11-07 08:01:42,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1880 to 1880. [2021-11-07 08:01:42,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1880 states, 1880 states have (on average 1.4877659574468085) internal successors, (2797), 1879 states have internal predecessors, (2797), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:42,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1880 states to 1880 states and 2797 transitions. [2021-11-07 08:01:42,764 INFO L704 BuchiCegarLoop]: Abstraction has 1880 states and 2797 transitions. [2021-11-07 08:01:42,764 INFO L587 BuchiCegarLoop]: Abstraction has 1880 states and 2797 transitions. [2021-11-07 08:01:42,764 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-07 08:01:42,764 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1880 states and 2797 transitions. [2021-11-07 08:01:42,778 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:42,779 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:42,779 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:42,783 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:42,783 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:42,783 INFO L791 eck$LassoCheckResult]: Stem: 15931#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 15932#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 15759#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15476#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 15477#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16361#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15612#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15613#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16055#L901-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 15893#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 15894#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 15682#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 15683#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16065#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16241#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16395#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 16431#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 15693#L946-1 assume !(0 == ~M_E~0); 15694#L1258-1 assume !(0 == ~T1_E~0); 15974#L1263-1 assume !(0 == ~T2_E~0); 15975#L1268-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16275#L1273-1 assume !(0 == ~T4_E~0); 16818#L1278-1 assume !(0 == ~T5_E~0); 16684#L1283-1 assume !(0 == ~T6_E~0); 16685#L1288-1 assume !(0 == ~T7_E~0); 16914#L1293-1 assume !(0 == ~T8_E~0); 16902#L1298-1 assume !(0 == ~T9_E~0); 16830#L1303-1 assume !(0 == ~T10_E~0); 15505#L1308-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 15447#L1313-1 assume !(0 == ~T12_E~0); 15448#L1318-1 assume !(0 == ~T13_E~0); 15454#L1323-1 assume !(0 == ~E_1~0); 15455#L1328-1 assume !(0 == ~E_2~0); 15622#L1333-1 assume !(0 == ~E_3~0); 16562#L1338-1 assume !(0 == ~E_4~0); 16563#L1343-1 assume !(0 == ~E_5~0); 16658#L1348-1 assume 0 == ~E_6~0;~E_6~0 := 1; 16936#L1353-1 assume !(0 == ~E_7~0); 16294#L1358-1 assume !(0 == ~E_8~0); 16295#L1363-1 assume !(0 == ~E_9~0); 16578#L1368-1 assume !(0 == ~E_10~0); 15286#L1373-1 assume !(0 == ~E_11~0); 15287#L1378-1 assume !(0 == ~E_12~0); 15571#L1383-1 assume !(0 == ~E_13~0); 15572#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16301#L607 assume 1 == ~m_pc~0; 16302#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 15645#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16656#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 16220#L1560 assume !(0 != activate_threads_~tmp~1); 16221#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15467#L626 assume 1 == ~t1_pc~0; 15468#L627 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 15735#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15736#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 15897#L1568 assume !(0 != activate_threads_~tmp___0~0); 15367#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15368#L645 assume !(1 == ~t2_pc~0); 15440#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 15441#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16104#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 16105#L1576 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 16196#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16197#L664 assume 1 == ~t3_pc~0; 16935#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 15211#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15212#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 15864#L1584 assume !(0 != activate_threads_~tmp___2~0); 15865#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16845#L683 assume !(1 == ~t4_pc~0); 16417#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 16369#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16370#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 16404#L1592 assume !(0 != activate_threads_~tmp___3~0); 16524#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16145#L702 assume 1 == ~t5_pc~0; 16146#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 16074#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16519#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 16805#L1600 assume !(0 != activate_threads_~tmp___4~0); 16748#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 15259#L721 assume !(1 == ~t6_pc~0); 15233#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 15234#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 15394#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 15871#L1608 assume !(0 != activate_threads_~tmp___5~0); 15872#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 16462#L740 assume 1 == ~t7_pc~0; 15307#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 15119#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 15120#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 15109#L1616 assume !(0 != activate_threads_~tmp___6~0); 15110#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 15810#L759 assume !(1 == ~t8_pc~0); 15811#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 15840#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 16517#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 16518#L1624 assume !(0 != activate_threads_~tmp___7~0); 16643#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 16913#L778 assume 1 == ~t9_pc~0; 16802#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 15285#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 15226#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 15153#L1632 assume !(0 != activate_threads_~tmp___8~0); 15154#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 15480#L797 assume 1 == ~t10_pc~0; 15481#L798 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 15599#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 16707#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 15972#L1640 assume !(0 != activate_threads_~tmp___9~0); 15973#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 16259#L816 assume !(1 == ~t11_pc~0); 15193#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 15192#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 15935#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 15878#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 15879#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 16394#L835 assume 1 == ~t12_pc~0; 16272#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 15352#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 15374#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 15515#L1656 assume !(0 != activate_threads_~tmp___11~0); 16028#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 16029#L854 assume !(1 == ~t13_pc~0); 15684#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 15685#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 15731#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 15392#L1664 assume !(0 != activate_threads_~tmp___12~0); 15393#L1664-2 assume !(1 == ~M_E~0); 16182#L1401-1 assume !(1 == ~T1_E~0); 16183#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16451#L1411-1 assume !(1 == ~T3_E~0); 16452#L1416-1 assume !(1 == ~T4_E~0); 16120#L1421-1 assume !(1 == ~T5_E~0); 15680#L1426-1 assume !(1 == ~T6_E~0); 15681#L1431-1 assume !(1 == ~T7_E~0); 15229#L1436-1 assume !(1 == ~T8_E~0); 15230#L1441-1 assume !(1 == ~T9_E~0); 15965#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 15966#L1451-1 assume !(1 == ~T11_E~0); 16655#L1456-1 assume !(1 == ~T12_E~0); 16319#L1461-1 assume !(1 == ~T13_E~0); 15888#L1466-1 assume !(1 == ~E_1~0); 15889#L1471-1 assume !(1 == ~E_2~0); 16641#L1476-1 assume !(1 == ~E_3~0); 16642#L1481-1 assume !(1 == ~E_4~0); 16785#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 15520#L1491-1 assume !(1 == ~E_6~0); 15161#L1496-1 assume !(1 == ~E_7~0); 15162#L1501-1 assume !(1 == ~E_8~0); 15963#L1506-1 assume !(1 == ~E_9~0); 15964#L1511-1 assume !(1 == ~E_10~0); 15920#L1516-1 assume !(1 == ~E_11~0); 15105#L1521-1 assume !(1 == ~E_12~0); 15106#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 15160#L1892-1 [2021-11-07 08:01:42,784 INFO L793 eck$LassoCheckResult]: Loop: 15160#L1892-1 assume !false; 15169#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 15281#L1233 assume !false; 16875#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 16223#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 16202#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 16362#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 15205#L1046 assume !(0 != eval_~tmp~0); 15207#L1248 start_simulation_~kernel_st~0 := 2; 15241#L874-1 start_simulation_~kernel_st~0 := 3; 16396#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 16289#L1258-4 assume !(0 == ~T1_E~0); 15380#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15381#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16927#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16933#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16934#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15604#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15605#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16697#L1298-3 assume !(0 == ~T9_E~0); 16698#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16851#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 16696#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 16207#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 15382#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15383#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16777#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15525#L1338-3 assume !(0 == ~E_4~0); 15526#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16616#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16782#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16783#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16161#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15737#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15738#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16478#L1378-3 assume !(0 == ~E_12~0); 16479#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 16652#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16653#L607-42 assume 1 == ~m_pc~0; 16277#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 16007#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16008#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 15751#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 15752#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16260#L626-42 assume 1 == ~t1_pc~0; 15834#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 15835#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16127#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 16128#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15416#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15417#L645-42 assume !(1 == ~t2_pc~0); 16595#L645-44 is_transmit2_triggered_~__retres1~2 := 0; 16596#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16754#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 15625#L1576-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 15131#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15132#L664-42 assume 1 == ~t3_pc~0; 15924#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 15661#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16878#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 16429#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 16430#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16589#L683-42 assume !(1 == ~t4_pc~0); 16304#L683-44 is_transmit4_triggered_~__retres1~4 := 0; 16305#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16436#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 16840#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 16841#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16691#L702-42 assume !(1 == ~t5_pc~0); 15826#L702-44 is_transmit5_triggered_~__retres1~5 := 0; 15827#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16111#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 16769#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 15147#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 15148#L721-42 assume 1 == ~t6_pc~0; 15302#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 15322#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 15782#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 16919#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 15947#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 15800#L740-42 assume !(1 == ~t7_pc~0); 15539#L740-44 is_transmit7_triggered_~__retres1~7 := 0; 15540#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 16068#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 15927#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 15928#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 16195#L759-42 assume !(1 == ~t8_pc~0); 16048#L759-44 is_transmit8_triggered_~__retres1~8 := 0; 15980#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 15981#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 16058#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 16059#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 16150#L778-42 assume 1 == ~t9_pc~0; 15991#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 15993#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 16401#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 16306#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 16307#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 16364#L797-42 assume 1 == ~t10_pc~0; 15545#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 15546#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 16529#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 16826#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 16402#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 16403#L816-42 assume 1 == ~t11_pc~0; 15095#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 15096#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 15640#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 15641#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 15719#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 15720#L835-42 assume !(1 == ~t12_pc~0); 16002#L835-44 is_transmit12_triggered_~__retres1~12 := 0; 16003#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 15695#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 15696#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 16747#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 16541#L854-42 assume !(1 == ~t13_pc~0); 15638#L854-44 is_transmit13_triggered_~__retres1~13 := 0; 15639#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 15249#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 15250#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 15886#L1664-44 assume !(1 == ~M_E~0); 15887#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15483#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15347#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15348#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15938#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15939#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15523#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15524#L1436-3 assume !(1 == ~T8_E~0); 15111#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15112#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16675#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16019#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 15687#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 15688#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16930#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15626#L1476-3 assume !(1 == ~E_3~0); 15627#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16013#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15655#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15656#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16053#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16054#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 16475#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16466#L1516-3 assume !(1 == ~E_11~0); 16467#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 16165#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 16166#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 16558#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 15459#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 16337#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 15982#L1911 assume !(0 == start_simulation_~tmp~3); 15204#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 15628#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 15583#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 16439#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 15290#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15291#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 15518#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 15519#L1924 assume !(0 != start_simulation_~tmp___0~1); 15160#L1892-1 [2021-11-07 08:01:42,785 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:42,785 INFO L85 PathProgramCache]: Analyzing trace with hash -1150251327, now seen corresponding path program 1 times [2021-11-07 08:01:42,786 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:42,786 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [776101287] [2021-11-07 08:01:42,786 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:42,787 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:42,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:42,834 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:42,835 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:42,835 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [776101287] [2021-11-07 08:01:42,835 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [776101287] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:42,836 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:42,836 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:42,836 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1887218127] [2021-11-07 08:01:42,837 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:42,837 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:42,838 INFO L85 PathProgramCache]: Analyzing trace with hash 1312828292, now seen corresponding path program 1 times [2021-11-07 08:01:42,838 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:42,838 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2037668935] [2021-11-07 08:01:42,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:42,839 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:42,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:42,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:42,967 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:42,967 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2037668935] [2021-11-07 08:01:42,968 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2037668935] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:42,968 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:42,968 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:42,968 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [956064752] [2021-11-07 08:01:42,969 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:01:42,969 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:42,970 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 08:01:42,970 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 08:01:42,970 INFO L87 Difference]: Start difference. First operand 1880 states and 2797 transitions. cyclomatic complexity: 918 Second operand has 3 states, 3 states have (on average 51.666666666666664) internal successors, (155), 3 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:43,010 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:43,010 INFO L93 Difference]: Finished difference Result 1880 states and 2796 transitions. [2021-11-07 08:01:43,010 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 08:01:43,011 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1880 states and 2796 transitions. [2021-11-07 08:01:43,025 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:43,041 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1880 states to 1880 states and 2796 transitions. [2021-11-07 08:01:43,041 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1880 [2021-11-07 08:01:43,044 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1880 [2021-11-07 08:01:43,044 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1880 states and 2796 transitions. [2021-11-07 08:01:43,047 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:43,048 INFO L681 BuchiCegarLoop]: Abstraction has 1880 states and 2796 transitions. [2021-11-07 08:01:43,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1880 states and 2796 transitions. [2021-11-07 08:01:43,081 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1880 to 1880. [2021-11-07 08:01:43,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1880 states, 1880 states have (on average 1.4872340425531916) internal successors, (2796), 1879 states have internal predecessors, (2796), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:43,097 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1880 states to 1880 states and 2796 transitions. [2021-11-07 08:01:43,097 INFO L704 BuchiCegarLoop]: Abstraction has 1880 states and 2796 transitions. [2021-11-07 08:01:43,098 INFO L587 BuchiCegarLoop]: Abstraction has 1880 states and 2796 transitions. [2021-11-07 08:01:43,098 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-07 08:01:43,098 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1880 states and 2796 transitions. [2021-11-07 08:01:43,108 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:43,109 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:43,109 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:43,113 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:43,113 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:43,113 INFO L791 eck$LassoCheckResult]: Stem: 19698#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 19699#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 19526#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 19243#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 19244#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20128#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19379#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19380#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19822#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19660#L906-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19661#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 19449#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19450#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19832#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20008#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20162#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 20198#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 19460#L946-1 assume !(0 == ~M_E~0); 19461#L1258-1 assume !(0 == ~T1_E~0); 19741#L1263-1 assume !(0 == ~T2_E~0); 19742#L1268-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20042#L1273-1 assume !(0 == ~T4_E~0); 20585#L1278-1 assume !(0 == ~T5_E~0); 20451#L1283-1 assume !(0 == ~T6_E~0); 20452#L1288-1 assume !(0 == ~T7_E~0); 20681#L1293-1 assume !(0 == ~T8_E~0); 20669#L1298-1 assume !(0 == ~T9_E~0); 20597#L1303-1 assume !(0 == ~T10_E~0); 19272#L1308-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 19214#L1313-1 assume !(0 == ~T12_E~0); 19215#L1318-1 assume !(0 == ~T13_E~0); 19221#L1323-1 assume !(0 == ~E_1~0); 19222#L1328-1 assume !(0 == ~E_2~0); 19389#L1333-1 assume !(0 == ~E_3~0); 20329#L1338-1 assume !(0 == ~E_4~0); 20330#L1343-1 assume !(0 == ~E_5~0); 20425#L1348-1 assume 0 == ~E_6~0;~E_6~0 := 1; 20703#L1353-1 assume !(0 == ~E_7~0); 20061#L1358-1 assume !(0 == ~E_8~0); 20062#L1363-1 assume !(0 == ~E_9~0); 20345#L1368-1 assume !(0 == ~E_10~0); 19053#L1373-1 assume !(0 == ~E_11~0); 19054#L1378-1 assume !(0 == ~E_12~0); 19338#L1383-1 assume !(0 == ~E_13~0); 19339#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20068#L607 assume 1 == ~m_pc~0; 20069#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 19412#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20423#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 19987#L1560 assume !(0 != activate_threads_~tmp~1); 19988#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19234#L626 assume 1 == ~t1_pc~0; 19235#L627 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 19502#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 19503#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 19664#L1568 assume !(0 != activate_threads_~tmp___0~0); 19134#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19135#L645 assume !(1 == ~t2_pc~0); 19207#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 19208#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 19871#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 19872#L1576 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 19963#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 19964#L664 assume 1 == ~t3_pc~0; 20702#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 18978#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18979#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 19631#L1584 assume !(0 != activate_threads_~tmp___2~0); 19632#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20612#L683 assume !(1 == ~t4_pc~0); 20184#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 20136#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20137#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 20171#L1592 assume !(0 != activate_threads_~tmp___3~0); 20291#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 19912#L702 assume 1 == ~t5_pc~0; 19913#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 19841#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 20286#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 20572#L1600 assume !(0 != activate_threads_~tmp___4~0); 20515#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 19026#L721 assume !(1 == ~t6_pc~0); 19000#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 19001#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 19161#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 19638#L1608 assume !(0 != activate_threads_~tmp___5~0); 19639#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 20229#L740 assume 1 == ~t7_pc~0; 19074#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 18886#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 18887#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 18876#L1616 assume !(0 != activate_threads_~tmp___6~0); 18877#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 19577#L759 assume !(1 == ~t8_pc~0); 19578#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 19607#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 20284#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 20285#L1624 assume !(0 != activate_threads_~tmp___7~0); 20410#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 20680#L778 assume 1 == ~t9_pc~0; 20569#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 19052#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 18993#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 18920#L1632 assume !(0 != activate_threads_~tmp___8~0); 18921#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 19247#L797 assume 1 == ~t10_pc~0; 19248#L798 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 19366#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 20474#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 19739#L1640 assume !(0 != activate_threads_~tmp___9~0); 19740#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 20026#L816 assume !(1 == ~t11_pc~0); 18960#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 18959#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 19702#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 19645#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 19646#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 20161#L835 assume 1 == ~t12_pc~0; 20039#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 19119#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 19141#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 19282#L1656 assume !(0 != activate_threads_~tmp___11~0); 19795#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 19796#L854 assume !(1 == ~t13_pc~0); 19451#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 19452#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 19498#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 19159#L1664 assume !(0 != activate_threads_~tmp___12~0); 19160#L1664-2 assume !(1 == ~M_E~0); 19949#L1401-1 assume !(1 == ~T1_E~0); 19950#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20218#L1411-1 assume !(1 == ~T3_E~0); 20219#L1416-1 assume !(1 == ~T4_E~0); 19887#L1421-1 assume !(1 == ~T5_E~0); 19447#L1426-1 assume !(1 == ~T6_E~0); 19448#L1431-1 assume !(1 == ~T7_E~0); 18996#L1436-1 assume !(1 == ~T8_E~0); 18997#L1441-1 assume !(1 == ~T9_E~0); 19732#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19733#L1451-1 assume !(1 == ~T11_E~0); 20422#L1456-1 assume !(1 == ~T12_E~0); 20086#L1461-1 assume !(1 == ~T13_E~0); 19655#L1466-1 assume !(1 == ~E_1~0); 19656#L1471-1 assume !(1 == ~E_2~0); 20408#L1476-1 assume !(1 == ~E_3~0); 20409#L1481-1 assume !(1 == ~E_4~0); 20552#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 19287#L1491-1 assume !(1 == ~E_6~0); 18928#L1496-1 assume !(1 == ~E_7~0); 18929#L1501-1 assume !(1 == ~E_8~0); 19730#L1506-1 assume !(1 == ~E_9~0); 19731#L1511-1 assume !(1 == ~E_10~0); 19687#L1516-1 assume !(1 == ~E_11~0); 18872#L1521-1 assume !(1 == ~E_12~0); 18873#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 18927#L1892-1 [2021-11-07 08:01:43,114 INFO L793 eck$LassoCheckResult]: Loop: 18927#L1892-1 assume !false; 18936#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 19048#L1233 assume !false; 20642#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 19990#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 19969#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 20129#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 18972#L1046 assume !(0 != eval_~tmp~0); 18974#L1248 start_simulation_~kernel_st~0 := 2; 19008#L874-1 start_simulation_~kernel_st~0 := 3; 20163#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 20056#L1258-4 assume !(0 == ~T1_E~0); 19147#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19148#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20694#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20700#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20701#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19371#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19372#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20464#L1298-3 assume !(0 == ~T9_E~0); 20465#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 20618#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20463#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 19974#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 19149#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19150#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20544#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19292#L1338-3 assume !(0 == ~E_4~0); 19293#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20383#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20549#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20550#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19928#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19504#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19505#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 20245#L1378-3 assume !(0 == ~E_12~0); 20246#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 20419#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20420#L607-42 assume 1 == ~m_pc~0; 20044#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 19774#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19775#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 19518#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 19519#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20027#L626-42 assume 1 == ~t1_pc~0; 19601#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 19602#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 19894#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 19895#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 19183#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19184#L645-42 assume 1 == ~t2_pc~0; 20611#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 20363#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20521#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 19392#L1576-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 18898#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18899#L664-42 assume !(1 == ~t3_pc~0); 19427#L664-44 is_transmit3_triggered_~__retres1~3 := 0; 19428#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20645#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 20196#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 20197#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20356#L683-42 assume 1 == ~t4_pc~0; 20709#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 20072#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20203#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 20607#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 20608#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 20458#L702-42 assume 1 == ~t5_pc~0; 19956#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 19594#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 19878#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 20536#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 18914#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 18915#L721-42 assume 1 == ~t6_pc~0; 19069#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 19089#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 19549#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 20686#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 19714#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 19567#L740-42 assume 1 == ~t7_pc~0; 19568#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 19307#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 19835#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 19694#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 19695#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 19962#L759-42 assume 1 == ~t8_pc~0; 19814#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 19747#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 19748#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 19825#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 19826#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 19917#L778-42 assume 1 == ~t9_pc~0; 19758#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 19760#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 20168#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 20073#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 20074#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 20131#L797-42 assume 1 == ~t10_pc~0; 19312#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 19313#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 20296#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 20593#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 20169#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 20170#L816-42 assume !(1 == ~t11_pc~0); 18864#L816-44 is_transmit11_triggered_~__retres1~11 := 0; 18863#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 19407#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 19408#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 19486#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 19487#L835-42 assume 1 == ~t12_pc~0; 19875#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 19770#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 19462#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 19463#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 20514#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 20308#L854-42 assume 1 == ~t13_pc~0; 20309#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 19406#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 19016#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 19017#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 19653#L1664-44 assume !(1 == ~M_E~0); 19654#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19250#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19114#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19115#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19705#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19706#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19290#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19291#L1436-3 assume !(1 == ~T8_E~0); 18878#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 18879#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 20442#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 19786#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 19454#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 19455#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20697#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19393#L1476-3 assume !(1 == ~E_3~0); 19394#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19780#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19422#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19423#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19820#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19821#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 20242#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20233#L1516-3 assume !(1 == ~E_11~0); 20234#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 19932#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 19933#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 20325#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 19226#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 20104#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 19749#L1911 assume !(0 == start_simulation_~tmp~3); 18971#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 19395#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 19350#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 20206#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 19057#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 19058#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 19285#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 19286#L1924 assume !(0 != start_simulation_~tmp___0~1); 18927#L1892-1 [2021-11-07 08:01:43,115 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:43,115 INFO L85 PathProgramCache]: Analyzing trace with hash 1213590335, now seen corresponding path program 1 times [2021-11-07 08:01:43,116 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:43,116 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1860267841] [2021-11-07 08:01:43,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:43,117 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:43,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:43,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:43,176 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:43,177 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1860267841] [2021-11-07 08:01:43,177 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1860267841] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:43,178 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:43,178 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:43,178 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [433817990] [2021-11-07 08:01:43,179 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:43,180 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:43,180 INFO L85 PathProgramCache]: Analyzing trace with hash -812884033, now seen corresponding path program 1 times [2021-11-07 08:01:43,180 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:43,181 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1531070129] [2021-11-07 08:01:43,181 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:43,181 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:43,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:43,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:43,245 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:43,251 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1531070129] [2021-11-07 08:01:43,251 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1531070129] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:43,252 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:43,253 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:43,253 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [116960555] [2021-11-07 08:01:43,254 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:01:43,254 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:43,257 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 08:01:43,258 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 08:01:43,258 INFO L87 Difference]: Start difference. First operand 1880 states and 2796 transitions. cyclomatic complexity: 917 Second operand has 3 states, 3 states have (on average 51.666666666666664) internal successors, (155), 3 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:43,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:43,308 INFO L93 Difference]: Finished difference Result 1880 states and 2795 transitions. [2021-11-07 08:01:43,309 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 08:01:43,309 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1880 states and 2795 transitions. [2021-11-07 08:01:43,326 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:43,347 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1880 states to 1880 states and 2795 transitions. [2021-11-07 08:01:43,349 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1880 [2021-11-07 08:01:43,353 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1880 [2021-11-07 08:01:43,353 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1880 states and 2795 transitions. [2021-11-07 08:01:43,357 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:43,357 INFO L681 BuchiCegarLoop]: Abstraction has 1880 states and 2795 transitions. [2021-11-07 08:01:43,362 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1880 states and 2795 transitions. [2021-11-07 08:01:43,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1880 to 1880. [2021-11-07 08:01:43,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1880 states, 1880 states have (on average 1.4867021276595744) internal successors, (2795), 1879 states have internal predecessors, (2795), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:43,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1880 states to 1880 states and 2795 transitions. [2021-11-07 08:01:43,425 INFO L704 BuchiCegarLoop]: Abstraction has 1880 states and 2795 transitions. [2021-11-07 08:01:43,425 INFO L587 BuchiCegarLoop]: Abstraction has 1880 states and 2795 transitions. [2021-11-07 08:01:43,425 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-07 08:01:43,425 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1880 states and 2795 transitions. [2021-11-07 08:01:43,436 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:43,436 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:43,436 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:43,440 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:43,440 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:43,441 INFO L791 eck$LassoCheckResult]: Stem: 23465#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 23466#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 23293#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 23010#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 23011#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23895#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23146#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23147#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23589#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23427#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23428#L911-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23216#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23217#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 23599#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 23775#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 23929#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 23965#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 23227#L946-1 assume !(0 == ~M_E~0); 23228#L1258-1 assume !(0 == ~T1_E~0); 23508#L1263-1 assume !(0 == ~T2_E~0); 23509#L1268-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 23809#L1273-1 assume !(0 == ~T4_E~0); 24352#L1278-1 assume !(0 == ~T5_E~0); 24218#L1283-1 assume !(0 == ~T6_E~0); 24219#L1288-1 assume !(0 == ~T7_E~0); 24448#L1293-1 assume !(0 == ~T8_E~0); 24436#L1298-1 assume !(0 == ~T9_E~0); 24364#L1303-1 assume !(0 == ~T10_E~0); 23039#L1308-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 22981#L1313-1 assume !(0 == ~T12_E~0); 22982#L1318-1 assume !(0 == ~T13_E~0); 22988#L1323-1 assume !(0 == ~E_1~0); 22989#L1328-1 assume !(0 == ~E_2~0); 23156#L1333-1 assume !(0 == ~E_3~0); 24096#L1338-1 assume !(0 == ~E_4~0); 24097#L1343-1 assume !(0 == ~E_5~0); 24192#L1348-1 assume 0 == ~E_6~0;~E_6~0 := 1; 24470#L1353-1 assume !(0 == ~E_7~0); 23828#L1358-1 assume !(0 == ~E_8~0); 23829#L1363-1 assume !(0 == ~E_9~0); 24112#L1368-1 assume !(0 == ~E_10~0); 22820#L1373-1 assume !(0 == ~E_11~0); 22821#L1378-1 assume !(0 == ~E_12~0); 23105#L1383-1 assume !(0 == ~E_13~0); 23106#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23835#L607 assume 1 == ~m_pc~0; 23836#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 23179#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 24190#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 23754#L1560 assume !(0 != activate_threads_~tmp~1); 23755#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23001#L626 assume 1 == ~t1_pc~0; 23002#L627 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 23269#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23270#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 23431#L1568 assume !(0 != activate_threads_~tmp___0~0); 22901#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22902#L645 assume !(1 == ~t2_pc~0); 22974#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 22975#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23638#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 23639#L1576 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 23730#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 23731#L664 assume 1 == ~t3_pc~0; 24469#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 22745#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22746#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 23398#L1584 assume !(0 != activate_threads_~tmp___2~0); 23399#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 24379#L683 assume !(1 == ~t4_pc~0); 23951#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 23903#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 23904#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 23938#L1592 assume !(0 != activate_threads_~tmp___3~0); 24058#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 23679#L702 assume 1 == ~t5_pc~0; 23680#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 23608#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 24053#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 24339#L1600 assume !(0 != activate_threads_~tmp___4~0); 24282#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 22793#L721 assume !(1 == ~t6_pc~0); 22767#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 22768#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 22928#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 23405#L1608 assume !(0 != activate_threads_~tmp___5~0); 23406#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 23996#L740 assume 1 == ~t7_pc~0; 22841#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 22653#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 22654#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 22643#L1616 assume !(0 != activate_threads_~tmp___6~0); 22644#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 23344#L759 assume !(1 == ~t8_pc~0); 23345#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 23374#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 24051#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 24052#L1624 assume !(0 != activate_threads_~tmp___7~0); 24177#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 24447#L778 assume 1 == ~t9_pc~0; 24336#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 22819#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 22760#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 22687#L1632 assume !(0 != activate_threads_~tmp___8~0); 22688#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 23014#L797 assume 1 == ~t10_pc~0; 23015#L798 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 23133#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 24241#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 23506#L1640 assume !(0 != activate_threads_~tmp___9~0); 23507#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 23793#L816 assume !(1 == ~t11_pc~0); 22727#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 22726#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 23469#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 23412#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 23413#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 23928#L835 assume 1 == ~t12_pc~0; 23806#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 22886#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 22908#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 23049#L1656 assume !(0 != activate_threads_~tmp___11~0); 23562#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 23563#L854 assume !(1 == ~t13_pc~0); 23218#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 23219#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 23265#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 22926#L1664 assume !(0 != activate_threads_~tmp___12~0); 22927#L1664-2 assume !(1 == ~M_E~0); 23716#L1401-1 assume !(1 == ~T1_E~0); 23717#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23985#L1411-1 assume !(1 == ~T3_E~0); 23986#L1416-1 assume !(1 == ~T4_E~0); 23654#L1421-1 assume !(1 == ~T5_E~0); 23214#L1426-1 assume !(1 == ~T6_E~0); 23215#L1431-1 assume !(1 == ~T7_E~0); 22763#L1436-1 assume !(1 == ~T8_E~0); 22764#L1441-1 assume !(1 == ~T9_E~0); 23499#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 23500#L1451-1 assume !(1 == ~T11_E~0); 24189#L1456-1 assume !(1 == ~T12_E~0); 23853#L1461-1 assume !(1 == ~T13_E~0); 23422#L1466-1 assume !(1 == ~E_1~0); 23423#L1471-1 assume !(1 == ~E_2~0); 24175#L1476-1 assume !(1 == ~E_3~0); 24176#L1481-1 assume !(1 == ~E_4~0); 24319#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 23054#L1491-1 assume !(1 == ~E_6~0); 22695#L1496-1 assume !(1 == ~E_7~0); 22696#L1501-1 assume !(1 == ~E_8~0); 23497#L1506-1 assume !(1 == ~E_9~0); 23498#L1511-1 assume !(1 == ~E_10~0); 23454#L1516-1 assume !(1 == ~E_11~0); 22639#L1521-1 assume !(1 == ~E_12~0); 22640#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 22694#L1892-1 [2021-11-07 08:01:43,442 INFO L793 eck$LassoCheckResult]: Loop: 22694#L1892-1 assume !false; 22703#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 22815#L1233 assume !false; 24409#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 23757#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 23736#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 23896#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 22739#L1046 assume !(0 != eval_~tmp~0); 22741#L1248 start_simulation_~kernel_st~0 := 2; 22775#L874-1 start_simulation_~kernel_st~0 := 3; 23930#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 23823#L1258-4 assume !(0 == ~T1_E~0); 22914#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22915#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24461#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24467#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24468#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23138#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23139#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24231#L1298-3 assume !(0 == ~T9_E~0); 24232#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24385#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24230#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 23741#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 22916#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22917#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24311#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23059#L1338-3 assume !(0 == ~E_4~0); 23060#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24150#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24316#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24317#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23695#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 23271#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 23272#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 24012#L1378-3 assume !(0 == ~E_12~0); 24013#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 24186#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 24187#L607-42 assume 1 == ~m_pc~0; 23811#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 23541#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23542#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 23285#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 23286#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23794#L626-42 assume 1 == ~t1_pc~0; 23368#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 23369#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23661#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 23662#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22950#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22951#L645-42 assume !(1 == ~t2_pc~0); 24129#L645-44 is_transmit2_triggered_~__retres1~2 := 0; 24130#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 24288#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 23159#L1576-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 22665#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22666#L664-42 assume 1 == ~t3_pc~0; 23458#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 23195#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 24412#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 23963#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 23964#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 24123#L683-42 assume 1 == ~t4_pc~0; 24476#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 23839#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 23970#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 24374#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 24375#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 24225#L702-42 assume !(1 == ~t5_pc~0); 23360#L702-44 is_transmit5_triggered_~__retres1~5 := 0; 23361#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 23645#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 24303#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 22681#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 22682#L721-42 assume 1 == ~t6_pc~0; 22836#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 22856#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 23316#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 24453#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 23481#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 23334#L740-42 assume !(1 == ~t7_pc~0); 23073#L740-44 is_transmit7_triggered_~__retres1~7 := 0; 23074#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 23602#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 23461#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 23462#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 23729#L759-42 assume 1 == ~t8_pc~0; 23581#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 23514#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 23515#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 23592#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 23593#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 23684#L778-42 assume 1 == ~t9_pc~0; 23525#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 23527#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 23935#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 23840#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 23841#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 23898#L797-42 assume 1 == ~t10_pc~0; 23079#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 23080#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 24063#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 24360#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 23936#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 23937#L816-42 assume 1 == ~t11_pc~0; 22629#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 22630#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 23174#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 23175#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 23253#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 23254#L835-42 assume !(1 == ~t12_pc~0); 23536#L835-44 is_transmit12_triggered_~__retres1~12 := 0; 23537#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 23229#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 23230#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 24281#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 24075#L854-42 assume !(1 == ~t13_pc~0); 23172#L854-44 is_transmit13_triggered_~__retres1~13 := 0; 23173#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 22783#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 22784#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 23420#L1664-44 assume !(1 == ~M_E~0); 23421#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23017#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22881#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22882#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23472#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23473#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23057#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23058#L1436-3 assume !(1 == ~T8_E~0); 22645#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22646#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24209#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 23553#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 23221#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 23222#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 24464#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23160#L1476-3 assume !(1 == ~E_3~0); 23161#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23547#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23189#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23190#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 23587#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23588#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 24009#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 24000#L1516-3 assume !(1 == ~E_11~0); 24001#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 23699#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 23700#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 24092#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 22993#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 23871#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 23516#L1911 assume !(0 == start_simulation_~tmp~3); 22738#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 23162#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 23117#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 23973#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 22824#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 22825#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 23052#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 23053#L1924 assume !(0 != start_simulation_~tmp___0~1); 22694#L1892-1 [2021-11-07 08:01:43,443 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:43,443 INFO L85 PathProgramCache]: Analyzing trace with hash -1758198015, now seen corresponding path program 1 times [2021-11-07 08:01:43,443 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:43,443 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [363226983] [2021-11-07 08:01:43,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:43,444 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:43,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:43,490 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:43,490 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:43,491 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [363226983] [2021-11-07 08:01:43,491 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [363226983] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:43,491 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:43,491 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:43,492 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [399672002] [2021-11-07 08:01:43,492 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:43,493 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:43,493 INFO L85 PathProgramCache]: Analyzing trace with hash -1012671870, now seen corresponding path program 1 times [2021-11-07 08:01:43,493 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:43,494 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [159777626] [2021-11-07 08:01:43,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:43,494 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:43,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:43,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:43,553 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:43,553 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [159777626] [2021-11-07 08:01:43,553 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [159777626] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:43,553 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:43,554 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:43,554 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [996514273] [2021-11-07 08:01:43,555 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:01:43,555 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:43,555 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 08:01:43,556 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 08:01:43,556 INFO L87 Difference]: Start difference. First operand 1880 states and 2795 transitions. cyclomatic complexity: 916 Second operand has 3 states, 3 states have (on average 51.666666666666664) internal successors, (155), 3 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:43,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:43,664 INFO L93 Difference]: Finished difference Result 1880 states and 2794 transitions. [2021-11-07 08:01:43,665 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 08:01:43,665 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1880 states and 2794 transitions. [2021-11-07 08:01:43,681 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:43,702 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1880 states to 1880 states and 2794 transitions. [2021-11-07 08:01:43,702 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1880 [2021-11-07 08:01:43,708 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1880 [2021-11-07 08:01:43,708 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1880 states and 2794 transitions. [2021-11-07 08:01:43,712 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:43,712 INFO L681 BuchiCegarLoop]: Abstraction has 1880 states and 2794 transitions. [2021-11-07 08:01:43,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1880 states and 2794 transitions. [2021-11-07 08:01:43,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1880 to 1880. [2021-11-07 08:01:43,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1880 states, 1880 states have (on average 1.4861702127659575) internal successors, (2794), 1879 states have internal predecessors, (2794), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:43,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1880 states to 1880 states and 2794 transitions. [2021-11-07 08:01:43,763 INFO L704 BuchiCegarLoop]: Abstraction has 1880 states and 2794 transitions. [2021-11-07 08:01:43,763 INFO L587 BuchiCegarLoop]: Abstraction has 1880 states and 2794 transitions. [2021-11-07 08:01:43,764 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-07 08:01:43,764 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1880 states and 2794 transitions. [2021-11-07 08:01:43,773 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:43,774 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:43,774 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:43,777 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:43,777 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:43,778 INFO L791 eck$LassoCheckResult]: Stem: 27232#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 27233#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 27060#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 26777#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 26778#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27662#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26913#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26914#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27360#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27194#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 27195#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26983#L916-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 26984#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27366#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 27542#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 27697#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 27732#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 26996#L946-1 assume !(0 == ~M_E~0); 26997#L1258-1 assume !(0 == ~T1_E~0); 27275#L1263-1 assume !(0 == ~T2_E~0); 27276#L1268-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27576#L1273-1 assume !(0 == ~T4_E~0); 28119#L1278-1 assume !(0 == ~T5_E~0); 27985#L1283-1 assume !(0 == ~T6_E~0); 27986#L1288-1 assume !(0 == ~T7_E~0); 28216#L1293-1 assume !(0 == ~T8_E~0); 28203#L1298-1 assume !(0 == ~T9_E~0); 28131#L1303-1 assume !(0 == ~T10_E~0); 26806#L1308-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 26751#L1313-1 assume !(0 == ~T12_E~0); 26752#L1318-1 assume !(0 == ~T13_E~0); 26757#L1323-1 assume !(0 == ~E_1~0); 26758#L1328-1 assume !(0 == ~E_2~0); 26925#L1333-1 assume !(0 == ~E_3~0); 27863#L1338-1 assume !(0 == ~E_4~0); 27864#L1343-1 assume !(0 == ~E_5~0); 27959#L1348-1 assume 0 == ~E_6~0;~E_6~0 := 1; 28237#L1353-1 assume !(0 == ~E_7~0); 27595#L1358-1 assume !(0 == ~E_8~0); 27596#L1363-1 assume !(0 == ~E_9~0); 27880#L1368-1 assume !(0 == ~E_10~0); 26587#L1373-1 assume !(0 == ~E_11~0); 26588#L1378-1 assume !(0 == ~E_12~0); 26874#L1383-1 assume !(0 == ~E_13~0); 26875#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27602#L607 assume 1 == ~m_pc~0; 27603#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 26946#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27957#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 27521#L1560 assume !(0 != activate_threads_~tmp~1); 27522#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26768#L626 assume 1 == ~t1_pc~0; 26769#L627 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 27038#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27039#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 27200#L1568 assume !(0 != activate_threads_~tmp___0~0); 26671#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26672#L645 assume !(1 == ~t2_pc~0); 26741#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 26742#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27408#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 27409#L1576 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 27497#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27498#L664 assume 1 == ~t3_pc~0; 28236#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 26516#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 26517#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 27165#L1584 assume !(0 != activate_threads_~tmp___2~0); 27166#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 28146#L683 assume !(1 == ~t4_pc~0); 27718#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 27670#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 27671#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 27705#L1592 assume !(0 != activate_threads_~tmp___3~0); 27825#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 27446#L702 assume 1 == ~t5_pc~0; 27447#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 27375#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 27820#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 28106#L1600 assume !(0 != activate_threads_~tmp___4~0); 28049#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 26560#L721 assume !(1 == ~t6_pc~0); 26534#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 26535#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 26695#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 27172#L1608 assume !(0 != activate_threads_~tmp___5~0); 27173#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 27763#L740 assume 1 == ~t7_pc~0; 26608#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 26420#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 26421#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 26410#L1616 assume !(0 != activate_threads_~tmp___6~0); 26411#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 27111#L759 assume !(1 == ~t8_pc~0); 27112#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 27141#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 27818#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 27819#L1624 assume !(0 != activate_threads_~tmp___7~0); 27944#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 28214#L778 assume 1 == ~t9_pc~0; 28103#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 26586#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 26527#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 26454#L1632 assume !(0 != activate_threads_~tmp___8~0); 26455#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 26781#L797 assume 1 == ~t10_pc~0; 26782#L798 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 26900#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 28008#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 27273#L1640 assume !(0 != activate_threads_~tmp___9~0); 27274#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 27560#L816 assume !(1 == ~t11_pc~0); 26494#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 26493#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 27236#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 27179#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 27180#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 27695#L835 assume 1 == ~t12_pc~0; 27573#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 26653#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 26675#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 26816#L1656 assume !(0 != activate_threads_~tmp___11~0); 27329#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 27330#L854 assume !(1 == ~t13_pc~0); 26985#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 26986#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 27032#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 26693#L1664 assume !(0 != activate_threads_~tmp___12~0); 26694#L1664-2 assume !(1 == ~M_E~0); 27483#L1401-1 assume !(1 == ~T1_E~0); 27484#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27752#L1411-1 assume !(1 == ~T3_E~0); 27753#L1416-1 assume !(1 == ~T4_E~0); 27421#L1421-1 assume !(1 == ~T5_E~0); 26981#L1426-1 assume !(1 == ~T6_E~0); 26982#L1431-1 assume !(1 == ~T7_E~0); 26530#L1436-1 assume !(1 == ~T8_E~0); 26531#L1441-1 assume !(1 == ~T9_E~0); 27266#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 27267#L1451-1 assume !(1 == ~T11_E~0); 27956#L1456-1 assume !(1 == ~T12_E~0); 27620#L1461-1 assume !(1 == ~T13_E~0); 27189#L1466-1 assume !(1 == ~E_1~0); 27190#L1471-1 assume !(1 == ~E_2~0); 27942#L1476-1 assume !(1 == ~E_3~0); 27943#L1481-1 assume !(1 == ~E_4~0); 28086#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26821#L1491-1 assume !(1 == ~E_6~0); 26462#L1496-1 assume !(1 == ~E_7~0); 26463#L1501-1 assume !(1 == ~E_8~0); 27264#L1506-1 assume !(1 == ~E_9~0); 27265#L1511-1 assume !(1 == ~E_10~0); 27221#L1516-1 assume !(1 == ~E_11~0); 26406#L1521-1 assume !(1 == ~E_12~0); 26407#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 26461#L1892-1 [2021-11-07 08:01:43,778 INFO L793 eck$LassoCheckResult]: Loop: 26461#L1892-1 assume !false; 26470#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 26582#L1233 assume !false; 28176#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 27524#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 27503#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 27663#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 26506#L1046 assume !(0 != eval_~tmp~0); 26508#L1248 start_simulation_~kernel_st~0 := 2; 26542#L874-1 start_simulation_~kernel_st~0 := 3; 27696#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 27590#L1258-4 assume !(0 == ~T1_E~0); 26681#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26682#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 28228#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 28234#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 28235#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26905#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 26906#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 27998#L1298-3 assume !(0 == ~T9_E~0); 27999#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28152#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 27997#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 27508#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 26683#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26684#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 28078#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26826#L1338-3 assume !(0 == ~E_4~0); 26827#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 27917#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28083#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28084#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27462#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27036#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 27037#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 27779#L1378-3 assume !(0 == ~E_12~0); 27780#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 27953#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27954#L607-42 assume 1 == ~m_pc~0; 27578#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 27308#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27309#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 27052#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 27053#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27561#L626-42 assume !(1 == ~t1_pc~0); 27137#L626-44 is_transmit1_triggered_~__retres1~1 := 0; 27136#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27428#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 27429#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 26717#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26718#L645-42 assume 1 == ~t2_pc~0; 28145#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 27897#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28055#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 26926#L1576-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 26432#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 26433#L664-42 assume !(1 == ~t3_pc~0); 26961#L664-44 is_transmit3_triggered_~__retres1~3 := 0; 26962#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28179#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 27730#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 27731#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 27890#L683-42 assume 1 == ~t4_pc~0; 28243#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 27606#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 27737#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 28141#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 28142#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 27992#L702-42 assume 1 == ~t5_pc~0; 27490#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 27128#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 27412#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 28070#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 26448#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 26449#L721-42 assume 1 == ~t6_pc~0; 26603#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 26623#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 27083#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 28220#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 27248#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 27101#L740-42 assume !(1 == ~t7_pc~0); 26840#L740-44 is_transmit7_triggered_~__retres1~7 := 0; 26841#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 27369#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 27228#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 27229#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 27496#L759-42 assume 1 == ~t8_pc~0; 27348#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 27281#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 27282#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 27358#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 27359#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 27451#L778-42 assume 1 == ~t9_pc~0; 27292#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 27294#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 27702#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 27607#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 27608#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 27665#L797-42 assume !(1 == ~t10_pc~0); 26848#L797-44 is_transmit10_triggered_~__retres1~10 := 0; 26847#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 27830#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 28127#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 27703#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 27704#L816-42 assume 1 == ~t11_pc~0; 26396#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 26397#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 26941#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 26942#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 27020#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 27021#L835-42 assume !(1 == ~t12_pc~0); 27303#L835-44 is_transmit12_triggered_~__retres1~12 := 0; 27304#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 26994#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 26995#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 28048#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 27842#L854-42 assume 1 == ~t13_pc~0; 27843#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 26940#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 26550#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 26551#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 27187#L1664-44 assume !(1 == ~M_E~0); 27188#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26784#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26648#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26649#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27239#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 27240#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26824#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26825#L1436-3 assume !(1 == ~T8_E~0); 26412#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26413#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 27976#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 27320#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 26988#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 26989#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28231#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26927#L1476-3 assume !(1 == ~E_3~0); 26928#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27314#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26956#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26957#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27354#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27355#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 27776#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 27767#L1516-3 assume !(1 == ~E_11~0); 27768#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 27466#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 27467#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 27859#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 26760#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 27638#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 27283#L1911 assume !(0 == start_simulation_~tmp~3); 26505#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 26929#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 26884#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 27740#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 26591#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 26592#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 26819#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 26820#L1924 assume !(0 != start_simulation_~tmp___0~1); 26461#L1892-1 [2021-11-07 08:01:43,779 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:43,779 INFO L85 PathProgramCache]: Analyzing trace with hash 639789823, now seen corresponding path program 1 times [2021-11-07 08:01:43,780 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:43,780 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [203895870] [2021-11-07 08:01:43,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:43,780 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:43,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:43,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:43,826 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:43,826 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [203895870] [2021-11-07 08:01:43,826 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [203895870] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:43,827 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:43,827 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:43,827 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [610289757] [2021-11-07 08:01:43,828 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:43,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:43,828 INFO L85 PathProgramCache]: Analyzing trace with hash -1699557886, now seen corresponding path program 1 times [2021-11-07 08:01:43,829 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:43,829 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2127515310] [2021-11-07 08:01:43,829 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:43,829 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:43,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:43,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:43,910 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:43,910 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2127515310] [2021-11-07 08:01:43,912 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2127515310] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:43,918 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:43,918 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:43,918 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1277024951] [2021-11-07 08:01:43,919 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:01:43,919 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:43,920 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 08:01:43,920 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 08:01:43,920 INFO L87 Difference]: Start difference. First operand 1880 states and 2794 transitions. cyclomatic complexity: 915 Second operand has 3 states, 3 states have (on average 51.666666666666664) internal successors, (155), 3 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:43,965 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:43,965 INFO L93 Difference]: Finished difference Result 1880 states and 2793 transitions. [2021-11-07 08:01:43,970 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 08:01:43,971 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1880 states and 2793 transitions. [2021-11-07 08:01:43,990 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:44,018 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1880 states to 1880 states and 2793 transitions. [2021-11-07 08:01:44,019 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1880 [2021-11-07 08:01:44,021 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1880 [2021-11-07 08:01:44,022 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1880 states and 2793 transitions. [2021-11-07 08:01:44,025 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:44,026 INFO L681 BuchiCegarLoop]: Abstraction has 1880 states and 2793 transitions. [2021-11-07 08:01:44,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1880 states and 2793 transitions. [2021-11-07 08:01:44,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1880 to 1880. [2021-11-07 08:01:44,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1880 states, 1880 states have (on average 1.4856382978723404) internal successors, (2793), 1879 states have internal predecessors, (2793), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:44,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1880 states to 1880 states and 2793 transitions. [2021-11-07 08:01:44,077 INFO L704 BuchiCegarLoop]: Abstraction has 1880 states and 2793 transitions. [2021-11-07 08:01:44,078 INFO L587 BuchiCegarLoop]: Abstraction has 1880 states and 2793 transitions. [2021-11-07 08:01:44,078 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-07 08:01:44,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1880 states and 2793 transitions. [2021-11-07 08:01:44,088 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:44,089 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:44,089 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:44,092 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:44,092 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:44,093 INFO L791 eck$LassoCheckResult]: Stem: 30999#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 31000#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 30827#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 30544#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 30545#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31429#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30680#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30681#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31127#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30961#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30962#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30750#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 30751#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31133#L926-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 31309#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 31463#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 31499#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 30763#L946-1 assume !(0 == ~M_E~0); 30764#L1258-1 assume !(0 == ~T1_E~0); 31042#L1263-1 assume !(0 == ~T2_E~0); 31043#L1268-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31343#L1273-1 assume !(0 == ~T4_E~0); 31886#L1278-1 assume !(0 == ~T5_E~0); 31752#L1283-1 assume !(0 == ~T6_E~0); 31753#L1288-1 assume !(0 == ~T7_E~0); 31983#L1293-1 assume !(0 == ~T8_E~0); 31970#L1298-1 assume !(0 == ~T9_E~0); 31898#L1303-1 assume !(0 == ~T10_E~0); 30573#L1308-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 30515#L1313-1 assume !(0 == ~T12_E~0); 30516#L1318-1 assume !(0 == ~T13_E~0); 30524#L1323-1 assume !(0 == ~E_1~0); 30525#L1328-1 assume !(0 == ~E_2~0); 30692#L1333-1 assume !(0 == ~E_3~0); 31630#L1338-1 assume !(0 == ~E_4~0); 31631#L1343-1 assume !(0 == ~E_5~0); 31726#L1348-1 assume 0 == ~E_6~0;~E_6~0 := 1; 32004#L1353-1 assume !(0 == ~E_7~0); 31362#L1358-1 assume !(0 == ~E_8~0); 31363#L1363-1 assume !(0 == ~E_9~0); 31647#L1368-1 assume !(0 == ~E_10~0); 30354#L1373-1 assume !(0 == ~E_11~0); 30355#L1378-1 assume !(0 == ~E_12~0); 30641#L1383-1 assume !(0 == ~E_13~0); 30642#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 31369#L607 assume 1 == ~m_pc~0; 31370#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 30713#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 31724#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 31288#L1560 assume !(0 != activate_threads_~tmp~1); 31289#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30535#L626 assume 1 == ~t1_pc~0; 30536#L627 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 30805#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30806#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 30967#L1568 assume !(0 != activate_threads_~tmp___0~0); 30437#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30438#L645 assume !(1 == ~t2_pc~0); 30508#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 30509#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 31175#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 31176#L1576 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 31264#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 31265#L664 assume 1 == ~t3_pc~0; 32003#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 30283#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30284#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 30932#L1584 assume !(0 != activate_threads_~tmp___2~0); 30933#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 31913#L683 assume !(1 == ~t4_pc~0); 31485#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 31437#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 31438#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 31472#L1592 assume !(0 != activate_threads_~tmp___3~0); 31592#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 31217#L702 assume 1 == ~t5_pc~0; 31218#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 31143#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 31587#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 31874#L1600 assume !(0 != activate_threads_~tmp___4~0); 31817#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 30327#L721 assume !(1 == ~t6_pc~0); 30301#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 30302#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 30462#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 30939#L1608 assume !(0 != activate_threads_~tmp___5~0); 30940#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 31530#L740 assume 1 == ~t7_pc~0; 30375#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 30187#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 30188#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 30177#L1616 assume !(0 != activate_threads_~tmp___6~0); 30178#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 30879#L759 assume !(1 == ~t8_pc~0); 30880#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 30908#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 31585#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 31586#L1624 assume !(0 != activate_threads_~tmp___7~0); 31711#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 31981#L778 assume 1 == ~t9_pc~0; 31872#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 30353#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 30294#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 30221#L1632 assume !(0 != activate_threads_~tmp___8~0); 30222#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 30549#L797 assume 1 == ~t10_pc~0; 30550#L798 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 30667#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 31775#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 31040#L1640 assume !(0 != activate_threads_~tmp___9~0); 31041#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 31327#L816 assume !(1 == ~t11_pc~0); 30261#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 30260#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 31005#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 30946#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 30947#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 31462#L835 assume 1 == ~t12_pc~0; 31340#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 30420#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 30442#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 30583#L1656 assume !(0 != activate_threads_~tmp___11~0); 31096#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 31097#L854 assume !(1 == ~t13_pc~0); 30752#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 30753#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 30801#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 30460#L1664 assume !(0 != activate_threads_~tmp___12~0); 30461#L1664-2 assume !(1 == ~M_E~0); 31250#L1401-1 assume !(1 == ~T1_E~0); 31251#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31519#L1411-1 assume !(1 == ~T3_E~0); 31520#L1416-1 assume !(1 == ~T4_E~0); 31188#L1421-1 assume !(1 == ~T5_E~0); 30748#L1426-1 assume !(1 == ~T6_E~0); 30749#L1431-1 assume !(1 == ~T7_E~0); 30297#L1436-1 assume !(1 == ~T8_E~0); 30298#L1441-1 assume !(1 == ~T9_E~0); 31035#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 31036#L1451-1 assume !(1 == ~T11_E~0); 31723#L1456-1 assume !(1 == ~T12_E~0); 31387#L1461-1 assume !(1 == ~T13_E~0); 30956#L1466-1 assume !(1 == ~E_1~0); 30957#L1471-1 assume !(1 == ~E_2~0); 31709#L1476-1 assume !(1 == ~E_3~0); 31710#L1481-1 assume !(1 == ~E_4~0); 31853#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30588#L1491-1 assume !(1 == ~E_6~0); 30229#L1496-1 assume !(1 == ~E_7~0); 30230#L1501-1 assume !(1 == ~E_8~0); 31031#L1506-1 assume !(1 == ~E_9~0); 31032#L1511-1 assume !(1 == ~E_10~0); 30988#L1516-1 assume !(1 == ~E_11~0); 30175#L1521-1 assume !(1 == ~E_12~0); 30176#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 30228#L1892-1 [2021-11-07 08:01:44,094 INFO L793 eck$LassoCheckResult]: Loop: 30228#L1892-1 assume !false; 30237#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 30349#L1233 assume !false; 31943#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 31291#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 31270#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 31430#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 30273#L1046 assume !(0 != eval_~tmp~0); 30275#L1248 start_simulation_~kernel_st~0 := 2; 30309#L874-1 start_simulation_~kernel_st~0 := 3; 31464#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 31357#L1258-4 assume !(0 == ~T1_E~0); 30450#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 30451#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31995#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32001#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32002#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 30674#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 30675#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 31765#L1298-3 assume !(0 == ~T9_E~0); 31766#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31919#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 31764#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 31275#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 30452#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30453#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 31845#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30593#L1338-3 assume !(0 == ~E_4~0); 30594#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 31684#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31850#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 31851#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 31229#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 30803#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 30804#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31546#L1378-3 assume !(0 == ~E_12~0); 31547#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 31720#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 31721#L607-42 assume 1 == ~m_pc~0; 31345#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 31075#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 31076#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 30819#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 30820#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 31328#L626-42 assume 1 == ~t1_pc~0; 30902#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 30903#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 31195#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 31196#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 30484#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30485#L645-42 assume 1 == ~t2_pc~0; 31912#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 31664#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 31822#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 30693#L1576-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 30199#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30200#L664-42 assume 1 == ~t3_pc~0; 30992#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 30729#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 31946#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 31497#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 31498#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 31657#L683-42 assume 1 == ~t4_pc~0; 32010#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 31373#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 31504#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 31908#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 31909#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 31759#L702-42 assume 1 == ~t5_pc~0; 31257#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 30895#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 31179#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 31837#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 30215#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 30216#L721-42 assume 1 == ~t6_pc~0; 30370#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 30390#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 30850#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 31987#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 31015#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 30868#L740-42 assume 1 == ~t7_pc~0; 30869#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 30608#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 31136#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 30995#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 30996#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 31263#L759-42 assume 1 == ~t8_pc~0; 31115#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 31048#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 31049#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 31125#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 31126#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 31216#L778-42 assume 1 == ~t9_pc~0; 31059#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 31061#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 31468#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 31374#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 31375#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 31432#L797-42 assume 1 == ~t10_pc~0; 30613#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 30614#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 31597#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 31894#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 31470#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 31471#L816-42 assume 1 == ~t11_pc~0; 30163#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 30164#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 30708#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 30709#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 30787#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 30788#L835-42 assume 1 == ~t12_pc~0; 31174#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 31071#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 30761#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 30762#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 31815#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 31609#L854-42 assume !(1 == ~t13_pc~0); 30704#L854-44 is_transmit13_triggered_~__retres1~13 := 0; 30705#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 30317#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 30318#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 30954#L1664-44 assume !(1 == ~M_E~0); 30955#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30548#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30415#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30416#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31006#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31007#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30591#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30592#L1436-3 assume !(1 == ~T8_E~0); 30179#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30180#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 31743#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31087#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 30755#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 30756#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 31998#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30694#L1476-3 assume !(1 == ~E_3~0); 30695#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31081#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 30723#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 30724#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 31121#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31122#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 31543#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 31534#L1516-3 assume !(1 == ~E_11~0); 31535#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 31233#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 31234#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 31626#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 30527#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 31405#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 31050#L1911 assume !(0 == start_simulation_~tmp~3); 30272#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 30696#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 30651#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 31507#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 30358#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 30359#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 30586#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 30587#L1924 assume !(0 != start_simulation_~tmp___0~1); 30228#L1892-1 [2021-11-07 08:01:44,094 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:44,095 INFO L85 PathProgramCache]: Analyzing trace with hash 301502273, now seen corresponding path program 1 times [2021-11-07 08:01:44,095 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:44,095 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [437984981] [2021-11-07 08:01:44,096 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:44,096 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:44,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:44,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:44,137 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:44,140 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [437984981] [2021-11-07 08:01:44,140 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [437984981] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:44,140 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:44,141 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:44,141 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1441845473] [2021-11-07 08:01:44,142 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:44,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:44,142 INFO L85 PathProgramCache]: Analyzing trace with hash 2080878334, now seen corresponding path program 1 times [2021-11-07 08:01:44,142 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:44,143 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [791555986] [2021-11-07 08:01:44,143 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:44,143 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:44,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:44,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:44,206 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:44,206 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [791555986] [2021-11-07 08:01:44,207 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [791555986] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:44,207 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:44,207 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:44,207 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1879515820] [2021-11-07 08:01:44,208 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:01:44,208 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:44,209 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 08:01:44,209 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 08:01:44,209 INFO L87 Difference]: Start difference. First operand 1880 states and 2793 transitions. cyclomatic complexity: 914 Second operand has 3 states, 3 states have (on average 51.666666666666664) internal successors, (155), 3 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:44,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:44,252 INFO L93 Difference]: Finished difference Result 1880 states and 2792 transitions. [2021-11-07 08:01:44,253 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 08:01:44,253 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1880 states and 2792 transitions. [2021-11-07 08:01:44,267 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:44,286 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1880 states to 1880 states and 2792 transitions. [2021-11-07 08:01:44,286 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1880 [2021-11-07 08:01:44,289 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1880 [2021-11-07 08:01:44,289 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1880 states and 2792 transitions. [2021-11-07 08:01:44,293 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:44,293 INFO L681 BuchiCegarLoop]: Abstraction has 1880 states and 2792 transitions. [2021-11-07 08:01:44,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1880 states and 2792 transitions. [2021-11-07 08:01:44,406 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1880 to 1880. [2021-11-07 08:01:44,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1880 states, 1880 states have (on average 1.4851063829787234) internal successors, (2792), 1879 states have internal predecessors, (2792), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:44,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1880 states to 1880 states and 2792 transitions. [2021-11-07 08:01:44,426 INFO L704 BuchiCegarLoop]: Abstraction has 1880 states and 2792 transitions. [2021-11-07 08:01:44,426 INFO L587 BuchiCegarLoop]: Abstraction has 1880 states and 2792 transitions. [2021-11-07 08:01:44,426 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-07 08:01:44,426 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1880 states and 2792 transitions. [2021-11-07 08:01:44,437 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:44,438 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:44,438 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:44,442 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:44,442 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:44,444 INFO L791 eck$LassoCheckResult]: Stem: 34766#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 34767#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 34594#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 34311#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 34312#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35196#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34447#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34448#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34894#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34728#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 34729#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34517#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 34518#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 34900#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 35076#L931-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 35230#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 35266#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 34530#L946-1 assume !(0 == ~M_E~0); 34531#L1258-1 assume !(0 == ~T1_E~0); 34809#L1263-1 assume !(0 == ~T2_E~0); 34810#L1268-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35110#L1273-1 assume !(0 == ~T4_E~0); 35653#L1278-1 assume !(0 == ~T5_E~0); 35519#L1283-1 assume !(0 == ~T6_E~0); 35520#L1288-1 assume !(0 == ~T7_E~0); 35749#L1293-1 assume !(0 == ~T8_E~0); 35737#L1298-1 assume !(0 == ~T9_E~0); 35665#L1303-1 assume !(0 == ~T10_E~0); 34340#L1308-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 34282#L1313-1 assume !(0 == ~T12_E~0); 34283#L1318-1 assume !(0 == ~T13_E~0); 34291#L1323-1 assume !(0 == ~E_1~0); 34292#L1328-1 assume !(0 == ~E_2~0); 34459#L1333-1 assume !(0 == ~E_3~0); 35397#L1338-1 assume !(0 == ~E_4~0); 35398#L1343-1 assume !(0 == ~E_5~0); 35493#L1348-1 assume 0 == ~E_6~0;~E_6~0 := 1; 35771#L1353-1 assume !(0 == ~E_7~0); 35129#L1358-1 assume !(0 == ~E_8~0); 35130#L1363-1 assume !(0 == ~E_9~0); 35413#L1368-1 assume !(0 == ~E_10~0); 34121#L1373-1 assume !(0 == ~E_11~0); 34122#L1378-1 assume !(0 == ~E_12~0); 34408#L1383-1 assume !(0 == ~E_13~0); 34409#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35136#L607 assume 1 == ~m_pc~0; 35137#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 34480#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35491#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 35055#L1560 assume !(0 != activate_threads_~tmp~1); 35056#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 34302#L626 assume 1 == ~t1_pc~0; 34303#L627 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 34570#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 34571#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 34734#L1568 assume !(0 != activate_threads_~tmp___0~0); 34204#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 34205#L645 assume !(1 == ~t2_pc~0); 34275#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 34276#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 34942#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 34943#L1576 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 35031#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 35032#L664 assume 1 == ~t3_pc~0; 35770#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 34050#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 34051#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 34699#L1584 assume !(0 != activate_threads_~tmp___2~0); 34700#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 35680#L683 assume !(1 == ~t4_pc~0); 35252#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 35204#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 35205#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 35239#L1592 assume !(0 != activate_threads_~tmp___3~0); 35359#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 34984#L702 assume 1 == ~t5_pc~0; 34985#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 34910#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 35354#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 35641#L1600 assume !(0 != activate_threads_~tmp___4~0); 35584#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 34094#L721 assume !(1 == ~t6_pc~0); 34068#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 34069#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 34229#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 34706#L1608 assume !(0 != activate_threads_~tmp___5~0); 34707#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 35297#L740 assume 1 == ~t7_pc~0; 34142#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 33954#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 33955#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 33944#L1616 assume !(0 != activate_threads_~tmp___6~0); 33945#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 34646#L759 assume !(1 == ~t8_pc~0); 34647#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 34675#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 35352#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 35353#L1624 assume !(0 != activate_threads_~tmp___7~0); 35478#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 35748#L778 assume 1 == ~t9_pc~0; 35637#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 34120#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 34061#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 33988#L1632 assume !(0 != activate_threads_~tmp___8~0); 33989#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 34316#L797 assume 1 == ~t10_pc~0; 34317#L798 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 34434#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 35542#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 34807#L1640 assume !(0 != activate_threads_~tmp___9~0); 34808#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 35094#L816 assume !(1 == ~t11_pc~0); 34028#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 34027#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 34772#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 34713#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 34714#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 35229#L835 assume 1 == ~t12_pc~0; 35107#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 34187#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 34209#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 34350#L1656 assume !(0 != activate_threads_~tmp___11~0); 34863#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 34864#L854 assume !(1 == ~t13_pc~0); 34519#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 34520#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 34566#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 34227#L1664 assume !(0 != activate_threads_~tmp___12~0); 34228#L1664-2 assume !(1 == ~M_E~0); 35017#L1401-1 assume !(1 == ~T1_E~0); 35018#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35286#L1411-1 assume !(1 == ~T3_E~0); 35287#L1416-1 assume !(1 == ~T4_E~0); 34955#L1421-1 assume !(1 == ~T5_E~0); 34515#L1426-1 assume !(1 == ~T6_E~0); 34516#L1431-1 assume !(1 == ~T7_E~0); 34064#L1436-1 assume !(1 == ~T8_E~0); 34065#L1441-1 assume !(1 == ~T9_E~0); 34802#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 34803#L1451-1 assume !(1 == ~T11_E~0); 35490#L1456-1 assume !(1 == ~T12_E~0); 35154#L1461-1 assume !(1 == ~T13_E~0); 34723#L1466-1 assume !(1 == ~E_1~0); 34724#L1471-1 assume !(1 == ~E_2~0); 35476#L1476-1 assume !(1 == ~E_3~0); 35477#L1481-1 assume !(1 == ~E_4~0); 35620#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 34355#L1491-1 assume !(1 == ~E_6~0); 33996#L1496-1 assume !(1 == ~E_7~0); 33997#L1501-1 assume !(1 == ~E_8~0); 34798#L1506-1 assume !(1 == ~E_9~0); 34799#L1511-1 assume !(1 == ~E_10~0); 34755#L1516-1 assume !(1 == ~E_11~0); 33942#L1521-1 assume !(1 == ~E_12~0); 33943#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 33995#L1892-1 [2021-11-07 08:01:44,445 INFO L793 eck$LassoCheckResult]: Loop: 33995#L1892-1 assume !false; 34004#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 34116#L1233 assume !false; 35710#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 35058#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 35037#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 35197#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 34040#L1046 assume !(0 != eval_~tmp~0); 34042#L1248 start_simulation_~kernel_st~0 := 2; 34076#L874-1 start_simulation_~kernel_st~0 := 3; 35231#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 35124#L1258-4 assume !(0 == ~T1_E~0); 34217#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34218#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35762#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35768#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35769#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 34441#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 34442#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 35532#L1298-3 assume !(0 == ~T9_E~0); 35533#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 35686#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 35531#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 35042#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 34219#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 34220#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35612#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34360#L1338-3 assume !(0 == ~E_4~0); 34361#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35451#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35618#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 35619#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34998#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 34572#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34573#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35313#L1378-3 assume !(0 == ~E_12~0); 35314#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 35487#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35488#L607-42 assume 1 == ~m_pc~0; 35114#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 34842#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 34843#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 34586#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 34587#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 35098#L626-42 assume 1 == ~t1_pc~0; 34669#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 34670#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 34962#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 34963#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 34251#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 34252#L645-42 assume !(1 == ~t2_pc~0); 35429#L645-44 is_transmit2_triggered_~__retres1~2 := 0; 35430#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 35589#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 34460#L1576-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 33966#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 33967#L664-42 assume 1 == ~t3_pc~0; 34759#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 34493#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 35713#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 35264#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 35265#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 35424#L683-42 assume 1 == ~t4_pc~0; 35777#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 35140#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 35270#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 35675#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 35676#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 35526#L702-42 assume 1 == ~t5_pc~0; 35024#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 34662#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 34946#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 35604#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 33980#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 33981#L721-42 assume 1 == ~t6_pc~0; 34137#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 34157#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 34617#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 35754#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 34782#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 34635#L740-42 assume !(1 == ~t7_pc~0); 34374#L740-44 is_transmit7_triggered_~__retres1~7 := 0; 34375#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 34903#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 34762#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 34763#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 35030#L759-42 assume 1 == ~t8_pc~0; 34882#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 34815#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 34816#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 34892#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 34893#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 34983#L778-42 assume 1 == ~t9_pc~0; 34826#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 34828#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 35235#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 35141#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 35142#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 35199#L797-42 assume 1 == ~t10_pc~0; 34380#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 34381#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 35364#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 35661#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 35237#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 35238#L816-42 assume 1 == ~t11_pc~0; 33930#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 33931#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 34475#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 34476#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 34554#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 34555#L835-42 assume !(1 == ~t12_pc~0); 34834#L835-44 is_transmit12_triggered_~__retres1~12 := 0; 34835#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 34528#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 34529#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 35582#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 35376#L854-42 assume 1 == ~t13_pc~0; 35377#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 34472#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 34084#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 34085#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 34721#L1664-44 assume !(1 == ~M_E~0); 34722#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34315#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34182#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34183#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34773#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34774#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34358#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34359#L1436-3 assume !(1 == ~T8_E~0); 33946#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 33947#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 35510#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34854#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 34522#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 34523#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35765#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34461#L1476-3 assume !(1 == ~E_3~0); 34462#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34848#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34490#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 34491#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 34887#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 34888#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35310#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35301#L1516-3 assume !(1 == ~E_11~0); 35302#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 35000#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 35001#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 35393#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 34294#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 35172#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 34817#L1911 assume !(0 == start_simulation_~tmp~3); 34039#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 34463#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 34418#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 35274#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 34125#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 34126#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 34353#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 34354#L1924 assume !(0 != start_simulation_~tmp___0~1); 33995#L1892-1 [2021-11-07 08:01:44,446 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:44,446 INFO L85 PathProgramCache]: Analyzing trace with hash 841931779, now seen corresponding path program 1 times [2021-11-07 08:01:44,446 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:44,447 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1936256020] [2021-11-07 08:01:44,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:44,447 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:44,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:44,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:44,509 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:44,509 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1936256020] [2021-11-07 08:01:44,510 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1936256020] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:44,510 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:44,510 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:44,510 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1637243885] [2021-11-07 08:01:44,512 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:44,512 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:44,513 INFO L85 PathProgramCache]: Analyzing trace with hash -1256379136, now seen corresponding path program 1 times [2021-11-07 08:01:44,513 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:44,513 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [996622891] [2021-11-07 08:01:44,513 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:44,514 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:44,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:44,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:44,588 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:44,588 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [996622891] [2021-11-07 08:01:44,592 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [996622891] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:44,592 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:44,592 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:44,593 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1748242491] [2021-11-07 08:01:44,594 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:01:44,594 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:44,595 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 08:01:44,595 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 08:01:44,596 INFO L87 Difference]: Start difference. First operand 1880 states and 2792 transitions. cyclomatic complexity: 913 Second operand has 3 states, 3 states have (on average 51.666666666666664) internal successors, (155), 3 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:44,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:44,646 INFO L93 Difference]: Finished difference Result 1880 states and 2791 transitions. [2021-11-07 08:01:44,647 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 08:01:44,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1880 states and 2791 transitions. [2021-11-07 08:01:44,663 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:44,692 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1880 states to 1880 states and 2791 transitions. [2021-11-07 08:01:44,693 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1880 [2021-11-07 08:01:44,695 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1880 [2021-11-07 08:01:44,695 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1880 states and 2791 transitions. [2021-11-07 08:01:44,699 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:44,699 INFO L681 BuchiCegarLoop]: Abstraction has 1880 states and 2791 transitions. [2021-11-07 08:01:44,704 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1880 states and 2791 transitions. [2021-11-07 08:01:44,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1880 to 1880. [2021-11-07 08:01:44,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1880 states, 1880 states have (on average 1.4845744680851063) internal successors, (2791), 1879 states have internal predecessors, (2791), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:44,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1880 states to 1880 states and 2791 transitions. [2021-11-07 08:01:44,772 INFO L704 BuchiCegarLoop]: Abstraction has 1880 states and 2791 transitions. [2021-11-07 08:01:44,772 INFO L587 BuchiCegarLoop]: Abstraction has 1880 states and 2791 transitions. [2021-11-07 08:01:44,772 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-07 08:01:44,772 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1880 states and 2791 transitions. [2021-11-07 08:01:44,783 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:44,783 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:44,784 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:44,788 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:44,788 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:44,788 INFO L791 eck$LassoCheckResult]: Stem: 38533#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 38534#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 38361#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 38078#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 38079#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38963#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38214#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38215#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38661#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38495#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 38496#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38284#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38285#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38667#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 38843#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 38997#L936-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 39033#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 38297#L946-1 assume !(0 == ~M_E~0); 38298#L1258-1 assume !(0 == ~T1_E~0); 38576#L1263-1 assume !(0 == ~T2_E~0); 38577#L1268-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38877#L1273-1 assume !(0 == ~T4_E~0); 39420#L1278-1 assume !(0 == ~T5_E~0); 39286#L1283-1 assume !(0 == ~T6_E~0); 39287#L1288-1 assume !(0 == ~T7_E~0); 39516#L1293-1 assume !(0 == ~T8_E~0); 39504#L1298-1 assume !(0 == ~T9_E~0); 39432#L1303-1 assume !(0 == ~T10_E~0); 38107#L1308-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 38049#L1313-1 assume !(0 == ~T12_E~0); 38050#L1318-1 assume !(0 == ~T13_E~0); 38058#L1323-1 assume !(0 == ~E_1~0); 38059#L1328-1 assume !(0 == ~E_2~0); 38226#L1333-1 assume !(0 == ~E_3~0); 39164#L1338-1 assume !(0 == ~E_4~0); 39165#L1343-1 assume !(0 == ~E_5~0); 39260#L1348-1 assume 0 == ~E_6~0;~E_6~0 := 1; 39538#L1353-1 assume !(0 == ~E_7~0); 38896#L1358-1 assume !(0 == ~E_8~0); 38897#L1363-1 assume !(0 == ~E_9~0); 39180#L1368-1 assume !(0 == ~E_10~0); 37888#L1373-1 assume !(0 == ~E_11~0); 37889#L1378-1 assume !(0 == ~E_12~0); 38175#L1383-1 assume !(0 == ~E_13~0); 38176#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 38903#L607 assume 1 == ~m_pc~0; 38904#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 38247#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 39258#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 38822#L1560 assume !(0 != activate_threads_~tmp~1); 38823#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 38069#L626 assume 1 == ~t1_pc~0; 38070#L627 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 38337#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 38338#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 38499#L1568 assume !(0 != activate_threads_~tmp___0~0); 37971#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 37972#L645 assume !(1 == ~t2_pc~0); 38042#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 38043#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 38709#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 38710#L1576 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 38798#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 38799#L664 assume 1 == ~t3_pc~0; 39537#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 37815#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 37816#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 38466#L1584 assume !(0 != activate_threads_~tmp___2~0); 38467#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 39447#L683 assume !(1 == ~t4_pc~0); 39019#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 38971#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 38972#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 39006#L1592 assume !(0 != activate_threads_~tmp___3~0); 39126#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 38751#L702 assume 1 == ~t5_pc~0; 38752#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 38677#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 39121#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 39408#L1600 assume !(0 != activate_threads_~tmp___4~0); 39351#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 37861#L721 assume !(1 == ~t6_pc~0); 37835#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 37836#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 37996#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 38473#L1608 assume !(0 != activate_threads_~tmp___5~0); 38474#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 39064#L740 assume 1 == ~t7_pc~0; 37909#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 37721#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 37722#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 37711#L1616 assume !(0 != activate_threads_~tmp___6~0); 37712#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 38413#L759 assume !(1 == ~t8_pc~0); 38414#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 38442#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 39119#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 39120#L1624 assume !(0 != activate_threads_~tmp___7~0); 39245#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 39515#L778 assume 1 == ~t9_pc~0; 39404#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 37887#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 37828#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 37755#L1632 assume !(0 != activate_threads_~tmp___8~0); 37756#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 38083#L797 assume 1 == ~t10_pc~0; 38084#L798 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 38201#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 39309#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 38574#L1640 assume !(0 != activate_threads_~tmp___9~0); 38575#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 38861#L816 assume !(1 == ~t11_pc~0); 37795#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 37794#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 38539#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 38480#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 38481#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 38996#L835 assume 1 == ~t12_pc~0; 38874#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 37954#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 37976#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 38117#L1656 assume !(0 != activate_threads_~tmp___11~0); 38630#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 38631#L854 assume !(1 == ~t13_pc~0); 38286#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 38287#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 38333#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 37994#L1664 assume !(0 != activate_threads_~tmp___12~0); 37995#L1664-2 assume !(1 == ~M_E~0); 38784#L1401-1 assume !(1 == ~T1_E~0); 38785#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39053#L1411-1 assume !(1 == ~T3_E~0); 39054#L1416-1 assume !(1 == ~T4_E~0); 38722#L1421-1 assume !(1 == ~T5_E~0); 38282#L1426-1 assume !(1 == ~T6_E~0); 38283#L1431-1 assume !(1 == ~T7_E~0); 37831#L1436-1 assume !(1 == ~T8_E~0); 37832#L1441-1 assume !(1 == ~T9_E~0); 38569#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38570#L1451-1 assume !(1 == ~T11_E~0); 39257#L1456-1 assume !(1 == ~T12_E~0); 38921#L1461-1 assume !(1 == ~T13_E~0); 38490#L1466-1 assume !(1 == ~E_1~0); 38491#L1471-1 assume !(1 == ~E_2~0); 39243#L1476-1 assume !(1 == ~E_3~0); 39244#L1481-1 assume !(1 == ~E_4~0); 39387#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 38122#L1491-1 assume !(1 == ~E_6~0); 37763#L1496-1 assume !(1 == ~E_7~0); 37764#L1501-1 assume !(1 == ~E_8~0); 38565#L1506-1 assume !(1 == ~E_9~0); 38566#L1511-1 assume !(1 == ~E_10~0); 38522#L1516-1 assume !(1 == ~E_11~0); 37707#L1521-1 assume !(1 == ~E_12~0); 37708#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 37762#L1892-1 [2021-11-07 08:01:44,789 INFO L793 eck$LassoCheckResult]: Loop: 37762#L1892-1 assume !false; 37771#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 37883#L1233 assume !false; 39477#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 38825#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 38804#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 38964#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 37807#L1046 assume !(0 != eval_~tmp~0); 37809#L1248 start_simulation_~kernel_st~0 := 2; 37843#L874-1 start_simulation_~kernel_st~0 := 3; 38998#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 38891#L1258-4 assume !(0 == ~T1_E~0); 37982#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37983#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 39529#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39535#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 39536#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38208#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38209#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 39299#L1298-3 assume !(0 == ~T9_E~0); 39300#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 39453#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 39298#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 38809#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 37984#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37985#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 39379#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38127#L1338-3 assume !(0 == ~E_4~0); 38128#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39218#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 39385#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 39386#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38765#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 38339#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38340#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 39080#L1378-3 assume !(0 == ~E_12~0); 39081#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 39254#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 39255#L607-42 assume 1 == ~m_pc~0; 38881#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 38609#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 38610#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 38353#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 38354#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 38865#L626-42 assume 1 == ~t1_pc~0; 38439#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 38440#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 38729#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 38730#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 38018#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 38019#L645-42 assume 1 == ~t2_pc~0; 39446#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 39198#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 39356#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 38227#L1576-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 37733#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 37734#L664-42 assume 1 == ~t3_pc~0; 38528#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 38264#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 39480#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 39031#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 39032#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 39191#L683-42 assume 1 == ~t4_pc~0; 39544#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 38909#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 39038#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 39442#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 39443#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 39293#L702-42 assume 1 == ~t5_pc~0; 38791#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 38428#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 38713#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 39371#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 37747#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 37748#L721-42 assume !(1 == ~t6_pc~0); 37904#L721-44 is_transmit6_triggered_~__retres1~6 := 0; 37924#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 38384#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 39521#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 38549#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 38402#L740-42 assume 1 == ~t7_pc~0; 38403#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 38142#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 38670#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 38529#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 38530#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 38797#L759-42 assume 1 == ~t8_pc~0; 38649#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 38582#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 38583#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 38659#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 38660#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 38750#L778-42 assume 1 == ~t9_pc~0; 38593#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 38595#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 39002#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 38905#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 38906#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 38966#L797-42 assume 1 == ~t10_pc~0; 38147#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 38148#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 39131#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 39428#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 39004#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 39005#L816-42 assume 1 == ~t11_pc~0; 37697#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 37698#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 38242#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 38243#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 38321#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 38322#L835-42 assume 1 == ~t12_pc~0; 38708#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 38602#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 38295#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 38296#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 39349#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 39143#L854-42 assume 1 == ~t13_pc~0; 39144#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 38239#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 37851#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 37852#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 38488#L1664-44 assume !(1 == ~M_E~0); 38489#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38082#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 37949#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37950#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38540#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 38541#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 38125#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38126#L1436-3 assume !(1 == ~T8_E~0); 37713#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37714#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 39277#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 38621#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 38289#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 38290#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 39532#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38228#L1476-3 assume !(1 == ~E_3~0); 38229#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38615#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38257#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38258#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38654#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38655#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 39077#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 39067#L1516-3 assume !(1 == ~E_11~0); 39068#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 38767#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 38768#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 39160#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 38061#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 38939#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 38584#L1911 assume !(0 == start_simulation_~tmp~3); 37806#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 38230#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 38185#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 39041#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 37892#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 37893#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 38120#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 38121#L1924 assume !(0 != start_simulation_~tmp___0~1); 37762#L1892-1 [2021-11-07 08:01:44,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:44,790 INFO L85 PathProgramCache]: Analyzing trace with hash 997912321, now seen corresponding path program 1 times [2021-11-07 08:01:44,791 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:44,791 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1915402113] [2021-11-07 08:01:44,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:44,792 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:44,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:44,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:44,850 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:44,850 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1915402113] [2021-11-07 08:01:44,850 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1915402113] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:44,851 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:44,851 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:44,851 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [655274719] [2021-11-07 08:01:44,852 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:44,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:44,853 INFO L85 PathProgramCache]: Analyzing trace with hash 1469115838, now seen corresponding path program 1 times [2021-11-07 08:01:44,853 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:44,853 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [638627034] [2021-11-07 08:01:44,854 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:44,854 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:44,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:44,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:44,924 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:44,924 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [638627034] [2021-11-07 08:01:44,925 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [638627034] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:44,925 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:44,925 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:44,925 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [217070736] [2021-11-07 08:01:44,926 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:01:44,926 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:44,927 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 08:01:44,927 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 08:01:44,928 INFO L87 Difference]: Start difference. First operand 1880 states and 2791 transitions. cyclomatic complexity: 912 Second operand has 3 states, 3 states have (on average 51.666666666666664) internal successors, (155), 3 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:44,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:44,977 INFO L93 Difference]: Finished difference Result 1880 states and 2790 transitions. [2021-11-07 08:01:44,978 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 08:01:44,978 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1880 states and 2790 transitions. [2021-11-07 08:01:44,993 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:45,008 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1880 states to 1880 states and 2790 transitions. [2021-11-07 08:01:45,008 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1880 [2021-11-07 08:01:45,011 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1880 [2021-11-07 08:01:45,011 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1880 states and 2790 transitions. [2021-11-07 08:01:45,015 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:45,015 INFO L681 BuchiCegarLoop]: Abstraction has 1880 states and 2790 transitions. [2021-11-07 08:01:45,020 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1880 states and 2790 transitions. [2021-11-07 08:01:45,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1880 to 1880. [2021-11-07 08:01:45,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1880 states, 1880 states have (on average 1.4840425531914894) internal successors, (2790), 1879 states have internal predecessors, (2790), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:45,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1880 states to 1880 states and 2790 transitions. [2021-11-07 08:01:45,070 INFO L704 BuchiCegarLoop]: Abstraction has 1880 states and 2790 transitions. [2021-11-07 08:01:45,070 INFO L587 BuchiCegarLoop]: Abstraction has 1880 states and 2790 transitions. [2021-11-07 08:01:45,071 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-07 08:01:45,071 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1880 states and 2790 transitions. [2021-11-07 08:01:45,082 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:45,082 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:45,083 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:45,087 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:45,087 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:45,088 INFO L791 eck$LassoCheckResult]: Stem: 42300#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 42301#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 42128#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 41845#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 41846#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42730#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41981#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41982#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42426#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42262#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42263#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42051#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 42052#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 42434#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 42610#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 42764#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 42800#L941-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 42064#L946-1 assume !(0 == ~M_E~0); 42065#L1258-1 assume !(0 == ~T1_E~0); 42343#L1263-1 assume !(0 == ~T2_E~0); 42344#L1268-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 42644#L1273-1 assume !(0 == ~T4_E~0); 43187#L1278-1 assume !(0 == ~T5_E~0); 43053#L1283-1 assume !(0 == ~T6_E~0); 43054#L1288-1 assume !(0 == ~T7_E~0); 43283#L1293-1 assume !(0 == ~T8_E~0); 43271#L1298-1 assume !(0 == ~T9_E~0); 43199#L1303-1 assume !(0 == ~T10_E~0); 41874#L1308-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41816#L1313-1 assume !(0 == ~T12_E~0); 41817#L1318-1 assume !(0 == ~T13_E~0); 41823#L1323-1 assume !(0 == ~E_1~0); 41824#L1328-1 assume !(0 == ~E_2~0); 41993#L1333-1 assume !(0 == ~E_3~0); 42931#L1338-1 assume !(0 == ~E_4~0); 42932#L1343-1 assume !(0 == ~E_5~0); 43027#L1348-1 assume 0 == ~E_6~0;~E_6~0 := 1; 43305#L1353-1 assume !(0 == ~E_7~0); 42663#L1358-1 assume !(0 == ~E_8~0); 42664#L1363-1 assume !(0 == ~E_9~0); 42947#L1368-1 assume !(0 == ~E_10~0); 41655#L1373-1 assume !(0 == ~E_11~0); 41656#L1378-1 assume !(0 == ~E_12~0); 41940#L1383-1 assume !(0 == ~E_13~0); 41941#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 42670#L607 assume 1 == ~m_pc~0; 42671#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 42014#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 43025#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 42589#L1560 assume !(0 != activate_threads_~tmp~1); 42590#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 41836#L626 assume 1 == ~t1_pc~0; 41837#L627 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 42104#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 42105#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 42266#L1568 assume !(0 != activate_threads_~tmp___0~0); 41736#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 41737#L645 assume !(1 == ~t2_pc~0); 41809#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 41810#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 42476#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 42477#L1576 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 42565#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 42566#L664 assume 1 == ~t3_pc~0; 43304#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 41580#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 41581#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 42233#L1584 assume !(0 != activate_threads_~tmp___2~0); 42234#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 43214#L683 assume !(1 == ~t4_pc~0); 42786#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 42738#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 42739#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 42773#L1592 assume !(0 != activate_threads_~tmp___3~0); 42893#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 42515#L702 assume 1 == ~t5_pc~0; 42516#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 42443#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 42888#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 43175#L1600 assume !(0 != activate_threads_~tmp___4~0); 43117#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 41628#L721 assume !(1 == ~t6_pc~0); 41602#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 41603#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 41763#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 42240#L1608 assume !(0 != activate_threads_~tmp___5~0); 42241#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 42831#L740 assume 1 == ~t7_pc~0; 41676#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 41488#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 41489#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 41478#L1616 assume !(0 != activate_threads_~tmp___6~0); 41479#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 42180#L759 assume !(1 == ~t8_pc~0); 42181#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 42209#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 42886#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 42887#L1624 assume !(0 != activate_threads_~tmp___7~0); 43012#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 43282#L778 assume 1 == ~t9_pc~0; 43171#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 41654#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 41595#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 41522#L1632 assume !(0 != activate_threads_~tmp___8~0); 41523#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 41850#L797 assume 1 == ~t10_pc~0; 41851#L798 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 41968#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 43076#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 42341#L1640 assume !(0 != activate_threads_~tmp___9~0); 42342#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 42628#L816 assume !(1 == ~t11_pc~0); 41562#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 41561#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 42306#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 42247#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 42248#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 42763#L835 assume 1 == ~t12_pc~0; 42641#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 41721#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 41743#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 41884#L1656 assume !(0 != activate_threads_~tmp___11~0); 42397#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 42398#L854 assume !(1 == ~t13_pc~0); 42053#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 42054#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 42100#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 41761#L1664 assume !(0 != activate_threads_~tmp___12~0); 41762#L1664-2 assume !(1 == ~M_E~0); 42551#L1401-1 assume !(1 == ~T1_E~0); 42552#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42820#L1411-1 assume !(1 == ~T3_E~0); 42821#L1416-1 assume !(1 == ~T4_E~0); 42489#L1421-1 assume !(1 == ~T5_E~0); 42049#L1426-1 assume !(1 == ~T6_E~0); 42050#L1431-1 assume !(1 == ~T7_E~0); 41598#L1436-1 assume !(1 == ~T8_E~0); 41599#L1441-1 assume !(1 == ~T9_E~0); 42334#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 42335#L1451-1 assume !(1 == ~T11_E~0); 43024#L1456-1 assume !(1 == ~T12_E~0); 42688#L1461-1 assume !(1 == ~T13_E~0); 42257#L1466-1 assume !(1 == ~E_1~0); 42258#L1471-1 assume !(1 == ~E_2~0); 43010#L1476-1 assume !(1 == ~E_3~0); 43011#L1481-1 assume !(1 == ~E_4~0); 43154#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 41889#L1491-1 assume !(1 == ~E_6~0); 41530#L1496-1 assume !(1 == ~E_7~0); 41531#L1501-1 assume !(1 == ~E_8~0); 42332#L1506-1 assume !(1 == ~E_9~0); 42333#L1511-1 assume !(1 == ~E_10~0); 42289#L1516-1 assume !(1 == ~E_11~0); 41474#L1521-1 assume !(1 == ~E_12~0); 41475#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 41529#L1892-1 [2021-11-07 08:01:45,089 INFO L793 eck$LassoCheckResult]: Loop: 41529#L1892-1 assume !false; 41538#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 41650#L1233 assume !false; 43244#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 42592#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 42571#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 42731#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 41574#L1046 assume !(0 != eval_~tmp~0); 41576#L1248 start_simulation_~kernel_st~0 := 2; 41610#L874-1 start_simulation_~kernel_st~0 := 3; 42765#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 42658#L1258-4 assume !(0 == ~T1_E~0); 41749#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 41750#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43296#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43302#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 43303#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41973#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41974#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 43066#L1298-3 assume !(0 == ~T9_E~0); 43067#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 43220#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 43065#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 42576#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 41751#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41752#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43146#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41894#L1338-3 assume !(0 == ~E_4~0); 41895#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42985#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 43152#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 43153#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 42532#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42106#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 42107#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 42847#L1378-3 assume !(0 == ~E_12~0); 42848#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 43021#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 43022#L607-42 assume 1 == ~m_pc~0; 42648#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 42376#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 42377#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 42120#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 42121#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 42629#L626-42 assume !(1 == ~t1_pc~0); 42208#L626-44 is_transmit1_triggered_~__retres1~1 := 0; 42207#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 42496#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 42497#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 41785#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 41786#L645-42 assume !(1 == ~t2_pc~0); 42964#L645-44 is_transmit2_triggered_~__retres1~2 := 0; 42965#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 43123#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 41994#L1576-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 41500#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 41501#L664-42 assume 1 == ~t3_pc~0; 42295#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 42031#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 43247#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 42798#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 42799#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 42958#L683-42 assume !(1 == ~t4_pc~0); 42675#L683-44 is_transmit4_triggered_~__retres1~4 := 0; 42676#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 42805#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 43209#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 43210#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 43061#L702-42 assume 1 == ~t5_pc~0; 42561#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 42196#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 42482#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 43138#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 41516#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 41517#L721-42 assume 1 == ~t6_pc~0; 41671#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 41694#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 42151#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 43288#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 42316#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 42169#L740-42 assume !(1 == ~t7_pc~0); 41910#L740-44 is_transmit7_triggered_~__retres1~7 := 0; 41911#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 42437#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 42296#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 42297#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 42564#L759-42 assume 1 == ~t8_pc~0; 42416#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 42349#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 42350#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 42424#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 42425#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 42514#L778-42 assume 1 == ~t9_pc~0; 42360#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 42362#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 42768#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 42672#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 42673#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 42732#L797-42 assume 1 == ~t10_pc~0; 41914#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 41915#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 42898#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 43195#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 42771#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 42772#L816-42 assume 1 == ~t11_pc~0; 41464#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 41465#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 42009#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 42010#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 42088#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 42089#L835-42 assume !(1 == ~t12_pc~0); 42368#L835-44 is_transmit12_triggered_~__retres1~12 := 0; 42369#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 42062#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 42063#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 43116#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 42910#L854-42 assume !(1 == ~t13_pc~0); 42005#L854-44 is_transmit13_triggered_~__retres1~13 := 0; 42006#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 41618#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 41619#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 42255#L1664-44 assume !(1 == ~M_E~0); 42256#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41849#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 41716#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41717#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42307#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 42308#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41892#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 41893#L1436-3 assume !(1 == ~T8_E~0); 41480#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41481#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 43044#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 42388#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 42056#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 42057#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 43299#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41995#L1476-3 assume !(1 == ~E_3~0); 41996#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 42382#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42024#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 42025#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 42421#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 42422#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 42842#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 42834#L1516-3 assume !(1 == ~E_11~0); 42835#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 42534#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 42535#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 42927#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 41828#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 42706#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 42351#L1911 assume !(0 == start_simulation_~tmp~3); 41571#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 41997#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 41952#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 42808#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 41659#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 41660#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 41887#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 41888#L1924 assume !(0 != start_simulation_~tmp___0~1); 41529#L1892-1 [2021-11-07 08:01:45,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:45,090 INFO L85 PathProgramCache]: Analyzing trace with hash 587301955, now seen corresponding path program 1 times [2021-11-07 08:01:45,090 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:45,090 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [542359322] [2021-11-07 08:01:45,091 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:45,091 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:45,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:45,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:45,138 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:45,138 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [542359322] [2021-11-07 08:01:45,138 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [542359322] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:45,138 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:45,139 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:45,139 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [970349878] [2021-11-07 08:01:45,140 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:45,140 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:45,140 INFO L85 PathProgramCache]: Analyzing trace with hash -527944061, now seen corresponding path program 1 times [2021-11-07 08:01:45,141 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:45,141 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [767162003] [2021-11-07 08:01:45,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:45,141 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:45,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:45,221 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:45,222 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:45,222 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [767162003] [2021-11-07 08:01:45,222 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [767162003] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:45,222 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:45,223 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:45,223 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1121920633] [2021-11-07 08:01:45,224 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:01:45,224 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:45,225 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 08:01:45,225 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 08:01:45,225 INFO L87 Difference]: Start difference. First operand 1880 states and 2790 transitions. cyclomatic complexity: 911 Second operand has 3 states, 3 states have (on average 51.666666666666664) internal successors, (155), 3 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:45,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:45,273 INFO L93 Difference]: Finished difference Result 1880 states and 2789 transitions. [2021-11-07 08:01:45,273 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 08:01:45,274 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1880 states and 2789 transitions. [2021-11-07 08:01:45,288 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:45,301 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1880 states to 1880 states and 2789 transitions. [2021-11-07 08:01:45,301 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1880 [2021-11-07 08:01:45,304 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1880 [2021-11-07 08:01:45,304 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1880 states and 2789 transitions. [2021-11-07 08:01:45,307 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:45,308 INFO L681 BuchiCegarLoop]: Abstraction has 1880 states and 2789 transitions. [2021-11-07 08:01:45,311 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1880 states and 2789 transitions. [2021-11-07 08:01:45,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1880 to 1880. [2021-11-07 08:01:45,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1880 states, 1880 states have (on average 1.4835106382978724) internal successors, (2789), 1879 states have internal predecessors, (2789), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:45,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1880 states to 1880 states and 2789 transitions. [2021-11-07 08:01:45,353 INFO L704 BuchiCegarLoop]: Abstraction has 1880 states and 2789 transitions. [2021-11-07 08:01:45,353 INFO L587 BuchiCegarLoop]: Abstraction has 1880 states and 2789 transitions. [2021-11-07 08:01:45,353 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-07 08:01:45,353 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1880 states and 2789 transitions. [2021-11-07 08:01:45,361 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:45,362 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:45,362 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:45,365 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:45,365 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:45,396 INFO L791 eck$LassoCheckResult]: Stem: 46067#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 46068#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 45895#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 45612#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 45613#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46497#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45748#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45749#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46191#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46029#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46030#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45818#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45819#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46201#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 46377#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 46531#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 46567#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 45829#L946-1 assume !(0 == ~M_E~0); 45830#L1258-1 assume !(0 == ~T1_E~0); 46110#L1263-1 assume !(0 == ~T2_E~0); 46111#L1268-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 46411#L1273-1 assume !(0 == ~T4_E~0); 46954#L1278-1 assume !(0 == ~T5_E~0); 46820#L1283-1 assume !(0 == ~T6_E~0); 46821#L1288-1 assume !(0 == ~T7_E~0); 47050#L1293-1 assume !(0 == ~T8_E~0); 47038#L1298-1 assume !(0 == ~T9_E~0); 46966#L1303-1 assume !(0 == ~T10_E~0); 45641#L1308-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 45583#L1313-1 assume !(0 == ~T12_E~0); 45584#L1318-1 assume !(0 == ~T13_E~0); 45590#L1323-1 assume !(0 == ~E_1~0); 45591#L1328-1 assume !(0 == ~E_2~0); 45760#L1333-1 assume !(0 == ~E_3~0); 46698#L1338-1 assume !(0 == ~E_4~0); 46699#L1343-1 assume !(0 == ~E_5~0); 46794#L1348-1 assume 0 == ~E_6~0;~E_6~0 := 1; 47072#L1353-1 assume !(0 == ~E_7~0); 46430#L1358-1 assume !(0 == ~E_8~0); 46431#L1363-1 assume !(0 == ~E_9~0); 46714#L1368-1 assume !(0 == ~E_10~0); 45422#L1373-1 assume !(0 == ~E_11~0); 45423#L1378-1 assume !(0 == ~E_12~0); 45707#L1383-1 assume !(0 == ~E_13~0); 45708#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 46437#L607 assume 1 == ~m_pc~0; 46438#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 45781#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 46792#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 46356#L1560 assume !(0 != activate_threads_~tmp~1); 46357#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 45603#L626 assume 1 == ~t1_pc~0; 45604#L627 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 45871#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 45872#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 46033#L1568 assume !(0 != activate_threads_~tmp___0~0); 45503#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 45504#L645 assume !(1 == ~t2_pc~0); 45576#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 45577#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 46240#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 46241#L1576 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 46332#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 46333#L664 assume 1 == ~t3_pc~0; 47071#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 45347#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 45348#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 46000#L1584 assume !(0 != activate_threads_~tmp___2~0); 46001#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 46981#L683 assume !(1 == ~t4_pc~0); 46553#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 46505#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 46506#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 46540#L1592 assume !(0 != activate_threads_~tmp___3~0); 46660#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 46281#L702 assume 1 == ~t5_pc~0; 46282#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 46210#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 46655#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 46941#L1600 assume !(0 != activate_threads_~tmp___4~0); 46884#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 45395#L721 assume !(1 == ~t6_pc~0); 45369#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 45370#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 45530#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 46007#L1608 assume !(0 != activate_threads_~tmp___5~0); 46008#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 46598#L740 assume 1 == ~t7_pc~0; 45443#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 45255#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 45256#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 45245#L1616 assume !(0 != activate_threads_~tmp___6~0); 45246#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 45946#L759 assume !(1 == ~t8_pc~0); 45947#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 45976#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 46653#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 46654#L1624 assume !(0 != activate_threads_~tmp___7~0); 46779#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 47049#L778 assume 1 == ~t9_pc~0; 46938#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 45421#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 45362#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 45289#L1632 assume !(0 != activate_threads_~tmp___8~0); 45290#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 45616#L797 assume 1 == ~t10_pc~0; 45617#L798 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 45735#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 46843#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 46108#L1640 assume !(0 != activate_threads_~tmp___9~0); 46109#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 46395#L816 assume !(1 == ~t11_pc~0); 45329#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 45328#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 46071#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 46014#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 46015#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 46530#L835 assume 1 == ~t12_pc~0; 46408#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 45488#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 45510#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 45651#L1656 assume !(0 != activate_threads_~tmp___11~0); 46164#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 46165#L854 assume !(1 == ~t13_pc~0); 45820#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 45821#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 45867#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 45528#L1664 assume !(0 != activate_threads_~tmp___12~0); 45529#L1664-2 assume !(1 == ~M_E~0); 46318#L1401-1 assume !(1 == ~T1_E~0); 46319#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46587#L1411-1 assume !(1 == ~T3_E~0); 46588#L1416-1 assume !(1 == ~T4_E~0); 46256#L1421-1 assume !(1 == ~T5_E~0); 45816#L1426-1 assume !(1 == ~T6_E~0); 45817#L1431-1 assume !(1 == ~T7_E~0); 45365#L1436-1 assume !(1 == ~T8_E~0); 45366#L1441-1 assume !(1 == ~T9_E~0); 46101#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46102#L1451-1 assume !(1 == ~T11_E~0); 46791#L1456-1 assume !(1 == ~T12_E~0); 46455#L1461-1 assume !(1 == ~T13_E~0); 46024#L1466-1 assume !(1 == ~E_1~0); 46025#L1471-1 assume !(1 == ~E_2~0); 46777#L1476-1 assume !(1 == ~E_3~0); 46778#L1481-1 assume !(1 == ~E_4~0); 46921#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 45656#L1491-1 assume !(1 == ~E_6~0); 45297#L1496-1 assume !(1 == ~E_7~0); 45298#L1501-1 assume !(1 == ~E_8~0); 46099#L1506-1 assume !(1 == ~E_9~0); 46100#L1511-1 assume !(1 == ~E_10~0); 46056#L1516-1 assume !(1 == ~E_11~0); 45241#L1521-1 assume !(1 == ~E_12~0); 45242#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 45296#L1892-1 [2021-11-07 08:01:45,396 INFO L793 eck$LassoCheckResult]: Loop: 45296#L1892-1 assume !false; 45305#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 45417#L1233 assume !false; 47011#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 46359#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 46338#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 46498#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 45341#L1046 assume !(0 != eval_~tmp~0); 45343#L1248 start_simulation_~kernel_st~0 := 2; 45377#L874-1 start_simulation_~kernel_st~0 := 3; 46532#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 46425#L1258-4 assume !(0 == ~T1_E~0); 45516#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 45517#L1268-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47063#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47069#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47070#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 45740#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45741#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 46833#L1298-3 assume !(0 == ~T9_E~0); 46834#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 46987#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 46832#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 46343#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 45518#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45519#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46913#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 45661#L1338-3 assume !(0 == ~E_4~0); 45662#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46752#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 46918#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 46919#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 46297#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 45873#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 45874#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 46614#L1378-3 assume !(0 == ~E_12~0); 46615#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 46788#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 46789#L607-42 assume !(1 == ~m_pc~0); 46416#L607-44 is_master_triggered_~__retres1~0 := 0; 46143#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 46144#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 45887#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 45888#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 46396#L626-42 assume 1 == ~t1_pc~0; 45973#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 45974#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 46263#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 46264#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 45552#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 45553#L645-42 assume 1 == ~t2_pc~0; 46980#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 46732#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 46890#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 45761#L1576-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 45267#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 45268#L664-42 assume !(1 == ~t3_pc~0); 45796#L664-44 is_transmit3_triggered_~__retres1~3 := 0; 45797#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 47014#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 46565#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 46566#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 46725#L683-42 assume 1 == ~t4_pc~0; 47078#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 46441#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 46572#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 46976#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 46977#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 46828#L702-42 assume 1 == ~t5_pc~0; 46328#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 45963#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 46247#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 46905#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 45283#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 45284#L721-42 assume 1 == ~t6_pc~0; 45438#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 45461#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 45918#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 47055#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 46083#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 45936#L740-42 assume 1 == ~t7_pc~0; 45937#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 45676#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 46204#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 46063#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 46064#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 46331#L759-42 assume 1 == ~t8_pc~0; 46185#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 46116#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 46117#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 46194#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 46195#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 46286#L778-42 assume 1 == ~t9_pc~0; 46130#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 46132#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 46537#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 46442#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 46443#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 46500#L797-42 assume 1 == ~t10_pc~0; 45684#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 45685#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 46665#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 46962#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 46538#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 46539#L816-42 assume 1 == ~t11_pc~0; 45234#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 45235#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 45778#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 45779#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 45855#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 45856#L835-42 assume 1 == ~t12_pc~0; 46244#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 46139#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 45831#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 45832#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 46883#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 46677#L854-42 assume 1 == ~t13_pc~0; 46678#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 45775#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 45385#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 45386#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 46022#L1664-44 assume !(1 == ~M_E~0); 46023#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45619#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 45485#L1411-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 45486#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46074#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 46075#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 45659#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 45660#L1436-3 assume !(1 == ~T8_E~0); 45247#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 45248#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46812#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46155#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 45823#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 45824#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47066#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 45762#L1476-3 assume !(1 == ~E_3~0); 45763#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46149#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 45791#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 45792#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 46189#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 46190#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 46611#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 46602#L1516-3 assume !(1 == ~E_11~0); 46603#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 46301#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 46302#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 46696#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 45595#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 46473#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 46118#L1911 assume !(0 == start_simulation_~tmp~3); 45338#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 45764#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 45719#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 46575#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 45426#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 45427#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 45654#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 45655#L1924 assume !(0 != start_simulation_~tmp___0~1); 45296#L1892-1 [2021-11-07 08:01:45,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:45,397 INFO L85 PathProgramCache]: Analyzing trace with hash -1919795519, now seen corresponding path program 1 times [2021-11-07 08:01:45,397 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:45,397 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2011134219] [2021-11-07 08:01:45,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:45,398 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:45,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:45,451 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:45,451 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:45,451 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2011134219] [2021-11-07 08:01:45,451 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2011134219] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:45,452 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:45,452 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 08:01:45,452 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1402280453] [2021-11-07 08:01:45,454 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:45,454 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:45,454 INFO L85 PathProgramCache]: Analyzing trace with hash 107006847, now seen corresponding path program 1 times [2021-11-07 08:01:45,454 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:45,455 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364061912] [2021-11-07 08:01:45,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:45,455 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:45,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:45,497 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:45,497 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:45,498 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [364061912] [2021-11-07 08:01:45,498 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [364061912] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:45,498 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:45,498 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:45,498 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1652703027] [2021-11-07 08:01:45,499 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:01:45,499 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:45,500 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 08:01:45,500 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 08:01:45,500 INFO L87 Difference]: Start difference. First operand 1880 states and 2789 transitions. cyclomatic complexity: 910 Second operand has 3 states, 3 states have (on average 51.666666666666664) internal successors, (155), 2 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:45,537 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:45,537 INFO L93 Difference]: Finished difference Result 1880 states and 2784 transitions. [2021-11-07 08:01:45,537 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 08:01:45,537 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1880 states and 2784 transitions. [2021-11-07 08:01:45,548 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:45,572 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1880 states to 1880 states and 2784 transitions. [2021-11-07 08:01:45,573 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1880 [2021-11-07 08:01:45,575 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1880 [2021-11-07 08:01:45,575 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1880 states and 2784 transitions. [2021-11-07 08:01:45,579 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:45,579 INFO L681 BuchiCegarLoop]: Abstraction has 1880 states and 2784 transitions. [2021-11-07 08:01:45,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1880 states and 2784 transitions. [2021-11-07 08:01:45,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1880 to 1880. [2021-11-07 08:01:45,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1880 states, 1880 states have (on average 1.4808510638297872) internal successors, (2784), 1879 states have internal predecessors, (2784), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:45,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1880 states to 1880 states and 2784 transitions. [2021-11-07 08:01:45,625 INFO L704 BuchiCegarLoop]: Abstraction has 1880 states and 2784 transitions. [2021-11-07 08:01:45,625 INFO L587 BuchiCegarLoop]: Abstraction has 1880 states and 2784 transitions. [2021-11-07 08:01:45,625 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-07 08:01:45,625 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1880 states and 2784 transitions. [2021-11-07 08:01:45,635 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:45,635 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:45,635 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:45,639 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:45,639 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:45,640 INFO L791 eck$LassoCheckResult]: Stem: 49834#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 49835#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 49662#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 49379#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 49380#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50264#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49515#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49516#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 49958#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 49796#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49797#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49585#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49586#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 49968#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 50144#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 50298#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 50334#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 49596#L946-1 assume !(0 == ~M_E~0); 49597#L1258-1 assume !(0 == ~T1_E~0); 49877#L1263-1 assume !(0 == ~T2_E~0); 49878#L1268-1 assume !(0 == ~T3_E~0); 50178#L1273-1 assume !(0 == ~T4_E~0); 50721#L1278-1 assume !(0 == ~T5_E~0); 50587#L1283-1 assume !(0 == ~T6_E~0); 50588#L1288-1 assume !(0 == ~T7_E~0); 50817#L1293-1 assume !(0 == ~T8_E~0); 50805#L1298-1 assume !(0 == ~T9_E~0); 50733#L1303-1 assume !(0 == ~T10_E~0); 49408#L1308-1 assume 0 == ~T11_E~0;~T11_E~0 := 1; 49350#L1313-1 assume !(0 == ~T12_E~0); 49351#L1318-1 assume !(0 == ~T13_E~0); 49357#L1323-1 assume !(0 == ~E_1~0); 49358#L1328-1 assume !(0 == ~E_2~0); 49525#L1333-1 assume !(0 == ~E_3~0); 50465#L1338-1 assume !(0 == ~E_4~0); 50466#L1343-1 assume !(0 == ~E_5~0); 50561#L1348-1 assume 0 == ~E_6~0;~E_6~0 := 1; 50839#L1353-1 assume !(0 == ~E_7~0); 50197#L1358-1 assume !(0 == ~E_8~0); 50198#L1363-1 assume !(0 == ~E_9~0); 50481#L1368-1 assume !(0 == ~E_10~0); 49189#L1373-1 assume !(0 == ~E_11~0); 49190#L1378-1 assume !(0 == ~E_12~0); 49474#L1383-1 assume !(0 == ~E_13~0); 49475#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 50204#L607 assume 1 == ~m_pc~0; 50205#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 49548#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 50559#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 50123#L1560 assume !(0 != activate_threads_~tmp~1); 50124#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 49370#L626 assume 1 == ~t1_pc~0; 49371#L627 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 49638#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 49639#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 49800#L1568 assume !(0 != activate_threads_~tmp___0~0); 49270#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 49271#L645 assume !(1 == ~t2_pc~0); 49343#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 49344#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 50007#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 50008#L1576 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 50099#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 50100#L664 assume 1 == ~t3_pc~0; 50838#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 49114#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 49115#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 49767#L1584 assume !(0 != activate_threads_~tmp___2~0); 49768#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 50748#L683 assume !(1 == ~t4_pc~0); 50320#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 50272#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 50273#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 50307#L1592 assume !(0 != activate_threads_~tmp___3~0); 50427#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 50048#L702 assume 1 == ~t5_pc~0; 50049#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 49977#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 50422#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 50708#L1600 assume !(0 != activate_threads_~tmp___4~0); 50651#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 49162#L721 assume !(1 == ~t6_pc~0); 49136#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 49137#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 49297#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 49774#L1608 assume !(0 != activate_threads_~tmp___5~0); 49775#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 50365#L740 assume 1 == ~t7_pc~0; 49210#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 49022#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 49023#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 49012#L1616 assume !(0 != activate_threads_~tmp___6~0); 49013#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 49713#L759 assume !(1 == ~t8_pc~0); 49714#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 49743#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 50420#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 50421#L1624 assume !(0 != activate_threads_~tmp___7~0); 50546#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 50816#L778 assume 1 == ~t9_pc~0; 50705#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 49188#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 49129#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 49056#L1632 assume !(0 != activate_threads_~tmp___8~0); 49057#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 49383#L797 assume 1 == ~t10_pc~0; 49384#L798 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 49502#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 50610#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 49875#L1640 assume !(0 != activate_threads_~tmp___9~0); 49876#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 50162#L816 assume !(1 == ~t11_pc~0); 49096#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 49095#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 49838#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 49781#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 49782#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 50297#L835 assume 1 == ~t12_pc~0; 50175#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 49255#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 49277#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 49418#L1656 assume !(0 != activate_threads_~tmp___11~0); 49931#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 49932#L854 assume !(1 == ~t13_pc~0); 49587#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 49588#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 49634#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 49295#L1664 assume !(0 != activate_threads_~tmp___12~0); 49296#L1664-2 assume !(1 == ~M_E~0); 50085#L1401-1 assume !(1 == ~T1_E~0); 50086#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50354#L1411-1 assume !(1 == ~T3_E~0); 50355#L1416-1 assume !(1 == ~T4_E~0); 50023#L1421-1 assume !(1 == ~T5_E~0); 49583#L1426-1 assume !(1 == ~T6_E~0); 49584#L1431-1 assume !(1 == ~T7_E~0); 49132#L1436-1 assume !(1 == ~T8_E~0); 49133#L1441-1 assume !(1 == ~T9_E~0); 49868#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 49869#L1451-1 assume !(1 == ~T11_E~0); 50558#L1456-1 assume !(1 == ~T12_E~0); 50222#L1461-1 assume !(1 == ~T13_E~0); 49791#L1466-1 assume !(1 == ~E_1~0); 49792#L1471-1 assume !(1 == ~E_2~0); 50544#L1476-1 assume !(1 == ~E_3~0); 50545#L1481-1 assume !(1 == ~E_4~0); 50688#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 49423#L1491-1 assume !(1 == ~E_6~0); 49064#L1496-1 assume !(1 == ~E_7~0); 49065#L1501-1 assume !(1 == ~E_8~0); 49866#L1506-1 assume !(1 == ~E_9~0); 49867#L1511-1 assume !(1 == ~E_10~0); 49823#L1516-1 assume !(1 == ~E_11~0); 49008#L1521-1 assume !(1 == ~E_12~0); 49009#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 49063#L1892-1 [2021-11-07 08:01:45,640 INFO L793 eck$LassoCheckResult]: Loop: 49063#L1892-1 assume !false; 49072#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 49184#L1233 assume !false; 50778#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 50126#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 50105#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 50265#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 49108#L1046 assume !(0 != eval_~tmp~0); 49110#L1248 start_simulation_~kernel_st~0 := 2; 49144#L874-1 start_simulation_~kernel_st~0 := 3; 50299#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 50192#L1258-4 assume !(0 == ~T1_E~0); 49283#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 49284#L1268-3 assume !(0 == ~T3_E~0); 50830#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 50836#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 50837#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49507#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49508#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 50600#L1298-3 assume !(0 == ~T9_E~0); 50601#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 50754#L1308-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 50599#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 50110#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 49285#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49286#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 50680#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49428#L1338-3 assume !(0 == ~E_4~0); 49429#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50519#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 50685#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 50686#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 50064#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 49640#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 49641#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 50381#L1378-3 assume !(0 == ~E_12~0); 50382#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 50555#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 50556#L607-42 assume 1 == ~m_pc~0; 50180#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 49910#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 49911#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 49654#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 49655#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 50163#L626-42 assume 1 == ~t1_pc~0; 49737#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 49738#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 50030#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 50031#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 49319#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 49320#L645-42 assume !(1 == ~t2_pc~0); 50498#L645-44 is_transmit2_triggered_~__retres1~2 := 0; 50499#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 50657#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 49528#L1576-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 49034#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 49035#L664-42 assume 1 == ~t3_pc~0; 49827#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 49564#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 50781#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 50332#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 50333#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 50492#L683-42 assume 1 == ~t4_pc~0; 50845#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 50208#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 50339#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 50743#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 50744#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 50594#L702-42 assume !(1 == ~t5_pc~0); 49729#L702-44 is_transmit5_triggered_~__retres1~5 := 0; 49730#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 50014#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 50672#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 49050#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 49051#L721-42 assume 1 == ~t6_pc~0; 49205#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 49225#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 49685#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 50822#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 49850#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 49703#L740-42 assume !(1 == ~t7_pc~0); 49442#L740-44 is_transmit7_triggered_~__retres1~7 := 0; 49443#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 49971#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 49830#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 49831#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 50098#L759-42 assume 1 == ~t8_pc~0; 49950#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 49883#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 49884#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 49961#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 49962#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 50053#L778-42 assume 1 == ~t9_pc~0; 49894#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 49896#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 50304#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 50209#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 50210#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 50267#L797-42 assume 1 == ~t10_pc~0; 49448#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 49449#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 50432#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 50729#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 50305#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 50306#L816-42 assume 1 == ~t11_pc~0; 48998#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 48999#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 49543#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 49544#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 49622#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 49623#L835-42 assume !(1 == ~t12_pc~0); 49905#L835-44 is_transmit12_triggered_~__retres1~12 := 0; 49906#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 49598#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 49599#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 50650#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 50444#L854-42 assume !(1 == ~t13_pc~0); 49541#L854-44 is_transmit13_triggered_~__retres1~13 := 0; 49542#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 49152#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 49153#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 49789#L1664-44 assume !(1 == ~M_E~0); 49790#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49386#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 49250#L1411-3 assume !(1 == ~T3_E~0); 49251#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49841#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49842#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49426#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49427#L1436-3 assume !(1 == ~T8_E~0); 49014#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49015#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50578#L1451-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49922#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 49590#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 49591#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 50833#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49529#L1476-3 assume !(1 == ~E_3~0); 49530#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49916#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49558#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49559#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49956#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49957#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 50378#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 50369#L1516-3 assume !(1 == ~E_11~0); 50370#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50068#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 50069#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 50461#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 49362#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 50240#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 49885#L1911 assume !(0 == start_simulation_~tmp~3); 49107#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 49531#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 49486#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 50342#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 49193#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 49194#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 49421#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 49422#L1924 assume !(0 != start_simulation_~tmp___0~1); 49063#L1892-1 [2021-11-07 08:01:45,641 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:45,641 INFO L85 PathProgramCache]: Analyzing trace with hash -520841917, now seen corresponding path program 1 times [2021-11-07 08:01:45,642 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:45,642 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1627445384] [2021-11-07 08:01:45,642 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:45,642 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:45,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:45,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:45,695 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:45,696 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1627445384] [2021-11-07 08:01:45,696 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1627445384] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:45,696 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:45,696 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 08:01:45,697 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [494793914] [2021-11-07 08:01:45,697 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:45,698 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:45,698 INFO L85 PathProgramCache]: Analyzing trace with hash -617787838, now seen corresponding path program 1 times [2021-11-07 08:01:45,698 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:45,698 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [21315855] [2021-11-07 08:01:45,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:45,699 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:45,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:45,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:45,756 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:45,756 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [21315855] [2021-11-07 08:01:45,756 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [21315855] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:45,756 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:45,757 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:45,757 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1508187747] [2021-11-07 08:01:45,757 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:01:45,758 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:45,760 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 08:01:45,761 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 08:01:45,761 INFO L87 Difference]: Start difference. First operand 1880 states and 2784 transitions. cyclomatic complexity: 905 Second operand has 3 states, 3 states have (on average 51.666666666666664) internal successors, (155), 2 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:45,805 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:45,805 INFO L93 Difference]: Finished difference Result 1880 states and 2779 transitions. [2021-11-07 08:01:45,806 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 08:01:45,807 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1880 states and 2779 transitions. [2021-11-07 08:01:45,819 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:45,834 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1880 states to 1880 states and 2779 transitions. [2021-11-07 08:01:45,834 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1880 [2021-11-07 08:01:45,837 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1880 [2021-11-07 08:01:45,837 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1880 states and 2779 transitions. [2021-11-07 08:01:45,841 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:45,841 INFO L681 BuchiCegarLoop]: Abstraction has 1880 states and 2779 transitions. [2021-11-07 08:01:45,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1880 states and 2779 transitions. [2021-11-07 08:01:45,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1880 to 1880. [2021-11-07 08:01:45,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1880 states, 1880 states have (on average 1.478191489361702) internal successors, (2779), 1879 states have internal predecessors, (2779), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:45,888 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1880 states to 1880 states and 2779 transitions. [2021-11-07 08:01:45,888 INFO L704 BuchiCegarLoop]: Abstraction has 1880 states and 2779 transitions. [2021-11-07 08:01:45,888 INFO L587 BuchiCegarLoop]: Abstraction has 1880 states and 2779 transitions. [2021-11-07 08:01:45,888 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-07 08:01:45,889 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1880 states and 2779 transitions. [2021-11-07 08:01:45,898 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:45,899 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:45,899 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:45,903 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:45,903 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:45,904 INFO L791 eck$LassoCheckResult]: Stem: 53601#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 53602#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 53429#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 53146#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 53147#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54031#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53282#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53283#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53725#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53563#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53564#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53352#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53353#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 53735#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 53911#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 54065#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 54101#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 53363#L946-1 assume !(0 == ~M_E~0); 53364#L1258-1 assume !(0 == ~T1_E~0); 53644#L1263-1 assume !(0 == ~T2_E~0); 53645#L1268-1 assume !(0 == ~T3_E~0); 53945#L1273-1 assume !(0 == ~T4_E~0); 54488#L1278-1 assume !(0 == ~T5_E~0); 54354#L1283-1 assume !(0 == ~T6_E~0); 54355#L1288-1 assume !(0 == ~T7_E~0); 54584#L1293-1 assume !(0 == ~T8_E~0); 54572#L1298-1 assume !(0 == ~T9_E~0); 54500#L1303-1 assume !(0 == ~T10_E~0); 53175#L1308-1 assume !(0 == ~T11_E~0); 53117#L1313-1 assume !(0 == ~T12_E~0); 53118#L1318-1 assume !(0 == ~T13_E~0); 53124#L1323-1 assume !(0 == ~E_1~0); 53125#L1328-1 assume !(0 == ~E_2~0); 53292#L1333-1 assume !(0 == ~E_3~0); 54232#L1338-1 assume !(0 == ~E_4~0); 54233#L1343-1 assume !(0 == ~E_5~0); 54328#L1348-1 assume 0 == ~E_6~0;~E_6~0 := 1; 54606#L1353-1 assume !(0 == ~E_7~0); 53964#L1358-1 assume !(0 == ~E_8~0); 53965#L1363-1 assume !(0 == ~E_9~0); 54248#L1368-1 assume !(0 == ~E_10~0); 52956#L1373-1 assume !(0 == ~E_11~0); 52957#L1378-1 assume !(0 == ~E_12~0); 53241#L1383-1 assume !(0 == ~E_13~0); 53242#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 53971#L607 assume 1 == ~m_pc~0; 53972#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 53315#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 54326#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 53890#L1560 assume !(0 != activate_threads_~tmp~1); 53891#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 53137#L626 assume 1 == ~t1_pc~0; 53138#L627 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 53405#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 53406#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 53567#L1568 assume !(0 != activate_threads_~tmp___0~0); 53037#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 53038#L645 assume !(1 == ~t2_pc~0); 53110#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 53111#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 53774#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 53775#L1576 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 53866#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 53867#L664 assume 1 == ~t3_pc~0; 54605#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 52881#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 52882#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 53534#L1584 assume !(0 != activate_threads_~tmp___2~0); 53535#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 54515#L683 assume !(1 == ~t4_pc~0); 54087#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 54039#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 54040#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 54074#L1592 assume !(0 != activate_threads_~tmp___3~0); 54194#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 53815#L702 assume 1 == ~t5_pc~0; 53816#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 53744#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 54189#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 54475#L1600 assume !(0 != activate_threads_~tmp___4~0); 54418#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 52929#L721 assume !(1 == ~t6_pc~0); 52903#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 52904#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 53064#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 53541#L1608 assume !(0 != activate_threads_~tmp___5~0); 53542#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 54132#L740 assume 1 == ~t7_pc~0; 52977#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 52789#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 52790#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 52779#L1616 assume !(0 != activate_threads_~tmp___6~0); 52780#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 53480#L759 assume !(1 == ~t8_pc~0); 53481#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 53510#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 54187#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 54188#L1624 assume !(0 != activate_threads_~tmp___7~0); 54313#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 54583#L778 assume 1 == ~t9_pc~0; 54472#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 52955#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 52896#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 52823#L1632 assume !(0 != activate_threads_~tmp___8~0); 52824#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 53150#L797 assume 1 == ~t10_pc~0; 53151#L798 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 53269#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 54377#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 53642#L1640 assume !(0 != activate_threads_~tmp___9~0); 53643#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 53929#L816 assume !(1 == ~t11_pc~0); 52863#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 52862#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 53605#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 53548#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 53549#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 54064#L835 assume 1 == ~t12_pc~0; 53942#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 53022#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 53044#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 53185#L1656 assume !(0 != activate_threads_~tmp___11~0); 53698#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 53699#L854 assume !(1 == ~t13_pc~0); 53354#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 53355#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 53401#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 53062#L1664 assume !(0 != activate_threads_~tmp___12~0); 53063#L1664-2 assume !(1 == ~M_E~0); 53852#L1401-1 assume !(1 == ~T1_E~0); 53853#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54121#L1411-1 assume !(1 == ~T3_E~0); 54122#L1416-1 assume !(1 == ~T4_E~0); 53790#L1421-1 assume !(1 == ~T5_E~0); 53350#L1426-1 assume !(1 == ~T6_E~0); 53351#L1431-1 assume !(1 == ~T7_E~0); 52899#L1436-1 assume !(1 == ~T8_E~0); 52900#L1441-1 assume !(1 == ~T9_E~0); 53635#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 53636#L1451-1 assume !(1 == ~T11_E~0); 54325#L1456-1 assume !(1 == ~T12_E~0); 53989#L1461-1 assume !(1 == ~T13_E~0); 53558#L1466-1 assume !(1 == ~E_1~0); 53559#L1471-1 assume !(1 == ~E_2~0); 54311#L1476-1 assume !(1 == ~E_3~0); 54312#L1481-1 assume !(1 == ~E_4~0); 54455#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 53190#L1491-1 assume !(1 == ~E_6~0); 52831#L1496-1 assume !(1 == ~E_7~0); 52832#L1501-1 assume !(1 == ~E_8~0); 53633#L1506-1 assume !(1 == ~E_9~0); 53634#L1511-1 assume !(1 == ~E_10~0); 53590#L1516-1 assume !(1 == ~E_11~0); 52775#L1521-1 assume !(1 == ~E_12~0); 52776#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 52830#L1892-1 [2021-11-07 08:01:45,905 INFO L793 eck$LassoCheckResult]: Loop: 52830#L1892-1 assume !false; 52839#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 52951#L1233 assume !false; 54545#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 53893#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 53872#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 54032#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 52875#L1046 assume !(0 != eval_~tmp~0); 52877#L1248 start_simulation_~kernel_st~0 := 2; 52911#L874-1 start_simulation_~kernel_st~0 := 3; 54066#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 53959#L1258-4 assume !(0 == ~T1_E~0); 53050#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 53051#L1268-3 assume !(0 == ~T3_E~0); 54597#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 54603#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 54604#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 53274#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53275#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 54367#L1298-3 assume !(0 == ~T9_E~0); 54368#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 54521#L1308-3 assume !(0 == ~T11_E~0); 54366#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 53877#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 53052#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53053#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 54447#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 53195#L1338-3 assume !(0 == ~E_4~0); 53196#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54286#L1348-3 assume 0 == ~E_6~0;~E_6~0 := 1; 54452#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 54453#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53831#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 53407#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 53408#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 54148#L1378-3 assume !(0 == ~E_12~0); 54149#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 54322#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 54323#L607-42 assume 1 == ~m_pc~0; 53947#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 53677#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 53678#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 53421#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 53422#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 53930#L626-42 assume 1 == ~t1_pc~0; 53504#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 53505#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 53797#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 53798#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 53086#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 53087#L645-42 assume 1 == ~t2_pc~0; 54514#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 54266#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 54424#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 53295#L1576-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 52801#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 52802#L664-42 assume !(1 == ~t3_pc~0); 53330#L664-44 is_transmit3_triggered_~__retres1~3 := 0; 53331#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 54548#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 54099#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 54100#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 54259#L683-42 assume 1 == ~t4_pc~0; 54612#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 53975#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 54106#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 54510#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 54511#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 54361#L702-42 assume 1 == ~t5_pc~0; 53859#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 53497#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 53781#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 54439#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 52817#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 52818#L721-42 assume 1 == ~t6_pc~0; 52972#L722-14 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 52992#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 53452#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 54589#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 53617#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 53470#L740-42 assume !(1 == ~t7_pc~0); 53209#L740-44 is_transmit7_triggered_~__retres1~7 := 0; 53210#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 53738#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 53597#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 53598#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 53865#L759-42 assume 1 == ~t8_pc~0; 53717#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 53650#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 53651#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 53728#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 53729#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 53820#L778-42 assume 1 == ~t9_pc~0; 53661#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 53663#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 54071#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 53976#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 53977#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 54034#L797-42 assume !(1 == ~t10_pc~0); 53217#L797-44 is_transmit10_triggered_~__retres1~10 := 0; 53216#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 54199#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 54496#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 54072#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 54073#L816-42 assume 1 == ~t11_pc~0; 52765#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 52766#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 53310#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 53311#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 53389#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 53390#L835-42 assume 1 == ~t12_pc~0; 53778#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 53673#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 53365#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 53366#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 54417#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 54211#L854-42 assume 1 == ~t13_pc~0; 54212#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 53309#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 52919#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 52920#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 53556#L1664-44 assume !(1 == ~M_E~0); 53557#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 53153#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53017#L1411-3 assume !(1 == ~T3_E~0); 53018#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 53608#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53609#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53193#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 53194#L1436-3 assume !(1 == ~T8_E~0); 52781#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 52782#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54345#L1451-3 assume !(1 == ~T11_E~0); 53689#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 53357#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 53358#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54600#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 53296#L1476-3 assume !(1 == ~E_3~0); 53297#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53683#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53325#L1491-3 assume 1 == ~E_6~0;~E_6~0 := 2; 53326#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53723#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53724#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 54145#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 54136#L1516-3 assume !(1 == ~E_11~0); 54137#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 53835#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 53836#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 54228#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 53129#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 54007#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 53652#L1911 assume !(0 == start_simulation_~tmp~3); 52874#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 53298#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 53253#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 54109#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 52960#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 52961#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 53188#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 53189#L1924 assume !(0 != start_simulation_~tmp___0~1); 52830#L1892-1 [2021-11-07 08:01:45,907 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:45,907 INFO L85 PathProgramCache]: Analyzing trace with hash -955347515, now seen corresponding path program 1 times [2021-11-07 08:01:45,907 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:45,907 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1750031263] [2021-11-07 08:01:45,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:45,908 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:45,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:45,955 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:45,956 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:45,956 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1750031263] [2021-11-07 08:01:45,956 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1750031263] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:45,956 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:45,956 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 08:01:45,957 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2080844964] [2021-11-07 08:01:45,957 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:45,958 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:45,958 INFO L85 PathProgramCache]: Analyzing trace with hash -1119498304, now seen corresponding path program 1 times [2021-11-07 08:01:45,958 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:45,958 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [324037258] [2021-11-07 08:01:45,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:45,959 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:45,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:46,014 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:46,015 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:46,015 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [324037258] [2021-11-07 08:01:46,015 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [324037258] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:46,016 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:46,017 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:46,017 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [633877728] [2021-11-07 08:01:46,018 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:01:46,018 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:46,018 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 08:01:46,018 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 08:01:46,019 INFO L87 Difference]: Start difference. First operand 1880 states and 2779 transitions. cyclomatic complexity: 900 Second operand has 3 states, 3 states have (on average 51.666666666666664) internal successors, (155), 2 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:46,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:46,110 INFO L93 Difference]: Finished difference Result 1880 states and 2759 transitions. [2021-11-07 08:01:46,111 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 08:01:46,111 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1880 states and 2759 transitions. [2021-11-07 08:01:46,122 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:46,131 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1880 states to 1880 states and 2759 transitions. [2021-11-07 08:01:46,132 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1880 [2021-11-07 08:01:46,134 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1880 [2021-11-07 08:01:46,134 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1880 states and 2759 transitions. [2021-11-07 08:01:46,137 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:46,138 INFO L681 BuchiCegarLoop]: Abstraction has 1880 states and 2759 transitions. [2021-11-07 08:01:46,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1880 states and 2759 transitions. [2021-11-07 08:01:46,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1880 to 1880. [2021-11-07 08:01:46,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1880 states, 1880 states have (on average 1.4675531914893618) internal successors, (2759), 1879 states have internal predecessors, (2759), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:46,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1880 states to 1880 states and 2759 transitions. [2021-11-07 08:01:46,180 INFO L704 BuchiCegarLoop]: Abstraction has 1880 states and 2759 transitions. [2021-11-07 08:01:46,180 INFO L587 BuchiCegarLoop]: Abstraction has 1880 states and 2759 transitions. [2021-11-07 08:01:46,180 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-07 08:01:46,180 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1880 states and 2759 transitions. [2021-11-07 08:01:46,189 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1711 [2021-11-07 08:01:46,190 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:46,190 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:46,193 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:46,194 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:46,194 INFO L791 eck$LassoCheckResult]: Stem: 57365#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 57366#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 57191#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 56911#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 56912#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 57797#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 57045#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 57046#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 57490#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 57327#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 57328#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 57114#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 57115#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 57500#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 57677#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 57830#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 57866#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 57125#L946-1 assume !(0 == ~M_E~0); 57126#L1258-1 assume !(0 == ~T1_E~0); 57409#L1263-1 assume !(0 == ~T2_E~0); 57410#L1268-1 assume !(0 == ~T3_E~0); 57711#L1273-1 assume !(0 == ~T4_E~0); 58254#L1278-1 assume !(0 == ~T5_E~0); 58119#L1283-1 assume !(0 == ~T6_E~0); 58120#L1288-1 assume !(0 == ~T7_E~0); 58351#L1293-1 assume !(0 == ~T8_E~0); 58338#L1298-1 assume !(0 == ~T9_E~0); 58266#L1303-1 assume !(0 == ~T10_E~0); 56940#L1308-1 assume !(0 == ~T11_E~0); 56882#L1313-1 assume !(0 == ~T12_E~0); 56883#L1318-1 assume !(0 == ~T13_E~0); 56889#L1323-1 assume !(0 == ~E_1~0); 56890#L1328-1 assume !(0 == ~E_2~0); 57055#L1333-1 assume !(0 == ~E_3~0); 57997#L1338-1 assume !(0 == ~E_4~0); 57998#L1343-1 assume !(0 == ~E_5~0); 58093#L1348-1 assume !(0 == ~E_6~0); 58373#L1353-1 assume !(0 == ~E_7~0); 57730#L1358-1 assume !(0 == ~E_8~0); 57731#L1363-1 assume !(0 == ~E_9~0); 58013#L1368-1 assume !(0 == ~E_10~0); 56722#L1373-1 assume !(0 == ~E_11~0); 56723#L1378-1 assume !(0 == ~E_12~0); 57005#L1383-1 assume !(0 == ~E_13~0); 57006#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 57737#L607 assume 1 == ~m_pc~0; 57738#L608 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 57077#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 58091#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 57656#L1560 assume !(0 != activate_threads_~tmp~1); 57657#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 56902#L626 assume 1 == ~t1_pc~0; 56903#L627 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 57167#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 57168#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 57331#L1568 assume !(0 != activate_threads_~tmp___0~0); 56802#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 56803#L645 assume !(1 == ~t2_pc~0); 56875#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 56876#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 57539#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 57540#L1576 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 57632#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 57633#L664 assume 1 == ~t3_pc~0; 58372#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 56647#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 56648#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 57297#L1584 assume !(0 != activate_threads_~tmp___2~0); 57298#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 58281#L683 assume !(1 == ~t4_pc~0); 57852#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 57804#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 57805#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 57839#L1592 assume !(0 != activate_threads_~tmp___3~0); 57959#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 57581#L702 assume 1 == ~t5_pc~0; 57582#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 57509#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 57954#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 58241#L1600 assume !(0 != activate_threads_~tmp___4~0); 58183#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 56695#L721 assume !(1 == ~t6_pc~0); 56669#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 56670#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 56829#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 57304#L1608 assume !(0 != activate_threads_~tmp___5~0); 57305#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 57897#L740 assume 1 == ~t7_pc~0; 56743#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 56556#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 56557#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 56546#L1616 assume !(0 != activate_threads_~tmp___6~0); 56547#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 57243#L759 assume !(1 == ~t8_pc~0); 57244#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 57273#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 57952#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 57953#L1624 assume !(0 != activate_threads_~tmp___7~0); 58078#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 58350#L778 assume 1 == ~t9_pc~0; 58238#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 56721#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 56662#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 56590#L1632 assume !(0 != activate_threads_~tmp___8~0); 56591#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 56915#L797 assume 1 == ~t10_pc~0; 56916#L798 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 57032#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 58142#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 57407#L1640 assume !(0 != activate_threads_~tmp___9~0); 57408#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 57695#L816 assume !(1 == ~t11_pc~0); 56630#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 56629#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 57369#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 57312#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 57313#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 57829#L835 assume 1 == ~t12_pc~0; 57708#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 56787#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 56809#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 56950#L1656 assume !(0 != activate_threads_~tmp___11~0); 57463#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 57464#L854 assume !(1 == ~t13_pc~0); 57116#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 57117#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 57163#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 56827#L1664 assume !(0 != activate_threads_~tmp___12~0); 56828#L1664-2 assume !(1 == ~M_E~0); 57618#L1401-1 assume !(1 == ~T1_E~0); 57619#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 57886#L1411-1 assume !(1 == ~T3_E~0); 57887#L1416-1 assume !(1 == ~T4_E~0); 57555#L1421-1 assume !(1 == ~T5_E~0); 57112#L1426-1 assume !(1 == ~T6_E~0); 57113#L1431-1 assume !(1 == ~T7_E~0); 56665#L1436-1 assume !(1 == ~T8_E~0); 56666#L1441-1 assume !(1 == ~T9_E~0); 57400#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 57401#L1451-1 assume !(1 == ~T11_E~0); 58090#L1456-1 assume !(1 == ~T12_E~0); 57755#L1461-1 assume !(1 == ~T13_E~0); 57322#L1466-1 assume !(1 == ~E_1~0); 57323#L1471-1 assume !(1 == ~E_2~0); 58076#L1476-1 assume !(1 == ~E_3~0); 58077#L1481-1 assume !(1 == ~E_4~0); 58221#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 56955#L1491-1 assume !(1 == ~E_6~0); 56598#L1496-1 assume !(1 == ~E_7~0); 56599#L1501-1 assume !(1 == ~E_8~0); 57398#L1506-1 assume !(1 == ~E_9~0); 57399#L1511-1 assume !(1 == ~E_10~0); 57354#L1516-1 assume !(1 == ~E_11~0); 56542#L1521-1 assume !(1 == ~E_12~0); 56543#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 56597#L1892-1 [2021-11-07 08:01:46,195 INFO L793 eck$LassoCheckResult]: Loop: 56597#L1892-1 assume !false; 56606#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 56717#L1233 assume !false; 58311#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 57659#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 57638#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 57798#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 56641#L1046 assume !(0 != eval_~tmp~0); 56643#L1248 start_simulation_~kernel_st~0 := 2; 56677#L874-1 start_simulation_~kernel_st~0 := 3; 57831#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 57725#L1258-4 assume !(0 == ~T1_E~0); 56815#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 56816#L1268-3 assume !(0 == ~T3_E~0); 58364#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 58370#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 58371#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 57037#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 57038#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 58132#L1298-3 assume !(0 == ~T9_E~0); 58133#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 58287#L1308-3 assume !(0 == ~T11_E~0); 58131#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 57643#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 56817#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 56818#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 58213#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 56960#L1338-3 assume !(0 == ~E_4~0); 56961#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 58051#L1348-3 assume !(0 == ~E_6~0); 58218#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 58219#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 57597#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 57169#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 57170#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 57913#L1378-3 assume !(0 == ~E_12~0); 57914#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 58087#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 58088#L607-42 assume 1 == ~m_pc~0; 57713#L608-14 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 57442#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 57443#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 57183#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 57184#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 57696#L626-42 assume 1 == ~t1_pc~0; 57267#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 57268#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 57562#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 57563#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 56851#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 56852#L645-42 assume 1 == ~t2_pc~0; 58280#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 58031#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 58190#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 57058#L1576-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 56568#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 56569#L664-42 assume !(1 == ~t3_pc~0); 57092#L664-44 is_transmit3_triggered_~__retres1~3 := 0; 57093#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 58314#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 57864#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 57865#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 58024#L683-42 assume 1 == ~t4_pc~0; 58379#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 57741#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 57871#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 58276#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 58277#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 58126#L702-42 assume 1 == ~t5_pc~0; 57625#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 57260#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 57546#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 58205#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 56584#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 56585#L721-42 assume !(1 == ~t6_pc~0); 56739#L721-44 is_transmit6_triggered_~__retres1~6 := 0; 57214#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 57215#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 58356#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 57381#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 57233#L740-42 assume 1 == ~t7_pc~0; 57234#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 56975#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 57503#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 57361#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 57362#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 57631#L759-42 assume 1 == ~t8_pc~0; 57482#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 57415#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 57416#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 57493#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 57494#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 57586#L778-42 assume 1 == ~t9_pc~0; 57426#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 57428#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 57836#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 57742#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 57743#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 57800#L797-42 assume 1 == ~t10_pc~0; 56980#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 56981#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 57964#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 58262#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 57837#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 57838#L816-42 assume 1 == ~t11_pc~0; 56532#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 56533#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 57072#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 57073#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 57151#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 57152#L835-42 assume 1 == ~t12_pc~0; 57543#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 57438#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 57127#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 57128#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 58182#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 57976#L854-42 assume 1 == ~t13_pc~0; 57977#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 57071#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 56685#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 56686#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 57320#L1664-44 assume !(1 == ~M_E~0); 57321#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 56918#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 56782#L1411-3 assume !(1 == ~T3_E~0); 56783#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 57372#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 57373#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 56958#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 56959#L1436-3 assume !(1 == ~T8_E~0); 56548#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 56549#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 58110#L1451-3 assume !(1 == ~T11_E~0); 57454#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 57119#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 57120#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 58367#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 57059#L1476-3 assume !(1 == ~E_3~0); 57060#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 57448#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 57087#L1491-3 assume !(1 == ~E_6~0); 57088#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 57488#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 57489#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 57910#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 57901#L1516-3 assume !(1 == ~E_11~0); 57902#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 57601#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 57602#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 57993#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 56894#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 57773#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 57417#L1911 assume !(0 == start_simulation_~tmp~3); 56640#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 57061#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 57016#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 57874#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 56726#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 56727#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 56953#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 56954#L1924 assume !(0 != start_simulation_~tmp___0~1); 56597#L1892-1 [2021-11-07 08:01:46,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:46,196 INFO L85 PathProgramCache]: Analyzing trace with hash 2057447495, now seen corresponding path program 1 times [2021-11-07 08:01:46,196 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:46,196 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1508226303] [2021-11-07 08:01:46,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:46,197 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:46,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:46,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:46,245 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:46,245 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1508226303] [2021-11-07 08:01:46,246 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1508226303] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:46,246 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:46,246 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-07 08:01:46,246 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1769297555] [2021-11-07 08:01:46,247 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:46,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:46,247 INFO L85 PathProgramCache]: Analyzing trace with hash 364827455, now seen corresponding path program 1 times [2021-11-07 08:01:46,248 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:46,248 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [550552247] [2021-11-07 08:01:46,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:46,248 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:46,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:46,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:46,298 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:46,298 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [550552247] [2021-11-07 08:01:46,298 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [550552247] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:46,299 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:46,299 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:46,299 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [640211264] [2021-11-07 08:01:46,300 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:01:46,300 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:46,300 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-07 08:01:46,301 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-07 08:01:46,301 INFO L87 Difference]: Start difference. First operand 1880 states and 2759 transitions. cyclomatic complexity: 880 Second operand has 3 states, 3 states have (on average 51.666666666666664) internal successors, (155), 2 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:46,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:46,461 INFO L93 Difference]: Finished difference Result 3574 states and 5207 transitions. [2021-11-07 08:01:46,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-07 08:01:46,462 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3574 states and 5207 transitions. [2021-11-07 08:01:46,487 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3405 [2021-11-07 08:01:46,503 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3574 states to 3574 states and 5207 transitions. [2021-11-07 08:01:46,503 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3574 [2021-11-07 08:01:46,508 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3574 [2021-11-07 08:01:46,508 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3574 states and 5207 transitions. [2021-11-07 08:01:46,516 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:46,516 INFO L681 BuchiCegarLoop]: Abstraction has 3574 states and 5207 transitions. [2021-11-07 08:01:46,525 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3574 states and 5207 transitions. [2021-11-07 08:01:46,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3574 to 3476. [2021-11-07 08:01:46,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3476 states, 3476 states have (on average 1.458573072497123) internal successors, (5070), 3475 states have internal predecessors, (5070), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:46,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3476 states to 3476 states and 5070 transitions. [2021-11-07 08:01:46,621 INFO L704 BuchiCegarLoop]: Abstraction has 3476 states and 5070 transitions. [2021-11-07 08:01:46,621 INFO L587 BuchiCegarLoop]: Abstraction has 3476 states and 5070 transitions. [2021-11-07 08:01:46,621 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-07 08:01:46,621 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3476 states and 5070 transitions. [2021-11-07 08:01:46,636 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3307 [2021-11-07 08:01:46,637 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:46,637 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:46,640 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:46,640 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:46,641 INFO L791 eck$LassoCheckResult]: Stem: 62830#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 62831#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 62655#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 62372#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 62373#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 63263#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62508#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62509#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62957#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62791#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 62792#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 62577#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 62578#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 62967#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 63144#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 63296#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 63336#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 62588#L946-1 assume !(0 == ~M_E~0); 62589#L1258-1 assume !(0 == ~T1_E~0); 62874#L1263-1 assume !(0 == ~T2_E~0); 62875#L1268-1 assume !(0 == ~T3_E~0); 63178#L1273-1 assume !(0 == ~T4_E~0); 63736#L1278-1 assume !(0 == ~T5_E~0); 63600#L1283-1 assume !(0 == ~T6_E~0); 63601#L1288-1 assume !(0 == ~T7_E~0); 63841#L1293-1 assume !(0 == ~T8_E~0); 63828#L1298-1 assume !(0 == ~T9_E~0); 63748#L1303-1 assume !(0 == ~T10_E~0); 62401#L1308-1 assume !(0 == ~T11_E~0); 62343#L1313-1 assume !(0 == ~T12_E~0); 62344#L1318-1 assume !(0 == ~T13_E~0); 62350#L1323-1 assume !(0 == ~E_1~0); 62351#L1328-1 assume !(0 == ~E_2~0); 62518#L1333-1 assume !(0 == ~E_3~0); 63473#L1338-1 assume !(0 == ~E_4~0); 63474#L1343-1 assume !(0 == ~E_5~0); 63574#L1348-1 assume !(0 == ~E_6~0); 63867#L1353-1 assume !(0 == ~E_7~0); 63197#L1358-1 assume !(0 == ~E_8~0); 63198#L1363-1 assume !(0 == ~E_9~0); 63490#L1368-1 assume !(0 == ~E_10~0); 62183#L1373-1 assume !(0 == ~E_11~0); 62184#L1378-1 assume !(0 == ~E_12~0); 62467#L1383-1 assume !(0 == ~E_13~0); 62468#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 63204#L607 assume !(1 == ~m_pc~0); 62539#L607-2 is_master_triggered_~__retres1~0 := 0; 62540#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 63572#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 63123#L1560 assume !(0 != activate_threads_~tmp~1); 63124#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 62363#L626 assume 1 == ~t1_pc~0; 62364#L627 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 62631#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 62632#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 62795#L1568 assume !(0 != activate_threads_~tmp___0~0); 62263#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 62264#L645 assume !(1 == ~t2_pc~0); 62336#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 62337#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 63006#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 63007#L1576 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 63099#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 63100#L664 assume 1 == ~t3_pc~0; 63866#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 62108#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 62109#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 62761#L1584 assume !(0 != activate_threads_~tmp___2~0); 62762#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 63763#L683 assume !(1 == ~t4_pc~0); 63321#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 63270#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 63271#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 63305#L1592 assume !(0 != activate_threads_~tmp___3~0); 63435#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 63048#L702 assume 1 == ~t5_pc~0; 63049#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 62976#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 63430#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 63723#L1600 assume !(0 != activate_threads_~tmp___4~0); 63663#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 62156#L721 assume !(1 == ~t6_pc~0); 62130#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 62131#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 62290#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 62768#L1608 assume !(0 != activate_threads_~tmp___5~0); 62769#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 63368#L740 assume 1 == ~t7_pc~0; 62204#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 62017#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 62018#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 62007#L1616 assume !(0 != activate_threads_~tmp___6~0); 62008#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 62707#L759 assume !(1 == ~t8_pc~0); 62708#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 62737#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 63428#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 63429#L1624 assume !(0 != activate_threads_~tmp___7~0); 63557#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 63840#L778 assume 1 == ~t9_pc~0; 63720#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 62182#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 62123#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 62051#L1632 assume !(0 != activate_threads_~tmp___8~0); 62052#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 62376#L797 assume 1 == ~t10_pc~0; 62377#L798 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 62495#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 63622#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 62872#L1640 assume !(0 != activate_threads_~tmp___9~0); 62873#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 63162#L816 assume !(1 == ~t11_pc~0); 62091#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 62090#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 62834#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 62776#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 62777#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 63295#L835 assume 1 == ~t12_pc~0; 63175#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 62248#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 62270#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 62411#L1656 assume !(0 != activate_threads_~tmp___11~0); 62930#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 62931#L854 assume !(1 == ~t13_pc~0); 62579#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 62580#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 62627#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 62288#L1664 assume !(0 != activate_threads_~tmp___12~0); 62289#L1664-2 assume !(1 == ~M_E~0); 63085#L1401-1 assume !(1 == ~T1_E~0); 63086#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 63357#L1411-1 assume !(1 == ~T3_E~0); 63358#L1416-1 assume !(1 == ~T4_E~0); 63022#L1421-1 assume !(1 == ~T5_E~0); 62575#L1426-1 assume !(1 == ~T6_E~0); 62576#L1431-1 assume !(1 == ~T7_E~0); 62126#L1436-1 assume !(1 == ~T8_E~0); 62127#L1441-1 assume !(1 == ~T9_E~0); 62865#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 62866#L1451-1 assume !(1 == ~T11_E~0); 63571#L1456-1 assume !(1 == ~T12_E~0); 63221#L1461-1 assume !(1 == ~T13_E~0); 62786#L1466-1 assume !(1 == ~E_1~0); 62787#L1471-1 assume !(1 == ~E_2~0); 63555#L1476-1 assume !(1 == ~E_3~0); 63556#L1481-1 assume !(1 == ~E_4~0); 63703#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 62416#L1491-1 assume !(1 == ~E_6~0); 62059#L1496-1 assume !(1 == ~E_7~0); 62060#L1501-1 assume !(1 == ~E_8~0); 62863#L1506-1 assume !(1 == ~E_9~0); 62864#L1511-1 assume !(1 == ~E_10~0); 62819#L1516-1 assume !(1 == ~E_11~0); 62003#L1521-1 assume !(1 == ~E_12~0); 62004#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 62058#L1892-1 [2021-11-07 08:01:46,641 INFO L793 eck$LassoCheckResult]: Loop: 62058#L1892-1 assume !false; 62067#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 62178#L1233 assume !false; 63797#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 63126#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 63105#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 63264#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 62102#L1046 assume !(0 != eval_~tmp~0); 62104#L1248 start_simulation_~kernel_st~0 := 2; 64653#L874-1 start_simulation_~kernel_st~0 := 3; 64650#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 64648#L1258-4 assume !(0 == ~T1_E~0); 64646#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 64644#L1268-3 assume !(0 == ~T3_E~0); 64642#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 64640#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 64637#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 64635#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 64633#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 64631#L1298-3 assume !(0 == ~T9_E~0); 64629#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 64627#L1308-3 assume !(0 == ~T11_E~0); 64624#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 64622#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 64620#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 64618#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 64616#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 64614#L1338-3 assume !(0 == ~E_4~0); 64611#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 64609#L1348-3 assume !(0 == ~E_6~0); 64607#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 64605#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 64603#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 64602#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 64601#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 64583#L1378-3 assume !(0 == ~E_12~0); 64579#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 64578#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 63887#L607-42 assume !(1 == ~m_pc~0); 63411#L607-44 is_master_triggered_~__retres1~0 := 0; 62909#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 62910#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 62647#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 62648#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 63163#L626-42 assume 1 == ~t1_pc~0; 62731#L627-14 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 62732#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 63029#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 63030#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 62312#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 62313#L645-42 assume 1 == ~t2_pc~0; 63762#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 63508#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 63670#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 62521#L1576-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 62029#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 62030#L664-42 assume 1 == ~t3_pc~0; 62823#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 62556#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 65148#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 65147#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 65146#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 65145#L683-42 assume !(1 == ~t4_pc~0); 65143#L683-44 is_transmit4_triggered_~__retres1~4 := 0; 65142#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 65141#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 65140#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 65139#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 65138#L702-42 assume 1 == ~t5_pc~0; 65136#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 65135#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 65134#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 63686#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 62045#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 62046#L721-42 assume !(1 == ~t6_pc~0); 62200#L721-44 is_transmit6_triggered_~__retres1~6 := 0; 62678#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 62679#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 63848#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 62846#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 62697#L740-42 assume !(1 == ~t7_pc~0); 62436#L740-44 is_transmit7_triggered_~__retres1~7 := 0; 62437#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 62970#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 62826#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 62827#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 63098#L759-42 assume 1 == ~t8_pc~0; 62949#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 62880#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 62881#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 62960#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 62961#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 63053#L778-42 assume 1 == ~t9_pc~0; 62892#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 62894#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 63302#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 63208#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 63209#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 63266#L797-42 assume 1 == ~t10_pc~0; 62442#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 62443#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 63440#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 63744#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 63303#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 63304#L816-42 assume 1 == ~t11_pc~0; 61993#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 61994#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 62535#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 62536#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 62615#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 62616#L835-42 assume 1 == ~t12_pc~0; 63010#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 62904#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 62590#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 62591#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 63662#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 63452#L854-42 assume !(1 == ~t13_pc~0); 62533#L854-44 is_transmit13_triggered_~__retres1~13 := 0; 62534#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 62147#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 62148#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 62784#L1664-44 assume !(1 == ~M_E~0); 62785#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 62379#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 62243#L1411-3 assume !(1 == ~T3_E~0); 62244#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 62837#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 62838#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 62419#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 62420#L1436-3 assume !(1 == ~T8_E~0); 62009#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 62010#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 63591#L1451-3 assume !(1 == ~T11_E~0); 62921#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 62582#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 62583#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 63859#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 62522#L1476-3 assume !(1 == ~E_3~0); 62523#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 62915#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 62550#L1491-3 assume !(1 == ~E_6~0); 62551#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 62955#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 62956#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 63383#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 63374#L1516-3 assume !(1 == ~E_11~0); 63375#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 63068#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 63069#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 63469#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 62355#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 63239#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 62882#L1911 assume !(0 == start_simulation_~tmp~3); 62101#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 62524#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 62478#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 63344#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 62187#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 62188#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 62414#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 62415#L1924 assume !(0 != start_simulation_~tmp___0~1); 62058#L1892-1 [2021-11-07 08:01:46,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:46,642 INFO L85 PathProgramCache]: Analyzing trace with hash -2075582810, now seen corresponding path program 1 times [2021-11-07 08:01:46,643 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:46,643 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2000530767] [2021-11-07 08:01:46,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:46,643 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:46,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:46,735 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:46,736 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:46,736 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2000530767] [2021-11-07 08:01:46,736 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2000530767] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:46,736 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:46,737 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:46,737 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1540436711] [2021-11-07 08:01:46,737 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:46,738 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:46,738 INFO L85 PathProgramCache]: Analyzing trace with hash -286524670, now seen corresponding path program 1 times [2021-11-07 08:01:46,738 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:46,738 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [961936377] [2021-11-07 08:01:46,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:46,739 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:46,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:46,791 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:46,791 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:46,791 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [961936377] [2021-11-07 08:01:46,791 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [961936377] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:46,792 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:46,792 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:46,792 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [468873078] [2021-11-07 08:01:46,793 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:01:46,793 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:46,793 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-07 08:01:46,793 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-07 08:01:46,794 INFO L87 Difference]: Start difference. First operand 3476 states and 5070 transitions. cyclomatic complexity: 1596 Second operand has 4 states, 4 states have (on average 38.75) internal successors, (155), 3 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:47,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:47,237 INFO L93 Difference]: Finished difference Result 8320 states and 12041 transitions. [2021-11-07 08:01:47,238 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 08:01:47,238 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8320 states and 12041 transitions. [2021-11-07 08:01:47,288 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 8046 [2021-11-07 08:01:47,326 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8320 states to 8320 states and 12041 transitions. [2021-11-07 08:01:47,326 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8320 [2021-11-07 08:01:47,338 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8320 [2021-11-07 08:01:47,338 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8320 states and 12041 transitions. [2021-11-07 08:01:47,348 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:47,348 INFO L681 BuchiCegarLoop]: Abstraction has 8320 states and 12041 transitions. [2021-11-07 08:01:47,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8320 states and 12041 transitions. [2021-11-07 08:01:47,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8320 to 6555. [2021-11-07 08:01:47,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6555 states, 6555 states have (on average 1.4517162471395881) internal successors, (9516), 6554 states have internal predecessors, (9516), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:47,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6555 states to 6555 states and 9516 transitions. [2021-11-07 08:01:47,491 INFO L704 BuchiCegarLoop]: Abstraction has 6555 states and 9516 transitions. [2021-11-07 08:01:47,492 INFO L587 BuchiCegarLoop]: Abstraction has 6555 states and 9516 transitions. [2021-11-07 08:01:47,492 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-07 08:01:47,492 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6555 states and 9516 transitions. [2021-11-07 08:01:47,524 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6386 [2021-11-07 08:01:47,524 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:47,524 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:47,529 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:47,529 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:47,530 INFO L791 eck$LassoCheckResult]: Stem: 74634#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 74635#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 74459#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 74176#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 74177#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75075#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 74312#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 74313#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 74765#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 74596#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 74597#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 74381#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 74382#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 74771#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 74952#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 75109#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 75146#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 74394#L946-1 assume !(0 == ~M_E~0); 74395#L1258-1 assume !(0 == ~T1_E~0); 74679#L1263-1 assume !(0 == ~T2_E~0); 74680#L1268-1 assume !(0 == ~T3_E~0); 74988#L1273-1 assume !(0 == ~T4_E~0); 75563#L1278-1 assume !(0 == ~T5_E~0); 75417#L1283-1 assume !(0 == ~T6_E~0); 75418#L1288-1 assume !(0 == ~T7_E~0); 75671#L1293-1 assume !(0 == ~T8_E~0); 75657#L1298-1 assume !(0 == ~T9_E~0); 75578#L1303-1 assume !(0 == ~T10_E~0); 74205#L1308-1 assume !(0 == ~T11_E~0); 74151#L1313-1 assume !(0 == ~T12_E~0); 74152#L1318-1 assume !(0 == ~T13_E~0); 74157#L1323-1 assume !(0 == ~E_1~0); 74158#L1328-1 assume !(0 == ~E_2~0); 74324#L1333-1 assume !(0 == ~E_3~0); 75284#L1338-1 assume !(0 == ~E_4~0); 75285#L1343-1 assume !(0 == ~E_5~0); 75391#L1348-1 assume !(0 == ~E_6~0); 75696#L1353-1 assume !(0 == ~E_7~0); 75007#L1358-1 assume !(0 == ~E_8~0); 75008#L1363-1 assume !(0 == ~E_9~0); 75304#L1368-1 assume !(0 == ~E_10~0); 73989#L1373-1 assume !(0 == ~E_11~0); 73990#L1378-1 assume !(0 == ~E_12~0); 74273#L1383-1 assume !(0 == ~E_13~0); 74274#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 75014#L607 assume !(1 == ~m_pc~0); 74343#L607-2 is_master_triggered_~__retres1~0 := 0; 74344#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 75386#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 74929#L1560 assume !(0 != activate_threads_~tmp~1); 74930#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 74168#L626 assume !(1 == ~t1_pc~0); 74169#L626-2 is_transmit1_triggered_~__retres1~1 := 0; 74437#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 74438#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 74602#L1568 assume !(0 != activate_threads_~tmp___0~0); 74071#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 74072#L645 assume !(1 == ~t2_pc~0); 74141#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 74142#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 74813#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 74814#L1576 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 74905#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 74906#L664 assume 1 == ~t3_pc~0; 75695#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 73918#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 73919#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 74566#L1584 assume !(0 != activate_threads_~tmp___2~0); 74567#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 75593#L683 assume !(1 == ~t4_pc~0); 75132#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 75082#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 75083#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 75117#L1592 assume !(0 != activate_threads_~tmp___3~0); 75245#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 74854#L702 assume 1 == ~t5_pc~0; 74855#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 74780#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 75240#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 75550#L1600 assume !(0 != activate_threads_~tmp___4~0); 75486#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 73962#L721 assume !(1 == ~t6_pc~0); 73936#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 73937#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 74095#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 74573#L1608 assume !(0 != activate_threads_~tmp___5~0); 74574#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 75179#L740 assume 1 == ~t7_pc~0; 74010#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 73823#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 73824#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 73813#L1616 assume !(0 != activate_threads_~tmp___6~0); 73814#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 74511#L759 assume !(1 == ~t8_pc~0); 74512#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 74540#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 75238#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 75239#L1624 assume !(0 != activate_threads_~tmp___7~0); 75371#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 75669#L778 assume 1 == ~t9_pc~0; 75547#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 73988#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 73929#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 73857#L1632 assume !(0 != activate_threads_~tmp___8~0); 73858#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 74180#L797 assume 1 == ~t10_pc~0; 74181#L798 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 74299#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 75439#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 74677#L1640 assume !(0 != activate_threads_~tmp___9~0); 74678#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 74972#L816 assume !(1 == ~t11_pc~0); 73897#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 73896#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 74638#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 74581#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 74582#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 75107#L835 assume 1 == ~t12_pc~0; 74985#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 74053#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 74075#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 74215#L1656 assume !(0 != activate_threads_~tmp___11~0); 74733#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 74734#L854 assume !(1 == ~t13_pc~0); 74383#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 74384#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 74430#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 74093#L1664 assume !(0 != activate_threads_~tmp___12~0); 74094#L1664-2 assume !(1 == ~M_E~0); 74891#L1401-1 assume !(1 == ~T1_E~0); 74892#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 75168#L1411-1 assume !(1 == ~T3_E~0); 75169#L1416-1 assume !(1 == ~T4_E~0); 74826#L1421-1 assume !(1 == ~T5_E~0); 74379#L1426-1 assume !(1 == ~T6_E~0); 74380#L1431-1 assume !(1 == ~T7_E~0); 73932#L1436-1 assume !(1 == ~T8_E~0); 73933#L1441-1 assume !(1 == ~T9_E~0); 74669#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 74670#L1451-1 assume !(1 == ~T11_E~0); 75385#L1456-1 assume !(1 == ~T12_E~0); 75031#L1461-1 assume !(1 == ~T13_E~0); 74591#L1466-1 assume !(1 == ~E_1~0); 74592#L1471-1 assume !(1 == ~E_2~0); 75369#L1476-1 assume !(1 == ~E_3~0); 75370#L1481-1 assume !(1 == ~E_4~0); 75528#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 74220#L1491-1 assume !(1 == ~E_6~0); 73865#L1496-1 assume !(1 == ~E_7~0); 73866#L1501-1 assume !(1 == ~E_8~0); 74667#L1506-1 assume !(1 == ~E_9~0); 74668#L1511-1 assume !(1 == ~E_10~0); 74623#L1516-1 assume !(1 == ~E_11~0); 73809#L1521-1 assume !(1 == ~E_12~0); 73810#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 73864#L1892-1 [2021-11-07 08:01:47,531 INFO L793 eck$LassoCheckResult]: Loop: 73864#L1892-1 assume !false; 73873#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 73984#L1233 assume !false; 75626#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 74932#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 74911#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 75076#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 73908#L1046 assume !(0 != eval_~tmp~0); 73910#L1248 start_simulation_~kernel_st~0 := 2; 73944#L874-1 start_simulation_~kernel_st~0 := 3; 75108#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 75002#L1258-4 assume !(0 == ~T1_E~0); 74081#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 74082#L1268-3 assume !(0 == ~T3_E~0); 75686#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 75693#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 75694#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 74304#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 74305#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 75429#L1298-3 assume !(0 == ~T9_E~0); 75430#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 75602#L1308-3 assume !(0 == ~T11_E~0); 75428#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 74916#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 74083#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 74084#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 75520#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 74225#L1338-3 assume !(0 == ~E_4~0); 74226#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 75342#L1348-3 assume !(0 == ~E_6~0); 75525#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 75526#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 74870#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 74435#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 74436#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 75198#L1378-3 assume !(0 == ~E_12~0); 75199#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 75382#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 75383#L607-42 assume !(1 == ~m_pc~0); 75222#L607-44 is_master_triggered_~__retres1~0 := 0; 74712#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 74713#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 74451#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 74452#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 74973#L626-42 assume !(1 == ~t1_pc~0); 74555#L626-44 is_transmit1_triggered_~__retres1~1 := 0; 74556#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 74833#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 74834#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 74117#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 74118#L645-42 assume !(1 == ~t2_pc~0); 75319#L645-44 is_transmit2_triggered_~__retres1~2 := 0; 75320#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 75496#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 74325#L1576-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 73835#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 73836#L664-42 assume 1 == ~t3_pc~0; 74627#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 74360#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 75630#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 75144#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 75145#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 75313#L683-42 assume !(1 == ~t4_pc~0); 75016#L683-44 is_transmit4_triggered_~__retres1~4 := 0; 75017#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 75151#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 75588#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 75589#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 75423#L702-42 assume 1 == ~t5_pc~0; 74898#L703-14 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 74528#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 74817#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 75512#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 73851#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 73852#L721-42 assume !(1 == ~t6_pc~0); 74006#L721-44 is_transmit6_triggered_~__retres1~6 := 0; 74482#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 74483#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 75675#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 74650#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 74501#L740-42 assume !(1 == ~t7_pc~0); 74240#L740-44 is_transmit7_triggered_~__retres1~7 := 0; 74241#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 74774#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 74630#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 74631#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 74904#L759-42 assume !(1 == ~t8_pc~0); 74753#L759-44 is_transmit8_triggered_~__retres1~8 := 0; 74685#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 74686#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 74761#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 74762#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 74859#L778-42 assume !(1 == ~t9_pc~0); 74697#L778-44 is_transmit9_triggered_~__retres1~9 := 0; 74698#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 75114#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 75018#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 75019#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 75078#L797-42 assume 1 == ~t10_pc~0; 74246#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 74247#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 75250#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 75573#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 75115#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 75116#L816-42 assume 1 == ~t11_pc~0; 73799#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 73800#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 74339#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 74340#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 74418#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 74419#L835-42 assume !(1 == ~t12_pc~0); 74707#L835-44 is_transmit12_triggered_~__retres1~12 := 0; 74708#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 74392#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 74393#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 75485#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 75262#L854-42 assume !(1 == ~t13_pc~0); 74337#L854-44 is_transmit13_triggered_~__retres1~13 := 0; 74338#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 73952#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 73953#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 74589#L1664-44 assume !(1 == ~M_E~0); 74590#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 74183#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 74048#L1411-3 assume !(1 == ~T3_E~0); 74049#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 74641#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 74642#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 74223#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 74224#L1436-3 assume !(1 == ~T8_E~0); 73815#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 73816#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 75408#L1451-3 assume !(1 == ~T11_E~0); 74724#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 74386#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 74387#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 75690#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 74326#L1476-3 assume !(1 == ~E_3~0); 74327#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 74718#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 74354#L1491-3 assume !(1 == ~E_6~0); 74355#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 74759#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 74760#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 75195#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 75185#L1516-3 assume !(1 == ~E_11~0); 75186#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 74874#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 74875#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 75280#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 74160#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 75051#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 74687#L1911 assume !(0 == start_simulation_~tmp~3); 73907#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 74328#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 74282#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 75154#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 73993#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 73994#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 74218#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 74219#L1924 assume !(0 != start_simulation_~tmp___0~1); 73864#L1892-1 [2021-11-07 08:01:47,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:47,536 INFO L85 PathProgramCache]: Analyzing trace with hash 981731397, now seen corresponding path program 1 times [2021-11-07 08:01:47,536 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:47,536 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [220616107] [2021-11-07 08:01:47,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:47,537 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:47,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:47,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:47,593 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:47,593 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [220616107] [2021-11-07 08:01:47,594 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [220616107] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:47,594 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:47,594 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-07 08:01:47,594 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [771731610] [2021-11-07 08:01:47,595 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:47,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:47,596 INFO L85 PathProgramCache]: Analyzing trace with hash -966045945, now seen corresponding path program 1 times [2021-11-07 08:01:47,596 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:47,596 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [737925983] [2021-11-07 08:01:47,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:47,597 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:47,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:47,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:47,643 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:47,643 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [737925983] [2021-11-07 08:01:47,644 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [737925983] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:47,644 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:47,644 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:47,644 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [204613944] [2021-11-07 08:01:47,645 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:01:47,645 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:47,646 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-07 08:01:47,646 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-07 08:01:47,646 INFO L87 Difference]: Start difference. First operand 6555 states and 9516 transitions. cyclomatic complexity: 2963 Second operand has 5 states, 5 states have (on average 31.0) internal successors, (155), 5 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:48,231 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:48,232 INFO L93 Difference]: Finished difference Result 18306 states and 26563 transitions. [2021-11-07 08:01:48,232 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-07 08:01:48,233 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18306 states and 26563 transitions. [2021-11-07 08:01:48,346 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 17922 [2021-11-07 08:01:48,425 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18306 states to 18306 states and 26563 transitions. [2021-11-07 08:01:48,425 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18306 [2021-11-07 08:01:48,447 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18306 [2021-11-07 08:01:48,448 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18306 states and 26563 transitions. [2021-11-07 08:01:48,468 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:48,468 INFO L681 BuchiCegarLoop]: Abstraction has 18306 states and 26563 transitions. [2021-11-07 08:01:48,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18306 states and 26563 transitions. [2021-11-07 08:01:48,633 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18306 to 6726. [2021-11-07 08:01:48,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6726 states, 6726 states have (on average 1.4402319357716324) internal successors, (9687), 6725 states have internal predecessors, (9687), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:48,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6726 states to 6726 states and 9687 transitions. [2021-11-07 08:01:48,670 INFO L704 BuchiCegarLoop]: Abstraction has 6726 states and 9687 transitions. [2021-11-07 08:01:48,670 INFO L587 BuchiCegarLoop]: Abstraction has 6726 states and 9687 transitions. [2021-11-07 08:01:48,670 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-07 08:01:48,670 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6726 states and 9687 transitions. [2021-11-07 08:01:48,703 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6554 [2021-11-07 08:01:48,704 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:48,704 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:48,708 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:48,708 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:48,708 INFO L791 eck$LassoCheckResult]: Stem: 99509#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 99510#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 99331#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 99049#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 99050#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 99958#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 99185#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 99186#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 99639#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 99469#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 99470#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 99254#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 99255#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 99649#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 99831#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 99995#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 100033#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 99265#L946-1 assume !(0 == ~M_E~0); 99266#L1258-1 assume !(0 == ~T1_E~0); 99554#L1263-1 assume !(0 == ~T2_E~0); 99555#L1268-1 assume !(0 == ~T3_E~0); 99869#L1273-1 assume !(0 == ~T4_E~0); 100483#L1278-1 assume !(0 == ~T5_E~0); 100321#L1283-1 assume !(0 == ~T6_E~0); 100322#L1288-1 assume !(0 == ~T7_E~0); 100611#L1293-1 assume !(0 == ~T8_E~0); 100596#L1298-1 assume !(0 == ~T9_E~0); 100500#L1303-1 assume !(0 == ~T10_E~0); 99079#L1308-1 assume !(0 == ~T11_E~0); 99021#L1313-1 assume !(0 == ~T12_E~0); 99022#L1318-1 assume !(0 == ~T13_E~0); 99028#L1323-1 assume !(0 == ~E_1~0); 99029#L1328-1 assume !(0 == ~E_2~0); 99197#L1333-1 assume !(0 == ~E_3~0); 100179#L1338-1 assume !(0 == ~E_4~0); 100180#L1343-1 assume !(0 == ~E_5~0); 100291#L1348-1 assume !(0 == ~E_6~0); 100655#L1353-1 assume !(0 == ~E_7~0); 99889#L1358-1 assume !(0 == ~E_8~0); 99890#L1363-1 assume !(0 == ~E_9~0); 100201#L1368-1 assume !(0 == ~E_10~0); 98862#L1373-1 assume !(0 == ~E_11~0); 98863#L1378-1 assume !(0 == ~E_12~0); 99145#L1383-1 assume !(0 == ~E_13~0); 99146#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 99896#L607 assume !(1 == ~m_pc~0); 99216#L607-2 is_master_triggered_~__retres1~0 := 0; 99217#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 100287#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 99809#L1560 assume !(0 != activate_threads_~tmp~1); 99810#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 99041#L626 assume !(1 == ~t1_pc~0); 99042#L626-2 is_transmit1_triggered_~__retres1~1 := 0; 99307#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 99308#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 99473#L1568 assume !(0 != activate_threads_~tmp___0~0); 98941#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 98942#L645 assume !(1 == ~t2_pc~0); 99014#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 99015#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 100433#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 100707#L1576 assume !(0 != activate_threads_~tmp___1~0); 99784#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 99785#L664 assume 1 == ~t3_pc~0; 100649#L665 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 98788#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 98789#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 99439#L1584 assume !(0 != activate_threads_~tmp___2~0); 99440#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 100522#L683 assume !(1 == ~t4_pc~0); 100019#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 99968#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 99969#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 100004#L1592 assume !(0 != activate_threads_~tmp___3~0); 100139#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 99732#L702 assume 1 == ~t5_pc~0; 99733#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 99659#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 100134#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 100468#L1600 assume !(0 != activate_threads_~tmp___4~0); 100396#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 98835#L721 assume !(1 == ~t6_pc~0); 98810#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 98811#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 98968#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 99446#L1608 assume !(0 != activate_threads_~tmp___5~0); 99447#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 100066#L740 assume 1 == ~t7_pc~0; 98883#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 98697#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 98698#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 98687#L1616 assume !(0 != activate_threads_~tmp___6~0); 98688#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 99384#L759 assume !(1 == ~t8_pc~0); 99385#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 99413#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 100132#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 100133#L1624 assume !(0 != activate_threads_~tmp___7~0); 100272#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 100610#L778 assume 1 == ~t9_pc~0; 100464#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 98861#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 98803#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 98731#L1632 assume !(0 != activate_threads_~tmp___8~0); 98732#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 99053#L797 assume 1 == ~t10_pc~0; 99054#L798 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 99172#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 100346#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 99552#L1640 assume !(0 != activate_threads_~tmp___9~0); 99553#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 99853#L816 assume !(1 == ~t11_pc~0); 98771#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 98770#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 99513#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 99454#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 99455#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 99994#L835 assume 1 == ~t12_pc~0; 99866#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 98926#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 98948#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 99090#L1656 assume !(0 != activate_threads_~tmp___11~0); 99609#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 99610#L854 assume !(1 == ~t13_pc~0); 99256#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 99257#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 99303#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 98966#L1664 assume !(0 != activate_threads_~tmp___12~0); 98967#L1664-2 assume !(1 == ~M_E~0); 99770#L1401-1 assume !(1 == ~T1_E~0); 99771#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 100054#L1411-1 assume !(1 == ~T3_E~0); 100055#L1416-1 assume !(1 == ~T4_E~0); 99705#L1421-1 assume !(1 == ~T5_E~0); 99252#L1426-1 assume !(1 == ~T6_E~0); 99253#L1431-1 assume !(1 == ~T7_E~0); 98806#L1436-1 assume !(1 == ~T8_E~0); 98807#L1441-1 assume !(1 == ~T9_E~0); 99544#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 99545#L1451-1 assume !(1 == ~T11_E~0); 100286#L1456-1 assume !(1 == ~T12_E~0); 99913#L1461-1 assume !(1 == ~T13_E~0); 99464#L1466-1 assume !(1 == ~E_1~0); 99465#L1471-1 assume !(1 == ~E_2~0); 100270#L1476-1 assume !(1 == ~E_3~0); 100271#L1481-1 assume !(1 == ~E_4~0); 100445#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 99095#L1491-1 assume !(1 == ~E_6~0); 98739#L1496-1 assume !(1 == ~E_7~0); 98740#L1501-1 assume !(1 == ~E_8~0); 99542#L1506-1 assume !(1 == ~E_9~0); 99543#L1511-1 assume !(1 == ~E_10~0); 99498#L1516-1 assume !(1 == ~E_11~0); 98683#L1521-1 assume !(1 == ~E_12~0); 98684#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 98738#L1892-1 [2021-11-07 08:01:48,709 INFO L793 eck$LassoCheckResult]: Loop: 98738#L1892-1 assume !false; 98747#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 98857#L1233 assume !false; 100561#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 99812#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 99790#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 99959#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 98782#L1046 assume !(0 != eval_~tmp~0); 98784#L1248 start_simulation_~kernel_st~0 := 2; 98818#L874-1 start_simulation_~kernel_st~0 := 3; 99996#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 99883#L1258-4 assume !(0 == ~T1_E~0); 98954#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 98955#L1268-3 assume !(0 == ~T3_E~0); 100639#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 100645#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 100646#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 99177#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 99178#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 100336#L1298-3 assume !(0 == ~T9_E~0); 100337#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 100534#L1308-3 assume !(0 == ~T11_E~0); 100335#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 99795#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 98956#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 98957#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 100434#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 100659#L1338-3 assume !(0 == ~E_4~0); 104451#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 104449#L1348-3 assume !(0 == ~E_6~0); 104447#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 104445#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 104443#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 104441#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 104438#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 104435#L1378-3 assume !(0 == ~E_12~0); 100556#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 100283#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 100284#L607-42 assume !(1 == ~m_pc~0); 100112#L607-44 is_master_triggered_~__retres1~0 := 0; 99588#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 99589#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 99323#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 99324#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 99854#L626-42 assume !(1 == ~t1_pc~0); 99428#L626-44 is_transmit1_triggered_~__retres1~1 := 0; 99429#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 99712#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 99713#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 98990#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 98991#L645-42 assume !(1 == ~t2_pc~0); 104951#L645-44 is_transmit2_triggered_~__retres1~2 := 0; 104949#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 104947#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 104945#L1576-42 assume !(0 != activate_threads_~tmp___1~0); 104942#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 104941#L664-42 assume 1 == ~t3_pc~0; 104937#L665-14 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 104935#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 104933#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 104931#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 104929#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 104927#L683-42 assume 1 == ~t4_pc~0; 104923#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 104920#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 104918#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 104916#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 104914#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 104911#L702-42 assume !(1 == ~t5_pc~0); 104901#L702-44 is_transmit5_triggered_~__retres1~5 := 0; 104898#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 104896#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 104893#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 104891#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 104889#L721-42 assume !(1 == ~t6_pc~0); 104886#L721-44 is_transmit6_triggered_~__retres1~6 := 0; 104885#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 104884#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 104883#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 104882#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 104881#L740-42 assume !(1 == ~t7_pc~0); 104880#L740-44 is_transmit7_triggered_~__retres1~7 := 0; 99653#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 99652#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 99505#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 99506#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 99783#L759-42 assume !(1 == ~t8_pc~0); 99631#L759-44 is_transmit8_triggered_~__retres1~8 := 0; 99560#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 99561#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 99640#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 99641#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 99737#L778-42 assume 1 == ~t9_pc~0; 99575#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 99577#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 100001#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 99900#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 99901#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 99961#L797-42 assume !(1 == ~t10_pc~0); 99963#L797-44 is_transmit10_triggered_~__retres1~10 := 0; 104591#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 104586#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 104582#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 100002#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 100003#L816-42 assume 1 == ~t11_pc~0; 98676#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 98677#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 99212#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 99213#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 99291#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 99292#L835-42 assume 1 == ~t12_pc~0; 99693#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 99584#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 99267#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 99268#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 100395#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 100157#L854-42 assume !(1 == ~t13_pc~0); 99210#L854-44 is_transmit13_triggered_~__retres1~13 := 0; 99211#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 98826#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 98827#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 99462#L1664-44 assume !(1 == ~M_E~0); 99463#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 99056#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 98923#L1411-3 assume !(1 == ~T3_E~0); 98924#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 99516#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 99517#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 99098#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 99099#L1436-3 assume !(1 == ~T8_E~0); 98689#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 98690#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 100309#L1451-3 assume !(1 == ~T11_E~0); 99600#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 99259#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 99260#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 100642#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 99199#L1476-3 assume !(1 == ~E_3~0); 99200#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 99594#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 99227#L1491-3 assume !(1 == ~E_6~0); 99228#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 99637#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 99638#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 100081#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 100071#L1516-3 assume !(1 == ~E_11~0); 100072#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 99752#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 99753#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 100175#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 99033#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 99933#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 99562#L1911 assume !(0 == start_simulation_~tmp~3); 99563#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 100108#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 99156#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 100041#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 98866#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 98867#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 99093#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 99094#L1924 assume !(0 != start_simulation_~tmp___0~1); 98738#L1892-1 [2021-11-07 08:01:48,710 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:48,710 INFO L85 PathProgramCache]: Analyzing trace with hash -637243517, now seen corresponding path program 1 times [2021-11-07 08:01:48,710 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:48,711 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [316790896] [2021-11-07 08:01:48,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:48,711 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:48,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:48,772 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:48,772 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:48,772 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [316790896] [2021-11-07 08:01:48,773 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [316790896] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:48,773 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:48,773 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:48,773 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1072769765] [2021-11-07 08:01:48,774 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:48,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:48,775 INFO L85 PathProgramCache]: Analyzing trace with hash 1659986184, now seen corresponding path program 1 times [2021-11-07 08:01:48,776 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:48,776 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [614961658] [2021-11-07 08:01:48,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:48,776 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:48,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:48,826 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:48,827 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:48,827 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [614961658] [2021-11-07 08:01:48,827 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [614961658] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:48,828 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:48,828 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:48,828 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1427230945] [2021-11-07 08:01:48,830 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:01:48,830 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:48,830 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-07 08:01:48,831 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-07 08:01:48,831 INFO L87 Difference]: Start difference. First operand 6726 states and 9687 transitions. cyclomatic complexity: 2963 Second operand has 4 states, 4 states have (on average 38.75) internal successors, (155), 3 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:49,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:49,271 INFO L93 Difference]: Finished difference Result 16260 states and 23261 transitions. [2021-11-07 08:01:49,271 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 08:01:49,271 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16260 states and 23261 transitions. [2021-11-07 08:01:49,553 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 15872 [2021-11-07 08:01:49,638 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16260 states to 16260 states and 23261 transitions. [2021-11-07 08:01:49,639 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16260 [2021-11-07 08:01:49,665 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16260 [2021-11-07 08:01:49,665 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16260 states and 23261 transitions. [2021-11-07 08:01:49,687 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:49,687 INFO L681 BuchiCegarLoop]: Abstraction has 16260 states and 23261 transitions. [2021-11-07 08:01:49,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16260 states and 23261 transitions. [2021-11-07 08:01:49,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16260 to 12817. [2021-11-07 08:01:49,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12817 states, 12817 states have (on average 1.4345010532886011) internal successors, (18386), 12816 states have internal predecessors, (18386), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:50,019 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12817 states to 12817 states and 18386 transitions. [2021-11-07 08:01:50,019 INFO L704 BuchiCegarLoop]: Abstraction has 12817 states and 18386 transitions. [2021-11-07 08:01:50,019 INFO L587 BuchiCegarLoop]: Abstraction has 12817 states and 18386 transitions. [2021-11-07 08:01:50,019 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-07 08:01:50,019 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12817 states and 18386 transitions. [2021-11-07 08:01:50,079 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12644 [2021-11-07 08:01:50,079 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:50,079 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:50,084 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:50,084 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:50,085 INFO L791 eck$LassoCheckResult]: Stem: 122505#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 122506#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 122326#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 122044#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 122045#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 122955#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 122180#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 122181#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 122637#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 122466#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 122467#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 122249#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 122250#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 122647#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 122830#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 122989#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 123027#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 122260#L946-1 assume !(0 == ~M_E~0); 122261#L1258-1 assume !(0 == ~T1_E~0); 122550#L1263-1 assume !(0 == ~T2_E~0); 122551#L1268-1 assume !(0 == ~T3_E~0); 122866#L1273-1 assume !(0 == ~T4_E~0); 123490#L1278-1 assume !(0 == ~T5_E~0); 123321#L1283-1 assume !(0 == ~T6_E~0); 123322#L1288-1 assume !(0 == ~T7_E~0); 123611#L1293-1 assume !(0 == ~T8_E~0); 123595#L1298-1 assume !(0 == ~T9_E~0); 123507#L1303-1 assume !(0 == ~T10_E~0); 122074#L1308-1 assume !(0 == ~T11_E~0); 122016#L1313-1 assume !(0 == ~T12_E~0); 122017#L1318-1 assume !(0 == ~T13_E~0); 122023#L1323-1 assume !(0 == ~E_1~0); 122024#L1328-1 assume !(0 == ~E_2~0); 122190#L1333-1 assume !(0 == ~E_3~0); 123181#L1338-1 assume !(0 == ~E_4~0); 123182#L1343-1 assume !(0 == ~E_5~0); 123292#L1348-1 assume !(0 == ~E_6~0); 123643#L1353-1 assume !(0 == ~E_7~0); 122886#L1358-1 assume !(0 == ~E_8~0); 122887#L1363-1 assume !(0 == ~E_9~0); 123205#L1368-1 assume !(0 == ~E_10~0); 121857#L1373-1 assume !(0 == ~E_11~0); 121858#L1378-1 assume !(0 == ~E_12~0); 122139#L1383-1 assume !(0 == ~E_13~0); 122140#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 122893#L607 assume !(1 == ~m_pc~0); 122211#L607-2 is_master_triggered_~__retres1~0 := 0; 122212#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 123289#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 122807#L1560 assume !(0 != activate_threads_~tmp~1); 122808#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 122036#L626 assume !(1 == ~t1_pc~0); 122037#L626-2 is_transmit1_triggered_~__retres1~1 := 0; 122302#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 122303#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 122470#L1568 assume !(0 != activate_threads_~tmp___0~0); 121936#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 121937#L645 assume !(1 == ~t2_pc~0); 122009#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 122010#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 122686#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 122687#L1576 assume !(0 != activate_threads_~tmp___1~0); 122782#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 122783#L664 assume !(1 == ~t3_pc~0); 123226#L664-2 is_transmit3_triggered_~__retres1~3 := 0; 121783#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 121784#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 122435#L1584 assume !(0 != activate_threads_~tmp___2~0); 122436#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 123523#L683 assume !(1 == ~t4_pc~0); 123013#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 122963#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 122964#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 122998#L1592 assume !(0 != activate_threads_~tmp___3~0); 123138#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 122730#L702 assume 1 == ~t5_pc~0; 122731#L703 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 122656#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 123133#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 123472#L1600 assume !(0 != activate_threads_~tmp___4~0); 123400#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 121830#L721 assume !(1 == ~t6_pc~0); 121805#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 121806#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 121963#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 122442#L1608 assume !(0 != activate_threads_~tmp___5~0); 122443#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 123064#L740 assume 1 == ~t7_pc~0; 121878#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 121693#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 121694#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 121683#L1616 assume !(0 != activate_threads_~tmp___6~0); 121684#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 122380#L759 assume !(1 == ~t8_pc~0); 122381#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 122409#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 123131#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 123132#L1624 assume !(0 != activate_threads_~tmp___7~0); 123275#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 123610#L778 assume 1 == ~t9_pc~0; 123469#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 121856#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 121798#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 121726#L1632 assume !(0 != activate_threads_~tmp___8~0); 121727#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 122048#L797 assume 1 == ~t10_pc~0; 122049#L798 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 122167#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 123344#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 122548#L1640 assume !(0 != activate_threads_~tmp___9~0); 122549#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 122850#L816 assume !(1 == ~t11_pc~0); 121766#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 121765#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 122509#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 122450#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 122451#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 122988#L835 assume 1 == ~t12_pc~0; 122863#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 121921#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 121943#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 122084#L1656 assume !(0 != activate_threads_~tmp___11~0); 122609#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 122610#L854 assume !(1 == ~t13_pc~0); 122251#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 122252#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 122298#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 121961#L1664 assume !(0 != activate_threads_~tmp___12~0); 121962#L1664-2 assume !(1 == ~M_E~0); 122768#L1401-1 assume !(1 == ~T1_E~0); 122769#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 123053#L1411-1 assume !(1 == ~T3_E~0); 123054#L1416-1 assume !(1 == ~T4_E~0); 122702#L1421-1 assume !(1 == ~T5_E~0); 122247#L1426-1 assume !(1 == ~T6_E~0); 122248#L1431-1 assume !(1 == ~T7_E~0); 121801#L1436-1 assume !(1 == ~T8_E~0); 121802#L1441-1 assume !(1 == ~T9_E~0); 122540#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 122541#L1451-1 assume !(1 == ~T11_E~0); 123288#L1456-1 assume !(1 == ~T12_E~0); 122911#L1461-1 assume !(1 == ~T13_E~0); 122461#L1466-1 assume !(1 == ~E_1~0); 122462#L1471-1 assume !(1 == ~E_2~0); 123273#L1476-1 assume !(1 == ~E_3~0); 123274#L1481-1 assume !(1 == ~E_4~0); 123450#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 122089#L1491-1 assume !(1 == ~E_6~0); 121734#L1496-1 assume !(1 == ~E_7~0); 121735#L1501-1 assume !(1 == ~E_8~0); 122538#L1506-1 assume !(1 == ~E_9~0); 122539#L1511-1 assume !(1 == ~E_10~0); 122493#L1516-1 assume !(1 == ~E_11~0); 121679#L1521-1 assume !(1 == ~E_12~0); 121680#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 121733#L1892-1 [2021-11-07 08:01:50,086 INFO L793 eck$LassoCheckResult]: Loop: 121733#L1892-1 assume !false; 121742#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 121852#L1233 assume !false; 123559#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 122810#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 122788#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 122956#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 121777#L1046 assume !(0 != eval_~tmp~0); 121779#L1248 start_simulation_~kernel_st~0 := 2; 121813#L874-1 start_simulation_~kernel_st~0 := 3; 122990#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 122880#L1258-4 assume !(0 == ~T1_E~0); 122881#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 134080#L1268-3 assume !(0 == ~T3_E~0); 134079#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 134078#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 134077#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 134076#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 134075#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 134074#L1298-3 assume !(0 == ~T9_E~0); 134073#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 134072#L1308-3 assume !(0 == ~T11_E~0); 134071#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 122794#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 121951#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 121952#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 133713#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 133712#L1338-3 assume !(0 == ~E_4~0); 133711#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 133710#L1348-3 assume !(0 == ~E_6~0); 133709#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 133673#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 133672#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 133671#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 133670#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 133669#L1378-3 assume !(0 == ~E_12~0); 123554#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 123285#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 123286#L607-42 assume !(1 == ~m_pc~0); 123111#L607-44 is_master_triggered_~__retres1~0 := 0; 122585#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 122586#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 122318#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 122319#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 122851#L626-42 assume !(1 == ~t1_pc~0); 123380#L626-44 is_transmit1_triggered_~__retres1~1 := 0; 134233#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 134232#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 134231#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 134230#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 134229#L645-42 assume !(1 == ~t2_pc~0); 134227#L645-44 is_transmit2_triggered_~__retres1~2 := 0; 134225#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 134223#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 134222#L1576-42 assume !(0 != activate_threads_~tmp___1~0); 134220#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 134219#L664-42 assume !(1 == ~t3_pc~0); 129729#L664-44 is_transmit3_triggered_~__retres1~3 := 0; 134218#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 134217#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 134216#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 134215#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 134214#L683-42 assume !(1 == ~t4_pc~0); 134212#L683-44 is_transmit4_triggered_~__retres1~4 := 0; 134211#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 134210#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 134209#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 134208#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 134207#L702-42 assume !(1 == ~t5_pc~0); 134206#L702-44 is_transmit5_triggered_~__retres1~5 := 0; 134204#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 134203#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 134202#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 134201#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 134200#L721-42 assume !(1 == ~t6_pc~0); 134198#L721-44 is_transmit6_triggered_~__retres1~6 := 0; 134197#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 134196#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 134195#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 134194#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 134193#L740-42 assume !(1 == ~t7_pc~0); 134192#L740-44 is_transmit7_triggered_~__retres1~7 := 0; 134190#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 134189#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 134188#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 134187#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 134186#L759-42 assume 1 == ~t8_pc~0; 134184#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 134183#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 134182#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 134181#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 134180#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 134179#L778-42 assume 1 == ~t9_pc~0; 134178#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 134176#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 134175#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 134174#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 134173#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 134172#L797-42 assume 1 == ~t10_pc~0; 134170#L798-14 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 134169#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 134168#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 134167#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 134166#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 134164#L816-42 assume 1 == ~t11_pc~0; 134162#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 134160#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 134159#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 134158#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 134157#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 134156#L835-42 assume 1 == ~t12_pc~0; 134154#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 134153#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 134152#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 134151#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 134150#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 134149#L854-42 assume !(1 == ~t13_pc~0); 134147#L854-44 is_transmit13_triggered_~__retres1~13 := 0; 134146#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 134145#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 134144#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 134143#L1664-44 assume !(1 == ~M_E~0); 134142#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 134141#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 134140#L1411-3 assume !(1 == ~T3_E~0); 134139#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 134138#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 134137#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 134136#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 134135#L1436-3 assume !(1 == ~T8_E~0); 134134#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 134133#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 134132#L1451-3 assume !(1 == ~T11_E~0); 134131#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 134130#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 134129#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 134128#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 134127#L1476-3 assume !(1 == ~E_3~0); 134126#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 134125#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 134124#L1491-3 assume !(1 == ~E_6~0); 134123#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 134122#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 134121#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 134120#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 134070#L1516-3 assume !(1 == ~E_11~0); 134069#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 134068#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 134067#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 134055#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 134052#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 134051#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 134050#L1911 assume !(0 == start_simulation_~tmp~3); 121776#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 122196#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 122150#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 123040#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 121861#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 121862#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 122599#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 134044#L1924 assume !(0 != start_simulation_~tmp___0~1); 121733#L1892-1 [2021-11-07 08:01:50,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:50,087 INFO L85 PathProgramCache]: Analyzing trace with hash 2031194018, now seen corresponding path program 1 times [2021-11-07 08:01:50,087 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:50,087 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [485427775] [2021-11-07 08:01:50,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:50,088 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:50,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:50,160 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:50,161 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:50,161 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [485427775] [2021-11-07 08:01:50,161 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [485427775] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:50,161 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:50,162 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:50,162 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1211056475] [2021-11-07 08:01:50,162 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:50,163 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:50,163 INFO L85 PathProgramCache]: Analyzing trace with hash -881148728, now seen corresponding path program 1 times [2021-11-07 08:01:50,164 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:50,164 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [716799318] [2021-11-07 08:01:50,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:50,164 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:50,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:50,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:50,223 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:50,223 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [716799318] [2021-11-07 08:01:50,224 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [716799318] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:50,224 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:50,224 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:50,224 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1260186271] [2021-11-07 08:01:50,225 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:01:50,225 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:50,226 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-07 08:01:50,226 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-07 08:01:50,226 INFO L87 Difference]: Start difference. First operand 12817 states and 18386 transitions. cyclomatic complexity: 5571 Second operand has 4 states, 4 states have (on average 38.75) internal successors, (155), 3 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:50,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:50,729 INFO L93 Difference]: Finished difference Result 31090 states and 44317 transitions. [2021-11-07 08:01:50,729 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 08:01:50,729 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31090 states and 44317 transitions. [2021-11-07 08:01:50,901 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 30486 [2021-11-07 08:01:51,047 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31090 states to 31090 states and 44317 transitions. [2021-11-07 08:01:51,047 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31090 [2021-11-07 08:01:51,082 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31090 [2021-11-07 08:01:51,083 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31090 states and 44317 transitions. [2021-11-07 08:01:51,420 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:51,420 INFO L681 BuchiCegarLoop]: Abstraction has 31090 states and 44317 transitions. [2021-11-07 08:01:51,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31090 states and 44317 transitions. [2021-11-07 08:01:51,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31090 to 24544. [2021-11-07 08:01:51,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24544 states, 24544 states have (on average 1.4290661668839635) internal successors, (35075), 24543 states have internal predecessors, (35075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:52,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24544 states to 24544 states and 35075 transitions. [2021-11-07 08:01:52,056 INFO L704 BuchiCegarLoop]: Abstraction has 24544 states and 35075 transitions. [2021-11-07 08:01:52,056 INFO L587 BuchiCegarLoop]: Abstraction has 24544 states and 35075 transitions. [2021-11-07 08:01:52,056 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-07 08:01:52,057 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24544 states and 35075 transitions. [2021-11-07 08:01:52,150 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 24368 [2021-11-07 08:01:52,150 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:52,151 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:52,156 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:52,156 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:52,156 INFO L791 eck$LassoCheckResult]: Stem: 166423#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 166424#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 166245#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 165962#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 165963#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 166871#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 166099#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 166100#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 166555#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 166383#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 166384#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 166168#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 166169#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 166565#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 166746#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 166905#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 166943#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 166179#L946-1 assume !(0 == ~M_E~0); 166180#L1258-1 assume !(0 == ~T1_E~0); 166471#L1263-1 assume !(0 == ~T2_E~0); 166472#L1268-1 assume !(0 == ~T3_E~0); 166783#L1273-1 assume !(0 == ~T4_E~0); 167437#L1278-1 assume !(0 == ~T5_E~0); 167254#L1283-1 assume !(0 == ~T6_E~0); 167255#L1288-1 assume !(0 == ~T7_E~0); 167574#L1293-1 assume !(0 == ~T8_E~0); 167558#L1298-1 assume !(0 == ~T9_E~0); 167451#L1303-1 assume !(0 == ~T10_E~0); 165991#L1308-1 assume !(0 == ~T11_E~0); 165934#L1313-1 assume !(0 == ~T12_E~0); 165935#L1318-1 assume !(0 == ~T13_E~0); 165941#L1323-1 assume !(0 == ~E_1~0); 165942#L1328-1 assume !(0 == ~E_2~0); 166109#L1333-1 assume !(0 == ~E_3~0); 167096#L1338-1 assume !(0 == ~E_4~0); 167097#L1343-1 assume !(0 == ~E_5~0); 167219#L1348-1 assume !(0 == ~E_6~0); 167613#L1353-1 assume !(0 == ~E_7~0); 166803#L1358-1 assume !(0 == ~E_8~0); 166804#L1363-1 assume !(0 == ~E_9~0); 167124#L1368-1 assume !(0 == ~E_10~0); 165774#L1373-1 assume !(0 == ~E_11~0); 165775#L1378-1 assume !(0 == ~E_12~0); 166058#L1383-1 assume !(0 == ~E_13~0); 166059#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 166810#L607 assume !(1 == ~m_pc~0); 166130#L607-2 is_master_triggered_~__retres1~0 := 0; 166131#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 167216#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 166722#L1560 assume !(0 != activate_threads_~tmp~1); 166723#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 165954#L626 assume !(1 == ~t1_pc~0); 165955#L626-2 is_transmit1_triggered_~__retres1~1 := 0; 166221#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 166222#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 166387#L1568 assume !(0 != activate_threads_~tmp___0~0); 165853#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 165854#L645 assume !(1 == ~t2_pc~0); 165927#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 165928#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 166604#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 166605#L1576 assume !(0 != activate_threads_~tmp___1~0); 166698#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 166699#L664 assume !(1 == ~t3_pc~0); 167148#L664-2 is_transmit3_triggered_~__retres1~3 := 0; 165698#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 165699#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 166353#L1584 assume !(0 != activate_threads_~tmp___2~0); 166354#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 167473#L683 assume !(1 == ~t4_pc~0); 166929#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 166879#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 166880#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 166914#L1592 assume !(0 != activate_threads_~tmp___3~0); 167052#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 166646#L702 assume !(1 == ~t5_pc~0); 166573#L702-2 is_transmit5_triggered_~__retres1~5 := 0; 166574#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 167047#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 167419#L1600 assume !(0 != activate_threads_~tmp___4~0); 167335#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 165746#L721 assume !(1 == ~t6_pc~0); 165720#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 165721#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 165881#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 166360#L1608 assume !(0 != activate_threads_~tmp___5~0); 166361#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 166977#L740 assume 1 == ~t7_pc~0; 165795#L741 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 165610#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 165611#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 165600#L1616 assume !(0 != activate_threads_~tmp___6~0); 165601#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 166298#L759 assume !(1 == ~t8_pc~0); 166299#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 166329#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 167045#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 167046#L1624 assume !(0 != activate_threads_~tmp___7~0); 167199#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 167573#L778 assume 1 == ~t9_pc~0; 167416#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 165772#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 165713#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 165641#L1632 assume !(0 != activate_threads_~tmp___8~0); 165642#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 165966#L797 assume 1 == ~t10_pc~0; 165967#L798 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 166086#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 167280#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 166469#L1640 assume !(0 != activate_threads_~tmp___9~0); 166470#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 166765#L816 assume !(1 == ~t11_pc~0); 165681#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 165680#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 166427#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 166368#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 166369#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 166904#L835 assume 1 == ~t12_pc~0; 166780#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 165838#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 165861#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 166003#L1656 assume !(0 != activate_threads_~tmp___11~0); 166528#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 166529#L854 assume !(1 == ~t13_pc~0); 166170#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 166171#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 166217#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 165879#L1664 assume !(0 != activate_threads_~tmp___12~0); 165880#L1664-2 assume !(1 == ~M_E~0); 166682#L1401-1 assume !(1 == ~T1_E~0); 166683#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 166964#L1411-1 assume !(1 == ~T3_E~0); 166965#L1416-1 assume !(1 == ~T4_E~0); 166620#L1421-1 assume !(1 == ~T5_E~0); 166166#L1426-1 assume !(1 == ~T6_E~0); 166167#L1431-1 assume !(1 == ~T7_E~0); 165716#L1436-1 assume !(1 == ~T8_E~0); 165717#L1441-1 assume !(1 == ~T9_E~0); 166461#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 166462#L1451-1 assume !(1 == ~T11_E~0); 167215#L1456-1 assume !(1 == ~T12_E~0); 166828#L1461-1 assume !(1 == ~T13_E~0); 166378#L1466-1 assume !(1 == ~E_1~0); 166379#L1471-1 assume !(1 == ~E_2~0); 167197#L1476-1 assume !(1 == ~E_3~0); 167198#L1481-1 assume !(1 == ~E_4~0); 167394#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 166008#L1491-1 assume !(1 == ~E_6~0); 165649#L1496-1 assume !(1 == ~E_7~0); 165650#L1501-1 assume !(1 == ~E_8~0); 166459#L1506-1 assume !(1 == ~E_9~0); 166460#L1511-1 assume !(1 == ~E_10~0); 166410#L1516-1 assume !(1 == ~E_11~0); 165596#L1521-1 assume !(1 == ~E_12~0); 165597#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 165648#L1892-1 [2021-11-07 08:01:52,157 INFO L793 eck$LassoCheckResult]: Loop: 165648#L1892-1 assume !false; 165657#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 165768#L1233 assume !false; 167515#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 166725#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 166704#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 166872#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 165692#L1046 assume !(0 != eval_~tmp~0); 165694#L1248 start_simulation_~kernel_st~0 := 2; 190082#L874-1 start_simulation_~kernel_st~0 := 3; 190081#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 190080#L1258-4 assume !(0 == ~T1_E~0); 190079#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 190078#L1268-3 assume !(0 == ~T3_E~0); 190077#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 190076#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 190075#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 190074#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 190073#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 190072#L1298-3 assume !(0 == ~T9_E~0); 190071#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 190070#L1308-3 assume !(0 == ~T11_E~0); 190069#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 190068#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 190067#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 190066#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 190065#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 190064#L1338-3 assume !(0 == ~E_4~0); 190063#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 190062#L1348-3 assume !(0 == ~E_6~0); 190061#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 167423#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 166661#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 166223#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 166224#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 166999#L1378-3 assume !(0 == ~E_12~0); 167000#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 167210#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 167211#L607-42 assume !(1 == ~m_pc~0); 167025#L607-44 is_master_triggered_~__retres1~0 := 0; 166507#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 166508#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 167189#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 188511#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 167318#L626-42 assume !(1 == ~t1_pc~0); 167319#L626-44 is_transmit1_triggered_~__retres1~1 := 0; 189198#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 189196#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 189194#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 189192#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 189187#L645-42 assume !(1 == ~t2_pc~0); 189185#L645-44 is_transmit2_triggered_~__retres1~2 := 0; 189183#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 189182#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 189179#L1576-42 assume !(0 != activate_threads_~tmp___1~0); 189176#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 189174#L664-42 assume !(1 == ~t3_pc~0); 188354#L664-44 is_transmit3_triggered_~__retres1~3 := 0; 189171#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 189169#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 189167#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 189164#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 167662#L683-42 assume 1 == ~t4_pc~0; 167633#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 166813#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 166947#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 167466#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 167467#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 167264#L702-42 assume !(1 == ~t5_pc~0); 166316#L702-44 is_transmit5_triggered_~__retres1~5 := 0; 166317#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 166611#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 167370#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 165635#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 165636#L721-42 assume !(1 == ~t6_pc~0); 165792#L721-44 is_transmit6_triggered_~__retres1~6 := 0; 166268#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 166269#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 167583#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 166439#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 166288#L740-42 assume 1 == ~t7_pc~0; 166289#L741-14 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 166028#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 166568#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 166419#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 166420#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 166696#L759-42 assume 1 == ~t8_pc~0; 166547#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 166477#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 166478#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 166556#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 166557#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 166647#L778-42 assume 1 == ~t9_pc~0; 166488#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 166490#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 166911#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 166814#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 166815#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 166874#L797-42 assume !(1 == ~t10_pc~0); 166035#L797-44 is_transmit10_triggered_~__retres1~10 := 0; 166034#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 167059#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 167446#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 166912#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 166913#L816-42 assume 1 == ~t11_pc~0; 165586#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 165587#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 166126#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 166127#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 166205#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 166206#L835-42 assume 1 == ~t12_pc~0; 166608#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 166503#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 188877#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 188875#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 188873#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 188871#L854-42 assume !(1 == ~t13_pc~0); 188868#L854-44 is_transmit13_triggered_~__retres1~13 := 0; 188866#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 188863#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 188862#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 188861#L1664-44 assume !(1 == ~M_E~0); 188860#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 188859#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 188858#L1411-3 assume !(1 == ~T3_E~0); 188857#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 188856#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 188855#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 188854#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 188853#L1436-3 assume !(1 == ~T8_E~0); 188851#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 167247#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 167240#L1451-3 assume !(1 == ~T11_E~0); 166519#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 166173#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 166174#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 167601#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 166113#L1476-3 assume !(1 == ~E_3~0); 166114#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 166513#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 166141#L1491-3 assume !(1 == ~E_6~0); 166142#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 166553#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 166554#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 166996#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 166985#L1516-3 assume !(1 == ~E_11~0); 166986#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 166665#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 166666#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 167092#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 165946#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 166847#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 166479#L1911 assume !(0 == start_simulation_~tmp~3); 165691#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 166115#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 166069#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 166951#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 165778#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 165779#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 166006#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 166007#L1924 assume !(0 != start_simulation_~tmp___0~1); 165648#L1892-1 [2021-11-07 08:01:52,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:52,158 INFO L85 PathProgramCache]: Analyzing trace with hash -1246845375, now seen corresponding path program 1 times [2021-11-07 08:01:52,159 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:52,159 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1994418597] [2021-11-07 08:01:52,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:52,159 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:52,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:52,225 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:52,225 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:52,225 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1994418597] [2021-11-07 08:01:52,226 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1994418597] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:52,226 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:52,226 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:52,226 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1290179261] [2021-11-07 08:01:52,227 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:52,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:52,227 INFO L85 PathProgramCache]: Analyzing trace with hash 346352647, now seen corresponding path program 1 times [2021-11-07 08:01:52,228 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:52,228 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1523962384] [2021-11-07 08:01:52,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:52,228 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:52,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:52,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:52,282 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:52,283 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1523962384] [2021-11-07 08:01:52,283 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1523962384] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:52,283 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:52,283 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:52,284 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1379796324] [2021-11-07 08:01:52,284 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:01:52,285 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:52,285 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-07 08:01:52,285 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-07 08:01:52,286 INFO L87 Difference]: Start difference. First operand 24544 states and 35075 transitions. cyclomatic complexity: 10533 Second operand has 4 states, 4 states have (on average 38.75) internal successors, (155), 3 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:53,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:53,139 INFO L93 Difference]: Finished difference Result 59511 states and 84556 transitions. [2021-11-07 08:01:53,140 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 08:01:53,140 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59511 states and 84556 transitions. [2021-11-07 08:01:53,649 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 58476 [2021-11-07 08:01:53,938 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59511 states to 59511 states and 84556 transitions. [2021-11-07 08:01:53,938 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 59511 [2021-11-07 08:01:53,999 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 59511 [2021-11-07 08:01:53,999 INFO L73 IsDeterministic]: Start isDeterministic. Operand 59511 states and 84556 transitions. [2021-11-07 08:01:54,068 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:54,068 INFO L681 BuchiCegarLoop]: Abstraction has 59511 states and 84556 transitions. [2021-11-07 08:01:54,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59511 states and 84556 transitions. [2021-11-07 08:01:54,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59511 to 47095. [2021-11-07 08:01:54,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47095 states, 47095 states have (on average 1.4243550270729377) internal successors, (67080), 47094 states have internal predecessors, (67080), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:55,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47095 states to 47095 states and 67080 transitions. [2021-11-07 08:01:55,113 INFO L704 BuchiCegarLoop]: Abstraction has 47095 states and 67080 transitions. [2021-11-07 08:01:55,113 INFO L587 BuchiCegarLoop]: Abstraction has 47095 states and 67080 transitions. [2021-11-07 08:01:55,113 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-07 08:01:55,114 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47095 states and 67080 transitions. [2021-11-07 08:01:55,489 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 46912 [2021-11-07 08:01:55,490 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:01:55,491 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:01:55,502 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:55,502 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:01:55,503 INFO L791 eck$LassoCheckResult]: Stem: 250489#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 250490#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 250304#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 250023#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 250024#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 250939#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 250158#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 250159#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 250617#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 250448#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 250449#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 250227#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 250228#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 250627#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 250813#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 250973#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 251012#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 250238#L946-1 assume !(0 == ~M_E~0); 250239#L1258-1 assume !(0 == ~T1_E~0); 250534#L1263-1 assume !(0 == ~T2_E~0); 250535#L1268-1 assume !(0 == ~T3_E~0); 250850#L1273-1 assume !(0 == ~T4_E~0); 251512#L1278-1 assume !(0 == ~T5_E~0); 251336#L1283-1 assume !(0 == ~T6_E~0); 251337#L1288-1 assume !(0 == ~T7_E~0); 251645#L1293-1 assume !(0 == ~T8_E~0); 251625#L1298-1 assume !(0 == ~T9_E~0); 251528#L1303-1 assume !(0 == ~T10_E~0); 250052#L1308-1 assume !(0 == ~T11_E~0); 249995#L1313-1 assume !(0 == ~T12_E~0); 249996#L1318-1 assume !(0 == ~T13_E~0); 250002#L1323-1 assume !(0 == ~E_1~0); 250003#L1328-1 assume !(0 == ~E_2~0); 250168#L1333-1 assume !(0 == ~E_3~0); 251166#L1338-1 assume !(0 == ~E_4~0); 251167#L1343-1 assume !(0 == ~E_5~0); 251293#L1348-1 assume !(0 == ~E_6~0); 251684#L1353-1 assume !(0 == ~E_7~0); 250870#L1358-1 assume !(0 == ~E_8~0); 250871#L1363-1 assume !(0 == ~E_9~0); 251189#L1368-1 assume !(0 == ~E_10~0); 249838#L1373-1 assume !(0 == ~E_11~0); 249839#L1378-1 assume !(0 == ~E_12~0); 250115#L1383-1 assume !(0 == ~E_13~0); 250116#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 250877#L607 assume !(1 == ~m_pc~0); 250189#L607-2 is_master_triggered_~__retres1~0 := 0; 250190#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 251287#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 250789#L1560 assume !(0 != activate_threads_~tmp~1); 250790#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 250015#L626 assume !(1 == ~t1_pc~0); 250016#L626-2 is_transmit1_triggered_~__retres1~1 := 0; 250280#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 250281#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 250452#L1568 assume !(0 != activate_threads_~tmp___0~0); 249914#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 249915#L645 assume !(1 == ~t2_pc~0); 249988#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 249989#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 250668#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 250669#L1576 assume !(0 != activate_threads_~tmp___1~0); 250764#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 250765#L664 assume !(1 == ~t3_pc~0); 251215#L664-2 is_transmit3_triggered_~__retres1~3 := 0; 249764#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 249765#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 250418#L1584 assume !(0 != activate_threads_~tmp___2~0); 250419#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 251550#L683 assume !(1 == ~t4_pc~0); 250997#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 250947#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 250948#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 250982#L1592 assume !(0 != activate_threads_~tmp___3~0); 251120#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 250711#L702 assume !(1 == ~t5_pc~0); 250635#L702-2 is_transmit5_triggered_~__retres1~5 := 0; 250636#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 251115#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 251495#L1600 assume !(0 != activate_threads_~tmp___4~0); 251416#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 249812#L721 assume !(1 == ~t6_pc~0); 249786#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 249787#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 249942#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 250425#L1608 assume !(0 != activate_threads_~tmp___5~0); 250426#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 251047#L740 assume !(1 == ~t7_pc~0); 251048#L740-2 is_transmit7_triggered_~__retres1~7 := 0; 249675#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 249676#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 249665#L1616 assume !(0 != activate_threads_~tmp___6~0); 249666#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 250358#L759 assume !(1 == ~t8_pc~0); 250359#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 250389#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 251113#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 251114#L1624 assume !(0 != activate_threads_~tmp___7~0); 251270#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 251644#L778 assume 1 == ~t9_pc~0; 251492#L779 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 249837#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 249779#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 249706#L1632 assume !(0 != activate_threads_~tmp___8~0); 249707#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 250027#L797 assume 1 == ~t10_pc~0; 250028#L798 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 250145#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 251362#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 250532#L1640 assume !(0 != activate_threads_~tmp___9~0); 250533#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 250833#L816 assume !(1 == ~t11_pc~0); 249747#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 249746#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 250493#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 250433#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 250434#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 250972#L835 assume 1 == ~t12_pc~0; 250847#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 249899#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 249922#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 250062#L1656 assume !(0 != activate_threads_~tmp___11~0); 250589#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 250590#L854 assume !(1 == ~t13_pc~0); 250229#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 250230#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 250276#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 249940#L1664 assume !(0 != activate_threads_~tmp___12~0); 249941#L1664-2 assume !(1 == ~M_E~0); 250748#L1401-1 assume !(1 == ~T1_E~0); 250749#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 251035#L1411-1 assume !(1 == ~T3_E~0); 251036#L1416-1 assume !(1 == ~T4_E~0); 250684#L1421-1 assume !(1 == ~T5_E~0); 250225#L1426-1 assume !(1 == ~T6_E~0); 250226#L1431-1 assume !(1 == ~T7_E~0); 249782#L1436-1 assume !(1 == ~T8_E~0); 249783#L1441-1 assume !(1 == ~T9_E~0); 250524#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 250525#L1451-1 assume !(1 == ~T11_E~0); 251286#L1456-1 assume !(1 == ~T12_E~0); 250896#L1461-1 assume !(1 == ~T13_E~0); 250443#L1466-1 assume !(1 == ~E_1~0); 250444#L1471-1 assume !(1 == ~E_2~0); 251268#L1476-1 assume !(1 == ~E_3~0); 251269#L1481-1 assume !(1 == ~E_4~0); 251469#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 250067#L1491-1 assume !(1 == ~E_6~0); 249714#L1496-1 assume !(1 == ~E_7~0); 249715#L1501-1 assume !(1 == ~E_8~0); 250522#L1506-1 assume !(1 == ~E_9~0); 250523#L1511-1 assume !(1 == ~E_10~0); 250477#L1516-1 assume !(1 == ~E_11~0); 249661#L1521-1 assume !(1 == ~E_12~0); 249662#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 249713#L1892-1 [2021-11-07 08:01:55,504 INFO L793 eck$LassoCheckResult]: Loop: 249713#L1892-1 assume !false; 249722#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 249833#L1233 assume !false; 251589#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 250792#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 250770#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 250940#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 249758#L1046 assume !(0 != eval_~tmp~0); 249760#L1248 start_simulation_~kernel_st~0 := 2; 296704#L874-1 start_simulation_~kernel_st~0 := 3; 251538#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 250864#L1258-4 assume !(0 == ~T1_E~0); 249928#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 249929#L1268-3 assume !(0 == ~T3_E~0); 251666#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 251674#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 251675#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 250150#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 250151#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 251350#L1298-3 assume !(0 == ~T9_E~0); 251351#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 251559#L1308-3 assume !(0 == ~T11_E~0); 251349#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 250775#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 249930#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 249931#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 251461#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 250072#L1338-3 assume !(0 == ~E_4~0); 250073#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 251236#L1348-3 assume !(0 == ~E_6~0); 251466#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 251467#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 250726#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 250282#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 250283#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 251068#L1378-3 assume !(0 == ~E_12~0); 251069#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 251282#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 251283#L607-42 assume !(1 == ~m_pc~0); 251093#L607-44 is_master_triggered_~__retres1~0 := 0; 250568#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 250569#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 250296#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 250297#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 250834#L626-42 assume !(1 == ~t1_pc~0); 251398#L626-44 is_transmit1_triggered_~__retres1~1 := 0; 296558#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 296555#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 296552#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 296550#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 296546#L645-42 assume !(1 == ~t2_pc~0); 251210#L645-44 is_transmit2_triggered_~__retres1~2 := 0; 251211#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 251430#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 250171#L1576-42 assume !(0 != activate_threads_~tmp___1~0); 249683#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 249684#L664-42 assume !(1 == ~t3_pc~0); 250205#L664-44 is_transmit3_triggered_~__retres1~3 := 0; 250206#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 251593#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 251010#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 251011#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 251202#L683-42 assume !(1 == ~t4_pc~0); 250879#L683-44 is_transmit4_triggered_~__retres1~4 := 0; 250880#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 251016#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 251544#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 251545#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 251343#L702-42 assume !(1 == ~t5_pc~0); 250376#L702-44 is_transmit5_triggered_~__retres1~5 := 0; 250377#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 250675#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 251449#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 249700#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 249701#L721-42 assume !(1 == ~t6_pc~0); 249855#L721-44 is_transmit6_triggered_~__retres1~6 := 0; 250329#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 250330#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 251656#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 250505#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 250349#L740-42 assume !(1 == ~t7_pc~0); 250086#L740-44 is_transmit7_triggered_~__retres1~7 := 0; 250087#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 250630#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 250485#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 250486#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 250762#L759-42 assume !(1 == ~t8_pc~0); 250609#L759-44 is_transmit8_triggered_~__retres1~8 := 0; 250540#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 250541#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 250618#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 250619#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 250712#L778-42 assume 1 == ~t9_pc~0; 250551#L779-14 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9 := 1; 250553#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 250979#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 250881#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 250882#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 250942#L797-42 assume !(1 == ~t10_pc~0); 250094#L797-44 is_transmit10_triggered_~__retres1~10 := 0; 250093#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 251127#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 251523#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 250980#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 250981#L816-42 assume 1 == ~t11_pc~0; 249651#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 249652#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 250185#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 250186#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 250264#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 250265#L835-42 assume !(1 == ~t12_pc~0); 250563#L835-44 is_transmit12_triggered_~__retres1~12 := 0; 250564#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 250240#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 250241#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 251415#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 251141#L854-42 assume !(1 == ~t13_pc~0); 250183#L854-44 is_transmit13_triggered_~__retres1~13 := 0; 250184#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 249803#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 249804#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 250441#L1664-44 assume !(1 == ~M_E~0); 250442#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 250030#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 249894#L1411-3 assume !(1 == ~T3_E~0); 249895#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 250496#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 250497#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 250070#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 250071#L1436-3 assume !(1 == ~T8_E~0); 249667#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 249668#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 251317#L1451-3 assume !(1 == ~T11_E~0); 250580#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 250232#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 250233#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 251671#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 250172#L1476-3 assume !(1 == ~E_3~0); 250173#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 250574#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 250200#L1491-3 assume !(1 == ~E_6~0); 250201#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 250615#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 250616#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 251065#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 251055#L1516-3 assume !(1 == ~E_11~0); 251056#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 250730#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 250731#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 251162#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 250007#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 250915#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 250542#L1911 assume !(0 == start_simulation_~tmp~3); 249757#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 250174#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 250126#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 251022#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 249842#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 249843#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 250065#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 250066#L1924 assume !(0 != start_simulation_~tmp___0~1); 249713#L1892-1 [2021-11-07 08:01:55,505 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:55,505 INFO L85 PathProgramCache]: Analyzing trace with hash 590967648, now seen corresponding path program 1 times [2021-11-07 08:01:55,505 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:55,505 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [394059706] [2021-11-07 08:01:55,506 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:55,507 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:55,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:55,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:55,572 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:55,573 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [394059706] [2021-11-07 08:01:55,574 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [394059706] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:55,574 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:55,575 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:55,575 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1097154583] [2021-11-07 08:01:55,576 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:01:55,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:01:55,577 INFO L85 PathProgramCache]: Analyzing trace with hash 2031005515, now seen corresponding path program 1 times [2021-11-07 08:01:55,577 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:01:55,577 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [846797510] [2021-11-07 08:01:55,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:01:55,580 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:01:55,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:01:55,640 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:01:55,641 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:01:55,641 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [846797510] [2021-11-07 08:01:55,641 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [846797510] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:01:55,641 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:01:55,642 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:01:55,642 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [518782919] [2021-11-07 08:01:55,642 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:01:55,643 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:01:55,643 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-07 08:01:55,643 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-07 08:01:55,644 INFO L87 Difference]: Start difference. First operand 47095 states and 67080 transitions. cyclomatic complexity: 19987 Second operand has 4 states, 4 states have (on average 38.75) internal successors, (155), 3 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:01:56,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:01:56,699 INFO L93 Difference]: Finished difference Result 113894 states and 161325 transitions. [2021-11-07 08:01:56,699 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 08:01:56,700 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 113894 states and 161325 transitions. [2021-11-07 08:01:57,323 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 112000 [2021-11-07 08:01:57,984 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 113894 states to 113894 states and 161325 transitions. [2021-11-07 08:01:57,984 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 113894 [2021-11-07 08:01:58,052 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 113894 [2021-11-07 08:01:58,055 INFO L73 IsDeterministic]: Start isDeterministic. Operand 113894 states and 161325 transitions. [2021-11-07 08:01:58,220 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:01:58,221 INFO L681 BuchiCegarLoop]: Abstraction has 113894 states and 161325 transitions. [2021-11-07 08:01:58,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113894 states and 161325 transitions. [2021-11-07 08:01:59,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113894 to 90406. [2021-11-07 08:01:59,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 90406 states, 90406 states have (on average 1.4199610645311151) internal successors, (128373), 90405 states have internal predecessors, (128373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:02:00,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90406 states to 90406 states and 128373 transitions. [2021-11-07 08:02:00,260 INFO L704 BuchiCegarLoop]: Abstraction has 90406 states and 128373 transitions. [2021-11-07 08:02:00,260 INFO L587 BuchiCegarLoop]: Abstraction has 90406 states and 128373 transitions. [2021-11-07 08:02:00,261 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-11-07 08:02:00,261 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90406 states and 128373 transitions. [2021-11-07 08:02:00,515 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 90208 [2021-11-07 08:02:00,515 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:02:00,515 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:02:00,527 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:02:00,527 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:02:00,527 INFO L791 eck$LassoCheckResult]: Stem: 411478#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 411479#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 411301#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 411020#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 411021#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 411941#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 411155#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 411156#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 411607#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 411440#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 411441#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 411224#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 411225#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 411617#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 411808#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 411975#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 412014#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 411235#L946-1 assume !(0 == ~M_E~0); 411236#L1258-1 assume !(0 == ~T1_E~0); 411524#L1263-1 assume !(0 == ~T2_E~0); 411525#L1268-1 assume !(0 == ~T3_E~0); 411849#L1273-1 assume !(0 == ~T4_E~0); 412525#L1278-1 assume !(0 == ~T5_E~0); 412336#L1283-1 assume !(0 == ~T6_E~0); 412337#L1288-1 assume !(0 == ~T7_E~0); 412665#L1293-1 assume !(0 == ~T8_E~0); 412644#L1298-1 assume !(0 == ~T9_E~0); 412542#L1303-1 assume !(0 == ~T10_E~0); 411049#L1308-1 assume !(0 == ~T11_E~0); 410992#L1313-1 assume !(0 == ~T12_E~0); 410993#L1318-1 assume !(0 == ~T13_E~0); 410999#L1323-1 assume !(0 == ~E_1~0); 411000#L1328-1 assume !(0 == ~E_2~0); 411165#L1333-1 assume !(0 == ~E_3~0); 412169#L1338-1 assume !(0 == ~E_4~0); 412170#L1343-1 assume !(0 == ~E_5~0); 412292#L1348-1 assume !(0 == ~E_6~0); 412703#L1353-1 assume !(0 == ~E_7~0); 411869#L1358-1 assume !(0 == ~E_8~0); 411870#L1363-1 assume !(0 == ~E_9~0); 412190#L1368-1 assume !(0 == ~E_10~0); 410837#L1373-1 assume !(0 == ~E_11~0); 410838#L1378-1 assume !(0 == ~E_12~0); 411113#L1383-1 assume !(0 == ~E_13~0); 411114#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 411876#L607 assume !(1 == ~m_pc~0); 411187#L607-2 is_master_triggered_~__retres1~0 := 0; 411188#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 412289#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 411782#L1560 assume !(0 != activate_threads_~tmp~1); 411783#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 411012#L626 assume !(1 == ~t1_pc~0); 411013#L626-2 is_transmit1_triggered_~__retres1~1 := 0; 411276#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 411277#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 411444#L1568 assume !(0 != activate_threads_~tmp___0~0); 410912#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 410913#L645 assume !(1 == ~t2_pc~0); 410985#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 410986#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 411660#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 411661#L1576 assume !(0 != activate_threads_~tmp___1~0); 411758#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 411759#L664 assume !(1 == ~t3_pc~0); 412214#L664-2 is_transmit3_triggered_~__retres1~3 := 0; 410762#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 410763#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 411409#L1584 assume !(0 != activate_threads_~tmp___2~0); 411410#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 412563#L683 assume !(1 == ~t4_pc~0); 412000#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 411949#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 411950#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 411984#L1592 assume !(0 != activate_threads_~tmp___3~0); 412122#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 411702#L702 assume !(1 == ~t5_pc~0); 411625#L702-2 is_transmit5_triggered_~__retres1~5 := 0; 411626#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 412117#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 412505#L1600 assume !(0 != activate_threads_~tmp___4~0); 412425#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 410810#L721 assume !(1 == ~t6_pc~0); 410784#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 410785#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 410939#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 411417#L1608 assume !(0 != activate_threads_~tmp___5~0); 411418#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 412048#L740 assume !(1 == ~t7_pc~0); 412049#L740-2 is_transmit7_triggered_~__retres1~7 := 0; 410674#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 410675#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 410664#L1616 assume !(0 != activate_threads_~tmp___6~0); 410665#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 411353#L759 assume !(1 == ~t8_pc~0); 411354#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 411384#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 412114#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 412115#L1624 assume !(0 != activate_threads_~tmp___7~0); 412269#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 412664#L778 assume !(1 == ~t9_pc~0); 410834#L778-2 is_transmit9_triggered_~__retres1~9 := 0; 410835#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 410777#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 410705#L1632 assume !(0 != activate_threads_~tmp___8~0); 410706#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 411024#L797 assume 1 == ~t10_pc~0; 411025#L798 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10 := 1; 411142#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 412369#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 411522#L1640 assume !(0 != activate_threads_~tmp___9~0); 411523#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 411832#L816 assume !(1 == ~t11_pc~0); 410745#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 410744#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 411482#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 411425#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 411426#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 411974#L835 assume 1 == ~t12_pc~0; 411846#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 410897#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 410919#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 411060#L1656 assume !(0 != activate_threads_~tmp___11~0); 411578#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 411579#L854 assume !(1 == ~t13_pc~0); 411226#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 411227#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 411272#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 410937#L1664 assume !(0 != activate_threads_~tmp___12~0); 410938#L1664-2 assume !(1 == ~M_E~0); 411744#L1401-1 assume !(1 == ~T1_E~0); 411745#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 412037#L1411-1 assume !(1 == ~T3_E~0); 412038#L1416-1 assume !(1 == ~T4_E~0); 411676#L1421-1 assume !(1 == ~T5_E~0); 411222#L1426-1 assume !(1 == ~T6_E~0); 411223#L1431-1 assume !(1 == ~T7_E~0); 410780#L1436-1 assume !(1 == ~T8_E~0); 410781#L1441-1 assume !(1 == ~T9_E~0); 411514#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 411515#L1451-1 assume !(1 == ~T11_E~0); 412288#L1456-1 assume !(1 == ~T12_E~0); 411893#L1461-1 assume !(1 == ~T13_E~0); 411435#L1466-1 assume !(1 == ~E_1~0); 411436#L1471-1 assume !(1 == ~E_2~0); 412267#L1476-1 assume !(1 == ~E_3~0); 412268#L1481-1 assume !(1 == ~E_4~0); 412479#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 411065#L1491-1 assume !(1 == ~E_6~0); 410713#L1496-1 assume !(1 == ~E_7~0); 410714#L1501-1 assume !(1 == ~E_8~0); 411512#L1506-1 assume !(1 == ~E_9~0); 411513#L1511-1 assume !(1 == ~E_10~0); 411467#L1516-1 assume !(1 == ~E_11~0); 410660#L1521-1 assume !(1 == ~E_12~0); 410661#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 410712#L1892-1 [2021-11-07 08:02:00,528 INFO L793 eck$LassoCheckResult]: Loop: 410712#L1892-1 assume !false; 410721#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 410831#L1233 assume !false; 412602#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 411785#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 411764#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 411942#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 410756#L1046 assume !(0 != eval_~tmp~0); 410758#L1248 start_simulation_~kernel_st~0 := 2; 500905#L874-1 start_simulation_~kernel_st~0 := 3; 500904#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 500903#L1258-4 assume !(0 == ~T1_E~0); 500902#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 500901#L1268-3 assume !(0 == ~T3_E~0); 500900#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 500899#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 500898#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 500897#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 500896#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 500895#L1298-3 assume !(0 == ~T9_E~0); 500893#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 500891#L1308-3 assume !(0 == ~T11_E~0); 500889#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 500887#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 500885#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 500883#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 500881#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 500879#L1338-3 assume !(0 == ~E_4~0); 500877#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 500875#L1348-3 assume !(0 == ~E_6~0); 500873#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 500871#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 500869#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 500867#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 500865#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 500863#L1378-3 assume !(0 == ~E_12~0); 500861#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 500859#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 500856#L607-42 assume !(1 == ~m_pc~0); 500854#L607-44 is_master_triggered_~__retres1~0 := 0; 500852#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 500849#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 500786#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 500785#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 412409#L626-42 assume !(1 == ~t1_pc~0); 412410#L626-44 is_transmit1_triggered_~__retres1~1 := 0; 499475#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 499431#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 499421#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 499418#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 499417#L645-42 assume 1 == ~t2_pc~0; 499415#L646-14 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 499413#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 499411#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 499405#L1576-42 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 499381#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 412708#L664-42 assume !(1 == ~t3_pc~0); 412709#L664-44 is_transmit3_triggered_~__retres1~3 := 0; 500318#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 500316#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 500314#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 500312#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 500310#L683-42 assume 1 == ~t4_pc~0; 500308#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 500306#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 500305#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 500303#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 500301#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 412349#L702-42 assume !(1 == ~t5_pc~0); 412350#L702-44 is_transmit5_triggered_~__retres1~5 := 0; 500102#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 412734#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 412457#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 410699#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 410700#L721-42 assume !(1 == ~t6_pc~0); 410854#L721-44 is_transmit6_triggered_~__retres1~6 := 0; 411324#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 411325#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 412676#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 411494#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 411344#L740-42 assume !(1 == ~t7_pc~0); 411084#L740-44 is_transmit7_triggered_~__retres1~7 := 0; 411085#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 411620#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 411474#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 411475#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 411756#L759-42 assume !(1 == ~t8_pc~0); 411600#L759-44 is_transmit8_triggered_~__retres1~8 := 0; 411530#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 411531#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 411608#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 411609#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 411703#L778-42 assume !(1 == ~t9_pc~0); 411710#L778-44 is_transmit9_triggered_~__retres1~9 := 0; 411711#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 411981#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 411880#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 411881#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 411944#L797-42 assume !(1 == ~t10_pc~0); 411092#L797-44 is_transmit10_triggered_~__retres1~10 := 0; 411091#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 412131#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 412536#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 411982#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 411983#L816-42 assume !(1 == ~t11_pc~0); 410652#L816-44 is_transmit11_triggered_~__retres1~11 := 0; 410651#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 411183#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 411184#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 411260#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 411261#L835-42 assume 1 == ~t12_pc~0; 411664#L836-14 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 411553#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 411237#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 411238#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 412424#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 412144#L854-42 assume 1 == ~t13_pc~0; 412145#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 411182#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 410801#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 410802#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 411433#L1664-44 assume !(1 == ~M_E~0); 411434#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 411027#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 410892#L1411-3 assume !(1 == ~T3_E~0); 410893#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 411485#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 411486#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 411068#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 411069#L1436-3 assume !(1 == ~T8_E~0); 410666#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 410667#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 412320#L1451-3 assume !(1 == ~T11_E~0); 411569#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 411229#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 411230#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 412692#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 411170#L1476-3 assume !(1 == ~E_3~0); 411171#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 411563#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 411198#L1491-3 assume !(1 == ~E_6~0); 411199#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 411605#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 411606#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 412067#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 412057#L1516-3 assume !(1 == ~E_11~0); 412058#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 411725#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 411726#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 412165#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 411004#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 411914#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 411532#L1911 assume !(0 == start_simulation_~tmp~3); 410755#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 411172#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 411124#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 412024#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 410841#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 410842#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 411063#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 411064#L1924 assume !(0 != start_simulation_~tmp___0~1); 410712#L1892-1 [2021-11-07 08:02:00,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:02:00,529 INFO L85 PathProgramCache]: Analyzing trace with hash 598718207, now seen corresponding path program 1 times [2021-11-07 08:02:00,529 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:02:00,530 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [82217251] [2021-11-07 08:02:00,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:02:00,530 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:02:00,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:02:00,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:02:00,584 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:02:00,585 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [82217251] [2021-11-07 08:02:00,585 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [82217251] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:02:00,585 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:02:00,585 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:02:00,586 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1736353606] [2021-11-07 08:02:00,586 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:02:00,586 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:02:00,587 INFO L85 PathProgramCache]: Analyzing trace with hash 1320633735, now seen corresponding path program 1 times [2021-11-07 08:02:00,587 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:02:00,587 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1127390703] [2021-11-07 08:02:00,587 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:02:00,588 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:02:00,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:02:00,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:02:00,631 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:02:00,631 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1127390703] [2021-11-07 08:02:00,631 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1127390703] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:02:00,632 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:02:00,632 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:02:00,632 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074979733] [2021-11-07 08:02:00,633 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:02:00,633 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:02:00,633 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-07 08:02:00,633 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-07 08:02:00,634 INFO L87 Difference]: Start difference. First operand 90406 states and 128373 transitions. cyclomatic complexity: 37969 Second operand has 4 states, 4 states have (on average 38.75) internal successors, (155), 3 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:02:02,182 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:02:02,182 INFO L93 Difference]: Finished difference Result 218229 states and 308210 transitions. [2021-11-07 08:02:02,182 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 08:02:02,183 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 218229 states and 308210 transitions. [2021-11-07 08:02:03,744 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 214624 [2021-11-07 08:02:05,065 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 218229 states to 218229 states and 308210 transitions. [2021-11-07 08:02:05,065 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 218229 [2021-11-07 08:02:05,123 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 218229 [2021-11-07 08:02:05,123 INFO L73 IsDeterministic]: Start isDeterministic. Operand 218229 states and 308210 transitions. [2021-11-07 08:02:05,179 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:02:05,179 INFO L681 BuchiCegarLoop]: Abstraction has 218229 states and 308210 transitions. [2021-11-07 08:02:05,385 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 218229 states and 308210 transitions. [2021-11-07 08:02:07,287 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 218229 to 173477. [2021-11-07 08:02:07,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 173477 states, 173477 states have (on average 1.4158533984332218) internal successors, (245618), 173476 states have internal predecessors, (245618), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:02:08,636 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173477 states to 173477 states and 245618 transitions. [2021-11-07 08:02:08,637 INFO L704 BuchiCegarLoop]: Abstraction has 173477 states and 245618 transitions. [2021-11-07 08:02:08,637 INFO L587 BuchiCegarLoop]: Abstraction has 173477 states and 245618 transitions. [2021-11-07 08:02:08,637 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-11-07 08:02:08,637 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 173477 states and 245618 transitions. [2021-11-07 08:02:09,087 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 173248 [2021-11-07 08:02:09,087 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:02:09,087 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:02:09,120 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:02:09,120 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:02:09,121 INFO L791 eck$LassoCheckResult]: Stem: 720137#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 720138#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 719952#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 719668#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 719669#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 720604#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 719802#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 719803#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 720270#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 720097#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 720098#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 719871#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 719872#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 720276#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 720474#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 720641#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 720678#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 719884#L946-1 assume !(0 == ~M_E~0); 719885#L1258-1 assume !(0 == ~T1_E~0); 720182#L1263-1 assume !(0 == ~T2_E~0); 720183#L1268-1 assume !(0 == ~T3_E~0); 720514#L1273-1 assume !(0 == ~T4_E~0); 721209#L1278-1 assume !(0 == ~T5_E~0); 721015#L1283-1 assume !(0 == ~T6_E~0); 721016#L1288-1 assume !(0 == ~T7_E~0); 721347#L1293-1 assume !(0 == ~T8_E~0); 721330#L1298-1 assume !(0 == ~T9_E~0); 721230#L1303-1 assume !(0 == ~T10_E~0); 719696#L1308-1 assume !(0 == ~T11_E~0); 719643#L1313-1 assume !(0 == ~T12_E~0); 719644#L1318-1 assume !(0 == ~T13_E~0); 719649#L1323-1 assume !(0 == ~E_1~0); 719650#L1328-1 assume !(0 == ~E_2~0); 719815#L1333-1 assume !(0 == ~E_3~0); 720840#L1338-1 assume !(0 == ~E_4~0); 720841#L1343-1 assume !(0 == ~E_5~0); 720975#L1348-1 assume !(0 == ~E_6~0); 721380#L1353-1 assume !(0 == ~E_7~0); 720534#L1358-1 assume !(0 == ~E_8~0); 720535#L1363-1 assume !(0 == ~E_9~0); 720864#L1368-1 assume !(0 == ~E_10~0); 719484#L1373-1 assume !(0 == ~E_11~0); 719485#L1378-1 assume !(0 == ~E_12~0); 719762#L1383-1 assume !(0 == ~E_13~0); 719763#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 720541#L607 assume !(1 == ~m_pc~0); 719834#L607-2 is_master_triggered_~__retres1~0 := 0; 719835#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 720970#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 720446#L1560 assume !(0 != activate_threads_~tmp~1); 720447#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 719660#L626 assume !(1 == ~t1_pc~0); 719661#L626-2 is_transmit1_triggered_~__retres1~1 := 0; 719929#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 719930#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 720103#L1568 assume !(0 != activate_threads_~tmp___0~0); 719563#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 719564#L645 assume !(1 == ~t2_pc~0); 719633#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 719634#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 720323#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 720324#L1576 assume !(0 != activate_threads_~tmp___1~0); 720421#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 720422#L664 assume !(1 == ~t3_pc~0); 720889#L664-2 is_transmit3_triggered_~__retres1~3 := 0; 719413#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 719414#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 720067#L1584 assume !(0 != activate_threads_~tmp___2~0); 720068#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 721252#L683 assume !(1 == ~t4_pc~0); 720665#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 720613#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 720614#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 720649#L1592 assume !(0 != activate_threads_~tmp___3~0); 720794#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 720368#L702 assume !(1 == ~t5_pc~0); 720287#L702-2 is_transmit5_triggered_~__retres1~5 := 0; 720288#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 720784#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 721194#L1600 assume !(0 != activate_threads_~tmp___4~0); 721099#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 719457#L721 assume !(1 == ~t6_pc~0); 719431#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 719432#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 719587#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 720074#L1608 assume !(0 != activate_threads_~tmp___5~0); 720075#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 720712#L740 assume !(1 == ~t7_pc~0); 720713#L740-2 is_transmit7_triggered_~__retres1~7 := 0; 719319#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 719320#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 719309#L1616 assume !(0 != activate_threads_~tmp___6~0); 719310#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 720008#L759 assume !(1 == ~t8_pc~0); 720009#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 720038#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 720782#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 720783#L1624 assume !(0 != activate_threads_~tmp___7~0); 720947#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 721345#L778 assume !(1 == ~t9_pc~0); 719482#L778-2 is_transmit9_triggered_~__retres1~9 := 0; 719483#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 719424#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 719350#L1632 assume !(0 != activate_threads_~tmp___8~0); 719351#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 719673#L797 assume !(1 == ~t10_pc~0); 719674#L797-2 is_transmit10_triggered_~__retres1~10 := 0; 719789#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 721043#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 720180#L1640 assume !(0 != activate_threads_~tmp___9~0); 720181#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 720496#L816 assume !(1 == ~t11_pc~0); 719392#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 719391#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 720143#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 720082#L1648 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 720083#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 720639#L835 assume 1 == ~t12_pc~0; 720510#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 719544#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 719567#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 719707#L1656 assume !(0 != activate_threads_~tmp___11~0); 720236#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 720237#L854 assume !(1 == ~t13_pc~0); 719873#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 719874#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 719925#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 719585#L1664 assume !(0 != activate_threads_~tmp___12~0); 719586#L1664-2 assume !(1 == ~M_E~0); 720407#L1401-1 assume !(1 == ~T1_E~0); 720408#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 720701#L1411-1 assume !(1 == ~T3_E~0); 720702#L1416-1 assume !(1 == ~T4_E~0); 720337#L1421-1 assume !(1 == ~T5_E~0); 719869#L1426-1 assume !(1 == ~T6_E~0); 719870#L1431-1 assume !(1 == ~T7_E~0); 719427#L1436-1 assume !(1 == ~T8_E~0); 719428#L1441-1 assume !(1 == ~T9_E~0); 720174#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 720175#L1451-1 assume !(1 == ~T11_E~0); 720969#L1456-1 assume !(1 == ~T12_E~0); 720558#L1461-1 assume !(1 == ~T13_E~0); 720092#L1466-1 assume !(1 == ~E_1~0); 720093#L1471-1 assume !(1 == ~E_2~0); 720945#L1476-1 assume !(1 == ~E_3~0); 720946#L1481-1 assume !(1 == ~E_4~0); 721163#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 719714#L1491-1 assume !(1 == ~E_6~0); 719358#L1496-1 assume !(1 == ~E_7~0); 719359#L1501-1 assume !(1 == ~E_8~0); 720170#L1506-1 assume !(1 == ~E_9~0); 720171#L1511-1 assume !(1 == ~E_10~0); 720125#L1516-1 assume !(1 == ~E_11~0); 719307#L1521-1 assume !(1 == ~E_12~0); 719308#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 719357#L1892-1 [2021-11-07 08:02:09,121 INFO L793 eck$LassoCheckResult]: Loop: 719357#L1892-1 assume !false; 883791#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 883782#L1233 assume !false; 883698#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 883665#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 883646#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 883642#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 883636#L1046 assume !(0 != eval_~tmp~0); 883637#L1248 start_simulation_~kernel_st~0 := 2; 892724#L874-1 start_simulation_~kernel_st~0 := 3; 892723#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 892722#L1258-4 assume !(0 == ~T1_E~0); 892721#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 892720#L1268-3 assume !(0 == ~T3_E~0); 892719#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 892718#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 892717#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 892716#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 892714#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 892712#L1298-3 assume !(0 == ~T9_E~0); 892710#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 892708#L1308-3 assume !(0 == ~T11_E~0); 892706#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 892704#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 892703#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 721151#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 721152#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 719717#L1338-3 assume !(0 == ~E_4~0); 719718#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 720910#L1348-3 assume !(0 == ~E_6~0); 721159#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 721160#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 720382#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 719927#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 719928#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 720735#L1378-3 assume !(0 == ~E_12~0); 720736#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 720963#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 720964#L607-42 assume !(1 == ~m_pc~0); 720761#L607-44 is_master_triggered_~__retres1~0 := 0; 720215#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 720216#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 719944#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 719945#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 720497#L626-42 assume !(1 == ~t1_pc~0); 721080#L626-44 is_transmit1_triggered_~__retres1~1 := 0; 890922#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 890920#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 890919#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 719609#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 719610#L645-42 assume !(1 == ~t2_pc~0); 721251#L645-44 is_transmit2_triggered_~__retres1~2 := 0; 891121#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 891119#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 719816#L1576-42 assume !(0 != activate_threads_~tmp___1~0); 719327#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 719328#L664-42 assume !(1 == ~t3_pc~0); 719850#L664-44 is_transmit3_triggered_~__retres1~3 := 0; 719851#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 721377#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 890881#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 890878#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 890873#L683-42 assume 1 == ~t4_pc~0; 890868#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 890862#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 890857#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 890853#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 890848#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 721023#L702-42 assume !(1 == ~t5_pc~0); 720025#L702-44 is_transmit5_triggered_~__retres1~5 := 0; 720026#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 891358#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 721136#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 721137#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 891321#L721-42 assume !(1 == ~t6_pc~0); 891314#L721-44 is_transmit6_triggered_~__retres1~6 := 0; 891266#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 891259#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 891254#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 891212#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 891205#L740-42 assume !(1 == ~t7_pc~0); 874206#L740-44 is_transmit7_triggered_~__retres1~7 := 0; 891201#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 891199#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 891197#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 891195#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 891193#L759-42 assume !(1 == ~t8_pc~0); 891192#L759-44 is_transmit8_triggered_~__retres1~8 := 0; 891190#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 891186#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 720266#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 720267#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 720364#L778-42 assume !(1 == ~t9_pc~0); 721033#L778-44 is_transmit9_triggered_~__retres1~9 := 0; 884386#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 884382#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 884377#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 884375#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 884373#L797-42 assume !(1 == ~t10_pc~0); 759281#L797-44 is_transmit10_triggered_~__retres1~10 := 0; 884370#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 884294#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 884292#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 884291#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 884290#L816-42 assume 1 == ~t11_pc~0; 884289#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 884286#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 884283#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 884280#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 884277#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 884274#L835-42 assume !(1 == ~t12_pc~0); 884271#L835-44 is_transmit12_triggered_~__retres1~12 := 0; 884267#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 884264#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 884262#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 884261#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 884259#L854-42 assume 1 == ~t13_pc~0; 884255#L855-14 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13 := 1; 884250#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 884246#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 884242#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 884238#L1664-44 assume !(1 == ~M_E~0); 884236#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 884233#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 884229#L1411-3 assume !(1 == ~T3_E~0); 884225#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 884221#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 884217#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 884211#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 884206#L1436-3 assume !(1 == ~T8_E~0); 884202#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 884198#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 884194#L1451-3 assume !(1 == ~T11_E~0); 884190#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 884184#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 884178#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 884173#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 884168#L1476-3 assume !(1 == ~E_3~0); 884163#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 884158#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 884151#L1491-3 assume !(1 == ~E_6~0); 884145#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 884141#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 884134#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 884132#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 884126#L1516-3 assume !(1 == ~E_11~0); 884124#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 884123#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 884122#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 883989#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 883979#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 883970#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 883962#L1911 assume !(0 == start_simulation_~tmp~3); 883957#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 883844#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 883830#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 883828#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 883826#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 883824#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 883822#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 883809#L1924 assume !(0 != start_simulation_~tmp___0~1); 719357#L1892-1 [2021-11-07 08:02:09,122 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:02:09,123 INFO L85 PathProgramCache]: Analyzing trace with hash -1131618850, now seen corresponding path program 1 times [2021-11-07 08:02:09,123 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:02:09,123 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [617158998] [2021-11-07 08:02:09,123 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:02:09,124 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:02:09,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:02:09,180 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:02:09,180 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:02:09,181 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [617158998] [2021-11-07 08:02:09,181 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [617158998] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:02:09,181 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:02:09,181 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-07 08:02:09,182 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1678627906] [2021-11-07 08:02:09,182 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:02:09,182 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:02:09,183 INFO L85 PathProgramCache]: Analyzing trace with hash 1857711434, now seen corresponding path program 1 times [2021-11-07 08:02:09,183 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:02:09,183 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [594189528] [2021-11-07 08:02:09,183 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:02:09,184 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:02:09,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:02:09,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:02:09,228 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:02:09,228 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [594189528] [2021-11-07 08:02:09,229 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [594189528] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:02:09,229 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:02:09,229 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:02:09,229 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [451132801] [2021-11-07 08:02:09,231 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:02:09,232 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:02:09,232 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-07 08:02:09,233 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-07 08:02:09,233 INFO L87 Difference]: Start difference. First operand 173477 states and 245618 transitions. cyclomatic complexity: 72143 Second operand has 5 states, 5 states have (on average 31.0) internal successors, (155), 5 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:02:11,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:02:11,603 INFO L93 Difference]: Finished difference Result 394042 states and 564227 transitions. [2021-11-07 08:02:11,604 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-07 08:02:11,604 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 394042 states and 564227 transitions. [2021-11-07 08:02:14,316 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 393600 [2021-11-07 08:02:15,944 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 394042 states to 394042 states and 564227 transitions. [2021-11-07 08:02:15,945 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 394042 [2021-11-07 08:02:16,101 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 394042 [2021-11-07 08:02:16,101 INFO L73 IsDeterministic]: Start isDeterministic. Operand 394042 states and 564227 transitions. [2021-11-07 08:02:16,237 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:02:16,237 INFO L681 BuchiCegarLoop]: Abstraction has 394042 states and 564227 transitions. [2021-11-07 08:02:16,386 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 394042 states and 564227 transitions. [2021-11-07 08:02:19,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 394042 to 177896. [2021-11-07 08:02:19,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 177896 states, 177896 states have (on average 1.4055234519044835) internal successors, (250037), 177895 states have internal predecessors, (250037), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:02:19,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177896 states to 177896 states and 250037 transitions. [2021-11-07 08:02:19,863 INFO L704 BuchiCegarLoop]: Abstraction has 177896 states and 250037 transitions. [2021-11-07 08:02:19,863 INFO L587 BuchiCegarLoop]: Abstraction has 177896 states and 250037 transitions. [2021-11-07 08:02:19,863 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-11-07 08:02:19,863 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 177896 states and 250037 transitions. [2021-11-07 08:02:20,418 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 177664 [2021-11-07 08:02:20,418 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-07 08:02:20,418 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-07 08:02:20,430 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:02:20,430 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-07 08:02:20,430 INFO L791 eck$LassoCheckResult]: Stem: 1287667#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2; 1287668#L-1 havoc main_#res;havoc main_~__retres1~15;havoc main_~__retres1~15;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1287479#L1855 havoc start_simulation_#t~ret37, start_simulation_#t~ret38, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1287201#L874 assume 1 == ~m_i~0;~m_st~0 := 0; 1287202#L881-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1288150#L886-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1287331#L891-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1287332#L896-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1287810#L901-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1287628#L906-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1287629#L911-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1287399#L916-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1287400#L921-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1287817#L926-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1288019#L931-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1288185#L936-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1288222#L941-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1287412#L946-1 assume !(0 == ~M_E~0); 1287413#L1258-1 assume !(0 == ~T1_E~0); 1287715#L1263-1 assume !(0 == ~T2_E~0); 1287716#L1268-1 assume !(0 == ~T3_E~0); 1288062#L1273-1 assume !(0 == ~T4_E~0); 1288760#L1278-1 assume !(0 == ~T5_E~0); 1288574#L1283-1 assume !(0 == ~T6_E~0); 1288575#L1288-1 assume !(0 == ~T7_E~0); 1288917#L1293-1 assume !(0 == ~T8_E~0); 1288898#L1298-1 assume !(0 == ~T9_E~0); 1288778#L1303-1 assume !(0 == ~T10_E~0); 1287229#L1308-1 assume !(0 == ~T11_E~0); 1287175#L1313-1 assume !(0 == ~T12_E~0); 1287176#L1318-1 assume !(0 == ~T13_E~0); 1287181#L1323-1 assume !(0 == ~E_1~0); 1287182#L1328-1 assume !(0 == ~E_2~0); 1287343#L1333-1 assume !(0 == ~E_3~0); 1288385#L1338-1 assume !(0 == ~E_4~0); 1288386#L1343-1 assume !(0 == ~E_5~0); 1288526#L1348-1 assume !(0 == ~E_6~0); 1288953#L1353-1 assume !(0 == ~E_7~0); 1288081#L1358-1 assume !(0 == ~E_8~0); 1288082#L1363-1 assume !(0 == ~E_9~0); 1288412#L1368-1 assume !(0 == ~E_10~0); 1287017#L1373-1 assume !(0 == ~E_11~0); 1287018#L1378-1 assume !(0 == ~E_12~0); 1287292#L1383-1 assume !(0 == ~E_13~0); 1287293#L1388-1 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1288088#L607 assume !(1 == ~m_pc~0); 1287362#L607-2 is_master_triggered_~__retres1~0 := 0; 1287363#L618 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1288523#L619 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1287995#L1560 assume !(0 != activate_threads_~tmp~1); 1287996#L1560-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1287192#L626 assume !(1 == ~t1_pc~0); 1287193#L626-2 is_transmit1_triggered_~__retres1~1 := 0; 1287456#L637 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1287457#L638 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1287634#L1568 assume !(0 != activate_threads_~tmp___0~0); 1287095#L1568-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1287096#L645 assume !(1 == ~t2_pc~0); 1287165#L645-2 is_transmit2_triggered_~__retres1~2 := 0; 1287166#L656 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1288707#L657 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1289051#L1576 assume !(0 != activate_threads_~tmp___1~0); 1287970#L1576-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1287971#L664 assume !(1 == ~t3_pc~0); 1288438#L664-2 is_transmit3_triggered_~__retres1~3 := 0; 1286946#L675 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1286947#L676 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1287595#L1584 assume !(0 != activate_threads_~tmp___2~0); 1287596#L1584-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1288806#L683 assume !(1 == ~t4_pc~0); 1288209#L683-2 is_transmit4_triggered_~__retres1~4 := 0; 1288159#L694 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1288160#L695 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1288194#L1592 assume !(0 != activate_threads_~tmp___3~0); 1288338#L1592-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1287911#L702 assume !(1 == ~t5_pc~0); 1287830#L702-2 is_transmit5_triggered_~__retres1~5 := 0; 1287831#L713 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1288326#L714 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1288745#L1600 assume !(0 != activate_threads_~tmp___4~0); 1288660#L1600-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1286991#L721 assume !(1 == ~t6_pc~0); 1286964#L721-2 is_transmit6_triggered_~__retres1~6 := 0; 1286965#L732 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1287119#L733 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1287602#L1608 assume !(0 != activate_threads_~tmp___5~0); 1287603#L1608-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1288256#L740 assume !(1 == ~t7_pc~0); 1288257#L740-2 is_transmit7_triggered_~__retres1~7 := 0; 1286851#L751 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1286852#L752 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1286841#L1616 assume !(0 != activate_threads_~tmp___6~0); 1286842#L1616-2 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1287536#L759 assume !(1 == ~t8_pc~0); 1287537#L759-2 is_transmit8_triggered_~__retres1~8 := 0; 1287566#L770 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1288323#L771 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1288324#L1624 assume !(0 != activate_threads_~tmp___7~0); 1288501#L1624-2 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1288915#L778 assume !(1 == ~t9_pc~0); 1287015#L778-2 is_transmit9_triggered_~__retres1~9 := 0; 1287016#L789 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1286957#L790 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1286882#L1632 assume !(0 != activate_threads_~tmp___8~0); 1286883#L1632-2 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1287206#L797 assume !(1 == ~t10_pc~0); 1287207#L797-2 is_transmit10_triggered_~__retres1~10 := 0; 1287318#L808 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1288603#L809 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1287713#L1640 assume !(0 != activate_threads_~tmp___9~0); 1287714#L1640-2 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1288042#L816 assume !(1 == ~t11_pc~0); 1286925#L816-2 is_transmit11_triggered_~__retres1~11 := 0; 1287198#L827 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1287867#L828 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 1287611#L1648 assume !(0 != activate_threads_~tmp___10~0); 1287612#L1648-2 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1288183#L835 assume 1 == ~t12_pc~0; 1288056#L836 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12 := 1; 1287077#L846 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1287099#L847 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 1287239#L1656 assume !(0 != activate_threads_~tmp___11~0); 1287775#L1656-2 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 1287776#L854 assume !(1 == ~t13_pc~0); 1287401#L854-2 is_transmit13_triggered_~__retres1~13 := 0; 1287402#L865 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 1287452#L866 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 1287117#L1664 assume !(0 != activate_threads_~tmp___12~0); 1287118#L1664-2 assume !(1 == ~M_E~0); 1287953#L1401-1 assume !(1 == ~T1_E~0); 1287954#L1406-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1288245#L1411-1 assume !(1 == ~T3_E~0); 1288246#L1416-1 assume !(1 == ~T4_E~0); 1287879#L1421-1 assume !(1 == ~T5_E~0); 1287397#L1426-1 assume !(1 == ~T6_E~0); 1287398#L1431-1 assume !(1 == ~T7_E~0); 1286960#L1436-1 assume !(1 == ~T8_E~0); 1286961#L1441-1 assume !(1 == ~T9_E~0); 1287706#L1446-1 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1287707#L1451-1 assume !(1 == ~T11_E~0); 1288522#L1456-1 assume !(1 == ~T12_E~0); 1288106#L1461-1 assume !(1 == ~T13_E~0); 1287623#L1466-1 assume !(1 == ~E_1~0); 1287624#L1471-1 assume !(1 == ~E_2~0); 1288499#L1476-1 assume !(1 == ~E_3~0); 1288500#L1481-1 assume !(1 == ~E_4~0); 1288718#L1486-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1287246#L1491-1 assume !(1 == ~E_6~0); 1286890#L1496-1 assume !(1 == ~E_7~0); 1286891#L1501-1 assume !(1 == ~E_8~0); 1287701#L1506-1 assume !(1 == ~E_9~0); 1287702#L1511-1 assume !(1 == ~E_10~0); 1287656#L1516-1 assume !(1 == ~E_11~0); 1286839#L1521-1 assume !(1 == ~E_12~0); 1286840#L1526-1 assume 1 == ~E_13~0;~E_13~0 := 2; 1286889#L1892-1 [2021-11-07 08:02:20,431 INFO L793 eck$LassoCheckResult]: Loop: 1286889#L1892-1 assume !false; 1357943#L1893 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_#t~nondet11, eval_~tmp_ndt_4~0, eval_#t~nondet12, eval_~tmp_ndt_5~0, eval_#t~nondet13, eval_~tmp_ndt_6~0, eval_#t~nondet14, eval_~tmp_ndt_7~0, eval_#t~nondet15, eval_~tmp_ndt_8~0, eval_#t~nondet16, eval_~tmp_ndt_9~0, eval_#t~nondet17, eval_~tmp_ndt_10~0, eval_#t~nondet18, eval_~tmp_ndt_11~0, eval_#t~nondet19, eval_~tmp_ndt_12~0, eval_#t~nondet20, eval_~tmp_ndt_13~0, eval_#t~nondet21, eval_~tmp_ndt_14~0, eval_~tmp~0;havoc eval_~tmp~0; 1357938#L1233 assume !false; 1357937#L1042 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1357936#L959 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1357922#L1031 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1357921#L1032 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 1357919#L1046 assume !(0 != eval_~tmp~0); 1357920#L1248 start_simulation_~kernel_st~0 := 2; 1463570#L874-1 start_simulation_~kernel_st~0 := 3; 1463568#L1258-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1463566#L1258-4 assume !(0 == ~T1_E~0); 1463564#L1263-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1463562#L1268-3 assume !(0 == ~T3_E~0); 1463560#L1273-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1463558#L1278-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1463556#L1283-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1463554#L1288-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1463552#L1293-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1463550#L1298-3 assume !(0 == ~T9_E~0); 1463548#L1303-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1463546#L1308-3 assume !(0 == ~T11_E~0); 1463544#L1313-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1463542#L1318-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1463540#L1323-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1463538#L1328-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1463536#L1333-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1463534#L1338-3 assume !(0 == ~E_4~0); 1463532#L1343-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1463530#L1348-3 assume !(0 == ~E_6~0); 1463528#L1353-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1463526#L1358-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1463524#L1363-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1463507#L1368-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1463505#L1373-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1463483#L1378-3 assume !(0 == ~E_12~0); 1463480#L1383-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1288518#L1388-3 havoc activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_#t~ret25, activate_threads_#t~ret26, activate_threads_#t~ret27, activate_threads_#t~ret28, activate_threads_#t~ret29, activate_threads_#t~ret30, activate_threads_#t~ret31, activate_threads_#t~ret32, activate_threads_#t~ret33, activate_threads_#t~ret34, activate_threads_#t~ret35, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0, activate_threads_~tmp___8~0, activate_threads_~tmp___9~0, activate_threads_~tmp___10~0, activate_threads_~tmp___11~0, activate_threads_~tmp___12~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;havoc activate_threads_~tmp___8~0;havoc activate_threads_~tmp___9~0;havoc activate_threads_~tmp___10~0;havoc activate_threads_~tmp___11~0;havoc activate_threads_~tmp___12~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1288519#L607-42 assume !(1 == ~m_pc~0); 1289003#L607-44 is_master_triggered_~__retres1~0 := 0; 1463719#L618-14 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1463718#L619-14 activate_threads_#t~ret22 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1462249#L1560-42 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1462248#L1560-44 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1462247#L626-42 assume !(1 == ~t1_pc~0); 1452490#L626-44 is_transmit1_triggered_~__retres1~1 := 0; 1462246#L637-14 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1462245#L638-14 activate_threads_#t~ret23 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1462244#L1568-42 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1462242#L1568-44 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1462239#L645-42 assume !(1 == ~t2_pc~0); 1462238#L645-44 is_transmit2_triggered_~__retres1~2 := 0; 1462236#L656-14 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1462234#L657-14 activate_threads_#t~ret24 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1462232#L1576-42 assume !(0 != activate_threads_~tmp___1~0); 1462229#L1576-44 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1462227#L664-42 assume !(1 == ~t3_pc~0); 1359307#L664-44 is_transmit3_triggered_~__retres1~3 := 0; 1462224#L675-14 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1462222#L676-14 activate_threads_#t~ret25 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret25;havoc activate_threads_#t~ret25; 1462220#L1584-42 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1462218#L1584-44 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1462216#L683-42 assume 1 == ~t4_pc~0; 1462214#L684-14 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1462211#L694-14 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1462209#L695-14 activate_threads_#t~ret26 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret26;havoc activate_threads_#t~ret26; 1462208#L1592-42 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1462207#L1592-44 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1452023#L702-42 assume !(1 == ~t5_pc~0); 1452021#L702-44 is_transmit5_triggered_~__retres1~5 := 0; 1452018#L713-14 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1452015#L714-14 activate_threads_#t~ret27 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret27;havoc activate_threads_#t~ret27; 1452013#L1600-42 assume !(0 != activate_threads_~tmp___4~0); 1452011#L1600-44 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1452009#L721-42 assume !(1 == ~t6_pc~0); 1452006#L721-44 is_transmit6_triggered_~__retres1~6 := 0; 1452004#L732-14 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1452002#L733-14 activate_threads_#t~ret28 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret28;havoc activate_threads_#t~ret28; 1452000#L1608-42 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1451997#L1608-44 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1451995#L740-42 assume !(1 == ~t7_pc~0); 1360954#L740-44 is_transmit7_triggered_~__retres1~7 := 0; 1451992#L751-14 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1451990#L752-14 activate_threads_#t~ret29 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret29;havoc activate_threads_#t~ret29; 1451988#L1616-42 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1451987#L1616-44 havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1451986#L759-42 assume 1 == ~t8_pc~0; 1451898#L760-14 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 1451896#L770-14 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1451893#L771-14 activate_threads_#t~ret30 := is_transmit8_triggered_#res;activate_threads_~tmp___7~0 := activate_threads_#t~ret30;havoc activate_threads_#t~ret30; 1451890#L1624-42 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 1451887#L1624-44 havoc is_transmit9_triggered_#res;havoc is_transmit9_triggered_~__retres1~9;havoc is_transmit9_triggered_~__retres1~9; 1451884#L778-42 assume !(1 == ~t9_pc~0); 1357017#L778-44 is_transmit9_triggered_~__retres1~9 := 0; 1451879#L789-14 is_transmit9_triggered_#res := is_transmit9_triggered_~__retres1~9; 1451877#L790-14 activate_threads_#t~ret31 := is_transmit9_triggered_#res;activate_threads_~tmp___8~0 := activate_threads_#t~ret31;havoc activate_threads_#t~ret31; 1451874#L1632-42 assume 0 != activate_threads_~tmp___8~0;~t9_st~0 := 0; 1451302#L1632-44 havoc is_transmit10_triggered_#res;havoc is_transmit10_triggered_~__retres1~10;havoc is_transmit10_triggered_~__retres1~10; 1358117#L797-42 assume !(1 == ~t10_pc~0); 1358116#L797-44 is_transmit10_triggered_~__retres1~10 := 0; 1358115#L808-14 is_transmit10_triggered_#res := is_transmit10_triggered_~__retres1~10; 1358114#L809-14 activate_threads_#t~ret32 := is_transmit10_triggered_#res;activate_threads_~tmp___9~0 := activate_threads_#t~ret32;havoc activate_threads_#t~ret32; 1358113#L1640-42 assume 0 != activate_threads_~tmp___9~0;~t10_st~0 := 0; 1358112#L1640-44 havoc is_transmit11_triggered_#res;havoc is_transmit11_triggered_~__retres1~11;havoc is_transmit11_triggered_~__retres1~11; 1358111#L816-42 assume 1 == ~t11_pc~0; 1358109#L817-14 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11 := 1; 1358107#L827-14 is_transmit11_triggered_#res := is_transmit11_triggered_~__retres1~11; 1358105#L828-14 activate_threads_#t~ret33 := is_transmit11_triggered_#res;activate_threads_~tmp___10~0 := activate_threads_#t~ret33;havoc activate_threads_#t~ret33; 1358103#L1648-42 assume 0 != activate_threads_~tmp___10~0;~t11_st~0 := 0; 1358101#L1648-44 havoc is_transmit12_triggered_#res;havoc is_transmit12_triggered_~__retres1~12;havoc is_transmit12_triggered_~__retres1~12; 1358099#L835-42 assume !(1 == ~t12_pc~0); 1358096#L835-44 is_transmit12_triggered_~__retres1~12 := 0; 1358093#L846-14 is_transmit12_triggered_#res := is_transmit12_triggered_~__retres1~12; 1358091#L847-14 activate_threads_#t~ret34 := is_transmit12_triggered_#res;activate_threads_~tmp___11~0 := activate_threads_#t~ret34;havoc activate_threads_#t~ret34; 1358089#L1656-42 assume 0 != activate_threads_~tmp___11~0;~t12_st~0 := 0; 1358087#L1656-44 havoc is_transmit13_triggered_#res;havoc is_transmit13_triggered_~__retres1~13;havoc is_transmit13_triggered_~__retres1~13; 1358085#L854-42 assume !(1 == ~t13_pc~0); 1358081#L854-44 is_transmit13_triggered_~__retres1~13 := 0; 1358079#L865-14 is_transmit13_triggered_#res := is_transmit13_triggered_~__retres1~13; 1358077#L866-14 activate_threads_#t~ret35 := is_transmit13_triggered_#res;activate_threads_~tmp___12~0 := activate_threads_#t~ret35;havoc activate_threads_#t~ret35; 1358075#L1664-42 assume 0 != activate_threads_~tmp___12~0;~t13_st~0 := 0; 1358073#L1664-44 assume !(1 == ~M_E~0); 1358071#L1401-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1358069#L1406-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1358067#L1411-3 assume !(1 == ~T3_E~0); 1358065#L1416-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1358063#L1421-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1358061#L1426-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1358059#L1431-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1358057#L1436-3 assume !(1 == ~T8_E~0); 1358055#L1441-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1358053#L1446-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1358051#L1451-3 assume !(1 == ~T11_E~0); 1358049#L1456-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1358047#L1461-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1358045#L1466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1358043#L1471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1358041#L1476-3 assume !(1 == ~E_3~0); 1358039#L1481-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1358037#L1486-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1358035#L1491-3 assume !(1 == ~E_6~0); 1358033#L1496-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1358031#L1501-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1358029#L1506-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1358027#L1511-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1358025#L1516-3 assume !(1 == ~E_11~0); 1358023#L1521-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1358022#L1526-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1358021#L1531-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1357994#L959-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1357990#L1031-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1357988#L1032-1 start_simulation_#t~ret37 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret37;havoc start_simulation_#t~ret37; 1357984#L1911 assume !(0 == start_simulation_~tmp~3); 1357981#L1911-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret36, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~14;havoc exists_runnable_thread_~__retres1~14; 1357975#L959-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14 := 1; 1357960#L1031-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~14; 1357958#L1032-2 stop_simulation_#t~ret36 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret36;havoc stop_simulation_#t~ret36; 1357956#L1866 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1357954#L1873 stop_simulation_#res := stop_simulation_~__retres2~0; 1357950#L1874 start_simulation_#t~ret38 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret38;havoc start_simulation_#t~ret38; 1357948#L1924 assume !(0 != start_simulation_~tmp___0~1); 1286889#L1892-1 [2021-11-07 08:02:20,432 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:02:20,432 INFO L85 PathProgramCache]: Analyzing trace with hash 1791541148, now seen corresponding path program 1 times [2021-11-07 08:02:20,433 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:02:20,433 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [667267010] [2021-11-07 08:02:20,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:02:20,434 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:02:20,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:02:20,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:02:20,508 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:02:20,508 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [667267010] [2021-11-07 08:02:20,509 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [667267010] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:02:20,509 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:02:20,509 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:02:20,509 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1503462857] [2021-11-07 08:02:20,510 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-07 08:02:20,510 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-07 08:02:20,511 INFO L85 PathProgramCache]: Analyzing trace with hash 843134218, now seen corresponding path program 1 times [2021-11-07 08:02:20,511 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-07 08:02:20,511 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1583528974] [2021-11-07 08:02:20,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-07 08:02:20,512 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-07 08:02:20,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-07 08:02:20,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-07 08:02:20,558 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-07 08:02:20,558 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1583528974] [2021-11-07 08:02:20,558 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1583528974] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-07 08:02:20,559 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-07 08:02:20,559 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-07 08:02:20,559 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1670630705] [2021-11-07 08:02:20,560 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-07 08:02:20,560 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-07 08:02:20,560 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-07 08:02:20,561 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-07 08:02:20,561 INFO L87 Difference]: Start difference. First operand 177896 states and 250037 transitions. cyclomatic complexity: 72143 Second operand has 4 states, 4 states have (on average 38.75) internal successors, (155), 3 states have internal predecessors, (155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-07 08:02:23,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-07 08:02:23,155 INFO L93 Difference]: Finished difference Result 427335 states and 597554 transitions. [2021-11-07 08:02:23,156 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-07 08:02:23,156 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 427335 states and 597554 transitions. [2021-11-07 08:02:26,123 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 420128 [2021-11-07 08:02:27,869 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 427335 states to 427335 states and 597554 transitions. [2021-11-07 08:02:27,869 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 427335 [2021-11-07 08:02:28,038 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 427335 [2021-11-07 08:02:28,038 INFO L73 IsDeterministic]: Start isDeterministic. Operand 427335 states and 597554 transitions. [2021-11-07 08:02:28,183 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-07 08:02:28,183 INFO L681 BuchiCegarLoop]: Abstraction has 427335 states and 597554 transitions. [2021-11-07 08:02:28,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 427335 states and 597554 transitions.