./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-crafted/LexIndexValue-Pointer-2.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f8e1c903 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-crafted/LexIndexValue-Pointer-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 1bedc761cea545b8144ad4138a379d7139cc98703c76e9b536a2e7389d5b6a10 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-f8e1c90 [2021-11-09 09:33:21,003 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-09 09:33:21,007 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-09 09:33:21,078 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-09 09:33:21,079 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-09 09:33:21,084 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-09 09:33:21,086 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-09 09:33:21,091 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-09 09:33:21,094 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-09 09:33:21,103 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-09 09:33:21,105 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-09 09:33:21,107 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-09 09:33:21,108 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-09 09:33:21,111 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-09 09:33:21,113 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-09 09:33:21,121 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-09 09:33:21,125 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-09 09:33:21,126 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-09 09:33:21,129 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-09 09:33:21,134 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-09 09:33:21,140 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-09 09:33:21,141 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-09 09:33:21,143 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-09 09:33:21,144 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-09 09:33:21,148 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-09 09:33:21,149 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-09 09:33:21,149 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-09 09:33:21,150 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-09 09:33:21,151 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-09 09:33:21,152 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-09 09:33:21,153 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-09 09:33:21,154 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-09 09:33:21,155 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-09 09:33:21,161 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-09 09:33:21,162 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-09 09:33:21,163 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-09 09:33:21,164 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-09 09:33:21,164 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-09 09:33:21,164 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-09 09:33:21,165 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-09 09:33:21,166 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-09 09:33:21,167 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/config/svcomp-Termination-64bit-Automizer_Default.epf [2021-11-09 09:33:21,208 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-09 09:33:21,208 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-09 09:33:21,208 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-09 09:33:21,209 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-09 09:33:21,210 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-09 09:33:21,210 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-09 09:33:21,210 INFO L138 SettingsManager]: * Use SBE=true [2021-11-09 09:33:21,211 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-09 09:33:21,211 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-09 09:33:21,211 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-09 09:33:21,211 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-09 09:33:21,211 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-09 09:33:21,212 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-09 09:33:21,212 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-09 09:33:21,212 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-09 09:33:21,212 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-09 09:33:21,212 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-09 09:33:21,213 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-09 09:33:21,213 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-09 09:33:21,213 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-09 09:33:21,213 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-09 09:33:21,213 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-09 09:33:21,213 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-09 09:33:21,214 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-09 09:33:21,214 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-09 09:33:21,214 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-09 09:33:21,214 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-09 09:33:21,215 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-09 09:33:21,215 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-09 09:33:21,220 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-09 09:33:21,220 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1bedc761cea545b8144ad4138a379d7139cc98703c76e9b536a2e7389d5b6a10 [2021-11-09 09:33:21,508 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-09 09:33:21,555 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-09 09:33:21,558 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-09 09:33:21,561 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-09 09:33:21,562 INFO L275 PluginConnector]: CDTParser initialized [2021-11-09 09:33:21,563 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/../../sv-benchmarks/c/termination-crafted/LexIndexValue-Pointer-2.c [2021-11-09 09:33:21,683 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/data/ba51d58dd/8831c6e30d72434abd916131cde86ccf/FLAGd6144af52 [2021-11-09 09:33:22,171 INFO L306 CDTParser]: Found 1 translation units. [2021-11-09 09:33:22,171 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/sv-benchmarks/c/termination-crafted/LexIndexValue-Pointer-2.c [2021-11-09 09:33:22,179 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/data/ba51d58dd/8831c6e30d72434abd916131cde86ccf/FLAGd6144af52 [2021-11-09 09:33:22,509 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/data/ba51d58dd/8831c6e30d72434abd916131cde86ccf [2021-11-09 09:33:22,512 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-09 09:33:22,513 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-09 09:33:22,515 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-09 09:33:22,515 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-09 09:33:22,519 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-09 09:33:22,519 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 09:33:22" (1/1) ... [2021-11-09 09:33:22,521 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2b6fac03 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:22, skipping insertion in model container [2021-11-09 09:33:22,521 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 09:33:22" (1/1) ... [2021-11-09 09:33:22,529 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-09 09:33:22,542 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-09 09:33:22,713 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-09 09:33:22,726 INFO L203 MainTranslator]: Completed pre-run [2021-11-09 09:33:22,746 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-09 09:33:22,758 INFO L208 MainTranslator]: Completed translation [2021-11-09 09:33:22,758 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:22 WrapperNode [2021-11-09 09:33:22,758 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-09 09:33:22,759 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-09 09:33:22,759 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-09 09:33:22,760 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-09 09:33:22,767 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:22" (1/1) ... [2021-11-09 09:33:22,775 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:22" (1/1) ... [2021-11-09 09:33:22,796 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-09 09:33:22,797 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-09 09:33:22,797 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-09 09:33:22,797 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-09 09:33:22,806 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:22" (1/1) ... [2021-11-09 09:33:22,806 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:22" (1/1) ... [2021-11-09 09:33:22,808 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:22" (1/1) ... [2021-11-09 09:33:22,808 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:22" (1/1) ... [2021-11-09 09:33:22,815 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:22" (1/1) ... [2021-11-09 09:33:22,819 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:22" (1/1) ... [2021-11-09 09:33:22,820 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:22" (1/1) ... [2021-11-09 09:33:22,822 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-09 09:33:22,823 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-09 09:33:22,823 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-09 09:33:22,824 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-09 09:33:22,825 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:22" (1/1) ... [2021-11-09 09:33:22,833 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:33:22,853 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:22,866 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:33:22,868 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-09 09:33:22,904 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2021-11-09 09:33:22,904 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2021-11-09 09:33:22,904 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-09 09:33:22,904 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-09 09:33:22,905 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2021-11-09 09:33:22,905 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2021-11-09 09:33:23,145 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-09 09:33:23,145 INFO L299 CfgBuilder]: Removed 6 assume(true) statements. [2021-11-09 09:33:23,147 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 09:33:23 BoogieIcfgContainer [2021-11-09 09:33:23,148 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-09 09:33:23,149 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-09 09:33:23,149 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-09 09:33:23,155 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-09 09:33:23,156 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-09 09:33:23,156 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 09.11 09:33:22" (1/3) ... [2021-11-09 09:33:23,158 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1e7dc227 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 09:33:23, skipping insertion in model container [2021-11-09 09:33:23,158 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-09 09:33:23,158 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:22" (2/3) ... [2021-11-09 09:33:23,159 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1e7dc227 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 09:33:23, skipping insertion in model container [2021-11-09 09:33:23,159 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-09 09:33:23,159 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 09:33:23" (3/3) ... [2021-11-09 09:33:23,161 INFO L389 chiAutomizerObserver]: Analyzing ICFG LexIndexValue-Pointer-2.c [2021-11-09 09:33:23,244 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-09 09:33:23,244 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-09 09:33:23,244 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-09 09:33:23,245 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-09 09:33:23,245 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-09 09:33:23,245 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-09 09:33:23,245 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-09 09:33:23,245 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-09 09:33:23,263 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 13 states, 12 states have (on average 1.5) internal successors, (18), 12 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:23,286 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2021-11-09 09:33:23,286 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:23,286 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:23,293 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1] [2021-11-09 09:33:23,294 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-09 09:33:23,294 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-09 09:33:23,294 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 13 states, 12 states have (on average 1.5) internal successors, (18), 12 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:23,297 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6 [2021-11-09 09:33:23,297 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:23,297 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:23,298 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1] [2021-11-09 09:33:23,298 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-09 09:33:23,322 INFO L791 eck$LassoCheckResult]: Stem: 5#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 8#L-1true havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 11#L18-3true [2021-11-09 09:33:23,322 INFO L793 eck$LassoCheckResult]: Loop: 11#L18-3true assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9#L18-2true main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11#L18-3true [2021-11-09 09:33:23,328 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:23,329 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2021-11-09 09:33:23,343 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:23,344 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [161515950] [2021-11-09 09:33:23,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:23,347 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:23,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:23,460 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:23,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:23,504 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:23,508 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:23,508 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2021-11-09 09:33:23,508 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:23,509 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [437916611] [2021-11-09 09:33:23,509 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:23,509 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:23,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:23,523 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:23,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:23,534 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:23,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:23,537 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2021-11-09 09:33:23,537 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:23,538 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2129797280] [2021-11-09 09:33:23,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:23,538 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:23,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:23,561 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:23,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:23,581 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:23,812 INFO L210 LassoAnalysis]: Preferences: [2021-11-09 09:33:23,812 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-11-09 09:33:23,813 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-11-09 09:33:23,813 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-11-09 09:33:23,813 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-11-09 09:33:23,813 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:33:23,813 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-11-09 09:33:23,814 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-11-09 09:33:23,814 INFO L133 ssoRankerPreferences]: Filename of dumped script: LexIndexValue-Pointer-2.c_Iteration1_Lasso [2021-11-09 09:33:23,814 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-11-09 09:33:23,814 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-11-09 09:33:23,835 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-09 09:33:23,841 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-09 09:33:23,844 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-09 09:33:23,942 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-09 09:33:23,960 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-09 09:33:23,963 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-09 09:33:23,965 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-09 09:33:23,969 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-09 09:33:23,972 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-09 09:33:23,975 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-09 09:33:23,978 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-09 09:33:23,982 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-09 09:33:23,985 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-09 09:33:23,989 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-09 09:33:24,341 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-11-09 09:33:24,346 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-11-09 09:33:24,349 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:33:24,349 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:24,356 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:33:24,377 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-09 09:33:24,389 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-09 09:33:24,389 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-09 09:33:24,390 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-09 09:33:24,390 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-09 09:33:24,390 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-09 09:33:24,393 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-09 09:33:24,393 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-09 09:33:24,395 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2021-11-09 09:33:24,412 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-09 09:33:24,452 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2021-11-09 09:33:24,452 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:33:24,452 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:24,454 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:33:24,460 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-09 09:33:24,471 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2021-11-09 09:33:24,477 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-09 09:33:24,477 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-09 09:33:24,478 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-09 09:33:24,478 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-09 09:33:24,478 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-09 09:33:24,479 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-09 09:33:24,479 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-09 09:33:24,484 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-09 09:33:24,532 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2021-11-09 09:33:24,532 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:33:24,532 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:24,534 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:33:24,542 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2021-11-09 09:33:24,546 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-09 09:33:24,556 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-09 09:33:24,556 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-09 09:33:24,557 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-09 09:33:24,557 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-09 09:33:24,557 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-09 09:33:24,563 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-09 09:33:24,564 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-09 09:33:24,582 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-09 09:33:24,625 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2021-11-09 09:33:24,626 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:33:24,626 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:24,628 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:33:24,632 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-09 09:33:24,643 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-09 09:33:24,644 INFO L203 nArgumentSynthesizer]: 2 stem disjuncts [2021-11-09 09:33:24,644 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-09 09:33:24,644 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-09 09:33:24,658 INFO L401 nArgumentSynthesizer]: We have 8 Motzkin's Theorem applications. [2021-11-09 09:33:24,658 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-09 09:33:24,661 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2021-11-09 09:33:24,679 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-09 09:33:24,724 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2021-11-09 09:33:24,725 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:33:24,725 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:24,728 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:33:24,735 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-09 09:33:24,746 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-09 09:33:24,746 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-09 09:33:24,746 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-09 09:33:24,747 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-09 09:33:24,756 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-09 09:33:24,756 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-09 09:33:24,762 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2021-11-09 09:33:24,771 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-09 09:33:24,817 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2021-11-09 09:33:24,818 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:33:24,818 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:24,820 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:33:24,827 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-09 09:33:24,838 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-09 09:33:24,839 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-09 09:33:24,839 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-09 09:33:24,839 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-09 09:33:24,859 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-09 09:33:24,860 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-09 09:33:24,863 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2021-11-09 09:33:24,883 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-11-09 09:33:24,933 INFO L443 ModelExtractionUtils]: Simplification made 12 calls to the SMT solver. [2021-11-09 09:33:24,933 INFO L444 ModelExtractionUtils]: 5 out of 19 variables were initially zero. Simplification set additionally 11 variables to zero. [2021-11-09 09:33:24,935 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:33:24,936 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:24,939 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:33:25,029 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-11-09 09:33:25,031 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2021-11-09 09:33:25,062 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2021-11-09 09:33:25,063 INFO L513 LassoAnalysis]: Proved termination. [2021-11-09 09:33:25,063 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0, v_rep(select #length ULTIMATE.start_main_~p~0.base)_1) = -8*ULTIMATE.start_main_~i~0 + 2095*v_rep(select #length ULTIMATE.start_main_~p~0.base)_1 Supporting invariants [] [2021-11-09 09:33:25,112 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2021-11-09 09:33:25,123 INFO L297 tatePredicateManager]: 2 out of 3 supporting invariants were superfluous and have been removed [2021-11-09 09:33:25,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:25,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:25,186 INFO L263 TraceCheckSpWp]: Trace formula consists of 22 conjuncts, 4 conjunts are in the unsatisfiable core [2021-11-09 09:33:25,189 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:25,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:25,215 WARN L261 TraceCheckSpWp]: Trace formula consists of 12 conjuncts, 8 conjunts are in the unsatisfiable core [2021-11-09 09:33:25,216 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:25,315 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:25,334 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2021-11-09 09:33:25,335 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 13 states, 12 states have (on average 1.5) internal successors, (18), 12 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:25,436 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 13 states, 12 states have (on average 1.5) internal successors, (18), 12 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 33 states and 48 transitions. Complement of second has 7 states. [2021-11-09 09:33:25,436 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2021-11-09 09:33:25,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:25,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 30 transitions. [2021-11-09 09:33:25,441 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 30 transitions. Stem has 2 letters. Loop has 2 letters. [2021-11-09 09:33:25,442 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-09 09:33:25,442 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 30 transitions. Stem has 4 letters. Loop has 2 letters. [2021-11-09 09:33:25,443 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-09 09:33:25,443 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 30 transitions. Stem has 2 letters. Loop has 4 letters. [2021-11-09 09:33:25,443 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-09 09:33:25,444 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33 states and 48 transitions. [2021-11-09 09:33:25,451 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:25,455 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33 states to 10 states and 14 transitions. [2021-11-09 09:33:25,456 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2021-11-09 09:33:25,456 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:25,457 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10 states and 14 transitions. [2021-11-09 09:33:25,457 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:25,458 INFO L681 BuchiCegarLoop]: Abstraction has 10 states and 14 transitions. [2021-11-09 09:33:25,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10 states and 14 transitions. [2021-11-09 09:33:25,482 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10 to 10. [2021-11-09 09:33:25,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 1.4) internal successors, (14), 9 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:25,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 14 transitions. [2021-11-09 09:33:25,484 INFO L704 BuchiCegarLoop]: Abstraction has 10 states and 14 transitions. [2021-11-09 09:33:25,485 INFO L587 BuchiCegarLoop]: Abstraction has 10 states and 14 transitions. [2021-11-09 09:33:25,485 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-09 09:33:25,485 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10 states and 14 transitions. [2021-11-09 09:33:25,486 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:25,486 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:25,487 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:25,487 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2021-11-09 09:33:25,487 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:25,488 INFO L791 eck$LassoCheckResult]: Stem: 104#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 105#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 109#L18-3 assume !(main_~i~0 < 1048); 110#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 108#L23-2 [2021-11-09 09:33:25,488 INFO L793 eck$LassoCheckResult]: Loop: 108#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 102#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 103#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 111#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 108#L23-2 [2021-11-09 09:33:25,490 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:25,490 INFO L85 PathProgramCache]: Analyzing trace with hash 925707, now seen corresponding path program 1 times [2021-11-09 09:33:25,490 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:25,491 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1248307652] [2021-11-09 09:33:25,491 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:25,491 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:25,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:25,580 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:25,580 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:25,580 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1248307652] [2021-11-09 09:33:25,581 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1248307652] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:33:25,581 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:33:25,581 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:33:25,582 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [694167471] [2021-11-09 09:33:25,588 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:25,588 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:25,588 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 1 times [2021-11-09 09:33:25,588 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:25,590 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1681057394] [2021-11-09 09:33:25,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:25,592 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:25,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:25,611 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:25,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:25,631 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:25,754 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:25,757 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:33:25,758 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:33:25,760 INFO L87 Difference]: Start difference. First operand 10 states and 14 transitions. cyclomatic complexity: 6 Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:25,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:25,775 INFO L93 Difference]: Finished difference Result 11 states and 14 transitions. [2021-11-09 09:33:25,775 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:33:25,776 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11 states and 14 transitions. [2021-11-09 09:33:25,779 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:25,780 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11 states to 11 states and 14 transitions. [2021-11-09 09:33:25,781 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:25,781 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:25,781 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11 states and 14 transitions. [2021-11-09 09:33:25,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:25,782 INFO L681 BuchiCegarLoop]: Abstraction has 11 states and 14 transitions. [2021-11-09 09:33:25,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states and 14 transitions. [2021-11-09 09:33:25,784 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 10. [2021-11-09 09:33:25,784 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 1.3) internal successors, (13), 9 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:25,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 13 transitions. [2021-11-09 09:33:25,786 INFO L704 BuchiCegarLoop]: Abstraction has 10 states and 13 transitions. [2021-11-09 09:33:25,786 INFO L587 BuchiCegarLoop]: Abstraction has 10 states and 13 transitions. [2021-11-09 09:33:25,786 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-09 09:33:25,786 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10 states and 13 transitions. [2021-11-09 09:33:25,787 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:25,787 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:25,788 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:25,788 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2021-11-09 09:33:25,788 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:25,788 INFO L791 eck$LassoCheckResult]: Stem: 129#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 130#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 136#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 133#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 134#L18-3 assume !(main_~i~0 < 1048); 137#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 135#L23-2 [2021-11-09 09:33:25,789 INFO L793 eck$LassoCheckResult]: Loop: 135#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 131#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 132#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 138#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 135#L23-2 [2021-11-09 09:33:25,790 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:25,790 INFO L85 PathProgramCache]: Analyzing trace with hash 889660429, now seen corresponding path program 1 times [2021-11-09 09:33:25,790 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:25,791 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [134544087] [2021-11-09 09:33:25,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:25,791 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:25,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:25,851 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:25,852 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:25,852 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [134544087] [2021-11-09 09:33:25,852 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [134544087] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:25,853 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [371705786] [2021-11-09 09:33:25,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:25,854 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:25,854 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:25,855 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:25,871 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2021-11-09 09:33:25,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:25,905 INFO L263 TraceCheckSpWp]: Trace formula consists of 35 conjuncts, 3 conjunts are in the unsatisfiable core [2021-11-09 09:33:25,906 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:25,948 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:25,949 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [371705786] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:25,950 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:25,950 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 5 [2021-11-09 09:33:25,950 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1703118350] [2021-11-09 09:33:25,951 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:25,952 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:25,952 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 2 times [2021-11-09 09:33:25,953 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:25,953 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1265655570] [2021-11-09 09:33:25,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:25,953 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:25,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:25,965 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:25,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:25,974 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:26,095 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:26,095 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-09 09:33:26,096 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2021-11-09 09:33:26,096 INFO L87 Difference]: Start difference. First operand 10 states and 13 transitions. cyclomatic complexity: 5 Second operand has 5 states, 5 states have (on average 1.8) internal successors, (9), 5 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:26,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:26,125 INFO L93 Difference]: Finished difference Result 13 states and 16 transitions. [2021-11-09 09:33:26,125 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-09 09:33:26,125 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13 states and 16 transitions. [2021-11-09 09:33:26,128 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:26,129 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13 states to 13 states and 16 transitions. [2021-11-09 09:33:26,130 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:26,130 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:26,130 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13 states and 16 transitions. [2021-11-09 09:33:26,130 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:26,130 INFO L681 BuchiCegarLoop]: Abstraction has 13 states and 16 transitions. [2021-11-09 09:33:26,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states and 16 transitions. [2021-11-09 09:33:26,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 12. [2021-11-09 09:33:26,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.25) internal successors, (15), 11 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:26,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 15 transitions. [2021-11-09 09:33:26,137 INFO L704 BuchiCegarLoop]: Abstraction has 12 states and 15 transitions. [2021-11-09 09:33:26,137 INFO L587 BuchiCegarLoop]: Abstraction has 12 states and 15 transitions. [2021-11-09 09:33:26,137 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-09 09:33:26,137 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 15 transitions. [2021-11-09 09:33:26,139 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:26,139 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:26,139 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:26,140 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1] [2021-11-09 09:33:26,140 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:26,141 INFO L791 eck$LassoCheckResult]: Stem: 175#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 176#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 182#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 183#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 184#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 179#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 180#L18-3 assume !(main_~i~0 < 1048); 185#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 181#L23-2 [2021-11-09 09:33:26,141 INFO L793 eck$LassoCheckResult]: Loop: 181#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 177#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 178#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 186#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 181#L23-2 [2021-11-09 09:33:26,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:26,142 INFO L85 PathProgramCache]: Analyzing trace with hash 265236367, now seen corresponding path program 2 times [2021-11-09 09:33:26,142 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:26,142 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2051214484] [2021-11-09 09:33:26,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:26,144 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:26,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:26,216 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:26,216 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:26,217 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2051214484] [2021-11-09 09:33:26,217 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2051214484] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:26,217 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [201862461] [2021-11-09 09:33:26,218 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:33:26,218 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:26,218 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:26,220 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:26,247 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2021-11-09 09:33:26,278 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:33:26,279 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:26,280 INFO L263 TraceCheckSpWp]: Trace formula consists of 43 conjuncts, 4 conjunts are in the unsatisfiable core [2021-11-09 09:33:26,280 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:26,352 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:26,353 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [201862461] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:26,353 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:26,353 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 6 [2021-11-09 09:33:26,353 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1425872082] [2021-11-09 09:33:26,354 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:26,354 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:26,354 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 3 times [2021-11-09 09:33:26,354 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:26,359 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [134988710] [2021-11-09 09:33:26,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:26,359 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:26,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:26,380 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:26,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:26,392 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2021-11-09 09:33:26,398 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:26,554 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:26,555 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-11-09 09:33:26,557 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2021-11-09 09:33:26,557 INFO L87 Difference]: Start difference. First operand 12 states and 15 transitions. cyclomatic complexity: 5 Second operand has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 6 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:26,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:26,585 INFO L93 Difference]: Finished difference Result 15 states and 18 transitions. [2021-11-09 09:33:26,586 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-11-09 09:33:26,586 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 18 transitions. [2021-11-09 09:33:26,587 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:26,588 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 15 states and 18 transitions. [2021-11-09 09:33:26,588 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:26,588 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:26,588 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15 states and 18 transitions. [2021-11-09 09:33:26,589 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:26,589 INFO L681 BuchiCegarLoop]: Abstraction has 15 states and 18 transitions. [2021-11-09 09:33:26,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states and 18 transitions. [2021-11-09 09:33:26,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 14. [2021-11-09 09:33:26,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.2142857142857142) internal successors, (17), 13 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:26,591 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 17 transitions. [2021-11-09 09:33:26,591 INFO L704 BuchiCegarLoop]: Abstraction has 14 states and 17 transitions. [2021-11-09 09:33:26,591 INFO L587 BuchiCegarLoop]: Abstraction has 14 states and 17 transitions. [2021-11-09 09:33:26,591 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-09 09:33:26,592 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14 states and 17 transitions. [2021-11-09 09:33:26,592 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:26,593 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:26,593 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:26,594 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 1, 1, 1, 1] [2021-11-09 09:33:26,594 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:26,595 INFO L791 eck$LassoCheckResult]: Stem: 234#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 235#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 239#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 240#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 241#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 236#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 237#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 245#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 244#L18-3 assume !(main_~i~0 < 1048); 242#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 238#L23-2 [2021-11-09 09:33:26,595 INFO L793 eck$LassoCheckResult]: Loop: 238#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 232#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 233#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 243#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 238#L23-2 [2021-11-09 09:33:26,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:26,595 INFO L85 PathProgramCache]: Analyzing trace with hash 1489134225, now seen corresponding path program 3 times [2021-11-09 09:33:26,596 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:26,596 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [106057107] [2021-11-09 09:33:26,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:26,596 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:26,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:26,645 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:26,646 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:26,646 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [106057107] [2021-11-09 09:33:26,646 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [106057107] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:26,647 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [480173246] [2021-11-09 09:33:26,647 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:33:26,647 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:26,647 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:26,648 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:26,671 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2021-11-09 09:33:26,708 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2021-11-09 09:33:26,709 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:26,709 INFO L263 TraceCheckSpWp]: Trace formula consists of 51 conjuncts, 5 conjunts are in the unsatisfiable core [2021-11-09 09:33:26,710 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:26,754 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:26,754 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [480173246] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:26,755 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:26,755 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 7 [2021-11-09 09:33:26,755 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1212336244] [2021-11-09 09:33:26,756 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:26,756 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:26,756 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 4 times [2021-11-09 09:33:26,757 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:26,757 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [630776705] [2021-11-09 09:33:26,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:26,757 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:26,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:26,764 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:26,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:26,771 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:26,875 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:26,875 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2021-11-09 09:33:26,875 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2021-11-09 09:33:26,876 INFO L87 Difference]: Start difference. First operand 14 states and 17 transitions. cyclomatic complexity: 5 Second operand has 7 states, 7 states have (on average 1.8571428571428572) internal successors, (13), 7 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:26,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:26,899 INFO L93 Difference]: Finished difference Result 17 states and 20 transitions. [2021-11-09 09:33:26,900 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-09 09:33:26,900 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17 states and 20 transitions. [2021-11-09 09:33:26,901 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:26,901 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17 states to 17 states and 20 transitions. [2021-11-09 09:33:26,901 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:26,902 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:26,902 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17 states and 20 transitions. [2021-11-09 09:33:26,902 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:26,902 INFO L681 BuchiCegarLoop]: Abstraction has 17 states and 20 transitions. [2021-11-09 09:33:26,902 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states and 20 transitions. [2021-11-09 09:33:26,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 16. [2021-11-09 09:33:26,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.1875) internal successors, (19), 15 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:26,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 19 transitions. [2021-11-09 09:33:26,904 INFO L704 BuchiCegarLoop]: Abstraction has 16 states and 19 transitions. [2021-11-09 09:33:26,904 INFO L587 BuchiCegarLoop]: Abstraction has 16 states and 19 transitions. [2021-11-09 09:33:26,905 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-09 09:33:26,905 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 19 transitions. [2021-11-09 09:33:26,905 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:26,905 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:26,906 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:26,906 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 1, 1, 1, 1] [2021-11-09 09:33:26,906 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:26,906 INFO L791 eck$LassoCheckResult]: Stem: 302#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 303#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 307#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 308#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 309#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 304#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 305#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 315#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 314#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 313#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 312#L18-3 assume !(main_~i~0 < 1048); 310#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 306#L23-2 [2021-11-09 09:33:26,907 INFO L793 eck$LassoCheckResult]: Loop: 306#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 300#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 301#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 311#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 306#L23-2 [2021-11-09 09:33:26,907 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:26,907 INFO L85 PathProgramCache]: Analyzing trace with hash 833936659, now seen corresponding path program 4 times [2021-11-09 09:33:26,907 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:26,908 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [439015477] [2021-11-09 09:33:26,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:26,908 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:26,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:26,956 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:26,956 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:26,957 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [439015477] [2021-11-09 09:33:26,957 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [439015477] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:26,957 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [993361452] [2021-11-09 09:33:26,957 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:33:26,957 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:26,958 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:26,959 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:26,985 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2021-11-09 09:33:27,024 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:33:27,025 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:27,025 INFO L263 TraceCheckSpWp]: Trace formula consists of 59 conjuncts, 6 conjunts are in the unsatisfiable core [2021-11-09 09:33:27,026 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:27,084 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:27,084 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [993361452] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:27,087 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:27,087 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 8 [2021-11-09 09:33:27,088 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [537718740] [2021-11-09 09:33:27,088 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:27,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:27,089 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 5 times [2021-11-09 09:33:27,089 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:27,089 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1927963183] [2021-11-09 09:33:27,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:27,090 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:27,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:27,099 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:27,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:27,119 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:27,253 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:27,254 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2021-11-09 09:33:27,254 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2021-11-09 09:33:27,254 INFO L87 Difference]: Start difference. First operand 16 states and 19 transitions. cyclomatic complexity: 5 Second operand has 8 states, 8 states have (on average 1.875) internal successors, (15), 8 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:27,299 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:27,299 INFO L93 Difference]: Finished difference Result 19 states and 22 transitions. [2021-11-09 09:33:27,300 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-11-09 09:33:27,300 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19 states and 22 transitions. [2021-11-09 09:33:27,301 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:27,301 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19 states to 19 states and 22 transitions. [2021-11-09 09:33:27,301 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:27,301 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:27,302 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19 states and 22 transitions. [2021-11-09 09:33:27,302 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:27,302 INFO L681 BuchiCegarLoop]: Abstraction has 19 states and 22 transitions. [2021-11-09 09:33:27,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states and 22 transitions. [2021-11-09 09:33:27,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 18. [2021-11-09 09:33:27,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 18 states have (on average 1.1666666666666667) internal successors, (21), 17 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:27,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 21 transitions. [2021-11-09 09:33:27,304 INFO L704 BuchiCegarLoop]: Abstraction has 18 states and 21 transitions. [2021-11-09 09:33:27,304 INFO L587 BuchiCegarLoop]: Abstraction has 18 states and 21 transitions. [2021-11-09 09:33:27,305 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-09 09:33:27,305 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18 states and 21 transitions. [2021-11-09 09:33:27,305 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:27,305 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:27,305 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:27,306 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 5, 1, 1, 1, 1] [2021-11-09 09:33:27,306 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:27,306 INFO L791 eck$LassoCheckResult]: Stem: 379#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 380#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 386#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 387#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 388#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 383#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 384#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 396#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 395#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 394#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 393#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 392#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 391#L18-3 assume !(main_~i~0 < 1048); 389#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 385#L23-2 [2021-11-09 09:33:27,306 INFO L793 eck$LassoCheckResult]: Loop: 385#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 381#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 382#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 390#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 385#L23-2 [2021-11-09 09:33:27,307 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:27,307 INFO L85 PathProgramCache]: Analyzing trace with hash -1745699051, now seen corresponding path program 5 times [2021-11-09 09:33:27,307 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:27,308 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1483889287] [2021-11-09 09:33:27,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:27,308 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:27,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:27,376 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 0 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:27,376 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:27,377 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1483889287] [2021-11-09 09:33:27,377 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1483889287] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:27,377 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1306428451] [2021-11-09 09:33:27,377 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:33:27,377 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:27,377 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:27,379 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:27,384 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2021-11-09 09:33:27,452 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2021-11-09 09:33:27,452 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:27,453 INFO L263 TraceCheckSpWp]: Trace formula consists of 67 conjuncts, 7 conjunts are in the unsatisfiable core [2021-11-09 09:33:27,454 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:27,522 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 0 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:27,523 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1306428451] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:27,523 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:27,523 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 9 [2021-11-09 09:33:27,523 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2130765037] [2021-11-09 09:33:27,524 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:27,524 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:27,524 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 6 times [2021-11-09 09:33:27,525 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:27,525 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510915708] [2021-11-09 09:33:27,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:27,525 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:27,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:27,531 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:27,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:27,536 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:27,650 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:27,651 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2021-11-09 09:33:27,651 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2021-11-09 09:33:27,652 INFO L87 Difference]: Start difference. First operand 18 states and 21 transitions. cyclomatic complexity: 5 Second operand has 9 states, 9 states have (on average 1.8888888888888888) internal successors, (17), 9 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:27,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:27,684 INFO L93 Difference]: Finished difference Result 21 states and 24 transitions. [2021-11-09 09:33:27,684 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2021-11-09 09:33:27,684 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21 states and 24 transitions. [2021-11-09 09:33:27,685 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:27,686 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21 states to 21 states and 24 transitions. [2021-11-09 09:33:27,686 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:27,686 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:27,686 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21 states and 24 transitions. [2021-11-09 09:33:27,686 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:27,686 INFO L681 BuchiCegarLoop]: Abstraction has 21 states and 24 transitions. [2021-11-09 09:33:27,686 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states and 24 transitions. [2021-11-09 09:33:27,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 20. [2021-11-09 09:33:27,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.15) internal successors, (23), 19 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:27,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 23 transitions. [2021-11-09 09:33:27,689 INFO L704 BuchiCegarLoop]: Abstraction has 20 states and 23 transitions. [2021-11-09 09:33:27,689 INFO L587 BuchiCegarLoop]: Abstraction has 20 states and 23 transitions. [2021-11-09 09:33:27,689 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-09 09:33:27,689 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20 states and 23 transitions. [2021-11-09 09:33:27,689 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:27,689 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:27,690 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:27,690 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 6, 1, 1, 1, 1] [2021-11-09 09:33:27,690 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:27,690 INFO L791 eck$LassoCheckResult]: Stem: 469#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 470#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 476#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 477#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 478#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 473#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 474#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 488#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 487#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 486#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 485#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 484#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 483#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 482#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 481#L18-3 assume !(main_~i~0 < 1048); 479#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 475#L23-2 [2021-11-09 09:33:27,691 INFO L793 eck$LassoCheckResult]: Loop: 475#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 471#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 472#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 480#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 475#L23-2 [2021-11-09 09:33:27,691 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:27,691 INFO L85 PathProgramCache]: Analyzing trace with hash 1715480727, now seen corresponding path program 6 times [2021-11-09 09:33:27,691 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:27,691 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [975062457] [2021-11-09 09:33:27,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:27,692 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:27,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:27,777 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:27,777 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:27,778 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [975062457] [2021-11-09 09:33:27,778 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [975062457] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:27,778 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [356683600] [2021-11-09 09:33:27,778 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:33:27,778 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:27,779 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:27,788 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:27,790 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2021-11-09 09:33:27,873 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2021-11-09 09:33:27,873 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:27,874 INFO L263 TraceCheckSpWp]: Trace formula consists of 75 conjuncts, 8 conjunts are in the unsatisfiable core [2021-11-09 09:33:27,875 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:27,953 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:27,953 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [356683600] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:27,953 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:27,953 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2021-11-09 09:33:27,954 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [451304512] [2021-11-09 09:33:27,954 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:27,955 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:27,955 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 7 times [2021-11-09 09:33:27,955 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:27,955 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [105605575] [2021-11-09 09:33:27,955 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:27,956 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:27,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:27,962 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:27,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:27,971 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:28,077 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:28,078 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2021-11-09 09:33:28,078 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2021-11-09 09:33:28,078 INFO L87 Difference]: Start difference. First operand 20 states and 23 transitions. cyclomatic complexity: 5 Second operand has 10 states, 10 states have (on average 1.9) internal successors, (19), 10 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:28,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:28,128 INFO L93 Difference]: Finished difference Result 23 states and 26 transitions. [2021-11-09 09:33:28,129 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2021-11-09 09:33:28,129 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23 states and 26 transitions. [2021-11-09 09:33:28,133 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:28,134 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23 states to 23 states and 26 transitions. [2021-11-09 09:33:28,134 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:28,134 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:28,135 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23 states and 26 transitions. [2021-11-09 09:33:28,135 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:28,135 INFO L681 BuchiCegarLoop]: Abstraction has 23 states and 26 transitions. [2021-11-09 09:33:28,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states and 26 transitions. [2021-11-09 09:33:28,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 22. [2021-11-09 09:33:28,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 22 states have (on average 1.1363636363636365) internal successors, (25), 21 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:28,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 25 transitions. [2021-11-09 09:33:28,144 INFO L704 BuchiCegarLoop]: Abstraction has 22 states and 25 transitions. [2021-11-09 09:33:28,144 INFO L587 BuchiCegarLoop]: Abstraction has 22 states and 25 transitions. [2021-11-09 09:33:28,145 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-09 09:33:28,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22 states and 25 transitions. [2021-11-09 09:33:28,145 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:28,145 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:28,146 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:28,147 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 1, 1, 1, 1] [2021-11-09 09:33:28,148 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:28,148 INFO L791 eck$LassoCheckResult]: Stem: 570#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 571#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 577#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 578#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 579#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 574#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 575#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 591#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 590#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 589#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 588#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 587#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 586#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 585#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 584#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 583#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 582#L18-3 assume !(main_~i~0 < 1048); 580#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 576#L23-2 [2021-11-09 09:33:28,148 INFO L793 eck$LassoCheckResult]: Loop: 576#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 572#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 573#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 581#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 576#L23-2 [2021-11-09 09:33:28,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:28,149 INFO L85 PathProgramCache]: Analyzing trace with hash -690407015, now seen corresponding path program 7 times [2021-11-09 09:33:28,149 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:28,149 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [640386467] [2021-11-09 09:33:28,149 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:28,150 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:28,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:28,308 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:28,309 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:28,309 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [640386467] [2021-11-09 09:33:28,309 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [640386467] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:28,310 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [224518689] [2021-11-09 09:33:28,310 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:33:28,310 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:28,310 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:28,314 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:28,316 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2021-11-09 09:33:28,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:28,388 INFO L263 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 9 conjunts are in the unsatisfiable core [2021-11-09 09:33:28,390 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:28,457 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:28,457 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [224518689] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:28,457 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:28,457 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 11 [2021-11-09 09:33:28,459 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [278120005] [2021-11-09 09:33:28,459 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:28,460 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:28,460 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 8 times [2021-11-09 09:33:28,460 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:28,460 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [420790240] [2021-11-09 09:33:28,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:28,461 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:28,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:28,471 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:28,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:28,486 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:28,605 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:28,607 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2021-11-09 09:33:28,608 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2021-11-09 09:33:28,608 INFO L87 Difference]: Start difference. First operand 22 states and 25 transitions. cyclomatic complexity: 5 Second operand has 11 states, 11 states have (on average 1.9090909090909092) internal successors, (21), 11 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:28,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:28,656 INFO L93 Difference]: Finished difference Result 25 states and 28 transitions. [2021-11-09 09:33:28,656 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-11-09 09:33:28,656 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25 states and 28 transitions. [2021-11-09 09:33:28,657 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:28,658 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25 states to 25 states and 28 transitions. [2021-11-09 09:33:28,658 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:28,658 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:28,658 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25 states and 28 transitions. [2021-11-09 09:33:28,658 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:28,658 INFO L681 BuchiCegarLoop]: Abstraction has 25 states and 28 transitions. [2021-11-09 09:33:28,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states and 28 transitions. [2021-11-09 09:33:28,660 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 24. [2021-11-09 09:33:28,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.125) internal successors, (27), 23 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:28,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 27 transitions. [2021-11-09 09:33:28,661 INFO L704 BuchiCegarLoop]: Abstraction has 24 states and 27 transitions. [2021-11-09 09:33:28,661 INFO L587 BuchiCegarLoop]: Abstraction has 24 states and 27 transitions. [2021-11-09 09:33:28,661 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-09 09:33:28,661 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 27 transitions. [2021-11-09 09:33:28,662 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:28,662 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:28,662 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:28,663 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [8, 8, 1, 1, 1, 1] [2021-11-09 09:33:28,663 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:28,663 INFO L791 eck$LassoCheckResult]: Stem: 682#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 683#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 689#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 690#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 691#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 686#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 687#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 705#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 704#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 703#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 702#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 701#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 700#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 699#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 698#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 697#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 696#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 695#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 694#L18-3 assume !(main_~i~0 < 1048); 692#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 688#L23-2 [2021-11-09 09:33:28,663 INFO L793 eck$LassoCheckResult]: Loop: 688#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 684#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 685#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 693#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 688#L23-2 [2021-11-09 09:33:28,664 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:28,664 INFO L85 PathProgramCache]: Analyzing trace with hash -2056121829, now seen corresponding path program 8 times [2021-11-09 09:33:28,664 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:28,664 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1650416784] [2021-11-09 09:33:28,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:28,665 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:28,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:28,763 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 0 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:28,763 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:28,763 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1650416784] [2021-11-09 09:33:28,764 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1650416784] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:28,764 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2097776848] [2021-11-09 09:33:28,764 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:33:28,764 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:28,764 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:28,772 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:28,793 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2021-11-09 09:33:28,865 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:33:28,865 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:28,866 INFO L263 TraceCheckSpWp]: Trace formula consists of 91 conjuncts, 10 conjunts are in the unsatisfiable core [2021-11-09 09:33:28,868 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:28,949 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 0 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:28,950 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2097776848] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:28,950 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:28,950 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 12 [2021-11-09 09:33:28,950 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2076845889] [2021-11-09 09:33:28,951 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:28,952 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:28,952 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 9 times [2021-11-09 09:33:28,952 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:28,952 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [158163130] [2021-11-09 09:33:28,952 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:28,953 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:28,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:28,962 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:28,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:28,972 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:29,079 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:29,079 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2021-11-09 09:33:29,080 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2021-11-09 09:33:29,080 INFO L87 Difference]: Start difference. First operand 24 states and 27 transitions. cyclomatic complexity: 5 Second operand has 12 states, 12 states have (on average 1.9166666666666667) internal successors, (23), 12 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:29,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:29,122 INFO L93 Difference]: Finished difference Result 27 states and 30 transitions. [2021-11-09 09:33:29,122 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-11-09 09:33:29,123 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 30 transitions. [2021-11-09 09:33:29,123 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:29,124 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 27 states and 30 transitions. [2021-11-09 09:33:29,124 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:29,124 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:29,125 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 30 transitions. [2021-11-09 09:33:29,125 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:29,125 INFO L681 BuchiCegarLoop]: Abstraction has 27 states and 30 transitions. [2021-11-09 09:33:29,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 30 transitions. [2021-11-09 09:33:29,127 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 26. [2021-11-09 09:33:29,127 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 1.1153846153846154) internal successors, (29), 25 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:29,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 29 transitions. [2021-11-09 09:33:29,128 INFO L704 BuchiCegarLoop]: Abstraction has 26 states and 29 transitions. [2021-11-09 09:33:29,128 INFO L587 BuchiCegarLoop]: Abstraction has 26 states and 29 transitions. [2021-11-09 09:33:29,128 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-09 09:33:29,129 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26 states and 29 transitions. [2021-11-09 09:33:29,129 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:29,129 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:29,129 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:29,130 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [9, 9, 1, 1, 1, 1] [2021-11-09 09:33:29,131 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:29,131 INFO L791 eck$LassoCheckResult]: Stem: 805#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 806#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 812#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 813#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 814#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 809#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 810#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 830#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 829#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 828#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 827#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 826#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 825#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 824#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 823#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 822#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 821#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 820#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 819#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 818#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 817#L18-3 assume !(main_~i~0 < 1048); 815#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 811#L23-2 [2021-11-09 09:33:29,131 INFO L793 eck$LassoCheckResult]: Loop: 811#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 807#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 808#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 816#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 811#L23-2 [2021-11-09 09:33:29,132 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:29,132 INFO L85 PathProgramCache]: Analyzing trace with hash -248065507, now seen corresponding path program 9 times [2021-11-09 09:33:29,132 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:29,132 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [537745404] [2021-11-09 09:33:29,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:29,133 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:29,159 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:29,314 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:29,314 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:29,314 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [537745404] [2021-11-09 09:33:29,314 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [537745404] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:29,315 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [966799825] [2021-11-09 09:33:29,315 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:33:29,315 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:29,315 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:29,321 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:29,338 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2021-11-09 09:33:29,462 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2021-11-09 09:33:29,462 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:29,463 INFO L263 TraceCheckSpWp]: Trace formula consists of 99 conjuncts, 11 conjunts are in the unsatisfiable core [2021-11-09 09:33:29,465 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:29,576 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:29,577 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [966799825] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:29,577 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:29,577 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 13 [2021-11-09 09:33:29,579 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [373102944] [2021-11-09 09:33:29,581 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:29,582 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:29,582 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 10 times [2021-11-09 09:33:29,582 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:29,582 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1255835691] [2021-11-09 09:33:29,583 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:29,583 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:29,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:29,589 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:29,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:29,594 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:29,710 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:29,711 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2021-11-09 09:33:29,711 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2021-11-09 09:33:29,711 INFO L87 Difference]: Start difference. First operand 26 states and 29 transitions. cyclomatic complexity: 5 Second operand has 13 states, 13 states have (on average 1.9230769230769231) internal successors, (25), 13 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:29,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:29,763 INFO L93 Difference]: Finished difference Result 29 states and 32 transitions. [2021-11-09 09:33:29,764 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2021-11-09 09:33:29,764 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29 states and 32 transitions. [2021-11-09 09:33:29,764 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:29,765 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29 states to 29 states and 32 transitions. [2021-11-09 09:33:29,765 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:29,765 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:29,765 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29 states and 32 transitions. [2021-11-09 09:33:29,766 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:29,766 INFO L681 BuchiCegarLoop]: Abstraction has 29 states and 32 transitions. [2021-11-09 09:33:29,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states and 32 transitions. [2021-11-09 09:33:29,768 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 28. [2021-11-09 09:33:29,769 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.1071428571428572) internal successors, (31), 27 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:29,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 31 transitions. [2021-11-09 09:33:29,769 INFO L704 BuchiCegarLoop]: Abstraction has 28 states and 31 transitions. [2021-11-09 09:33:29,769 INFO L587 BuchiCegarLoop]: Abstraction has 28 states and 31 transitions. [2021-11-09 09:33:29,770 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-09 09:33:29,770 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 31 transitions. [2021-11-09 09:33:29,770 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:29,771 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:29,771 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:29,772 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [10, 10, 1, 1, 1, 1] [2021-11-09 09:33:29,772 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:29,772 INFO L791 eck$LassoCheckResult]: Stem: 939#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 940#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 946#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 947#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 948#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 943#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 944#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 966#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 965#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 964#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 963#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 962#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 961#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 960#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 959#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 958#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 957#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 956#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 955#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 954#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 953#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 952#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 951#L18-3 assume !(main_~i~0 < 1048); 949#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 945#L23-2 [2021-11-09 09:33:29,772 INFO L793 eck$LassoCheckResult]: Loop: 945#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 941#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 942#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 950#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 945#L23-2 [2021-11-09 09:33:29,773 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:29,773 INFO L85 PathProgramCache]: Analyzing trace with hash 2127272351, now seen corresponding path program 10 times [2021-11-09 09:33:29,773 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:29,773 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1008045625] [2021-11-09 09:33:29,773 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:29,774 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:29,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:29,906 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:29,906 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:29,906 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1008045625] [2021-11-09 09:33:29,907 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1008045625] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:29,907 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [500034455] [2021-11-09 09:33:29,907 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:33:29,907 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:29,907 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:29,916 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:29,923 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2021-11-09 09:33:30,017 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:33:30,017 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:30,018 INFO L263 TraceCheckSpWp]: Trace formula consists of 107 conjuncts, 12 conjunts are in the unsatisfiable core [2021-11-09 09:33:30,019 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:30,148 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:30,149 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [500034455] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:30,149 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:30,149 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 14 [2021-11-09 09:33:30,149 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2010025906] [2021-11-09 09:33:30,150 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:30,150 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:30,150 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 11 times [2021-11-09 09:33:30,151 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:30,151 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [104445752] [2021-11-09 09:33:30,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:30,151 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:30,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:30,156 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:30,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:30,160 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:30,285 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:30,286 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2021-11-09 09:33:30,286 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2021-11-09 09:33:30,286 INFO L87 Difference]: Start difference. First operand 28 states and 31 transitions. cyclomatic complexity: 5 Second operand has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 14 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:30,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:30,332 INFO L93 Difference]: Finished difference Result 31 states and 34 transitions. [2021-11-09 09:33:30,334 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2021-11-09 09:33:30,334 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31 states and 34 transitions. [2021-11-09 09:33:30,335 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:30,335 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31 states to 31 states and 34 transitions. [2021-11-09 09:33:30,336 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:30,336 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:30,336 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31 states and 34 transitions. [2021-11-09 09:33:30,336 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:30,336 INFO L681 BuchiCegarLoop]: Abstraction has 31 states and 34 transitions. [2021-11-09 09:33:30,337 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states and 34 transitions. [2021-11-09 09:33:30,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 30. [2021-11-09 09:33:30,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30 states, 30 states have (on average 1.1) internal successors, (33), 29 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:30,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 33 transitions. [2021-11-09 09:33:30,339 INFO L704 BuchiCegarLoop]: Abstraction has 30 states and 33 transitions. [2021-11-09 09:33:30,340 INFO L587 BuchiCegarLoop]: Abstraction has 30 states and 33 transitions. [2021-11-09 09:33:30,340 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-09 09:33:30,340 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30 states and 33 transitions. [2021-11-09 09:33:30,340 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:30,340 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:30,341 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:30,342 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [11, 11, 1, 1, 1, 1] [2021-11-09 09:33:30,342 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:30,342 INFO L791 eck$LassoCheckResult]: Stem: 1084#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 1085#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 1091#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1092#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1093#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1088#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1089#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1113#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1112#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1111#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1110#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1109#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1108#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1107#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1106#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1105#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1104#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1103#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1102#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1101#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1100#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1099#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1098#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1097#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1096#L18-3 assume !(main_~i~0 < 1048); 1094#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 1090#L23-2 [2021-11-09 09:33:30,342 INFO L793 eck$LassoCheckResult]: Loop: 1090#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 1086#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 1087#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 1095#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 1090#L23-2 [2021-11-09 09:33:30,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:30,343 INFO L85 PathProgramCache]: Analyzing trace with hash -95647583, now seen corresponding path program 11 times [2021-11-09 09:33:30,343 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:30,343 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1601461120] [2021-11-09 09:33:30,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:30,344 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:30,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:30,482 INFO L134 CoverageAnalysis]: Checked inductivity of 121 backedges. 0 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:30,482 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:30,482 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1601461120] [2021-11-09 09:33:30,483 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1601461120] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:30,483 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [128502361] [2021-11-09 09:33:30,484 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:33:30,484 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:30,484 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:30,486 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:30,515 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2021-11-09 09:33:30,706 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2021-11-09 09:33:30,707 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:30,708 INFO L263 TraceCheckSpWp]: Trace formula consists of 115 conjuncts, 13 conjunts are in the unsatisfiable core [2021-11-09 09:33:30,710 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:30,842 INFO L134 CoverageAnalysis]: Checked inductivity of 121 backedges. 0 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:30,843 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [128502361] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:30,843 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:30,843 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 15 [2021-11-09 09:33:30,843 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [902942553] [2021-11-09 09:33:30,844 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:30,844 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:30,844 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 12 times [2021-11-09 09:33:30,845 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:30,845 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [680162797] [2021-11-09 09:33:30,845 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:30,845 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:30,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:30,852 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:30,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:30,857 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:30,964 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:30,964 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2021-11-09 09:33:30,965 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2021-11-09 09:33:30,965 INFO L87 Difference]: Start difference. First operand 30 states and 33 transitions. cyclomatic complexity: 5 Second operand has 15 states, 15 states have (on average 1.9333333333333333) internal successors, (29), 15 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:31,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:31,019 INFO L93 Difference]: Finished difference Result 33 states and 36 transitions. [2021-11-09 09:33:31,027 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2021-11-09 09:33:31,028 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33 states and 36 transitions. [2021-11-09 09:33:31,029 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:31,029 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33 states to 33 states and 36 transitions. [2021-11-09 09:33:31,029 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:31,030 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:31,030 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33 states and 36 transitions. [2021-11-09 09:33:31,030 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:31,030 INFO L681 BuchiCegarLoop]: Abstraction has 33 states and 36 transitions. [2021-11-09 09:33:31,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33 states and 36 transitions. [2021-11-09 09:33:31,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33 to 32. [2021-11-09 09:33:31,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 32 states have (on average 1.09375) internal successors, (35), 31 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:31,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 35 transitions. [2021-11-09 09:33:31,034 INFO L704 BuchiCegarLoop]: Abstraction has 32 states and 35 transitions. [2021-11-09 09:33:31,034 INFO L587 BuchiCegarLoop]: Abstraction has 32 states and 35 transitions. [2021-11-09 09:33:31,034 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-09 09:33:31,034 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32 states and 35 transitions. [2021-11-09 09:33:31,034 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:31,035 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:31,035 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:31,036 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [12, 12, 1, 1, 1, 1] [2021-11-09 09:33:31,036 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:31,036 INFO L791 eck$LassoCheckResult]: Stem: 1242#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 1243#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 1247#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1248#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1249#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1244#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1245#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1271#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1270#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1269#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1268#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1267#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1266#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1265#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1264#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1263#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1262#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1261#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1260#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1259#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1258#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1257#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1256#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1255#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1254#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1253#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1252#L18-3 assume !(main_~i~0 < 1048); 1250#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 1246#L23-2 [2021-11-09 09:33:31,036 INFO L793 eck$LassoCheckResult]: Loop: 1246#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 1240#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 1241#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 1251#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 1246#L23-2 [2021-11-09 09:33:31,037 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:31,037 INFO L85 PathProgramCache]: Analyzing trace with hash -1722958045, now seen corresponding path program 12 times [2021-11-09 09:33:31,037 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:31,038 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1534435878] [2021-11-09 09:33:31,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:31,038 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:31,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:31,221 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:31,221 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:31,221 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1534435878] [2021-11-09 09:33:31,221 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1534435878] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:31,221 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1734952065] [2021-11-09 09:33:31,221 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:33:31,221 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:31,222 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:31,224 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:31,256 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2021-11-09 09:33:31,549 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2021-11-09 09:33:31,549 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:31,552 INFO L263 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 14 conjunts are in the unsatisfiable core [2021-11-09 09:33:31,553 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:31,695 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:31,695 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1734952065] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:31,696 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:31,696 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 16 [2021-11-09 09:33:31,696 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [989276608] [2021-11-09 09:33:31,696 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:31,697 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:31,698 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 13 times [2021-11-09 09:33:31,698 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:31,698 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1742162716] [2021-11-09 09:33:31,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:31,699 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:31,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:31,705 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:31,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:31,712 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:31,818 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:31,819 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2021-11-09 09:33:31,819 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2021-11-09 09:33:31,819 INFO L87 Difference]: Start difference. First operand 32 states and 35 transitions. cyclomatic complexity: 5 Second operand has 16 states, 16 states have (on average 1.9375) internal successors, (31), 16 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:31,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:31,885 INFO L93 Difference]: Finished difference Result 35 states and 38 transitions. [2021-11-09 09:33:31,885 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-11-09 09:33:31,885 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 38 transitions. [2021-11-09 09:33:31,886 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:31,887 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 35 states and 38 transitions. [2021-11-09 09:33:31,888 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:31,888 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:31,888 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35 states and 38 transitions. [2021-11-09 09:33:31,888 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:31,888 INFO L681 BuchiCegarLoop]: Abstraction has 35 states and 38 transitions. [2021-11-09 09:33:31,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states and 38 transitions. [2021-11-09 09:33:31,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 34. [2021-11-09 09:33:31,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.088235294117647) internal successors, (37), 33 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:31,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 37 transitions. [2021-11-09 09:33:31,891 INFO L704 BuchiCegarLoop]: Abstraction has 34 states and 37 transitions. [2021-11-09 09:33:31,891 INFO L587 BuchiCegarLoop]: Abstraction has 34 states and 37 transitions. [2021-11-09 09:33:31,891 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-09 09:33:31,891 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 37 transitions. [2021-11-09 09:33:31,891 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:31,892 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:31,892 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:31,893 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [13, 13, 1, 1, 1, 1] [2021-11-09 09:33:31,893 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:31,893 INFO L791 eck$LassoCheckResult]: Stem: 1407#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 1408#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 1414#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1415#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1416#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1411#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1412#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1440#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1439#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1438#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1437#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1436#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1435#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1434#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1433#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1432#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1431#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1430#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1429#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1428#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1427#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1426#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1425#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1424#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1423#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1422#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1421#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1420#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1419#L18-3 assume !(main_~i~0 < 1048); 1417#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 1413#L23-2 [2021-11-09 09:33:31,894 INFO L793 eck$LassoCheckResult]: Loop: 1413#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 1409#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 1410#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 1418#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 1413#L23-2 [2021-11-09 09:33:31,894 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:31,894 INFO L85 PathProgramCache]: Analyzing trace with hash 2094751013, now seen corresponding path program 13 times [2021-11-09 09:33:31,894 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:31,894 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1613820153] [2021-11-09 09:33:31,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:31,895 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:31,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:32,064 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 0 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:32,064 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:32,064 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1613820153] [2021-11-09 09:33:32,064 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1613820153] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:32,064 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [837124387] [2021-11-09 09:33:32,064 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:33:32,064 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:32,065 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:32,067 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:32,068 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2021-11-09 09:33:32,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:32,196 INFO L263 TraceCheckSpWp]: Trace formula consists of 131 conjuncts, 15 conjunts are in the unsatisfiable core [2021-11-09 09:33:32,198 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:32,324 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 0 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:32,325 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [837124387] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:32,325 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:32,325 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 17 [2021-11-09 09:33:32,325 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [901192173] [2021-11-09 09:33:32,326 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:32,327 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:32,327 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 14 times [2021-11-09 09:33:32,328 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:32,328 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [436464382] [2021-11-09 09:33:32,328 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:32,328 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:32,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:32,333 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:32,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:32,339 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:32,443 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:32,444 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2021-11-09 09:33:32,444 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=136, Invalid=136, Unknown=0, NotChecked=0, Total=272 [2021-11-09 09:33:32,444 INFO L87 Difference]: Start difference. First operand 34 states and 37 transitions. cyclomatic complexity: 5 Second operand has 17 states, 17 states have (on average 1.9411764705882353) internal successors, (33), 17 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:32,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:32,503 INFO L93 Difference]: Finished difference Result 37 states and 40 transitions. [2021-11-09 09:33:32,504 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2021-11-09 09:33:32,504 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37 states and 40 transitions. [2021-11-09 09:33:32,505 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:32,505 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37 states to 37 states and 40 transitions. [2021-11-09 09:33:32,505 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:32,505 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:32,505 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37 states and 40 transitions. [2021-11-09 09:33:32,506 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:32,506 INFO L681 BuchiCegarLoop]: Abstraction has 37 states and 40 transitions. [2021-11-09 09:33:32,506 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states and 40 transitions. [2021-11-09 09:33:32,508 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 36. [2021-11-09 09:33:32,508 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 36 states have (on average 1.0833333333333333) internal successors, (39), 35 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:32,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 39 transitions. [2021-11-09 09:33:32,509 INFO L704 BuchiCegarLoop]: Abstraction has 36 states and 39 transitions. [2021-11-09 09:33:32,509 INFO L587 BuchiCegarLoop]: Abstraction has 36 states and 39 transitions. [2021-11-09 09:33:32,509 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-09 09:33:32,509 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36 states and 39 transitions. [2021-11-09 09:33:32,509 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:32,509 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:32,510 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:32,510 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [14, 14, 1, 1, 1, 1] [2021-11-09 09:33:32,510 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:32,511 INFO L791 eck$LassoCheckResult]: Stem: 1585#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 1586#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 1592#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1593#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1594#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1589#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1590#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1620#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1619#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1618#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1617#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1616#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1615#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1614#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1613#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1612#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1611#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1610#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1609#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1608#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1607#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1606#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1605#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1604#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1603#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1602#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1601#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1600#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1599#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1598#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1597#L18-3 assume !(main_~i~0 < 1048); 1595#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 1591#L23-2 [2021-11-09 09:33:32,511 INFO L793 eck$LassoCheckResult]: Loop: 1591#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 1587#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 1588#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 1596#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 1591#L23-2 [2021-11-09 09:33:32,511 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:32,511 INFO L85 PathProgramCache]: Analyzing trace with hash -1283882329, now seen corresponding path program 14 times [2021-11-09 09:33:32,512 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:32,512 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905144068] [2021-11-09 09:33:32,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:32,512 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:32,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:32,681 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:32,681 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:32,681 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [905144068] [2021-11-09 09:33:32,681 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [905144068] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:32,681 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [44373474] [2021-11-09 09:33:32,681 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:33:32,682 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:32,682 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:32,683 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:32,698 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2021-11-09 09:33:32,835 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:33:32,835 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:32,836 INFO L263 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 16 conjunts are in the unsatisfiable core [2021-11-09 09:33:32,838 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:32,988 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:32,988 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [44373474] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:32,988 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:32,989 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 18 [2021-11-09 09:33:32,989 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [924390674] [2021-11-09 09:33:32,989 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:32,990 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:32,990 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 15 times [2021-11-09 09:33:32,990 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:32,990 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019126185] [2021-11-09 09:33:32,991 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:32,991 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:32,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:32,997 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:33,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:33,002 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:33,119 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:33,120 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2021-11-09 09:33:33,120 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2021-11-09 09:33:33,121 INFO L87 Difference]: Start difference. First operand 36 states and 39 transitions. cyclomatic complexity: 5 Second operand has 18 states, 18 states have (on average 1.9444444444444444) internal successors, (35), 18 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:33,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:33,186 INFO L93 Difference]: Finished difference Result 39 states and 42 transitions. [2021-11-09 09:33:33,187 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2021-11-09 09:33:33,187 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39 states and 42 transitions. [2021-11-09 09:33:33,188 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:33,190 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39 states to 39 states and 42 transitions. [2021-11-09 09:33:33,190 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:33,190 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:33,190 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 42 transitions. [2021-11-09 09:33:33,194 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:33,196 INFO L681 BuchiCegarLoop]: Abstraction has 39 states and 42 transitions. [2021-11-09 09:33:33,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 42 transitions. [2021-11-09 09:33:33,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 38. [2021-11-09 09:33:33,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38 states, 38 states have (on average 1.0789473684210527) internal successors, (41), 37 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:33,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 41 transitions. [2021-11-09 09:33:33,201 INFO L704 BuchiCegarLoop]: Abstraction has 38 states and 41 transitions. [2021-11-09 09:33:33,201 INFO L587 BuchiCegarLoop]: Abstraction has 38 states and 41 transitions. [2021-11-09 09:33:33,201 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-09 09:33:33,202 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38 states and 41 transitions. [2021-11-09 09:33:33,202 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:33,202 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:33,202 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:33,204 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [15, 15, 1, 1, 1, 1] [2021-11-09 09:33:33,205 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:33,208 INFO L791 eck$LassoCheckResult]: Stem: 1774#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 1775#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 1781#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1782#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1783#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1778#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1779#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1811#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1810#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1809#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1808#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1807#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1806#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1805#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1804#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1803#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1802#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1801#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1800#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1799#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1798#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1797#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1796#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1795#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1794#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1793#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1792#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1791#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1790#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1789#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1788#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1787#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1786#L18-3 assume !(main_~i~0 < 1048); 1784#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 1780#L23-2 [2021-11-09 09:33:33,208 INFO L793 eck$LassoCheckResult]: Loop: 1780#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 1776#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 1777#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 1785#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 1780#L23-2 [2021-11-09 09:33:33,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:33,209 INFO L85 PathProgramCache]: Analyzing trace with hash -1155248215, now seen corresponding path program 15 times [2021-11-09 09:33:33,209 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:33,209 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1499574335] [2021-11-09 09:33:33,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:33,209 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:33,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:33,416 INFO L134 CoverageAnalysis]: Checked inductivity of 225 backedges. 0 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:33,416 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:33,416 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1499574335] [2021-11-09 09:33:33,416 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1499574335] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:33,416 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [547714522] [2021-11-09 09:33:33,416 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:33:33,417 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:33,417 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:33,418 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:33,419 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2021-11-09 09:33:33,770 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2021-11-09 09:33:33,770 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:33,773 INFO L263 TraceCheckSpWp]: Trace formula consists of 147 conjuncts, 17 conjunts are in the unsatisfiable core [2021-11-09 09:33:33,775 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:33,904 INFO L134 CoverageAnalysis]: Checked inductivity of 225 backedges. 0 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:33,904 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [547714522] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:33,904 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:33,904 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 19 [2021-11-09 09:33:33,905 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1467263896] [2021-11-09 09:33:33,905 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:33,905 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:33,906 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 16 times [2021-11-09 09:33:33,906 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:33,906 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [30665293] [2021-11-09 09:33:33,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:33,906 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:33,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:33,940 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:33,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:33,944 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:34,062 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:34,062 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2021-11-09 09:33:34,063 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2021-11-09 09:33:34,063 INFO L87 Difference]: Start difference. First operand 38 states and 41 transitions. cyclomatic complexity: 5 Second operand has 19 states, 19 states have (on average 1.9473684210526316) internal successors, (37), 19 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:34,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:34,125 INFO L93 Difference]: Finished difference Result 41 states and 44 transitions. [2021-11-09 09:33:34,126 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2021-11-09 09:33:34,126 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41 states and 44 transitions. [2021-11-09 09:33:34,127 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:34,127 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41 states to 41 states and 44 transitions. [2021-11-09 09:33:34,127 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:34,127 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:34,127 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41 states and 44 transitions. [2021-11-09 09:33:34,128 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:34,128 INFO L681 BuchiCegarLoop]: Abstraction has 41 states and 44 transitions. [2021-11-09 09:33:34,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states and 44 transitions. [2021-11-09 09:33:34,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 40. [2021-11-09 09:33:34,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40 states, 40 states have (on average 1.075) internal successors, (43), 39 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:34,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 43 transitions. [2021-11-09 09:33:34,131 INFO L704 BuchiCegarLoop]: Abstraction has 40 states and 43 transitions. [2021-11-09 09:33:34,131 INFO L587 BuchiCegarLoop]: Abstraction has 40 states and 43 transitions. [2021-11-09 09:33:34,131 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-09 09:33:34,131 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40 states and 43 transitions. [2021-11-09 09:33:34,132 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:34,132 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:34,132 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:34,133 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [16, 16, 1, 1, 1, 1] [2021-11-09 09:33:34,133 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:34,133 INFO L791 eck$LassoCheckResult]: Stem: 1974#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 1975#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 1981#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1982#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1983#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1978#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1979#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2013#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2012#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2011#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2010#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2009#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2008#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2007#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2006#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2005#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2004#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2003#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2002#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2001#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2000#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1999#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1998#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1997#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1996#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1995#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1994#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1993#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1992#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1991#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1990#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1989#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1988#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 1987#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 1986#L18-3 assume !(main_~i~0 < 1048); 1984#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 1980#L23-2 [2021-11-09 09:33:34,134 INFO L793 eck$LassoCheckResult]: Loop: 1980#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 1976#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 1977#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 1985#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 1980#L23-2 [2021-11-09 09:33:34,134 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:34,134 INFO L85 PathProgramCache]: Analyzing trace with hash -2091916245, now seen corresponding path program 16 times [2021-11-09 09:33:34,134 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:34,135 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1072958346] [2021-11-09 09:33:34,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:34,135 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:34,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:34,350 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:34,351 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:34,351 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1072958346] [2021-11-09 09:33:34,351 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1072958346] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:34,351 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2135035237] [2021-11-09 09:33:34,351 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:33:34,351 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:34,351 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:34,353 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:34,371 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2021-11-09 09:33:34,517 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:33:34,517 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:34,519 INFO L263 TraceCheckSpWp]: Trace formula consists of 155 conjuncts, 18 conjunts are in the unsatisfiable core [2021-11-09 09:33:34,520 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:34,646 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:34,647 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2135035237] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:34,647 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:34,647 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 20 [2021-11-09 09:33:34,647 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1680748856] [2021-11-09 09:33:34,648 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:34,648 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:34,648 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 17 times [2021-11-09 09:33:34,648 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:34,648 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [453491547] [2021-11-09 09:33:34,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:34,649 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:34,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:34,653 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:34,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:34,656 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:34,765 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:34,765 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2021-11-09 09:33:34,765 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2021-11-09 09:33:34,766 INFO L87 Difference]: Start difference. First operand 40 states and 43 transitions. cyclomatic complexity: 5 Second operand has 20 states, 20 states have (on average 1.95) internal successors, (39), 20 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:34,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:34,828 INFO L93 Difference]: Finished difference Result 43 states and 46 transitions. [2021-11-09 09:33:34,829 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2021-11-09 09:33:34,829 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 46 transitions. [2021-11-09 09:33:34,830 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:34,830 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 43 states and 46 transitions. [2021-11-09 09:33:34,830 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:34,831 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:34,831 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43 states and 46 transitions. [2021-11-09 09:33:34,831 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:34,831 INFO L681 BuchiCegarLoop]: Abstraction has 43 states and 46 transitions. [2021-11-09 09:33:34,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states and 46 transitions. [2021-11-09 09:33:34,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 42. [2021-11-09 09:33:34,833 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 42 states have (on average 1.0714285714285714) internal successors, (45), 41 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:34,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 45 transitions. [2021-11-09 09:33:34,834 INFO L704 BuchiCegarLoop]: Abstraction has 42 states and 45 transitions. [2021-11-09 09:33:34,834 INFO L587 BuchiCegarLoop]: Abstraction has 42 states and 45 transitions. [2021-11-09 09:33:34,834 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-09 09:33:34,834 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42 states and 45 transitions. [2021-11-09 09:33:34,835 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:34,835 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:34,835 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:34,836 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [17, 17, 1, 1, 1, 1] [2021-11-09 09:33:34,836 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:34,836 INFO L791 eck$LassoCheckResult]: Stem: 2187#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 2188#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 2192#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2193#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2194#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2189#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2190#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2226#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2225#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2224#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2223#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2222#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2221#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2220#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2219#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2218#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2217#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2216#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2215#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2214#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2213#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2212#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2211#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2210#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2209#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2208#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2207#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2206#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2205#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2204#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2203#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2202#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2201#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2200#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2199#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2198#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2197#L18-3 assume !(main_~i~0 < 1048); 2195#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 2191#L23-2 [2021-11-09 09:33:34,836 INFO L793 eck$LassoCheckResult]: Loop: 2191#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 2185#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 2186#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 2196#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 2191#L23-2 [2021-11-09 09:33:34,836 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:34,837 INFO L85 PathProgramCache]: Analyzing trace with hash -286760915, now seen corresponding path program 17 times [2021-11-09 09:33:34,837 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:34,837 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [84964655] [2021-11-09 09:33:34,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:34,837 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:34,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:35,095 INFO L134 CoverageAnalysis]: Checked inductivity of 289 backedges. 0 proven. 289 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:35,098 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:35,098 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [84964655] [2021-11-09 09:33:35,098 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [84964655] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:35,099 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [261061384] [2021-11-09 09:33:35,099 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:33:35,099 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:35,099 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:35,100 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:35,101 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2021-11-09 09:33:35,402 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2021-11-09 09:33:35,402 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:35,404 INFO L263 TraceCheckSpWp]: Trace formula consists of 163 conjuncts, 19 conjunts are in the unsatisfiable core [2021-11-09 09:33:35,406 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:35,572 INFO L134 CoverageAnalysis]: Checked inductivity of 289 backedges. 0 proven. 289 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:35,573 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [261061384] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:35,573 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:35,574 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 21 [2021-11-09 09:33:35,574 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1999595741] [2021-11-09 09:33:35,575 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:35,576 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:35,576 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 18 times [2021-11-09 09:33:35,576 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:35,576 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1435193992] [2021-11-09 09:33:35,577 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:35,577 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:35,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:35,583 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:35,585 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:35,589 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:35,681 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:35,682 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-11-09 09:33:35,682 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2021-11-09 09:33:35,682 INFO L87 Difference]: Start difference. First operand 42 states and 45 transitions. cyclomatic complexity: 5 Second operand has 21 states, 21 states have (on average 1.9523809523809523) internal successors, (41), 21 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:35,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:35,756 INFO L93 Difference]: Finished difference Result 45 states and 48 transitions. [2021-11-09 09:33:35,756 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2021-11-09 09:33:35,756 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45 states and 48 transitions. [2021-11-09 09:33:35,757 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:35,757 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45 states to 45 states and 48 transitions. [2021-11-09 09:33:35,758 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:35,758 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:35,758 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45 states and 48 transitions. [2021-11-09 09:33:35,758 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:35,758 INFO L681 BuchiCegarLoop]: Abstraction has 45 states and 48 transitions. [2021-11-09 09:33:35,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states and 48 transitions. [2021-11-09 09:33:35,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 44. [2021-11-09 09:33:35,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 44 states have (on average 1.0681818181818181) internal successors, (47), 43 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:35,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 47 transitions. [2021-11-09 09:33:35,762 INFO L704 BuchiCegarLoop]: Abstraction has 44 states and 47 transitions. [2021-11-09 09:33:35,762 INFO L587 BuchiCegarLoop]: Abstraction has 44 states and 47 transitions. [2021-11-09 09:33:35,762 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-09 09:33:35,762 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44 states and 47 transitions. [2021-11-09 09:33:35,763 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:35,763 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:35,763 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:35,764 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [18, 18, 1, 1, 1, 1] [2021-11-09 09:33:35,764 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:35,764 INFO L791 eck$LassoCheckResult]: Stem: 2409#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 2410#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 2414#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2415#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2416#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2411#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2412#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2450#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2449#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2448#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2447#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2446#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2445#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2444#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2443#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2442#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2441#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2440#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2439#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2438#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2437#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2436#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2435#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2434#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2433#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2432#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2431#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2430#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2429#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2428#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2427#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2426#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2425#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2424#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2423#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2422#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2421#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2420#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2419#L18-3 assume !(main_~i~0 < 1048); 2417#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 2413#L23-2 [2021-11-09 09:33:35,765 INFO L793 eck$LassoCheckResult]: Loop: 2413#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 2407#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 2408#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 2418#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 2413#L23-2 [2021-11-09 09:33:35,765 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:35,765 INFO L85 PathProgramCache]: Analyzing trace with hash -699276369, now seen corresponding path program 18 times [2021-11-09 09:33:35,765 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:35,766 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1876041051] [2021-11-09 09:33:35,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:35,766 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:35,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:36,064 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 0 proven. 324 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:36,064 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:36,064 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1876041051] [2021-11-09 09:33:36,064 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1876041051] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:36,064 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [660290176] [2021-11-09 09:33:36,064 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:33:36,064 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:36,064 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:36,066 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:36,067 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2021-11-09 09:33:36,536 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2021-11-09 09:33:36,536 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:36,538 INFO L263 TraceCheckSpWp]: Trace formula consists of 171 conjuncts, 20 conjunts are in the unsatisfiable core [2021-11-09 09:33:36,540 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:36,692 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 0 proven. 324 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:36,692 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [660290176] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:36,692 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:36,693 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 22 [2021-11-09 09:33:36,693 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074386820] [2021-11-09 09:33:36,693 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:36,694 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:36,694 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 19 times [2021-11-09 09:33:36,694 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:36,694 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1819289716] [2021-11-09 09:33:36,694 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:36,695 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:36,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:36,700 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:36,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:36,704 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:36,810 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:36,811 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2021-11-09 09:33:36,811 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2021-11-09 09:33:36,811 INFO L87 Difference]: Start difference. First operand 44 states and 47 transitions. cyclomatic complexity: 5 Second operand has 22 states, 22 states have (on average 1.9545454545454546) internal successors, (43), 22 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:36,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:36,888 INFO L93 Difference]: Finished difference Result 47 states and 50 transitions. [2021-11-09 09:33:36,888 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2021-11-09 09:33:36,889 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47 states and 50 transitions. [2021-11-09 09:33:36,889 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:36,890 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47 states to 47 states and 50 transitions. [2021-11-09 09:33:36,890 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:36,890 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:36,890 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 50 transitions. [2021-11-09 09:33:36,891 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:36,891 INFO L681 BuchiCegarLoop]: Abstraction has 47 states and 50 transitions. [2021-11-09 09:33:36,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 50 transitions. [2021-11-09 09:33:36,893 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 46. [2021-11-09 09:33:36,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46 states, 46 states have (on average 1.065217391304348) internal successors, (49), 45 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:36,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 49 transitions. [2021-11-09 09:33:36,894 INFO L704 BuchiCegarLoop]: Abstraction has 46 states and 49 transitions. [2021-11-09 09:33:36,894 INFO L587 BuchiCegarLoop]: Abstraction has 46 states and 49 transitions. [2021-11-09 09:33:36,894 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-09 09:33:36,894 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46 states and 49 transitions. [2021-11-09 09:33:36,895 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:36,895 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:36,895 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:36,895 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [19, 19, 1, 1, 1, 1] [2021-11-09 09:33:36,896 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:36,896 INFO L791 eck$LassoCheckResult]: Stem: 2642#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 2643#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 2647#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2648#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2649#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2644#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2645#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2685#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2684#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2683#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2682#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2681#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2680#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2679#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2678#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2677#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2676#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2675#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2674#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2673#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2672#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2671#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2670#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2669#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2668#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2667#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2666#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2665#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2664#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2663#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2662#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2661#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2660#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2659#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2658#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2657#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2656#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2655#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2654#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2653#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2652#L18-3 assume !(main_~i~0 < 1048); 2650#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 2646#L23-2 [2021-11-09 09:33:36,896 INFO L793 eck$LassoCheckResult]: Loop: 2646#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 2640#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 2641#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 2651#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 2646#L23-2 [2021-11-09 09:33:36,896 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:36,896 INFO L85 PathProgramCache]: Analyzing trace with hash -1989636431, now seen corresponding path program 19 times [2021-11-09 09:33:36,897 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:36,897 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [476338698] [2021-11-09 09:33:36,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:36,897 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:36,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:37,177 INFO L134 CoverageAnalysis]: Checked inductivity of 361 backedges. 0 proven. 361 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:37,177 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:37,178 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [476338698] [2021-11-09 09:33:37,178 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [476338698] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:37,178 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [369457489] [2021-11-09 09:33:37,178 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:33:37,178 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:37,178 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:37,180 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:37,181 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2021-11-09 09:33:37,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:37,427 INFO L263 TraceCheckSpWp]: Trace formula consists of 179 conjuncts, 21 conjunts are in the unsatisfiable core [2021-11-09 09:33:37,428 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:37,591 INFO L134 CoverageAnalysis]: Checked inductivity of 361 backedges. 0 proven. 361 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:37,592 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [369457489] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:37,592 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:37,592 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 23 [2021-11-09 09:33:37,593 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1891507286] [2021-11-09 09:33:37,593 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:37,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:37,594 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 20 times [2021-11-09 09:33:37,594 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:37,594 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1790471291] [2021-11-09 09:33:37,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:37,594 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:37,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:37,600 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:37,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:37,604 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:37,714 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:37,715 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2021-11-09 09:33:37,715 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=253, Unknown=0, NotChecked=0, Total=506 [2021-11-09 09:33:37,716 INFO L87 Difference]: Start difference. First operand 46 states and 49 transitions. cyclomatic complexity: 5 Second operand has 23 states, 23 states have (on average 1.9565217391304348) internal successors, (45), 23 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:37,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:37,790 INFO L93 Difference]: Finished difference Result 49 states and 52 transitions. [2021-11-09 09:33:37,791 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2021-11-09 09:33:37,791 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49 states and 52 transitions. [2021-11-09 09:33:37,792 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:37,792 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49 states to 49 states and 52 transitions. [2021-11-09 09:33:37,793 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:37,793 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:37,793 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49 states and 52 transitions. [2021-11-09 09:33:37,793 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:37,793 INFO L681 BuchiCegarLoop]: Abstraction has 49 states and 52 transitions. [2021-11-09 09:33:37,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states and 52 transitions. [2021-11-09 09:33:37,795 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 48. [2021-11-09 09:33:37,796 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48 states, 48 states have (on average 1.0625) internal successors, (51), 47 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:37,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 51 transitions. [2021-11-09 09:33:37,797 INFO L704 BuchiCegarLoop]: Abstraction has 48 states and 51 transitions. [2021-11-09 09:33:37,797 INFO L587 BuchiCegarLoop]: Abstraction has 48 states and 51 transitions. [2021-11-09 09:33:37,797 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-09 09:33:37,797 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48 states and 51 transitions. [2021-11-09 09:33:37,798 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:37,798 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:37,798 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:37,799 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [20, 20, 1, 1, 1, 1] [2021-11-09 09:33:37,799 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:37,799 INFO L791 eck$LassoCheckResult]: Stem: 2884#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 2885#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 2891#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2892#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2893#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2888#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2889#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2931#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2930#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2929#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2928#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2927#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2926#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2925#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2924#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2923#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2922#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2921#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2920#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2919#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2918#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2917#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2916#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2915#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2914#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2913#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2912#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2911#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2910#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2909#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2908#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2907#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2906#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2905#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2904#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2903#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2902#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2901#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2900#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2899#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2898#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 2897#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 2896#L18-3 assume !(main_~i~0 < 1048); 2894#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 2890#L23-2 [2021-11-09 09:33:37,799 INFO L793 eck$LassoCheckResult]: Loop: 2890#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 2886#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 2887#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 2895#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 2890#L23-2 [2021-11-09 09:33:37,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:37,800 INFO L85 PathProgramCache]: Analyzing trace with hash -780107469, now seen corresponding path program 20 times [2021-11-09 09:33:37,800 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:37,800 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [164067497] [2021-11-09 09:33:37,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:37,801 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:37,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:38,105 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 0 proven. 400 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:38,106 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:38,106 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [164067497] [2021-11-09 09:33:38,106 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [164067497] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:38,106 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1211357192] [2021-11-09 09:33:38,106 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:33:38,106 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:38,106 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:38,108 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:38,110 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2021-11-09 09:33:38,357 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:33:38,357 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:38,359 INFO L263 TraceCheckSpWp]: Trace formula consists of 187 conjuncts, 22 conjunts are in the unsatisfiable core [2021-11-09 09:33:38,360 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:38,523 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 0 proven. 400 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:38,523 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1211357192] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:38,523 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:38,523 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23] total 24 [2021-11-09 09:33:38,523 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [467911253] [2021-11-09 09:33:38,524 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:38,524 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:38,524 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 21 times [2021-11-09 09:33:38,524 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:38,526 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1598224253] [2021-11-09 09:33:38,526 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:38,526 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:38,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:38,530 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:38,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:38,533 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:38,629 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:38,629 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2021-11-09 09:33:38,630 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2021-11-09 09:33:38,630 INFO L87 Difference]: Start difference. First operand 48 states and 51 transitions. cyclomatic complexity: 5 Second operand has 24 states, 24 states have (on average 1.9583333333333333) internal successors, (47), 24 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:38,696 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:38,696 INFO L93 Difference]: Finished difference Result 51 states and 54 transitions. [2021-11-09 09:33:38,696 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2021-11-09 09:33:38,697 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51 states and 54 transitions. [2021-11-09 09:33:38,697 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:38,698 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51 states to 51 states and 54 transitions. [2021-11-09 09:33:38,698 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:38,698 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:38,698 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51 states and 54 transitions. [2021-11-09 09:33:38,698 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:38,698 INFO L681 BuchiCegarLoop]: Abstraction has 51 states and 54 transitions. [2021-11-09 09:33:38,698 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states and 54 transitions. [2021-11-09 09:33:38,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 50. [2021-11-09 09:33:38,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.06) internal successors, (53), 49 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:38,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 53 transitions. [2021-11-09 09:33:38,701 INFO L704 BuchiCegarLoop]: Abstraction has 50 states and 53 transitions. [2021-11-09 09:33:38,701 INFO L587 BuchiCegarLoop]: Abstraction has 50 states and 53 transitions. [2021-11-09 09:33:38,701 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-11-09 09:33:38,701 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50 states and 53 transitions. [2021-11-09 09:33:38,701 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:38,701 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:38,701 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:38,702 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [21, 21, 1, 1, 1, 1] [2021-11-09 09:33:38,702 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:38,702 INFO L791 eck$LassoCheckResult]: Stem: 3139#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 3140#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 3146#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3147#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3148#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3143#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3144#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3188#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3187#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3186#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3185#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3184#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3183#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3182#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3181#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3180#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3179#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3178#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3177#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3176#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3175#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3174#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3173#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3172#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3171#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3170#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3169#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3168#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3167#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3166#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3165#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3164#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3163#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3162#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3161#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3160#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3159#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3158#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3157#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3156#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3155#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3154#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3153#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3152#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3151#L18-3 assume !(main_~i~0 < 1048); 3149#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 3145#L23-2 [2021-11-09 09:33:38,702 INFO L793 eck$LassoCheckResult]: Loop: 3145#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 3141#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 3142#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 3150#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 3145#L23-2 [2021-11-09 09:33:38,702 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:38,703 INFO L85 PathProgramCache]: Analyzing trace with hash 1936055093, now seen corresponding path program 21 times [2021-11-09 09:33:38,703 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:38,703 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1749161777] [2021-11-09 09:33:38,703 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:38,703 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:38,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:38,983 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 0 proven. 441 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:38,984 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:38,984 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1749161777] [2021-11-09 09:33:38,984 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1749161777] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:38,984 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1907762728] [2021-11-09 09:33:38,984 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:33:38,984 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:38,984 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:38,985 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:38,987 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2021-11-09 09:33:39,902 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2021-11-09 09:33:39,903 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:39,907 INFO L263 TraceCheckSpWp]: Trace formula consists of 195 conjuncts, 23 conjunts are in the unsatisfiable core [2021-11-09 09:33:39,908 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:40,102 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 0 proven. 441 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:40,102 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1907762728] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:40,102 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:40,103 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 25 [2021-11-09 09:33:40,103 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [188277199] [2021-11-09 09:33:40,103 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:40,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:40,104 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 22 times [2021-11-09 09:33:40,104 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:40,104 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [549869414] [2021-11-09 09:33:40,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:40,105 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:40,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:40,110 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:40,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:40,113 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:40,222 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:40,223 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2021-11-09 09:33:40,224 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2021-11-09 09:33:40,224 INFO L87 Difference]: Start difference. First operand 50 states and 53 transitions. cyclomatic complexity: 5 Second operand has 25 states, 25 states have (on average 1.96) internal successors, (49), 25 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:40,303 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:40,303 INFO L93 Difference]: Finished difference Result 53 states and 56 transitions. [2021-11-09 09:33:40,304 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2021-11-09 09:33:40,304 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53 states and 56 transitions. [2021-11-09 09:33:40,305 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:40,306 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53 states to 53 states and 56 transitions. [2021-11-09 09:33:40,306 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:40,306 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:40,306 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53 states and 56 transitions. [2021-11-09 09:33:40,306 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:40,307 INFO L681 BuchiCegarLoop]: Abstraction has 53 states and 56 transitions. [2021-11-09 09:33:40,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states and 56 transitions. [2021-11-09 09:33:40,309 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 52. [2021-11-09 09:33:40,309 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.0576923076923077) internal successors, (55), 51 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:40,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 55 transitions. [2021-11-09 09:33:40,310 INFO L704 BuchiCegarLoop]: Abstraction has 52 states and 55 transitions. [2021-11-09 09:33:40,310 INFO L587 BuchiCegarLoop]: Abstraction has 52 states and 55 transitions. [2021-11-09 09:33:40,310 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-11-09 09:33:40,310 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 55 transitions. [2021-11-09 09:33:40,311 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:40,311 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:40,311 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:40,312 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [22, 22, 1, 1, 1, 1] [2021-11-09 09:33:40,312 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:40,312 INFO L791 eck$LassoCheckResult]: Stem: 3405#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 3406#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 3412#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3413#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3414#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3409#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3410#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3456#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3455#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3454#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3453#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3452#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3451#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3450#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3449#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3448#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3447#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3446#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3445#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3444#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3443#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3442#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3441#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3440#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3439#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3438#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3437#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3436#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3435#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3434#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3433#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3432#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3431#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3430#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3429#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3428#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3427#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3426#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3425#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3424#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3423#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3422#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3421#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3420#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3419#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3418#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3417#L18-3 assume !(main_~i~0 < 1048); 3415#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 3411#L23-2 [2021-11-09 09:33:40,313 INFO L793 eck$LassoCheckResult]: Loop: 3411#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 3407#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 3408#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 3416#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 3411#L23-2 [2021-11-09 09:33:40,313 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:40,313 INFO L85 PathProgramCache]: Analyzing trace with hash 828161207, now seen corresponding path program 22 times [2021-11-09 09:33:40,313 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:40,314 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [160181873] [2021-11-09 09:33:40,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:40,314 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:40,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:40,675 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:40,675 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:40,675 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [160181873] [2021-11-09 09:33:40,675 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [160181873] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:40,675 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1762539096] [2021-11-09 09:33:40,675 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:33:40,675 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:40,676 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:40,677 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:40,677 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2021-11-09 09:33:40,918 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:33:40,919 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:40,920 INFO L263 TraceCheckSpWp]: Trace formula consists of 203 conjuncts, 24 conjunts are in the unsatisfiable core [2021-11-09 09:33:40,922 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:41,080 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:41,080 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1762539096] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:41,080 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:41,080 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 26 [2021-11-09 09:33:41,080 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1425724842] [2021-11-09 09:33:41,081 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:41,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:41,081 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 23 times [2021-11-09 09:33:41,081 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:41,081 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [90417179] [2021-11-09 09:33:41,081 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:41,081 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:41,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:41,086 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:41,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:41,089 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:41,263 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:41,264 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2021-11-09 09:33:41,265 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2021-11-09 09:33:41,265 INFO L87 Difference]: Start difference. First operand 52 states and 55 transitions. cyclomatic complexity: 5 Second operand has 26 states, 26 states have (on average 1.9615384615384615) internal successors, (51), 26 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:41,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:41,369 INFO L93 Difference]: Finished difference Result 55 states and 58 transitions. [2021-11-09 09:33:41,369 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2021-11-09 09:33:41,370 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55 states and 58 transitions. [2021-11-09 09:33:41,370 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:41,371 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55 states to 55 states and 58 transitions. [2021-11-09 09:33:41,371 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:41,372 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:41,372 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55 states and 58 transitions. [2021-11-09 09:33:41,372 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:41,372 INFO L681 BuchiCegarLoop]: Abstraction has 55 states and 58 transitions. [2021-11-09 09:33:41,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states and 58 transitions. [2021-11-09 09:33:41,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 54. [2021-11-09 09:33:41,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54 states, 54 states have (on average 1.0555555555555556) internal successors, (57), 53 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:41,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 57 transitions. [2021-11-09 09:33:41,375 INFO L704 BuchiCegarLoop]: Abstraction has 54 states and 57 transitions. [2021-11-09 09:33:41,375 INFO L587 BuchiCegarLoop]: Abstraction has 54 states and 57 transitions. [2021-11-09 09:33:41,375 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-11-09 09:33:41,375 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54 states and 57 transitions. [2021-11-09 09:33:41,375 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:41,376 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:41,376 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:41,376 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [23, 23, 1, 1, 1, 1] [2021-11-09 09:33:41,376 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:41,377 INFO L791 eck$LassoCheckResult]: Stem: 3682#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 3683#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 3689#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3690#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3691#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3686#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3687#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3735#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3734#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3733#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3732#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3731#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3730#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3729#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3728#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3727#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3726#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3725#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3724#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3723#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3722#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3721#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3720#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3719#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3718#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3717#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3716#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3715#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3714#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3713#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3712#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3711#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3710#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3709#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3708#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3707#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3706#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3705#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3704#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3703#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3702#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3701#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3700#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3699#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3698#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3697#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3696#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3695#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3694#L18-3 assume !(main_~i~0 < 1048); 3692#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 3688#L23-2 [2021-11-09 09:33:41,377 INFO L793 eck$LassoCheckResult]: Loop: 3688#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 3684#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 3685#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 3693#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 3688#L23-2 [2021-11-09 09:33:41,377 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:41,377 INFO L85 PathProgramCache]: Analyzing trace with hash 1294026169, now seen corresponding path program 23 times [2021-11-09 09:33:41,377 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:41,377 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1859796935] [2021-11-09 09:33:41,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:41,378 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:41,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:41,802 INFO L134 CoverageAnalysis]: Checked inductivity of 529 backedges. 0 proven. 529 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:41,803 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:41,803 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1859796935] [2021-11-09 09:33:41,803 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1859796935] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:41,803 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1068686710] [2021-11-09 09:33:41,803 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:33:41,803 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:41,804 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:41,806 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:41,811 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2021-11-09 09:33:42,425 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2021-11-09 09:33:42,425 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:42,428 INFO L263 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 25 conjunts are in the unsatisfiable core [2021-11-09 09:33:42,431 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:42,628 INFO L134 CoverageAnalysis]: Checked inductivity of 529 backedges. 0 proven. 529 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:42,628 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1068686710] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:42,628 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:42,628 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26] total 27 [2021-11-09 09:33:42,629 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1920002721] [2021-11-09 09:33:42,629 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:42,629 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:42,630 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 24 times [2021-11-09 09:33:42,630 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:42,630 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1572993933] [2021-11-09 09:33:42,630 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:42,630 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:42,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:42,656 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:42,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:42,660 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:42,758 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:42,759 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2021-11-09 09:33:42,759 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2021-11-09 09:33:42,760 INFO L87 Difference]: Start difference. First operand 54 states and 57 transitions. cyclomatic complexity: 5 Second operand has 27 states, 27 states have (on average 1.962962962962963) internal successors, (53), 27 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:42,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:42,853 INFO L93 Difference]: Finished difference Result 57 states and 60 transitions. [2021-11-09 09:33:42,854 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2021-11-09 09:33:42,854 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57 states and 60 transitions. [2021-11-09 09:33:42,854 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:42,855 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57 states to 57 states and 60 transitions. [2021-11-09 09:33:42,855 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:42,855 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:42,855 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57 states and 60 transitions. [2021-11-09 09:33:42,855 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:42,856 INFO L681 BuchiCegarLoop]: Abstraction has 57 states and 60 transitions. [2021-11-09 09:33:42,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states and 60 transitions. [2021-11-09 09:33:42,857 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 56. [2021-11-09 09:33:42,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56 states, 56 states have (on average 1.0535714285714286) internal successors, (59), 55 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:42,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 59 transitions. [2021-11-09 09:33:42,858 INFO L704 BuchiCegarLoop]: Abstraction has 56 states and 59 transitions. [2021-11-09 09:33:42,859 INFO L587 BuchiCegarLoop]: Abstraction has 56 states and 59 transitions. [2021-11-09 09:33:42,859 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-11-09 09:33:42,859 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 56 states and 59 transitions. [2021-11-09 09:33:42,860 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:42,860 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:42,860 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:42,861 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [24, 24, 1, 1, 1, 1] [2021-11-09 09:33:42,861 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:42,861 INFO L791 eck$LassoCheckResult]: Stem: 3970#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 3971#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 3977#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3978#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3979#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3974#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3975#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4025#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4024#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4023#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4022#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4021#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4020#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4019#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4018#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4017#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4016#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4015#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4014#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4013#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4012#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4011#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4010#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4009#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4008#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4007#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4006#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4005#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4004#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4003#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4002#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4001#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4000#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3999#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3998#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3997#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3996#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3995#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3994#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3993#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3992#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3991#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3990#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3989#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3988#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3987#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3986#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3985#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3984#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 3983#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 3982#L18-3 assume !(main_~i~0 < 1048); 3980#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 3976#L23-2 [2021-11-09 09:33:42,861 INFO L793 eck$LassoCheckResult]: Loop: 3976#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 3972#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 3973#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 3981#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 3976#L23-2 [2021-11-09 09:33:42,862 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:42,862 INFO L85 PathProgramCache]: Analyzing trace with hash -1981311429, now seen corresponding path program 24 times [2021-11-09 09:33:42,862 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:42,862 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1631858185] [2021-11-09 09:33:42,863 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:42,863 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:42,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:43,230 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 576 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:43,231 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:43,231 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1631858185] [2021-11-09 09:33:43,231 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1631858185] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:43,232 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [417408438] [2021-11-09 09:33:43,232 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:33:43,232 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:43,232 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:43,234 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:43,236 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2021-11-09 09:33:45,205 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) [2021-11-09 09:33:45,206 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:45,212 INFO L263 TraceCheckSpWp]: Trace formula consists of 219 conjuncts, 26 conjunts are in the unsatisfiable core [2021-11-09 09:33:45,213 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:45,430 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 576 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:45,431 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [417408438] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:45,431 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:45,431 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27] total 28 [2021-11-09 09:33:45,432 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1637362298] [2021-11-09 09:33:45,432 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:45,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:45,433 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 25 times [2021-11-09 09:33:45,433 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:45,433 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [368595611] [2021-11-09 09:33:45,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:45,433 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:45,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:45,440 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:45,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:45,449 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:45,554 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:45,554 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2021-11-09 09:33:45,555 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2021-11-09 09:33:45,555 INFO L87 Difference]: Start difference. First operand 56 states and 59 transitions. cyclomatic complexity: 5 Second operand has 28 states, 28 states have (on average 1.9642857142857142) internal successors, (55), 28 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:45,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:45,650 INFO L93 Difference]: Finished difference Result 59 states and 62 transitions. [2021-11-09 09:33:45,650 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2021-11-09 09:33:45,650 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59 states and 62 transitions. [2021-11-09 09:33:45,651 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:45,652 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59 states to 59 states and 62 transitions. [2021-11-09 09:33:45,652 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:45,652 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:45,652 INFO L73 IsDeterministic]: Start isDeterministic. Operand 59 states and 62 transitions. [2021-11-09 09:33:45,652 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:45,652 INFO L681 BuchiCegarLoop]: Abstraction has 59 states and 62 transitions. [2021-11-09 09:33:45,652 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states and 62 transitions. [2021-11-09 09:33:45,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 58. [2021-11-09 09:33:45,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 58 states, 58 states have (on average 1.0517241379310345) internal successors, (61), 57 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:45,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 61 transitions. [2021-11-09 09:33:45,654 INFO L704 BuchiCegarLoop]: Abstraction has 58 states and 61 transitions. [2021-11-09 09:33:45,654 INFO L587 BuchiCegarLoop]: Abstraction has 58 states and 61 transitions. [2021-11-09 09:33:45,654 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-11-09 09:33:45,655 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 58 states and 61 transitions. [2021-11-09 09:33:45,655 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:45,655 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:45,655 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:45,656 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [25, 25, 1, 1, 1, 1] [2021-11-09 09:33:45,656 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:45,656 INFO L791 eck$LassoCheckResult]: Stem: 4271#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 4272#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 4276#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4277#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4278#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4273#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4274#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4326#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4325#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4324#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4323#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4322#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4321#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4320#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4319#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4318#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4317#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4316#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4315#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4314#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4313#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4312#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4311#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4310#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4309#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4308#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4307#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4306#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4305#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4304#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4303#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4302#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4301#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4300#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4299#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4298#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4297#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4296#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4295#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4294#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4293#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4292#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4291#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4290#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4289#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4288#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4287#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4286#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4285#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4284#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4283#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4282#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4281#L18-3 assume !(main_~i~0 < 1048); 4279#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 4275#L23-2 [2021-11-09 09:33:45,656 INFO L793 eck$LassoCheckResult]: Loop: 4275#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 4269#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 4270#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 4280#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 4275#L23-2 [2021-11-09 09:33:45,656 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:45,657 INFO L85 PathProgramCache]: Analyzing trace with hash -1369715139, now seen corresponding path program 25 times [2021-11-09 09:33:45,657 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:45,658 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [839111494] [2021-11-09 09:33:45,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:45,658 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:45,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:46,037 INFO L134 CoverageAnalysis]: Checked inductivity of 625 backedges. 0 proven. 625 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:46,037 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:46,037 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [839111494] [2021-11-09 09:33:46,038 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [839111494] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:46,038 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1518301742] [2021-11-09 09:33:46,038 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:33:46,038 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:46,038 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:46,040 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:46,099 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2021-11-09 09:33:46,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:46,497 INFO L263 TraceCheckSpWp]: Trace formula consists of 227 conjuncts, 27 conjunts are in the unsatisfiable core [2021-11-09 09:33:46,498 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:46,714 INFO L134 CoverageAnalysis]: Checked inductivity of 625 backedges. 0 proven. 625 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:46,714 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1518301742] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:46,714 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:46,714 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28] total 29 [2021-11-09 09:33:46,714 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1810325906] [2021-11-09 09:33:46,715 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:46,716 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:46,716 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 26 times [2021-11-09 09:33:46,716 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:46,716 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135167147] [2021-11-09 09:33:46,716 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:46,716 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:46,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:46,721 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:46,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:46,724 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:46,832 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:46,832 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2021-11-09 09:33:46,833 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2021-11-09 09:33:46,833 INFO L87 Difference]: Start difference. First operand 58 states and 61 transitions. cyclomatic complexity: 5 Second operand has 29 states, 29 states have (on average 1.9655172413793103) internal successors, (57), 29 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:46,924 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:46,924 INFO L93 Difference]: Finished difference Result 61 states and 64 transitions. [2021-11-09 09:33:46,924 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2021-11-09 09:33:46,925 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61 states and 64 transitions. [2021-11-09 09:33:46,925 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:46,926 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61 states to 61 states and 64 transitions. [2021-11-09 09:33:46,926 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:46,927 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:46,927 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61 states and 64 transitions. [2021-11-09 09:33:46,927 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:46,927 INFO L681 BuchiCegarLoop]: Abstraction has 61 states and 64 transitions. [2021-11-09 09:33:46,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states and 64 transitions. [2021-11-09 09:33:46,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 60. [2021-11-09 09:33:46,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 60 states have (on average 1.05) internal successors, (63), 59 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:46,929 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 63 transitions. [2021-11-09 09:33:46,929 INFO L704 BuchiCegarLoop]: Abstraction has 60 states and 63 transitions. [2021-11-09 09:33:46,929 INFO L587 BuchiCegarLoop]: Abstraction has 60 states and 63 transitions. [2021-11-09 09:33:46,929 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-11-09 09:33:46,929 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60 states and 63 transitions. [2021-11-09 09:33:46,930 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:46,930 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:46,930 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:46,931 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [26, 26, 1, 1, 1, 1] [2021-11-09 09:33:46,931 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:46,931 INFO L791 eck$LassoCheckResult]: Stem: 4579#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 4580#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 4586#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4587#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4588#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4583#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4584#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4638#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4637#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4636#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4635#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4634#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4633#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4632#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4631#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4630#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4629#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4628#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4627#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4626#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4625#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4624#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4623#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4622#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4621#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4620#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4619#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4618#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4617#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4616#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4615#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4614#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4613#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4612#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4611#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4610#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4609#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4608#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4607#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4606#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4605#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4604#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4603#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4602#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4601#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4600#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4599#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4598#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4597#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4596#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4595#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4594#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4593#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4592#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4591#L18-3 assume !(main_~i~0 < 1048); 4589#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 4585#L23-2 [2021-11-09 09:33:46,932 INFO L793 eck$LassoCheckResult]: Loop: 4585#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 4581#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 4582#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 4590#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 4585#L23-2 [2021-11-09 09:33:46,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:46,932 INFO L85 PathProgramCache]: Analyzing trace with hash -2036200001, now seen corresponding path program 26 times [2021-11-09 09:33:46,932 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:46,932 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1137258715] [2021-11-09 09:33:46,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:46,933 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:46,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:47,430 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 0 proven. 676 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:47,431 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:47,431 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1137258715] [2021-11-09 09:33:47,431 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1137258715] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:47,431 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2116049695] [2021-11-09 09:33:47,431 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:33:47,432 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:47,432 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:47,433 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:47,434 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2021-11-09 09:33:47,783 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:33:47,784 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:47,785 INFO L263 TraceCheckSpWp]: Trace formula consists of 235 conjuncts, 28 conjunts are in the unsatisfiable core [2021-11-09 09:33:47,787 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:48,016 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 0 proven. 676 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:48,016 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2116049695] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:48,016 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:48,017 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29] total 30 [2021-11-09 09:33:48,017 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1274637862] [2021-11-09 09:33:48,017 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:48,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:48,017 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 27 times [2021-11-09 09:33:48,017 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:48,018 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1791187851] [2021-11-09 09:33:48,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:48,018 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:48,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:48,022 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:48,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:48,025 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:48,121 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:48,122 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2021-11-09 09:33:48,122 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2021-11-09 09:33:48,122 INFO L87 Difference]: Start difference. First operand 60 states and 63 transitions. cyclomatic complexity: 5 Second operand has 30 states, 30 states have (on average 1.9666666666666666) internal successors, (59), 30 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:48,244 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:48,244 INFO L93 Difference]: Finished difference Result 63 states and 66 transitions. [2021-11-09 09:33:48,245 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2021-11-09 09:33:48,245 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63 states and 66 transitions. [2021-11-09 09:33:48,246 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:48,246 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63 states to 63 states and 66 transitions. [2021-11-09 09:33:48,247 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:48,247 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:48,247 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63 states and 66 transitions. [2021-11-09 09:33:48,247 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:48,247 INFO L681 BuchiCegarLoop]: Abstraction has 63 states and 66 transitions. [2021-11-09 09:33:48,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states and 66 transitions. [2021-11-09 09:33:48,248 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 62. [2021-11-09 09:33:48,249 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62 states, 62 states have (on average 1.0483870967741935) internal successors, (65), 61 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:48,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 65 transitions. [2021-11-09 09:33:48,249 INFO L704 BuchiCegarLoop]: Abstraction has 62 states and 65 transitions. [2021-11-09 09:33:48,250 INFO L587 BuchiCegarLoop]: Abstraction has 62 states and 65 transitions. [2021-11-09 09:33:48,250 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-11-09 09:33:48,250 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62 states and 65 transitions. [2021-11-09 09:33:48,250 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:48,251 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:48,251 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:48,251 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [27, 27, 1, 1, 1, 1] [2021-11-09 09:33:48,251 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:48,252 INFO L791 eck$LassoCheckResult]: Stem: 4902#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 4903#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 4907#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4908#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4909#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4904#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4905#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4961#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4960#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4959#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4958#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4957#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4956#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4955#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4954#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4953#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4952#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4951#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4950#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4949#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4948#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4947#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4946#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4945#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4944#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4943#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4942#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4941#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4940#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4939#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4938#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4937#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4936#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4935#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4934#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4933#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4932#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4931#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4930#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4929#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4928#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4927#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4926#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4925#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4924#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4923#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4922#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4921#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4920#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4919#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4918#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4917#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4916#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4915#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4914#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 4913#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 4912#L18-3 assume !(main_~i~0 < 1048); 4910#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 4906#L23-2 [2021-11-09 09:33:48,252 INFO L793 eck$LassoCheckResult]: Loop: 4906#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 4900#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 4901#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 4911#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 4906#L23-2 [2021-11-09 09:33:48,252 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:48,252 INFO L85 PathProgramCache]: Analyzing trace with hash 1716942017, now seen corresponding path program 27 times [2021-11-09 09:33:48,253 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:48,253 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [546089144] [2021-11-09 09:33:48,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:48,253 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:48,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:48,902 INFO L134 CoverageAnalysis]: Checked inductivity of 729 backedges. 0 proven. 729 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:48,902 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:48,902 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [546089144] [2021-11-09 09:33:48,903 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [546089144] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:48,903 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [295715604] [2021-11-09 09:33:48,903 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:33:48,903 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:48,903 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:48,913 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:48,935 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2021-11-09 09:33:50,385 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2021-11-09 09:33:50,385 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:50,390 INFO L263 TraceCheckSpWp]: Trace formula consists of 243 conjuncts, 29 conjunts are in the unsatisfiable core [2021-11-09 09:33:50,393 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:50,600 INFO L134 CoverageAnalysis]: Checked inductivity of 729 backedges. 0 proven. 729 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:50,602 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [295715604] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:50,602 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:50,603 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 31 [2021-11-09 09:33:50,603 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [340456211] [2021-11-09 09:33:50,603 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:50,603 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:50,603 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 28 times [2021-11-09 09:33:50,604 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:50,604 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1992887605] [2021-11-09 09:33:50,604 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:50,604 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:50,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:50,610 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:50,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:50,613 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:50,695 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:50,695 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2021-11-09 09:33:50,696 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2021-11-09 09:33:50,696 INFO L87 Difference]: Start difference. First operand 62 states and 65 transitions. cyclomatic complexity: 5 Second operand has 31 states, 31 states have (on average 1.967741935483871) internal successors, (61), 31 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:50,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:50,778 INFO L93 Difference]: Finished difference Result 65 states and 68 transitions. [2021-11-09 09:33:50,779 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2021-11-09 09:33:50,779 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65 states and 68 transitions. [2021-11-09 09:33:50,779 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:50,780 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65 states to 65 states and 68 transitions. [2021-11-09 09:33:50,780 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:50,780 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:50,780 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65 states and 68 transitions. [2021-11-09 09:33:50,780 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:50,781 INFO L681 BuchiCegarLoop]: Abstraction has 65 states and 68 transitions. [2021-11-09 09:33:50,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states and 68 transitions. [2021-11-09 09:33:50,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 64. [2021-11-09 09:33:50,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64 states, 64 states have (on average 1.046875) internal successors, (67), 63 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:50,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 67 transitions. [2021-11-09 09:33:50,782 INFO L704 BuchiCegarLoop]: Abstraction has 64 states and 67 transitions. [2021-11-09 09:33:50,782 INFO L587 BuchiCegarLoop]: Abstraction has 64 states and 67 transitions. [2021-11-09 09:33:50,782 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-11-09 09:33:50,782 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64 states and 67 transitions. [2021-11-09 09:33:50,783 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:50,783 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:50,783 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:50,784 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [28, 28, 1, 1, 1, 1] [2021-11-09 09:33:50,784 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:50,784 INFO L791 eck$LassoCheckResult]: Stem: 5232#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 5233#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 5239#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5240#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5241#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5236#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5237#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5295#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5294#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5293#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5292#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5291#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5290#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5289#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5288#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5287#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5286#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5285#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5284#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5283#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5282#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5281#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5280#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5279#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5278#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5277#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5276#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5275#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5274#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5273#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5272#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5271#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5270#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5269#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5268#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5267#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5266#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5265#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5264#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5263#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5262#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5261#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5260#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5259#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5258#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5257#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5256#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5255#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5254#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5253#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5252#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5251#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5250#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5249#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5248#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5247#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5246#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5245#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5244#L18-3 assume !(main_~i~0 < 1048); 5242#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 5238#L23-2 [2021-11-09 09:33:50,784 INFO L793 eck$LassoCheckResult]: Loop: 5238#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 5234#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 5235#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 5243#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 5238#L23-2 [2021-11-09 09:33:50,784 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:50,784 INFO L85 PathProgramCache]: Analyzing trace with hash 713892675, now seen corresponding path program 28 times [2021-11-09 09:33:50,785 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:50,785 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [794617309] [2021-11-09 09:33:50,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:50,785 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:50,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:51,258 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 0 proven. 784 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:51,258 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:51,258 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [794617309] [2021-11-09 09:33:51,258 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [794617309] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:51,258 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1070112493] [2021-11-09 09:33:51,258 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:33:51,259 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:51,259 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:51,260 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:51,261 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2021-11-09 09:33:51,641 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:33:51,641 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:51,642 INFO L263 TraceCheckSpWp]: Trace formula consists of 251 conjuncts, 30 conjunts are in the unsatisfiable core [2021-11-09 09:33:51,644 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:51,890 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 0 proven. 784 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:51,890 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1070112493] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:51,890 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:51,890 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31] total 32 [2021-11-09 09:33:51,890 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [54663119] [2021-11-09 09:33:51,891 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:51,891 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:51,891 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 29 times [2021-11-09 09:33:51,891 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:51,891 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [313337840] [2021-11-09 09:33:51,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:51,891 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:51,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:51,897 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:51,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:51,900 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:52,012 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:52,013 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2021-11-09 09:33:52,014 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2021-11-09 09:33:52,014 INFO L87 Difference]: Start difference. First operand 64 states and 67 transitions. cyclomatic complexity: 5 Second operand has 32 states, 32 states have (on average 1.96875) internal successors, (63), 32 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:52,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:52,089 INFO L93 Difference]: Finished difference Result 67 states and 70 transitions. [2021-11-09 09:33:52,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2021-11-09 09:33:52,089 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67 states and 70 transitions. [2021-11-09 09:33:52,090 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:52,091 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67 states to 67 states and 70 transitions. [2021-11-09 09:33:52,091 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:52,091 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:52,092 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67 states and 70 transitions. [2021-11-09 09:33:52,092 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:52,092 INFO L681 BuchiCegarLoop]: Abstraction has 67 states and 70 transitions. [2021-11-09 09:33:52,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states and 70 transitions. [2021-11-09 09:33:52,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 66. [2021-11-09 09:33:52,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 66 states have (on average 1.0454545454545454) internal successors, (69), 65 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:52,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 69 transitions. [2021-11-09 09:33:52,094 INFO L704 BuchiCegarLoop]: Abstraction has 66 states and 69 transitions. [2021-11-09 09:33:52,094 INFO L587 BuchiCegarLoop]: Abstraction has 66 states and 69 transitions. [2021-11-09 09:33:52,095 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-11-09 09:33:52,095 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66 states and 69 transitions. [2021-11-09 09:33:52,095 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:52,096 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:52,096 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:52,097 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [29, 29, 1, 1, 1, 1] [2021-11-09 09:33:52,097 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:52,097 INFO L791 eck$LassoCheckResult]: Stem: 5575#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 5576#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 5582#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5583#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5584#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5579#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5580#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5640#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5639#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5638#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5637#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5636#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5635#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5634#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5633#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5632#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5631#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5630#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5629#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5628#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5627#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5626#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5625#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5624#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5623#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5622#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5621#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5620#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5619#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5618#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5617#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5616#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5615#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5614#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5613#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5612#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5611#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5610#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5609#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5608#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5607#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5606#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5605#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5604#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5603#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5602#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5601#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5600#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5599#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5598#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5597#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5596#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5595#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5594#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5593#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5592#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5591#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5590#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5589#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5588#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5587#L18-3 assume !(main_~i~0 < 1048); 5585#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 5581#L23-2 [2021-11-09 09:33:52,097 INFO L793 eck$LassoCheckResult]: Loop: 5581#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 5577#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 5578#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 5586#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 5581#L23-2 [2021-11-09 09:33:52,098 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:52,098 INFO L85 PathProgramCache]: Analyzing trace with hash -1143850683, now seen corresponding path program 29 times [2021-11-09 09:33:52,098 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:52,098 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [322848344] [2021-11-09 09:33:52,098 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:52,099 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:52,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:52,690 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 841 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:52,691 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:52,691 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [322848344] [2021-11-09 09:33:52,691 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [322848344] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:52,691 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2077527104] [2021-11-09 09:33:52,691 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:33:52,691 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:52,692 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:52,697 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:52,715 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2021-11-09 09:33:54,035 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 30 check-sat command(s) [2021-11-09 09:33:54,035 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:54,041 INFO L263 TraceCheckSpWp]: Trace formula consists of 259 conjuncts, 31 conjunts are in the unsatisfiable core [2021-11-09 09:33:54,044 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:54,284 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 841 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:54,285 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2077527104] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:54,285 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:54,285 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32] total 33 [2021-11-09 09:33:54,285 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1199018417] [2021-11-09 09:33:54,286 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:33:54,286 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:54,286 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 30 times [2021-11-09 09:33:54,286 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:54,287 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1682638648] [2021-11-09 09:33:54,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:54,287 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:54,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:54,305 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:54,308 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:54,309 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:54,412 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:54,413 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2021-11-09 09:33:54,414 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2021-11-09 09:33:54,414 INFO L87 Difference]: Start difference. First operand 66 states and 69 transitions. cyclomatic complexity: 5 Second operand has 33 states, 33 states have (on average 1.9696969696969697) internal successors, (65), 33 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:54,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:54,527 INFO L93 Difference]: Finished difference Result 69 states and 72 transitions. [2021-11-09 09:33:54,528 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2021-11-09 09:33:54,528 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69 states and 72 transitions. [2021-11-09 09:33:54,529 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:54,529 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69 states to 69 states and 72 transitions. [2021-11-09 09:33:54,529 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:54,529 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:54,529 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69 states and 72 transitions. [2021-11-09 09:33:54,530 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:54,530 INFO L681 BuchiCegarLoop]: Abstraction has 69 states and 72 transitions. [2021-11-09 09:33:54,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states and 72 transitions. [2021-11-09 09:33:54,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 68. [2021-11-09 09:33:54,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.0441176470588236) internal successors, (71), 67 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:54,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 71 transitions. [2021-11-09 09:33:54,532 INFO L704 BuchiCegarLoop]: Abstraction has 68 states and 71 transitions. [2021-11-09 09:33:54,532 INFO L587 BuchiCegarLoop]: Abstraction has 68 states and 71 transitions. [2021-11-09 09:33:54,532 INFO L425 BuchiCegarLoop]: ======== Iteration 32============ [2021-11-09 09:33:54,533 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 71 transitions. [2021-11-09 09:33:54,533 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:54,534 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:54,534 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:54,535 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [30, 30, 1, 1, 1, 1] [2021-11-09 09:33:54,535 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:54,535 INFO L791 eck$LassoCheckResult]: Stem: 5931#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 5932#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 5936#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5937#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5938#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5933#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5934#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5996#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5995#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5994#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5993#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5992#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5991#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5990#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5989#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5988#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5987#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5986#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5985#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5984#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5983#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5982#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5981#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5980#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5979#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5978#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5977#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5976#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5975#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5974#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5973#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5972#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5971#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5970#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5969#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5968#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5967#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5966#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5965#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5964#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5963#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5962#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5961#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5960#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5959#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5958#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5957#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5956#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5955#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5954#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5953#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5952#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5951#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5950#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5949#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5948#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5947#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5946#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5945#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5944#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5943#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 5942#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 5941#L18-3 assume !(main_~i~0 < 1048); 5939#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 5935#L23-2 [2021-11-09 09:33:54,535 INFO L793 eck$LassoCheckResult]: Loop: 5935#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 5929#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 5930#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 5940#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 5935#L23-2 [2021-11-09 09:33:54,535 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:54,536 INFO L85 PathProgramCache]: Analyzing trace with hash 271177415, now seen corresponding path program 30 times [2021-11-09 09:33:54,536 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:54,536 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2018647866] [2021-11-09 09:33:54,536 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:54,536 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:54,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:55,132 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 0 proven. 900 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:55,132 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:55,132 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2018647866] [2021-11-09 09:33:55,132 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2018647866] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:55,132 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [558318327] [2021-11-09 09:33:55,132 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:33:55,133 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:55,133 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:55,135 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:55,154 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2021-11-09 09:34:05,997 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 31 check-sat command(s) [2021-11-09 09:34:05,997 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:06,018 INFO L263 TraceCheckSpWp]: Trace formula consists of 267 conjuncts, 32 conjunts are in the unsatisfiable core [2021-11-09 09:34:06,020 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:06,255 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 0 proven. 900 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:06,255 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [558318327] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:06,255 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:06,255 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 34 [2021-11-09 09:34:06,255 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1772010965] [2021-11-09 09:34:06,256 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:34:06,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:06,256 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 31 times [2021-11-09 09:34:06,256 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:06,256 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1676553651] [2021-11-09 09:34:06,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:06,257 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:06,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:06,262 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:06,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:06,265 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:06,375 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:06,375 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2021-11-09 09:34:06,376 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2021-11-09 09:34:06,376 INFO L87 Difference]: Start difference. First operand 68 states and 71 transitions. cyclomatic complexity: 5 Second operand has 34 states, 34 states have (on average 1.9705882352941178) internal successors, (67), 34 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:06,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:06,494 INFO L93 Difference]: Finished difference Result 71 states and 74 transitions. [2021-11-09 09:34:06,494 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2021-11-09 09:34:06,494 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71 states and 74 transitions. [2021-11-09 09:34:06,495 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:34:06,496 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71 states to 71 states and 74 transitions. [2021-11-09 09:34:06,496 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:34:06,496 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:34:06,496 INFO L73 IsDeterministic]: Start isDeterministic. Operand 71 states and 74 transitions. [2021-11-09 09:34:06,496 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:06,497 INFO L681 BuchiCegarLoop]: Abstraction has 71 states and 74 transitions. [2021-11-09 09:34:06,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states and 74 transitions. [2021-11-09 09:34:06,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 70. [2021-11-09 09:34:06,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 70 states, 70 states have (on average 1.042857142857143) internal successors, (73), 69 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:06,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 73 transitions. [2021-11-09 09:34:06,499 INFO L704 BuchiCegarLoop]: Abstraction has 70 states and 73 transitions. [2021-11-09 09:34:06,499 INFO L587 BuchiCegarLoop]: Abstraction has 70 states and 73 transitions. [2021-11-09 09:34:06,499 INFO L425 BuchiCegarLoop]: ======== Iteration 33============ [2021-11-09 09:34:06,500 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 70 states and 73 transitions. [2021-11-09 09:34:06,500 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:34:06,500 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:06,501 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:06,501 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [31, 31, 1, 1, 1, 1] [2021-11-09 09:34:06,502 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:34:06,502 INFO L791 eck$LassoCheckResult]: Stem: 6296#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 6297#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 6301#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6302#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6303#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6298#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6299#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6363#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6362#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6361#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6360#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6359#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6358#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6357#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6356#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6355#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6354#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6353#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6352#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6351#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6350#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6349#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6348#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6347#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6346#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6345#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6344#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6343#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6342#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6341#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6340#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6339#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6338#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6337#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6336#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6335#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6334#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6333#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6332#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6331#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6330#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6329#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6328#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6327#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6326#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6325#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6324#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6323#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6322#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6321#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6320#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6319#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6318#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6317#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6316#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6315#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6314#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6313#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6312#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6311#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6310#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6309#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6308#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6307#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6306#L18-3 assume !(main_~i~0 < 1048); 6304#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 6300#L23-2 [2021-11-09 09:34:06,502 INFO L793 eck$LassoCheckResult]: Loop: 6300#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 6294#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 6295#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 6305#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 6300#L23-2 [2021-11-09 09:34:06,503 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:06,503 INFO L85 PathProgramCache]: Analyzing trace with hash -1391453239, now seen corresponding path program 31 times [2021-11-09 09:34:06,503 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:06,504 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [307477024] [2021-11-09 09:34:06,504 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:06,504 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:06,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:07,117 INFO L134 CoverageAnalysis]: Checked inductivity of 961 backedges. 0 proven. 961 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:07,118 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:07,118 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [307477024] [2021-11-09 09:34:07,118 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [307477024] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:07,118 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [927578942] [2021-11-09 09:34:07,118 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:34:07,118 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:07,119 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:07,127 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:07,147 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2021-11-09 09:34:07,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:07,762 INFO L263 TraceCheckSpWp]: Trace formula consists of 275 conjuncts, 33 conjunts are in the unsatisfiable core [2021-11-09 09:34:07,764 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:07,973 INFO L134 CoverageAnalysis]: Checked inductivity of 961 backedges. 0 proven. 961 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:07,973 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [927578942] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:07,973 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:07,974 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34] total 35 [2021-11-09 09:34:07,974 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [696167541] [2021-11-09 09:34:07,974 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:34:07,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:07,975 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 32 times [2021-11-09 09:34:07,975 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:07,975 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [837149522] [2021-11-09 09:34:07,975 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:07,975 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:07,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:07,982 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:07,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:07,988 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:08,097 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:08,097 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2021-11-09 09:34:08,098 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=595, Invalid=595, Unknown=0, NotChecked=0, Total=1190 [2021-11-09 09:34:08,098 INFO L87 Difference]: Start difference. First operand 70 states and 73 transitions. cyclomatic complexity: 5 Second operand has 35 states, 35 states have (on average 1.9714285714285715) internal successors, (69), 35 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:08,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:08,219 INFO L93 Difference]: Finished difference Result 73 states and 76 transitions. [2021-11-09 09:34:08,220 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2021-11-09 09:34:08,221 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73 states and 76 transitions. [2021-11-09 09:34:08,222 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:34:08,222 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73 states to 73 states and 76 transitions. [2021-11-09 09:34:08,223 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:34:08,223 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:34:08,223 INFO L73 IsDeterministic]: Start isDeterministic. Operand 73 states and 76 transitions. [2021-11-09 09:34:08,223 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:08,224 INFO L681 BuchiCegarLoop]: Abstraction has 73 states and 76 transitions. [2021-11-09 09:34:08,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states and 76 transitions. [2021-11-09 09:34:08,225 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 72. [2021-11-09 09:34:08,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72 states, 72 states have (on average 1.0416666666666667) internal successors, (75), 71 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:08,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 75 transitions. [2021-11-09 09:34:08,226 INFO L704 BuchiCegarLoop]: Abstraction has 72 states and 75 transitions. [2021-11-09 09:34:08,227 INFO L587 BuchiCegarLoop]: Abstraction has 72 states and 75 transitions. [2021-11-09 09:34:08,227 INFO L425 BuchiCegarLoop]: ======== Iteration 34============ [2021-11-09 09:34:08,227 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72 states and 75 transitions. [2021-11-09 09:34:08,228 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:34:08,228 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:08,228 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:08,229 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [32, 32, 1, 1, 1, 1] [2021-11-09 09:34:08,229 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:34:08,229 INFO L791 eck$LassoCheckResult]: Stem: 6672#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 6673#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 6677#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6678#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6679#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6674#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6675#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6741#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6740#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6739#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6738#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6737#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6736#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6735#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6734#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6733#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6732#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6731#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6730#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6729#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6728#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6727#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6726#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6725#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6724#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6723#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6722#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6721#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6720#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6719#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6718#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6717#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6716#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6715#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6714#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6713#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6712#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6711#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6710#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6709#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6708#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6707#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6706#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6705#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6704#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6703#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6702#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6701#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6700#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6699#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6698#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6697#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6696#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6695#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6694#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6693#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6692#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6691#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6690#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6689#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6688#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6687#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6686#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6685#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6684#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 6683#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 6682#L18-3 assume !(main_~i~0 < 1048); 6680#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 6676#L23-2 [2021-11-09 09:34:08,230 INFO L793 eck$LassoCheckResult]: Loop: 6676#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 6670#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 6671#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 6681#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 6676#L23-2 [2021-11-09 09:34:08,230 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:08,230 INFO L85 PathProgramCache]: Analyzing trace with hash -1451677621, now seen corresponding path program 32 times [2021-11-09 09:34:08,230 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:08,230 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [101166461] [2021-11-09 09:34:08,231 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:08,231 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:08,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:08,852 INFO L134 CoverageAnalysis]: Checked inductivity of 1024 backedges. 0 proven. 1024 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:08,853 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:08,853 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [101166461] [2021-11-09 09:34:08,853 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [101166461] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:08,853 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1191662865] [2021-11-09 09:34:08,853 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:34:08,853 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:08,854 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:08,859 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:08,879 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2021-11-09 09:34:09,398 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:34:09,399 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:09,401 INFO L263 TraceCheckSpWp]: Trace formula consists of 283 conjuncts, 34 conjunts are in the unsatisfiable core [2021-11-09 09:34:09,402 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:09,646 INFO L134 CoverageAnalysis]: Checked inductivity of 1024 backedges. 0 proven. 1024 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:09,646 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1191662865] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:09,646 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:09,646 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35] total 36 [2021-11-09 09:34:09,646 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [832579837] [2021-11-09 09:34:09,647 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:34:09,647 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:09,647 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 33 times [2021-11-09 09:34:09,647 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:09,647 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [71455249] [2021-11-09 09:34:09,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:09,647 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:09,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:09,656 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:09,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:09,659 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:09,762 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:09,762 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2021-11-09 09:34:09,763 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2021-11-09 09:34:09,763 INFO L87 Difference]: Start difference. First operand 72 states and 75 transitions. cyclomatic complexity: 5 Second operand has 36 states, 36 states have (on average 1.9722222222222223) internal successors, (71), 36 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:09,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:09,873 INFO L93 Difference]: Finished difference Result 75 states and 78 transitions. [2021-11-09 09:34:09,873 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2021-11-09 09:34:09,873 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75 states and 78 transitions. [2021-11-09 09:34:09,874 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:34:09,875 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75 states to 75 states and 78 transitions. [2021-11-09 09:34:09,875 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:34:09,875 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:34:09,875 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75 states and 78 transitions. [2021-11-09 09:34:09,876 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:09,876 INFO L681 BuchiCegarLoop]: Abstraction has 75 states and 78 transitions. [2021-11-09 09:34:09,876 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states and 78 transitions. [2021-11-09 09:34:09,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 74. [2021-11-09 09:34:09,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74 states, 74 states have (on average 1.0405405405405406) internal successors, (77), 73 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:09,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 77 transitions. [2021-11-09 09:34:09,879 INFO L704 BuchiCegarLoop]: Abstraction has 74 states and 77 transitions. [2021-11-09 09:34:09,879 INFO L587 BuchiCegarLoop]: Abstraction has 74 states and 77 transitions. [2021-11-09 09:34:09,879 INFO L425 BuchiCegarLoop]: ======== Iteration 35============ [2021-11-09 09:34:09,879 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74 states and 77 transitions. [2021-11-09 09:34:09,880 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:34:09,880 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:09,880 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:09,881 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [33, 33, 1, 1, 1, 1] [2021-11-09 09:34:09,882 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:34:09,882 INFO L791 eck$LassoCheckResult]: Stem: 7059#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 7060#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 7064#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7065#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7066#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7061#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7062#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7130#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7129#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7128#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7127#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7126#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7125#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7124#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7123#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7122#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7121#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7120#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7119#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7118#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7117#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7116#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7115#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7114#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7113#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7112#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7111#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7110#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7109#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7108#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7107#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7106#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7105#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7104#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7103#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7102#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7101#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7100#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7099#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7098#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7097#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7096#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7095#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7094#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7093#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7092#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7091#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7090#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7089#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7088#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7087#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7086#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7085#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7084#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7083#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7082#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7081#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7080#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7079#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7078#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7077#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7076#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7075#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7074#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7073#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7072#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7071#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7070#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7069#L18-3 assume !(main_~i~0 < 1048); 7067#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 7063#L23-2 [2021-11-09 09:34:09,882 INFO L793 eck$LassoCheckResult]: Loop: 7063#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 7057#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 7058#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 7068#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 7063#L23-2 [2021-11-09 09:34:09,883 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:09,883 INFO L85 PathProgramCache]: Analyzing trace with hash 802233421, now seen corresponding path program 33 times [2021-11-09 09:34:09,883 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:09,883 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [209786216] [2021-11-09 09:34:09,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:09,884 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:09,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:10,635 INFO L134 CoverageAnalysis]: Checked inductivity of 1089 backedges. 0 proven. 1089 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:10,635 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:10,635 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [209786216] [2021-11-09 09:34:10,635 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [209786216] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:10,635 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1609460763] [2021-11-09 09:34:10,636 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:34:10,636 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:10,636 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:10,638 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:10,656 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2021-11-09 09:34:31,942 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 34 check-sat command(s) [2021-11-09 09:34:31,943 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:31,972 INFO L263 TraceCheckSpWp]: Trace formula consists of 291 conjuncts, 35 conjunts are in the unsatisfiable core [2021-11-09 09:34:31,973 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:32,230 INFO L134 CoverageAnalysis]: Checked inductivity of 1089 backedges. 0 proven. 1089 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:32,231 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1609460763] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:32,231 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:32,231 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36] total 37 [2021-11-09 09:34:32,231 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [402832326] [2021-11-09 09:34:32,232 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:34:32,232 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:32,232 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 34 times [2021-11-09 09:34:32,232 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:32,232 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786234592] [2021-11-09 09:34:32,233 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:32,233 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:32,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:32,274 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:32,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:32,277 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:32,377 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:32,378 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2021-11-09 09:34:32,378 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2021-11-09 09:34:32,379 INFO L87 Difference]: Start difference. First operand 74 states and 77 transitions. cyclomatic complexity: 5 Second operand has 37 states, 37 states have (on average 1.972972972972973) internal successors, (73), 37 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:32,486 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:32,486 INFO L93 Difference]: Finished difference Result 77 states and 80 transitions. [2021-11-09 09:34:32,486 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2021-11-09 09:34:32,486 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77 states and 80 transitions. [2021-11-09 09:34:32,491 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:34:32,492 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77 states to 77 states and 80 transitions. [2021-11-09 09:34:32,493 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:34:32,493 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:34:32,493 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77 states and 80 transitions. [2021-11-09 09:34:32,493 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:32,493 INFO L681 BuchiCegarLoop]: Abstraction has 77 states and 80 transitions. [2021-11-09 09:34:32,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states and 80 transitions. [2021-11-09 09:34:32,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 76. [2021-11-09 09:34:32,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76 states, 76 states have (on average 1.0394736842105263) internal successors, (79), 75 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:32,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 79 transitions. [2021-11-09 09:34:32,497 INFO L704 BuchiCegarLoop]: Abstraction has 76 states and 79 transitions. [2021-11-09 09:34:32,497 INFO L587 BuchiCegarLoop]: Abstraction has 76 states and 79 transitions. [2021-11-09 09:34:32,497 INFO L425 BuchiCegarLoop]: ======== Iteration 36============ [2021-11-09 09:34:32,497 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76 states and 79 transitions. [2021-11-09 09:34:32,498 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:34:32,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:32,498 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:32,499 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [34, 34, 1, 1, 1, 1] [2021-11-09 09:34:32,499 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:34:32,500 INFO L791 eck$LassoCheckResult]: Stem: 7457#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 7458#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 7462#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7463#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7464#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7459#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7460#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7530#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7529#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7528#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7527#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7526#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7525#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7524#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7523#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7522#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7521#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7520#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7519#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7518#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7517#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7516#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7515#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7514#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7513#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7512#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7511#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7510#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7509#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7508#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7507#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7506#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7505#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7504#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7503#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7502#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7501#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7500#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7499#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7498#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7497#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7496#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7495#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7494#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7493#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7492#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7491#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7490#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7489#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7488#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7487#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7486#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7485#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7484#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7483#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7482#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7481#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7480#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7479#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7478#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7477#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7476#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7475#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7474#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7473#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7472#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7471#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7470#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7469#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7468#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7467#L18-3 assume !(main_~i~0 < 1048); 7465#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 7461#L23-2 [2021-11-09 09:34:32,500 INFO L793 eck$LassoCheckResult]: Loop: 7461#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 7455#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 7456#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 7466#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 7461#L23-2 [2021-11-09 09:34:32,500 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:32,500 INFO L85 PathProgramCache]: Analyzing trace with hash 2147227599, now seen corresponding path program 34 times [2021-11-09 09:34:32,501 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:32,501 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [348458874] [2021-11-09 09:34:32,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:32,501 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:32,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:33,090 INFO L134 CoverageAnalysis]: Checked inductivity of 1156 backedges. 0 proven. 1156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:33,091 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:33,091 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [348458874] [2021-11-09 09:34:33,091 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [348458874] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:33,091 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1620328116] [2021-11-09 09:34:33,091 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:34:33,091 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:33,091 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:33,092 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:33,093 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2021-11-09 09:34:33,625 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:34:33,625 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:33,627 INFO L263 TraceCheckSpWp]: Trace formula consists of 299 conjuncts, 36 conjunts are in the unsatisfiable core [2021-11-09 09:34:33,628 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:33,871 INFO L134 CoverageAnalysis]: Checked inductivity of 1156 backedges. 0 proven. 1156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:33,871 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1620328116] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:33,871 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:33,871 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37] total 38 [2021-11-09 09:34:33,871 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [453701057] [2021-11-09 09:34:33,871 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:34:33,872 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:33,872 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 35 times [2021-11-09 09:34:33,872 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:33,872 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1492368500] [2021-11-09 09:34:33,872 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:33,872 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:33,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:33,884 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:33,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:33,897 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:33,987 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:33,991 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2021-11-09 09:34:33,992 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2021-11-09 09:34:33,993 INFO L87 Difference]: Start difference. First operand 76 states and 79 transitions. cyclomatic complexity: 5 Second operand has 38 states, 38 states have (on average 1.9736842105263157) internal successors, (75), 38 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:34,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:34,102 INFO L93 Difference]: Finished difference Result 79 states and 82 transitions. [2021-11-09 09:34:34,103 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2021-11-09 09:34:34,103 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79 states and 82 transitions. [2021-11-09 09:34:34,104 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:34:34,123 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79 states to 79 states and 82 transitions. [2021-11-09 09:34:34,123 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:34:34,124 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:34:34,124 INFO L73 IsDeterministic]: Start isDeterministic. Operand 79 states and 82 transitions. [2021-11-09 09:34:34,124 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:34,124 INFO L681 BuchiCegarLoop]: Abstraction has 79 states and 82 transitions. [2021-11-09 09:34:34,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states and 82 transitions. [2021-11-09 09:34:34,126 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 78. [2021-11-09 09:34:34,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78 states, 78 states have (on average 1.0384615384615385) internal successors, (81), 77 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:34,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 81 transitions. [2021-11-09 09:34:34,127 INFO L704 BuchiCegarLoop]: Abstraction has 78 states and 81 transitions. [2021-11-09 09:34:34,127 INFO L587 BuchiCegarLoop]: Abstraction has 78 states and 81 transitions. [2021-11-09 09:34:34,127 INFO L425 BuchiCegarLoop]: ======== Iteration 37============ [2021-11-09 09:34:34,127 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78 states and 81 transitions. [2021-11-09 09:34:34,128 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:34:34,128 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:34,128 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:34,129 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [35, 35, 1, 1, 1, 1] [2021-11-09 09:34:34,129 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:34:34,130 INFO L791 eck$LassoCheckResult]: Stem: 7866#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 7867#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 7871#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7872#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7873#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7868#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7869#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7941#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7940#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7939#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7938#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7937#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7936#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7935#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7934#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7933#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7932#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7931#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7930#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7929#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7928#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7927#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7926#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7925#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7924#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7923#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7922#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7921#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7920#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7919#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7918#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7917#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7916#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7915#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7914#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7913#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7912#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7911#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7910#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7909#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7908#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7907#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7906#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7905#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7904#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7903#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7902#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7901#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7900#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7899#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7898#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7897#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7896#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7895#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7894#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7893#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7892#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7891#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7890#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7889#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7888#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7887#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7886#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7885#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7884#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7883#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7882#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7881#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7880#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7879#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7878#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 7877#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 7876#L18-3 assume !(main_~i~0 < 1048); 7874#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 7870#L23-2 [2021-11-09 09:34:34,130 INFO L793 eck$LassoCheckResult]: Loop: 7870#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 7864#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 7865#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 7875#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 7870#L23-2 [2021-11-09 09:34:34,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:34,130 INFO L85 PathProgramCache]: Analyzing trace with hash 1901476561, now seen corresponding path program 35 times [2021-11-09 09:34:34,131 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:34,131 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1628398564] [2021-11-09 09:34:34,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:34,131 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:34,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:34,798 INFO L134 CoverageAnalysis]: Checked inductivity of 1225 backedges. 0 proven. 1225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:34,798 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:34,798 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1628398564] [2021-11-09 09:34:34,798 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1628398564] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:34,798 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1416379989] [2021-11-09 09:34:34,798 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:34:34,798 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:34,799 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:34,800 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:34,801 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2021-11-09 09:34:36,877 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 36 check-sat command(s) [2021-11-09 09:34:36,878 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:36,884 INFO L263 TraceCheckSpWp]: Trace formula consists of 307 conjuncts, 37 conjunts are in the unsatisfiable core [2021-11-09 09:34:36,885 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:37,112 INFO L134 CoverageAnalysis]: Checked inductivity of 1225 backedges. 0 proven. 1225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:37,112 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1416379989] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:37,112 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:37,112 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38] total 39 [2021-11-09 09:34:37,112 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2069972996] [2021-11-09 09:34:37,113 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:34:37,113 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:37,113 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 36 times [2021-11-09 09:34:37,113 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:37,113 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [170862287] [2021-11-09 09:34:37,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:37,114 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:37,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:37,120 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:37,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:37,123 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:37,242 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:37,242 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2021-11-09 09:34:37,243 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=741, Invalid=741, Unknown=0, NotChecked=0, Total=1482 [2021-11-09 09:34:37,243 INFO L87 Difference]: Start difference. First operand 78 states and 81 transitions. cyclomatic complexity: 5 Second operand has 39 states, 39 states have (on average 1.9743589743589745) internal successors, (77), 39 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:37,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:37,364 INFO L93 Difference]: Finished difference Result 81 states and 84 transitions. [2021-11-09 09:34:37,364 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2021-11-09 09:34:37,365 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81 states and 84 transitions. [2021-11-09 09:34:37,365 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:34:37,366 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81 states to 81 states and 84 transitions. [2021-11-09 09:34:37,366 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:34:37,366 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:34:37,366 INFO L73 IsDeterministic]: Start isDeterministic. Operand 81 states and 84 transitions. [2021-11-09 09:34:37,366 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:37,366 INFO L681 BuchiCegarLoop]: Abstraction has 81 states and 84 transitions. [2021-11-09 09:34:37,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states and 84 transitions. [2021-11-09 09:34:37,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 80. [2021-11-09 09:34:37,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80 states, 80 states have (on average 1.0375) internal successors, (83), 79 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:37,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 83 transitions. [2021-11-09 09:34:37,368 INFO L704 BuchiCegarLoop]: Abstraction has 80 states and 83 transitions. [2021-11-09 09:34:37,368 INFO L587 BuchiCegarLoop]: Abstraction has 80 states and 83 transitions. [2021-11-09 09:34:37,368 INFO L425 BuchiCegarLoop]: ======== Iteration 38============ [2021-11-09 09:34:37,368 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80 states and 83 transitions. [2021-11-09 09:34:37,369 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:34:37,369 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:37,369 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:37,370 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [36, 36, 1, 1, 1, 1] [2021-11-09 09:34:37,370 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:34:37,370 INFO L791 eck$LassoCheckResult]: Stem: 8284#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 8285#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 8291#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8292#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8293#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8288#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8289#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8363#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8362#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8361#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8360#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8359#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8358#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8357#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8356#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8355#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8354#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8353#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8352#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8351#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8350#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8349#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8348#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8347#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8346#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8345#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8344#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8343#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8342#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8341#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8340#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8339#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8338#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8337#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8336#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8335#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8334#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8333#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8332#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8331#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8330#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8329#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8328#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8327#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8326#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8325#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8324#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8323#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8322#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8321#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8320#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8319#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8318#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8317#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8316#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8315#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8314#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8313#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8312#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8311#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8310#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8309#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8308#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8307#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8306#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8305#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8304#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8303#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8302#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8301#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8300#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8299#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8298#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8297#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8296#L18-3 assume !(main_~i~0 < 1048); 8294#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 8290#L23-2 [2021-11-09 09:34:37,371 INFO L793 eck$LassoCheckResult]: Loop: 8290#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 8286#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 8287#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 8295#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 8290#L23-2 [2021-11-09 09:34:37,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:37,371 INFO L85 PathProgramCache]: Analyzing trace with hash 1957930323, now seen corresponding path program 36 times [2021-11-09 09:34:37,371 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:37,372 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [697565196] [2021-11-09 09:34:37,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:37,372 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:37,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:38,160 INFO L134 CoverageAnalysis]: Checked inductivity of 1296 backedges. 0 proven. 1296 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:38,160 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:38,160 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [697565196] [2021-11-09 09:34:38,161 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [697565196] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:38,161 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1801498908] [2021-11-09 09:34:38,161 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:34:38,161 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:38,161 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:38,167 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:38,187 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2021-11-09 09:35:07,830 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 37 check-sat command(s) [2021-11-09 09:35:07,830 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:35:07,873 INFO L263 TraceCheckSpWp]: Trace formula consists of 315 conjuncts, 38 conjunts are in the unsatisfiable core [2021-11-09 09:35:07,875 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:35:08,083 INFO L134 CoverageAnalysis]: Checked inductivity of 1296 backedges. 0 proven. 1296 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:08,087 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1801498908] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:08,087 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:35:08,088 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39] total 40 [2021-11-09 09:35:08,088 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [702158178] [2021-11-09 09:35:08,088 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:08,088 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:08,088 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 37 times [2021-11-09 09:35:08,088 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:08,088 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1549533939] [2021-11-09 09:35:08,088 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:08,089 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:08,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:08,094 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:08,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:08,096 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:08,223 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:08,223 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2021-11-09 09:35:08,224 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2021-11-09 09:35:08,224 INFO L87 Difference]: Start difference. First operand 80 states and 83 transitions. cyclomatic complexity: 5 Second operand has 40 states, 40 states have (on average 1.975) internal successors, (79), 40 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:08,347 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:08,347 INFO L93 Difference]: Finished difference Result 83 states and 86 transitions. [2021-11-09 09:35:08,347 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2021-11-09 09:35:08,348 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83 states and 86 transitions. [2021-11-09 09:35:08,348 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:35:08,349 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83 states to 83 states and 86 transitions. [2021-11-09 09:35:08,349 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:35:08,349 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:35:08,349 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83 states and 86 transitions. [2021-11-09 09:35:08,349 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:08,349 INFO L681 BuchiCegarLoop]: Abstraction has 83 states and 86 transitions. [2021-11-09 09:35:08,350 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states and 86 transitions. [2021-11-09 09:35:08,351 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 82. [2021-11-09 09:35:08,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82 states, 82 states have (on average 1.0365853658536586) internal successors, (85), 81 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:08,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 85 transitions. [2021-11-09 09:35:08,351 INFO L704 BuchiCegarLoop]: Abstraction has 82 states and 85 transitions. [2021-11-09 09:35:08,351 INFO L587 BuchiCegarLoop]: Abstraction has 82 states and 85 transitions. [2021-11-09 09:35:08,351 INFO L425 BuchiCegarLoop]: ======== Iteration 39============ [2021-11-09 09:35:08,352 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82 states and 85 transitions. [2021-11-09 09:35:08,352 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:35:08,352 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:08,352 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:08,353 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [37, 37, 1, 1, 1, 1] [2021-11-09 09:35:08,353 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:35:08,353 INFO L791 eck$LassoCheckResult]: Stem: 8717#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 8718#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 8722#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8723#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8724#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8719#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8720#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8796#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8795#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8794#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8793#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8792#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8791#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8790#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8789#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8788#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8787#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8786#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8785#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8784#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8783#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8782#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8781#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8780#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8779#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8778#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8777#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8776#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8775#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8774#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8773#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8772#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8771#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8770#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8769#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8768#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8767#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8766#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8765#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8764#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8763#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8762#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8761#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8760#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8759#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8758#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8757#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8756#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8755#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8754#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8753#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8752#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8751#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8750#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8749#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8748#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8747#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8746#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8745#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8744#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8743#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8742#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8741#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8740#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8739#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8738#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8737#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8736#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8735#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8734#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8733#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8732#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8731#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8730#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8729#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 8728#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 8727#L18-3 assume !(main_~i~0 < 1048); 8725#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 8721#L23-2 [2021-11-09 09:35:08,353 INFO L793 eck$LassoCheckResult]: Loop: 8721#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 8715#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 8716#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 8726#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 8721#L23-2 [2021-11-09 09:35:08,353 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:08,353 INFO L85 PathProgramCache]: Analyzing trace with hash 375420757, now seen corresponding path program 37 times [2021-11-09 09:35:08,354 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:08,354 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [311480262] [2021-11-09 09:35:08,354 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:08,354 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:08,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:09,015 INFO L134 CoverageAnalysis]: Checked inductivity of 1369 backedges. 0 proven. 1369 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:09,016 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:09,016 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [311480262] [2021-11-09 09:35:09,017 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [311480262] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:09,017 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2004987994] [2021-11-09 09:35:09,017 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:35:09,017 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:35:09,017 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:35:09,018 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:35:09,019 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2021-11-09 09:35:09,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:09,556 INFO L263 TraceCheckSpWp]: Trace formula consists of 323 conjuncts, 39 conjunts are in the unsatisfiable core [2021-11-09 09:35:09,558 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:35:09,802 INFO L134 CoverageAnalysis]: Checked inductivity of 1369 backedges. 0 proven. 1369 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:09,802 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2004987994] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:09,803 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:35:09,803 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40] total 41 [2021-11-09 09:35:09,803 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [119331470] [2021-11-09 09:35:09,804 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:09,804 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:09,804 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 38 times [2021-11-09 09:35:09,804 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:09,805 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2036301191] [2021-11-09 09:35:09,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:09,805 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:09,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:09,824 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:09,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:09,828 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:09,928 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:09,928 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2021-11-09 09:35:09,929 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=820, Invalid=820, Unknown=0, NotChecked=0, Total=1640 [2021-11-09 09:35:09,929 INFO L87 Difference]: Start difference. First operand 82 states and 85 transitions. cyclomatic complexity: 5 Second operand has 41 states, 41 states have (on average 1.975609756097561) internal successors, (81), 41 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:10,065 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:10,065 INFO L93 Difference]: Finished difference Result 85 states and 88 transitions. [2021-11-09 09:35:10,066 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2021-11-09 09:35:10,066 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 85 states and 88 transitions. [2021-11-09 09:35:10,067 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:35:10,068 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 85 states to 85 states and 88 transitions. [2021-11-09 09:35:10,068 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:35:10,068 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:35:10,068 INFO L73 IsDeterministic]: Start isDeterministic. Operand 85 states and 88 transitions. [2021-11-09 09:35:10,068 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:10,068 INFO L681 BuchiCegarLoop]: Abstraction has 85 states and 88 transitions. [2021-11-09 09:35:10,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states and 88 transitions. [2021-11-09 09:35:10,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 84. [2021-11-09 09:35:10,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84 states, 84 states have (on average 1.0357142857142858) internal successors, (87), 83 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:10,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 87 transitions. [2021-11-09 09:35:10,071 INFO L704 BuchiCegarLoop]: Abstraction has 84 states and 87 transitions. [2021-11-09 09:35:10,071 INFO L587 BuchiCegarLoop]: Abstraction has 84 states and 87 transitions. [2021-11-09 09:35:10,071 INFO L425 BuchiCegarLoop]: ======== Iteration 40============ [2021-11-09 09:35:10,071 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84 states and 87 transitions. [2021-11-09 09:35:10,072 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:35:10,072 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:10,072 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:10,072 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [38, 38, 1, 1, 1, 1] [2021-11-09 09:35:10,073 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:35:10,073 INFO L791 eck$LassoCheckResult]: Stem: 9159#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 9160#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 9164#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9165#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9166#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9161#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9162#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9240#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9239#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9238#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9237#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9236#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9235#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9234#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9233#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9232#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9231#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9230#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9229#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9228#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9227#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9226#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9225#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9224#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9223#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9222#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9221#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9220#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9219#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9218#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9217#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9216#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9215#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9214#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9213#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9212#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9211#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9210#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9209#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9208#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9207#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9206#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9205#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9204#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9203#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9202#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9201#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9200#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9199#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9198#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9197#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9196#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9195#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9194#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9193#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9192#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9191#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9190#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9189#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9188#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9187#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9186#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9185#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9184#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9183#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9182#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9181#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9180#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9179#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9178#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9177#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9176#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9175#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9174#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9173#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9172#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9171#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9170#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9169#L18-3 assume !(main_~i~0 < 1048); 9167#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 9163#L23-2 [2021-11-09 09:35:10,073 INFO L793 eck$LassoCheckResult]: Loop: 9163#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 9157#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 9158#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 9168#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 9163#L23-2 [2021-11-09 09:35:10,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:10,073 INFO L85 PathProgramCache]: Analyzing trace with hash 2150615, now seen corresponding path program 38 times [2021-11-09 09:35:10,074 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:10,074 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1723579476] [2021-11-09 09:35:10,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:10,074 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:10,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:10,874 INFO L134 CoverageAnalysis]: Checked inductivity of 1444 backedges. 0 proven. 1444 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:10,875 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:10,875 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1723579476] [2021-11-09 09:35:10,875 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1723579476] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:10,875 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1602562882] [2021-11-09 09:35:10,875 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:35:10,875 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:35:10,875 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:35:10,881 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:35:10,897 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2021-11-09 09:35:11,510 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:35:11,510 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:35:11,512 INFO L263 TraceCheckSpWp]: Trace formula consists of 331 conjuncts, 40 conjunts are in the unsatisfiable core [2021-11-09 09:35:11,514 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:35:11,764 INFO L134 CoverageAnalysis]: Checked inductivity of 1444 backedges. 0 proven. 1444 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:11,764 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1602562882] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:11,764 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:35:11,764 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41] total 42 [2021-11-09 09:35:11,764 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1124073683] [2021-11-09 09:35:11,788 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:11,788 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:11,788 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 39 times [2021-11-09 09:35:11,789 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:11,789 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [225604433] [2021-11-09 09:35:11,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:11,789 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:11,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:11,798 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:11,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:11,801 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:11,906 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:11,907 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2021-11-09 09:35:11,907 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2021-11-09 09:35:11,907 INFO L87 Difference]: Start difference. First operand 84 states and 87 transitions. cyclomatic complexity: 5 Second operand has 42 states, 42 states have (on average 1.9761904761904763) internal successors, (83), 42 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:12,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:12,022 INFO L93 Difference]: Finished difference Result 87 states and 90 transitions. [2021-11-09 09:35:12,023 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2021-11-09 09:35:12,023 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 87 states and 90 transitions. [2021-11-09 09:35:12,024 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:35:12,024 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 87 states to 87 states and 90 transitions. [2021-11-09 09:35:12,024 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:35:12,024 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:35:12,024 INFO L73 IsDeterministic]: Start isDeterministic. Operand 87 states and 90 transitions. [2021-11-09 09:35:12,024 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:12,025 INFO L681 BuchiCegarLoop]: Abstraction has 87 states and 90 transitions. [2021-11-09 09:35:12,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states and 90 transitions. [2021-11-09 09:35:12,026 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 86. [2021-11-09 09:35:12,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 86 states, 86 states have (on average 1.0348837209302326) internal successors, (89), 85 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:12,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 89 transitions. [2021-11-09 09:35:12,027 INFO L704 BuchiCegarLoop]: Abstraction has 86 states and 89 transitions. [2021-11-09 09:35:12,027 INFO L587 BuchiCegarLoop]: Abstraction has 86 states and 89 transitions. [2021-11-09 09:35:12,027 INFO L425 BuchiCegarLoop]: ======== Iteration 41============ [2021-11-09 09:35:12,027 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 86 states and 89 transitions. [2021-11-09 09:35:12,028 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:35:12,028 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:12,028 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:12,029 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [39, 39, 1, 1, 1, 1] [2021-11-09 09:35:12,029 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:35:12,030 INFO L791 eck$LassoCheckResult]: Stem: 9612#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 9613#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 9617#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9618#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9619#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9614#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9615#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9695#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9694#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9693#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9692#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9691#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9690#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9689#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9688#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9687#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9686#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9685#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9684#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9683#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9682#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9681#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9680#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9679#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9678#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9677#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9676#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9675#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9674#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9673#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9672#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9671#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9670#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9669#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9668#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9667#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9666#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9665#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9664#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9663#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9662#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9661#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9660#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9659#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9658#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9657#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9656#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9655#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9654#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9653#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9652#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9651#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9650#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9649#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9648#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9647#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9646#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9645#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9644#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9643#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9642#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9641#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9640#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9639#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9638#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9637#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9636#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9635#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9634#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9633#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9632#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9631#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9630#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9629#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9628#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9627#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9626#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9625#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9624#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 9623#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 9622#L18-3 assume !(main_~i~0 < 1048); 9620#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 9616#L23-2 [2021-11-09 09:35:12,030 INFO L793 eck$LassoCheckResult]: Loop: 9616#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 9610#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 9611#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 9621#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 9616#L23-2 [2021-11-09 09:35:12,030 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:12,031 INFO L85 PathProgramCache]: Analyzing trace with hash 2066797017, now seen corresponding path program 39 times [2021-11-09 09:35:12,031 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:12,031 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1107698554] [2021-11-09 09:35:12,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:12,031 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:12,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:12,723 INFO L134 CoverageAnalysis]: Checked inductivity of 1521 backedges. 0 proven. 1521 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:12,724 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:12,724 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1107698554] [2021-11-09 09:35:12,724 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1107698554] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:12,724 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1227887971] [2021-11-09 09:35:12,724 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:35:12,724 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:35:12,724 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:35:12,725 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:35:12,726 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2021-11-09 09:35:42,914 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 40 check-sat command(s) [2021-11-09 09:35:42,915 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:35:42,953 INFO L263 TraceCheckSpWp]: Trace formula consists of 339 conjuncts, 41 conjunts are in the unsatisfiable core [2021-11-09 09:35:42,955 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:35:43,239 INFO L134 CoverageAnalysis]: Checked inductivity of 1521 backedges. 0 proven. 1521 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:43,239 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1227887971] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:43,239 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:35:43,239 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42] total 43 [2021-11-09 09:35:43,239 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1906841836] [2021-11-09 09:35:43,240 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:43,240 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:43,240 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 40 times [2021-11-09 09:35:43,240 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:43,240 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [542673364] [2021-11-09 09:35:43,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:43,240 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:43,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:43,247 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:43,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:43,250 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:43,335 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:43,335 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2021-11-09 09:35:43,336 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=903, Invalid=903, Unknown=0, NotChecked=0, Total=1806 [2021-11-09 09:35:43,336 INFO L87 Difference]: Start difference. First operand 86 states and 89 transitions. cyclomatic complexity: 5 Second operand has 43 states, 43 states have (on average 1.9767441860465116) internal successors, (85), 43 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:43,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:43,428 INFO L93 Difference]: Finished difference Result 89 states and 92 transitions. [2021-11-09 09:35:43,428 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2021-11-09 09:35:43,428 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 89 states and 92 transitions. [2021-11-09 09:35:43,429 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:35:43,429 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 89 states to 89 states and 92 transitions. [2021-11-09 09:35:43,430 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:35:43,430 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:35:43,430 INFO L73 IsDeterministic]: Start isDeterministic. Operand 89 states and 92 transitions. [2021-11-09 09:35:43,430 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:43,430 INFO L681 BuchiCegarLoop]: Abstraction has 89 states and 92 transitions. [2021-11-09 09:35:43,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states and 92 transitions. [2021-11-09 09:35:43,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 88. [2021-11-09 09:35:43,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 88 states, 88 states have (on average 1.0340909090909092) internal successors, (91), 87 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:43,432 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 91 transitions. [2021-11-09 09:35:43,433 INFO L704 BuchiCegarLoop]: Abstraction has 88 states and 91 transitions. [2021-11-09 09:35:43,433 INFO L587 BuchiCegarLoop]: Abstraction has 88 states and 91 transitions. [2021-11-09 09:35:43,433 INFO L425 BuchiCegarLoop]: ======== Iteration 42============ [2021-11-09 09:35:43,433 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 88 states and 91 transitions. [2021-11-09 09:35:43,434 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:35:43,434 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:43,434 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:43,435 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [40, 40, 1, 1, 1, 1] [2021-11-09 09:35:43,435 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:35:43,435 INFO L791 eck$LassoCheckResult]: Stem: 10074#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 10075#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 10081#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10082#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10083#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10078#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10079#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10161#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10160#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10159#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10158#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10157#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10156#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10155#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10154#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10153#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10152#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10151#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10150#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10149#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10148#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10147#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10146#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10145#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10144#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10143#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10142#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10141#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10140#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10139#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10138#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10137#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10136#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10135#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10134#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10133#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10132#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10131#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10130#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10129#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10128#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10127#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10126#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10125#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10124#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10123#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10122#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10121#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10120#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10119#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10118#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10117#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10116#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10115#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10114#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10113#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10112#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10111#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10110#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10109#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10108#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10107#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10106#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10105#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10104#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10103#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10102#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10101#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10100#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10099#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10098#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10097#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10096#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10095#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10094#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10093#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10092#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10091#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10090#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10089#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10088#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10087#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10086#L18-3 assume !(main_~i~0 < 1048); 10084#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 10080#L23-2 [2021-11-09 09:35:43,435 INFO L793 eck$LassoCheckResult]: Loop: 10080#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 10076#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 10077#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 10085#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 10080#L23-2 [2021-11-09 09:35:43,435 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:43,436 INFO L85 PathProgramCache]: Analyzing trace with hash 1917098587, now seen corresponding path program 40 times [2021-11-09 09:35:43,436 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:43,436 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1516293596] [2021-11-09 09:35:43,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:43,436 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:43,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:44,251 INFO L134 CoverageAnalysis]: Checked inductivity of 1600 backedges. 0 proven. 1600 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:44,251 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:44,251 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1516293596] [2021-11-09 09:35:44,251 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1516293596] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:44,251 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [164800341] [2021-11-09 09:35:44,251 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:35:44,251 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:35:44,252 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:35:44,255 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:35:44,255 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2021-11-09 09:35:44,855 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:35:44,855 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:35:44,857 INFO L263 TraceCheckSpWp]: Trace formula consists of 347 conjuncts, 42 conjunts are in the unsatisfiable core [2021-11-09 09:35:44,860 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:35:45,127 INFO L134 CoverageAnalysis]: Checked inductivity of 1600 backedges. 0 proven. 1600 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:45,127 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [164800341] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:45,127 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:35:45,128 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43] total 44 [2021-11-09 09:35:45,128 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1612012769] [2021-11-09 09:35:45,128 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:45,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:45,128 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 41 times [2021-11-09 09:35:45,129 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:45,129 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1000150418] [2021-11-09 09:35:45,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:45,129 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:45,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:45,135 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:45,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:45,138 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:45,224 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:45,225 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2021-11-09 09:35:45,225 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2021-11-09 09:35:45,225 INFO L87 Difference]: Start difference. First operand 88 states and 91 transitions. cyclomatic complexity: 5 Second operand has 44 states, 44 states have (on average 1.9772727272727273) internal successors, (87), 44 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:45,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:45,318 INFO L93 Difference]: Finished difference Result 91 states and 94 transitions. [2021-11-09 09:35:45,319 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2021-11-09 09:35:45,319 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91 states and 94 transitions. [2021-11-09 09:35:45,319 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:35:45,320 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91 states to 91 states and 94 transitions. [2021-11-09 09:35:45,320 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:35:45,321 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:35:45,321 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91 states and 94 transitions. [2021-11-09 09:35:45,321 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:45,321 INFO L681 BuchiCegarLoop]: Abstraction has 91 states and 94 transitions. [2021-11-09 09:35:45,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states and 94 transitions. [2021-11-09 09:35:45,323 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 90. [2021-11-09 09:35:45,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 90 states, 90 states have (on average 1.0333333333333334) internal successors, (93), 89 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:45,324 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 93 transitions. [2021-11-09 09:35:45,324 INFO L704 BuchiCegarLoop]: Abstraction has 90 states and 93 transitions. [2021-11-09 09:35:45,324 INFO L587 BuchiCegarLoop]: Abstraction has 90 states and 93 transitions. [2021-11-09 09:35:45,324 INFO L425 BuchiCegarLoop]: ======== Iteration 43============ [2021-11-09 09:35:45,324 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90 states and 93 transitions. [2021-11-09 09:35:45,325 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:35:45,325 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:45,325 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:45,326 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [41, 41, 1, 1, 1, 1] [2021-11-09 09:35:45,326 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:35:45,326 INFO L791 eck$LassoCheckResult]: Stem: 10551#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 10552#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 10556#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10557#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10558#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10553#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10554#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10638#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10637#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10636#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10635#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10634#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10633#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10632#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10631#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10630#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10629#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10628#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10627#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10626#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10625#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10624#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10623#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10622#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10621#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10620#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10619#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10618#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10617#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10616#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10615#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10614#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10613#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10612#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10611#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10610#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10609#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10608#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10607#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10606#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10605#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10604#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10603#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10602#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10601#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10600#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10599#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10598#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10597#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10596#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10595#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10594#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10593#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10592#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10591#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10590#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10589#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10588#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10587#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10586#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10585#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10584#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10583#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10582#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10581#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10580#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10579#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10578#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10577#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10576#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10575#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10574#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10573#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10572#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10571#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10570#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10569#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10568#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10567#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10566#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10565#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10564#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10563#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 10562#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 10561#L18-3 assume !(main_~i~0 < 1048); 10559#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 10555#L23-2 [2021-11-09 09:35:45,326 INFO L793 eck$LassoCheckResult]: Loop: 10555#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 10549#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 10550#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 10560#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 10555#L23-2 [2021-11-09 09:35:45,327 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:45,327 INFO L85 PathProgramCache]: Analyzing trace with hash -209171875, now seen corresponding path program 41 times [2021-11-09 09:35:45,327 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:45,327 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1697695984] [2021-11-09 09:35:45,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:45,327 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:45,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:46,191 INFO L134 CoverageAnalysis]: Checked inductivity of 1681 backedges. 0 proven. 1681 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:46,192 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:46,192 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1697695984] [2021-11-09 09:35:46,192 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1697695984] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:46,192 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [696671150] [2021-11-09 09:35:46,192 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:35:46,192 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:35:46,192 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:35:46,193 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:35:46,194 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Waiting until timeout for monitored process [2021-11-09 09:35:49,041 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 42 check-sat command(s) [2021-11-09 09:35:49,041 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:35:49,049 INFO L263 TraceCheckSpWp]: Trace formula consists of 355 conjuncts, 43 conjunts are in the unsatisfiable core [2021-11-09 09:35:49,051 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:35:49,319 INFO L134 CoverageAnalysis]: Checked inductivity of 1681 backedges. 0 proven. 1681 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:49,319 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [696671150] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:49,319 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:35:49,319 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44] total 45 [2021-11-09 09:35:49,320 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1201760230] [2021-11-09 09:35:49,320 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:49,320 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:49,321 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 42 times [2021-11-09 09:35:49,321 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:49,321 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [600175907] [2021-11-09 09:35:49,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:49,325 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:49,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:49,334 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:49,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:49,337 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:49,428 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:49,429 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2021-11-09 09:35:49,430 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=990, Invalid=990, Unknown=0, NotChecked=0, Total=1980 [2021-11-09 09:35:49,430 INFO L87 Difference]: Start difference. First operand 90 states and 93 transitions. cyclomatic complexity: 5 Second operand has 45 states, 45 states have (on average 1.9777777777777779) internal successors, (89), 45 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:49,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:49,529 INFO L93 Difference]: Finished difference Result 93 states and 96 transitions. [2021-11-09 09:35:49,539 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2021-11-09 09:35:49,540 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 93 states and 96 transitions. [2021-11-09 09:35:49,540 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:35:49,541 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 93 states to 93 states and 96 transitions. [2021-11-09 09:35:49,541 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:35:49,542 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:35:49,542 INFO L73 IsDeterministic]: Start isDeterministic. Operand 93 states and 96 transitions. [2021-11-09 09:35:49,542 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:49,542 INFO L681 BuchiCegarLoop]: Abstraction has 93 states and 96 transitions. [2021-11-09 09:35:49,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states and 96 transitions. [2021-11-09 09:35:49,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 92. [2021-11-09 09:35:49,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 92 states, 92 states have (on average 1.0326086956521738) internal successors, (95), 91 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:49,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 95 transitions. [2021-11-09 09:35:49,545 INFO L704 BuchiCegarLoop]: Abstraction has 92 states and 95 transitions. [2021-11-09 09:35:49,545 INFO L587 BuchiCegarLoop]: Abstraction has 92 states and 95 transitions. [2021-11-09 09:35:49,545 INFO L425 BuchiCegarLoop]: ======== Iteration 44============ [2021-11-09 09:35:49,546 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 92 states and 95 transitions. [2021-11-09 09:35:49,546 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:35:49,546 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:49,546 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:49,547 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [42, 42, 1, 1, 1, 1] [2021-11-09 09:35:49,547 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:35:49,548 INFO L791 eck$LassoCheckResult]: Stem: 11037#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 11038#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 11042#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11043#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11044#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11039#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11040#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11126#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11125#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11124#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11123#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11122#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11121#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11120#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11119#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11118#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11117#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11116#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11115#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11114#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11113#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11112#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11111#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11110#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11109#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11108#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11107#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11106#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11105#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11104#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11103#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11102#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11101#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11100#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11099#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11098#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11097#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11096#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11095#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11094#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11093#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11092#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11091#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11090#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11089#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11088#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11087#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11086#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11085#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11084#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11083#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11082#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11081#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11080#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11079#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11078#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11077#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11076#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11075#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11074#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11073#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11072#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11071#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11070#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11069#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11068#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11067#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11066#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11065#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11064#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11063#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11062#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11061#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11060#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11059#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11058#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11057#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11056#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11055#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11054#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11053#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11052#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11051#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11050#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11049#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11048#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11047#L18-3 assume !(main_~i~0 < 1048); 11045#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 11041#L23-2 [2021-11-09 09:35:49,548 INFO L793 eck$LassoCheckResult]: Loop: 11041#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 11035#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 11036#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 11046#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 11041#L23-2 [2021-11-09 09:35:49,549 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:49,549 INFO L85 PathProgramCache]: Analyzing trace with hash 849347039, now seen corresponding path program 42 times [2021-11-09 09:35:49,549 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:49,549 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1622084481] [2021-11-09 09:35:49,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:49,550 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:49,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:50,505 INFO L134 CoverageAnalysis]: Checked inductivity of 1764 backedges. 0 proven. 1764 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:50,506 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:50,506 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1622084481] [2021-11-09 09:35:50,506 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1622084481] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:50,506 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [21995154] [2021-11-09 09:35:50,506 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:35:50,506 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:35:50,506 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:35:50,507 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:35:50,509 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Waiting until timeout for monitored process [2021-11-09 09:37:26,434 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 43 check-sat command(s) [2021-11-09 09:37:26,434 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:37:26,551 INFO L263 TraceCheckSpWp]: Trace formula consists of 363 conjuncts, 44 conjunts are in the unsatisfiable core [2021-11-09 09:37:26,553 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:37:26,797 INFO L134 CoverageAnalysis]: Checked inductivity of 1764 backedges. 0 proven. 1764 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:26,797 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [21995154] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:26,798 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:37:26,798 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45] total 46 [2021-11-09 09:37:26,798 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [898214585] [2021-11-09 09:37:26,798 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:37:26,798 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:37:26,798 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 43 times [2021-11-09 09:37:26,799 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:37:26,799 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [869817631] [2021-11-09 09:37:26,799 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:37:26,799 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:37:26,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:37:26,807 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:37:26,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:37:26,809 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:37:26,895 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:37:26,896 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2021-11-09 09:37:26,897 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2021-11-09 09:37:26,897 INFO L87 Difference]: Start difference. First operand 92 states and 95 transitions. cyclomatic complexity: 5 Second operand has 46 states, 46 states have (on average 1.9782608695652173) internal successors, (91), 46 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:37:27,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:37:27,054 INFO L93 Difference]: Finished difference Result 95 states and 98 transitions. [2021-11-09 09:37:27,054 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2021-11-09 09:37:27,054 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 95 states and 98 transitions. [2021-11-09 09:37:27,055 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:37:27,055 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 95 states to 95 states and 98 transitions. [2021-11-09 09:37:27,056 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:37:27,056 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:37:27,056 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95 states and 98 transitions. [2021-11-09 09:37:27,056 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:37:27,056 INFO L681 BuchiCegarLoop]: Abstraction has 95 states and 98 transitions. [2021-11-09 09:37:27,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states and 98 transitions. [2021-11-09 09:37:27,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 94. [2021-11-09 09:37:27,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 94 states, 94 states have (on average 1.0319148936170213) internal successors, (97), 93 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:37:27,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 97 transitions. [2021-11-09 09:37:27,058 INFO L704 BuchiCegarLoop]: Abstraction has 94 states and 97 transitions. [2021-11-09 09:37:27,058 INFO L587 BuchiCegarLoop]: Abstraction has 94 states and 97 transitions. [2021-11-09 09:37:27,058 INFO L425 BuchiCegarLoop]: ======== Iteration 45============ [2021-11-09 09:37:27,058 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 94 states and 97 transitions. [2021-11-09 09:37:27,059 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:37:27,059 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:37:27,059 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:37:27,060 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [43, 43, 1, 1, 1, 1] [2021-11-09 09:37:27,060 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:37:27,060 INFO L791 eck$LassoCheckResult]: Stem: 11534#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 11535#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 11539#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11540#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11541#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11536#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11537#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11625#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11624#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11623#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11622#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11621#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11620#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11619#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11618#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11617#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11616#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11615#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11614#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11613#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11612#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11611#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11610#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11609#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11608#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11607#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11606#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11605#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11604#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11603#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11602#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11601#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11600#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11599#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11598#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11597#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11596#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11595#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11594#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11593#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11592#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11591#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11590#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11589#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11588#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11587#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11586#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11585#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11584#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11583#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11582#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11581#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11580#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11579#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11578#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11577#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11576#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11575#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11574#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11573#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11572#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11571#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11570#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11569#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11568#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11567#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11566#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11565#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11564#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11563#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11562#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11561#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11560#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11559#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11558#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11557#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11556#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11555#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11554#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11553#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11552#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11551#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11550#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11549#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11548#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11547#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11546#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 11545#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 11544#L18-3 assume !(main_~i~0 < 1048); 11542#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 11538#L23-2 [2021-11-09 09:37:27,060 INFO L793 eck$LassoCheckResult]: Loop: 11538#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 11532#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 11533#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 11543#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 11538#L23-2 [2021-11-09 09:37:27,060 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:37:27,061 INFO L85 PathProgramCache]: Analyzing trace with hash 178774241, now seen corresponding path program 43 times [2021-11-09 09:37:27,061 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:37:27,061 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1710410100] [2021-11-09 09:37:27,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:37:27,061 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:37:27,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:37:27,936 INFO L134 CoverageAnalysis]: Checked inductivity of 1849 backedges. 0 proven. 1849 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:27,936 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:37:27,937 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1710410100] [2021-11-09 09:37:27,937 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1710410100] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:27,937 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1250530895] [2021-11-09 09:37:27,937 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:37:27,937 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:37:27,937 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:37:27,940 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:37:27,940 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Waiting until timeout for monitored process [2021-11-09 09:37:28,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:37:28,647 INFO L263 TraceCheckSpWp]: Trace formula consists of 371 conjuncts, 45 conjunts are in the unsatisfiable core [2021-11-09 09:37:28,649 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:37:28,889 INFO L134 CoverageAnalysis]: Checked inductivity of 1849 backedges. 0 proven. 1849 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:28,889 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1250530895] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:28,889 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:37:28,890 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46] total 47 [2021-11-09 09:37:28,890 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [360970427] [2021-11-09 09:37:28,890 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:37:28,890 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:37:28,890 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 44 times [2021-11-09 09:37:28,890 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:37:28,890 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [472705958] [2021-11-09 09:37:28,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:37:28,890 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:37:28,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:37:28,896 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:37:28,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:37:28,898 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:37:28,969 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:37:28,969 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2021-11-09 09:37:28,970 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1081, Invalid=1081, Unknown=0, NotChecked=0, Total=2162 [2021-11-09 09:37:28,970 INFO L87 Difference]: Start difference. First operand 94 states and 97 transitions. cyclomatic complexity: 5 Second operand has 47 states, 47 states have (on average 1.9787234042553192) internal successors, (93), 47 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:37:29,079 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:37:29,079 INFO L93 Difference]: Finished difference Result 97 states and 100 transitions. [2021-11-09 09:37:29,080 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2021-11-09 09:37:29,080 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97 states and 100 transitions. [2021-11-09 09:37:29,080 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:37:29,081 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97 states to 97 states and 100 transitions. [2021-11-09 09:37:29,081 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:37:29,081 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:37:29,081 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97 states and 100 transitions. [2021-11-09 09:37:29,082 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:37:29,082 INFO L681 BuchiCegarLoop]: Abstraction has 97 states and 100 transitions. [2021-11-09 09:37:29,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states and 100 transitions. [2021-11-09 09:37:29,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 96. [2021-11-09 09:37:29,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 96 states, 96 states have (on average 1.03125) internal successors, (99), 95 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:37:29,084 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96 states to 96 states and 99 transitions. [2021-11-09 09:37:29,084 INFO L704 BuchiCegarLoop]: Abstraction has 96 states and 99 transitions. [2021-11-09 09:37:29,084 INFO L587 BuchiCegarLoop]: Abstraction has 96 states and 99 transitions. [2021-11-09 09:37:29,084 INFO L425 BuchiCegarLoop]: ======== Iteration 46============ [2021-11-09 09:37:29,084 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 96 states and 99 transitions. [2021-11-09 09:37:29,085 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:37:29,085 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:37:29,085 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:37:29,085 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [44, 44, 1, 1, 1, 1] [2021-11-09 09:37:29,085 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:37:29,086 INFO L791 eck$LassoCheckResult]: Stem: 12042#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 12043#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 12047#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12048#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12049#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12044#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12045#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12135#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12134#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12133#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12132#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12131#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12130#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12129#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12128#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12127#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12126#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12125#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12124#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12123#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12122#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12121#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12120#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12119#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12118#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12117#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12116#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12115#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12114#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12113#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12112#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12111#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12110#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12109#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12108#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12107#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12106#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12105#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12104#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12103#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12102#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12101#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12100#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12099#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12098#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12097#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12096#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12095#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12094#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12093#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12092#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12091#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12090#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12089#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12088#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12087#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12086#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12085#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12084#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12083#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12082#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12081#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12080#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12079#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12078#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12077#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12076#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12075#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12074#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12073#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12072#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12071#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12070#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12069#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12068#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12067#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12066#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12065#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12064#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12063#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12062#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12061#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12060#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12059#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12058#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12057#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12056#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12055#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12054#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12053#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12052#L18-3 assume !(main_~i~0 < 1048); 12050#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 12046#L23-2 [2021-11-09 09:37:29,086 INFO L793 eck$LassoCheckResult]: Loop: 12046#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 12040#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 12041#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 12051#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 12046#L23-2 [2021-11-09 09:37:29,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:37:29,086 INFO L85 PathProgramCache]: Analyzing trace with hash 3409763, now seen corresponding path program 44 times [2021-11-09 09:37:29,086 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:37:29,086 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [178576165] [2021-11-09 09:37:29,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:37:29,087 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:37:29,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:37:30,274 INFO L134 CoverageAnalysis]: Checked inductivity of 1936 backedges. 0 proven. 1936 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:30,274 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:37:30,274 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [178576165] [2021-11-09 09:37:30,274 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [178576165] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:30,274 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [916154494] [2021-11-09 09:37:30,274 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:37:30,274 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:37:30,275 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:37:30,279 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:37:30,295 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Waiting until timeout for monitored process [2021-11-09 09:37:31,024 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:37:31,025 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:37:31,027 INFO L263 TraceCheckSpWp]: Trace formula consists of 379 conjuncts, 46 conjunts are in the unsatisfiable core [2021-11-09 09:37:31,028 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:37:31,297 INFO L134 CoverageAnalysis]: Checked inductivity of 1936 backedges. 0 proven. 1936 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:31,298 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [916154494] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:31,298 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:37:31,298 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47] total 48 [2021-11-09 09:37:31,298 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [926818216] [2021-11-09 09:37:31,298 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:37:31,299 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:37:31,299 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 45 times [2021-11-09 09:37:31,299 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:37:31,299 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [297040683] [2021-11-09 09:37:31,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:37:31,299 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:37:31,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:37:31,310 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:37:31,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:37:31,312 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:37:31,402 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:37:31,402 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2021-11-09 09:37:31,403 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2021-11-09 09:37:31,403 INFO L87 Difference]: Start difference. First operand 96 states and 99 transitions. cyclomatic complexity: 5 Second operand has 48 states, 48 states have (on average 1.9791666666666667) internal successors, (95), 48 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:37:31,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:37:31,518 INFO L93 Difference]: Finished difference Result 99 states and 102 transitions. [2021-11-09 09:37:31,519 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2021-11-09 09:37:31,519 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99 states and 102 transitions. [2021-11-09 09:37:31,520 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:37:31,521 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99 states to 99 states and 102 transitions. [2021-11-09 09:37:31,521 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:37:31,521 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:37:31,521 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99 states and 102 transitions. [2021-11-09 09:37:31,521 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:37:31,522 INFO L681 BuchiCegarLoop]: Abstraction has 99 states and 102 transitions. [2021-11-09 09:37:31,522 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states and 102 transitions. [2021-11-09 09:37:31,523 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 98. [2021-11-09 09:37:31,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98 states, 98 states have (on average 1.030612244897959) internal successors, (101), 97 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:37:31,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 101 transitions. [2021-11-09 09:37:31,524 INFO L704 BuchiCegarLoop]: Abstraction has 98 states and 101 transitions. [2021-11-09 09:37:31,524 INFO L587 BuchiCegarLoop]: Abstraction has 98 states and 101 transitions. [2021-11-09 09:37:31,525 INFO L425 BuchiCegarLoop]: ======== Iteration 47============ [2021-11-09 09:37:31,525 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98 states and 101 transitions. [2021-11-09 09:37:31,525 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:37:31,525 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:37:31,526 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:37:31,526 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [45, 45, 1, 1, 1, 1] [2021-11-09 09:37:31,527 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:37:31,527 INFO L791 eck$LassoCheckResult]: Stem: 12561#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 12562#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 12566#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12567#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12568#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12563#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12564#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12656#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12655#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12654#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12653#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12652#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12651#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12650#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12649#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12648#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12647#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12646#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12645#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12644#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12643#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12642#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12641#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12640#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12639#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12638#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12637#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12636#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12635#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12634#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12633#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12632#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12631#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12630#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12629#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12628#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12627#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12626#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12625#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12624#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12623#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12622#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12621#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12620#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12619#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12618#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12617#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12616#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12615#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12614#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12613#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12612#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12611#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12610#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12609#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12608#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12607#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12606#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12605#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12604#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12603#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12602#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12601#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12600#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12599#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12598#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12597#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12596#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12595#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12594#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12593#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12592#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12591#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12590#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12589#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12588#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12587#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12586#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12585#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12584#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12583#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12582#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12581#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12580#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12579#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12578#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12577#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12576#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12575#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12574#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12573#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 12572#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 12571#L18-3 assume !(main_~i~0 < 1048); 12569#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 12565#L23-2 [2021-11-09 09:37:31,527 INFO L793 eck$LassoCheckResult]: Loop: 12565#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 12559#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 12560#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 12570#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 12565#L23-2 [2021-11-09 09:37:31,527 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:37:31,528 INFO L85 PathProgramCache]: Analyzing trace with hash -1018129051, now seen corresponding path program 45 times [2021-11-09 09:37:31,528 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:37:31,528 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1554204401] [2021-11-09 09:37:31,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:37:31,528 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:37:31,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:37:32,408 INFO L134 CoverageAnalysis]: Checked inductivity of 2025 backedges. 0 proven. 2025 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:32,408 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:37:32,408 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1554204401] [2021-11-09 09:37:32,408 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1554204401] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:32,408 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [392403339] [2021-11-09 09:37:32,408 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:37:32,408 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:37:32,408 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:37:32,444 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:37:32,460 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Waiting until timeout for monitored process [2021-11-09 09:39:08,341 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 46 check-sat command(s) [2021-11-09 09:39:08,341 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:39:08,441 INFO L263 TraceCheckSpWp]: Trace formula consists of 387 conjuncts, 47 conjunts are in the unsatisfiable core [2021-11-09 09:39:08,444 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:39:08,728 INFO L134 CoverageAnalysis]: Checked inductivity of 2025 backedges. 0 proven. 2025 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:39:08,729 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [392403339] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:39:08,729 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:39:08,729 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48] total 49 [2021-11-09 09:39:08,729 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2109716135] [2021-11-09 09:39:08,729 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:39:08,730 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:39:08,730 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 46 times [2021-11-09 09:39:08,730 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:39:08,730 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1041995503] [2021-11-09 09:39:08,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:39:08,730 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:39:08,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:39:08,739 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:39:08,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:39:08,742 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:39:08,825 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:39:08,826 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2021-11-09 09:39:08,827 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2021-11-09 09:39:08,827 INFO L87 Difference]: Start difference. First operand 98 states and 101 transitions. cyclomatic complexity: 5 Second operand has 49 states, 49 states have (on average 1.9795918367346939) internal successors, (97), 49 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:39:08,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:39:08,958 INFO L93 Difference]: Finished difference Result 101 states and 104 transitions. [2021-11-09 09:39:08,958 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2021-11-09 09:39:08,958 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101 states and 104 transitions. [2021-11-09 09:39:08,959 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:39:08,959 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101 states to 101 states and 104 transitions. [2021-11-09 09:39:08,959 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:39:08,959 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:39:08,959 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101 states and 104 transitions. [2021-11-09 09:39:08,960 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:39:08,960 INFO L681 BuchiCegarLoop]: Abstraction has 101 states and 104 transitions. [2021-11-09 09:39:08,960 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states and 104 transitions. [2021-11-09 09:39:08,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 100. [2021-11-09 09:39:08,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 100 states have (on average 1.03) internal successors, (103), 99 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:39:08,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 103 transitions. [2021-11-09 09:39:08,962 INFO L704 BuchiCegarLoop]: Abstraction has 100 states and 103 transitions. [2021-11-09 09:39:08,962 INFO L587 BuchiCegarLoop]: Abstraction has 100 states and 103 transitions. [2021-11-09 09:39:08,962 INFO L425 BuchiCegarLoop]: ======== Iteration 48============ [2021-11-09 09:39:08,962 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100 states and 103 transitions. [2021-11-09 09:39:08,962 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:39:08,962 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:39:08,963 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:39:08,963 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [46, 46, 1, 1, 1, 1] [2021-11-09 09:39:08,963 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:39:08,963 INFO L791 eck$LassoCheckResult]: Stem: 13091#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 13092#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 13096#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13097#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13098#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13093#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13094#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13188#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13187#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13186#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13185#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13184#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13183#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13182#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13181#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13180#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13179#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13178#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13177#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13176#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13175#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13174#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13173#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13172#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13171#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13170#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13169#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13168#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13167#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13166#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13165#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13164#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13163#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13162#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13161#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13160#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13159#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13158#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13157#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13156#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13155#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13154#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13153#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13152#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13151#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13150#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13149#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13148#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13147#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13146#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13145#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13144#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13143#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13142#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13141#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13140#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13139#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13138#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13137#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13136#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13135#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13134#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13133#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13132#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13131#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13130#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13129#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13128#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13127#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13126#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13125#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13124#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13123#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13122#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13121#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13120#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13119#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13118#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13117#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13116#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13115#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13114#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13113#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13112#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13111#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13110#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13109#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13108#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13107#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13106#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13105#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13104#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13103#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13102#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13101#L18-3 assume !(main_~i~0 < 1048); 13099#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 13095#L23-2 [2021-11-09 09:39:08,964 INFO L793 eck$LassoCheckResult]: Loop: 13095#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 13089#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 13090#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 13100#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 13095#L23-2 [2021-11-09 09:39:08,964 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:39:08,964 INFO L85 PathProgramCache]: Analyzing trace with hash 830581479, now seen corresponding path program 46 times [2021-11-09 09:39:08,964 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:39:08,964 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [275704597] [2021-11-09 09:39:08,964 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:39:08,964 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:39:09,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:39:09,852 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:39:09,853 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:39:09,853 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [275704597] [2021-11-09 09:39:09,853 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [275704597] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:39:09,853 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [216155579] [2021-11-09 09:39:09,853 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:39:09,853 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:39:09,853 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:39:09,854 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:39:09,855 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Waiting until timeout for monitored process [2021-11-09 09:39:10,630 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:39:10,631 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:39:10,633 INFO L263 TraceCheckSpWp]: Trace formula consists of 395 conjuncts, 48 conjunts are in the unsatisfiable core [2021-11-09 09:39:10,634 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:39:10,919 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:39:10,920 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [216155579] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:39:10,920 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:39:10,920 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49] total 50 [2021-11-09 09:39:10,920 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1376993150] [2021-11-09 09:39:10,921 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:39:10,921 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:39:10,921 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 47 times [2021-11-09 09:39:10,921 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:39:10,921 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1282260190] [2021-11-09 09:39:10,921 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:39:10,921 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:39:10,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:39:10,941 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:39:10,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:39:10,945 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:39:11,034 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:39:11,035 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2021-11-09 09:39:11,036 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2021-11-09 09:39:11,036 INFO L87 Difference]: Start difference. First operand 100 states and 103 transitions. cyclomatic complexity: 5 Second operand has 50 states, 50 states have (on average 1.98) internal successors, (99), 50 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:39:11,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:39:11,168 INFO L93 Difference]: Finished difference Result 103 states and 106 transitions. [2021-11-09 09:39:11,169 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2021-11-09 09:39:11,169 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 103 states and 106 transitions. [2021-11-09 09:39:11,169 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:39:11,170 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 103 states to 103 states and 106 transitions. [2021-11-09 09:39:11,170 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:39:11,170 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:39:11,170 INFO L73 IsDeterministic]: Start isDeterministic. Operand 103 states and 106 transitions. [2021-11-09 09:39:11,170 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:39:11,170 INFO L681 BuchiCegarLoop]: Abstraction has 103 states and 106 transitions. [2021-11-09 09:39:11,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states and 106 transitions. [2021-11-09 09:39:11,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 102. [2021-11-09 09:39:11,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 102 states, 102 states have (on average 1.0294117647058822) internal successors, (105), 101 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:39:11,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 105 transitions. [2021-11-09 09:39:11,173 INFO L704 BuchiCegarLoop]: Abstraction has 102 states and 105 transitions. [2021-11-09 09:39:11,173 INFO L587 BuchiCegarLoop]: Abstraction has 102 states and 105 transitions. [2021-11-09 09:39:11,173 INFO L425 BuchiCegarLoop]: ======== Iteration 49============ [2021-11-09 09:39:11,173 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 102 states and 105 transitions. [2021-11-09 09:39:11,174 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:39:11,174 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:39:11,174 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:39:11,175 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [47, 47, 1, 1, 1, 1] [2021-11-09 09:39:11,175 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:39:11,175 INFO L791 eck$LassoCheckResult]: Stem: 13632#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 13633#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 13637#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13638#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13639#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13634#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13635#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13731#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13730#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13729#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13728#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13727#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13726#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13725#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13724#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13723#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13722#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13721#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13720#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13719#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13718#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13717#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13716#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13715#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13714#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13713#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13712#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13711#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13710#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13709#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13708#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13707#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13706#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13705#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13704#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13703#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13702#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13701#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13700#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13699#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13698#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13697#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13696#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13695#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13694#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13693#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13692#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13691#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13690#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13689#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13688#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13687#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13686#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13685#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13684#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13683#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13682#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13681#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13680#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13679#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13678#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13677#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13676#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13675#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13674#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13673#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13672#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13671#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13670#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13669#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13668#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13667#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13666#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13665#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13664#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13663#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13662#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13661#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13660#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13659#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13658#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13657#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13656#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13655#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13654#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13653#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13652#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13651#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13650#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13649#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13648#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13647#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13646#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13645#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13644#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 13643#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 13642#L18-3 assume !(main_~i~0 < 1048); 13640#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 13636#L23-2 [2021-11-09 09:39:11,175 INFO L793 eck$LassoCheckResult]: Loop: 13636#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 13630#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 13631#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 13641#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 13636#L23-2 [2021-11-09 09:39:11,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:39:11,176 INFO L85 PathProgramCache]: Analyzing trace with hash -675059735, now seen corresponding path program 47 times [2021-11-09 09:39:11,176 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:39:11,176 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1857789338] [2021-11-09 09:39:11,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:39:11,176 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:39:11,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:39:12,093 INFO L134 CoverageAnalysis]: Checked inductivity of 2209 backedges. 0 proven. 2209 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:39:12,093 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:39:12,093 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1857789338] [2021-11-09 09:39:12,093 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1857789338] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:39:12,095 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [365818369] [2021-11-09 09:39:12,096 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:39:12,096 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:39:12,096 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:39:12,098 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:39:12,100 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Waiting until timeout for monitored process [2021-11-09 09:39:15,573 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 48 check-sat command(s) [2021-11-09 09:39:15,573 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:39:15,582 INFO L263 TraceCheckSpWp]: Trace formula consists of 403 conjuncts, 49 conjunts are in the unsatisfiable core [2021-11-09 09:39:15,583 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:39:15,869 INFO L134 CoverageAnalysis]: Checked inductivity of 2209 backedges. 0 proven. 2209 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:39:15,869 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [365818369] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:39:15,869 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:39:15,870 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50] total 51 [2021-11-09 09:39:15,870 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [586335104] [2021-11-09 09:39:15,870 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:39:15,870 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:39:15,870 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 48 times [2021-11-09 09:39:15,871 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:39:15,871 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [415597631] [2021-11-09 09:39:15,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:39:15,871 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:39:15,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:39:15,901 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:39:15,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:39:15,903 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:39:15,993 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:39:15,993 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2021-11-09 09:39:15,994 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1275, Invalid=1275, Unknown=0, NotChecked=0, Total=2550 [2021-11-09 09:39:15,994 INFO L87 Difference]: Start difference. First operand 102 states and 105 transitions. cyclomatic complexity: 5 Second operand has 51 states, 51 states have (on average 1.9803921568627452) internal successors, (101), 51 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:39:16,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:39:16,139 INFO L93 Difference]: Finished difference Result 105 states and 108 transitions. [2021-11-09 09:39:16,140 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2021-11-09 09:39:16,140 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 105 states and 108 transitions. [2021-11-09 09:39:16,140 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:39:16,141 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 105 states to 105 states and 108 transitions. [2021-11-09 09:39:16,141 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:39:16,141 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:39:16,141 INFO L73 IsDeterministic]: Start isDeterministic. Operand 105 states and 108 transitions. [2021-11-09 09:39:16,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:39:16,141 INFO L681 BuchiCegarLoop]: Abstraction has 105 states and 108 transitions. [2021-11-09 09:39:16,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states and 108 transitions. [2021-11-09 09:39:16,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 104. [2021-11-09 09:39:16,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 104 states, 104 states have (on average 1.0288461538461537) internal successors, (107), 103 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:39:16,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 107 transitions. [2021-11-09 09:39:16,144 INFO L704 BuchiCegarLoop]: Abstraction has 104 states and 107 transitions. [2021-11-09 09:39:16,144 INFO L587 BuchiCegarLoop]: Abstraction has 104 states and 107 transitions. [2021-11-09 09:39:16,144 INFO L425 BuchiCegarLoop]: ======== Iteration 50============ [2021-11-09 09:39:16,144 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 104 states and 107 transitions. [2021-11-09 09:39:16,145 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:39:16,145 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:39:16,145 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:39:16,146 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [48, 48, 1, 1, 1, 1] [2021-11-09 09:39:16,146 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:39:16,146 INFO L791 eck$LassoCheckResult]: Stem: 14184#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 14185#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 14189#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14190#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14191#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14186#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14187#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14285#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14284#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14283#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14282#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14281#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14280#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14279#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14278#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14277#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14276#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14275#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14274#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14273#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14272#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14271#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14270#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14269#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14268#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14267#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14266#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14265#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14264#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14263#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14262#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14261#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14260#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14259#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14258#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14257#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14256#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14255#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14254#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14253#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14252#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14251#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14250#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14249#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14248#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14247#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14246#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14245#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14244#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14243#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14242#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14241#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14240#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14239#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14238#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14237#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14236#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14235#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14234#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14233#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14232#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14231#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14230#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14229#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14228#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14227#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14226#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14225#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14224#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14223#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14222#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14221#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14220#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14219#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14218#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14217#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14216#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14215#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14214#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14213#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14212#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14211#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14210#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14209#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14208#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14207#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14206#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14205#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14204#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14203#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14202#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14201#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14200#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14199#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14198#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14197#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14196#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14195#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14194#L18-3 assume !(main_~i~0 < 1048); 14192#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 14188#L23-2 [2021-11-09 09:39:16,146 INFO L793 eck$LassoCheckResult]: Loop: 14188#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 14182#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 14183#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 14193#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 14188#L23-2 [2021-11-09 09:39:16,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:39:16,146 INFO L85 PathProgramCache]: Analyzing trace with hash -192287637, now seen corresponding path program 48 times [2021-11-09 09:39:16,146 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:39:16,146 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [798020938] [2021-11-09 09:39:16,146 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:39:16,147 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:39:16,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:39:17,298 INFO L134 CoverageAnalysis]: Checked inductivity of 2304 backedges. 0 proven. 2304 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:39:17,298 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:39:17,298 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [798020938] [2021-11-09 09:39:17,298 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [798020938] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:39:17,298 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [529127803] [2021-11-09 09:39:17,299 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:39:17,299 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:39:17,299 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:39:17,315 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:39:17,332 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Waiting until timeout for monitored process [2021-11-09 09:44:34,668 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2021-11-09 09:44:34,669 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:44:34,877 INFO L263 TraceCheckSpWp]: Trace formula consists of 411 conjuncts, 50 conjunts are in the unsatisfiable core [2021-11-09 09:44:34,879 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:44:35,213 INFO L134 CoverageAnalysis]: Checked inductivity of 2304 backedges. 0 proven. 2304 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:44:35,213 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [529127803] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:44:35,213 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:44:35,214 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 51] total 52 [2021-11-09 09:44:35,214 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [370860344] [2021-11-09 09:44:35,214 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:44:35,214 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:44:35,215 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 49 times [2021-11-09 09:44:35,215 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:44:35,215 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1081408899] [2021-11-09 09:44:35,215 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:44:35,215 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:44:35,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:44:35,232 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:44:35,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:44:35,235 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:44:35,320 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:44:35,321 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2021-11-09 09:44:35,322 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2021-11-09 09:44:35,322 INFO L87 Difference]: Start difference. First operand 104 states and 107 transitions. cyclomatic complexity: 5 Second operand has 52 states, 52 states have (on average 1.9807692307692308) internal successors, (103), 52 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:44:35,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:44:35,458 INFO L93 Difference]: Finished difference Result 107 states and 110 transitions. [2021-11-09 09:44:35,458 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2021-11-09 09:44:35,458 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 107 states and 110 transitions. [2021-11-09 09:44:35,461 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:44:35,461 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 107 states to 107 states and 110 transitions. [2021-11-09 09:44:35,461 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:44:35,461 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:44:35,461 INFO L73 IsDeterministic]: Start isDeterministic. Operand 107 states and 110 transitions. [2021-11-09 09:44:35,461 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:44:35,461 INFO L681 BuchiCegarLoop]: Abstraction has 107 states and 110 transitions. [2021-11-09 09:44:35,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states and 110 transitions. [2021-11-09 09:44:35,462 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 106. [2021-11-09 09:44:35,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 106 states, 106 states have (on average 1.028301886792453) internal successors, (109), 105 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:44:35,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 109 transitions. [2021-11-09 09:44:35,463 INFO L704 BuchiCegarLoop]: Abstraction has 106 states and 109 transitions. [2021-11-09 09:44:35,463 INFO L587 BuchiCegarLoop]: Abstraction has 106 states and 109 transitions. [2021-11-09 09:44:35,463 INFO L425 BuchiCegarLoop]: ======== Iteration 51============ [2021-11-09 09:44:35,463 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 106 states and 109 transitions. [2021-11-09 09:44:35,464 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:44:35,464 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:44:35,464 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:44:35,465 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [49, 49, 1, 1, 1, 1] [2021-11-09 09:44:35,465 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:44:35,465 INFO L791 eck$LassoCheckResult]: Stem: 14745#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 14746#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 14752#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14753#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14754#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14749#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14750#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14850#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14849#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14848#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14847#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14846#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14845#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14844#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14843#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14842#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14841#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14840#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14839#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14838#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14837#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14836#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14835#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14834#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14833#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14832#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14831#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14830#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14829#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14828#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14827#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14826#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14825#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14824#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14823#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14822#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14821#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14820#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14819#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14818#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14817#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14816#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14815#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14814#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14813#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14812#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14811#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14810#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14809#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14808#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14807#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14806#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14805#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14804#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14803#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14802#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14801#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14800#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14799#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14798#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14797#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14796#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14795#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14794#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14793#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14792#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14791#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14790#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14789#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14788#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14787#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14786#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14785#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14784#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14783#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14782#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14781#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14780#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14779#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14778#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14777#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14776#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14775#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14774#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14773#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14772#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14771#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14770#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14769#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14768#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14767#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14766#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14765#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14764#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14763#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14762#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14761#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14760#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14759#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 14758#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 14757#L18-3 assume !(main_~i~0 < 1048); 14755#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 14751#L23-2 [2021-11-09 09:44:35,465 INFO L793 eck$LassoCheckResult]: Loop: 14751#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 14747#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 14748#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 14756#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 14751#L23-2 [2021-11-09 09:44:35,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:44:35,466 INFO L85 PathProgramCache]: Analyzing trace with hash -104769427, now seen corresponding path program 49 times [2021-11-09 09:44:35,466 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:44:35,466 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1726562096] [2021-11-09 09:44:35,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:44:35,466 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:44:35,499 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:44:36,504 INFO L134 CoverageAnalysis]: Checked inductivity of 2401 backedges. 0 proven. 2401 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:44:36,504 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:44:36,505 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1726562096] [2021-11-09 09:44:36,505 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1726562096] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:44:36,505 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1394353401] [2021-11-09 09:44:36,505 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:44:36,505 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:44:36,505 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:44:36,506 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:44:36,507 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Waiting until timeout for monitored process [2021-11-09 09:44:37,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:44:37,363 INFO L263 TraceCheckSpWp]: Trace formula consists of 419 conjuncts, 51 conjunts are in the unsatisfiable core [2021-11-09 09:44:37,364 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:44:37,743 INFO L134 CoverageAnalysis]: Checked inductivity of 2401 backedges. 0 proven. 2401 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:44:37,743 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1394353401] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:44:37,744 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:44:37,744 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 52] total 53 [2021-11-09 09:44:37,744 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1392813596] [2021-11-09 09:44:37,744 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:44:37,744 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:44:37,744 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 50 times [2021-11-09 09:44:37,745 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:44:37,745 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1393311485] [2021-11-09 09:44:37,745 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:44:37,745 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:44:37,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:44:37,756 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:44:37,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:44:37,761 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:44:37,847 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:44:37,847 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2021-11-09 09:44:37,849 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1378, Invalid=1378, Unknown=0, NotChecked=0, Total=2756 [2021-11-09 09:44:37,849 INFO L87 Difference]: Start difference. First operand 106 states and 109 transitions. cyclomatic complexity: 5 Second operand has 53 states, 53 states have (on average 1.9811320754716981) internal successors, (105), 53 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:44:38,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:44:38,002 INFO L93 Difference]: Finished difference Result 109 states and 112 transitions. [2021-11-09 09:44:38,002 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2021-11-09 09:44:38,003 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 109 states and 112 transitions. [2021-11-09 09:44:38,003 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:44:38,004 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 109 states to 109 states and 112 transitions. [2021-11-09 09:44:38,004 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:44:38,004 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:44:38,004 INFO L73 IsDeterministic]: Start isDeterministic. Operand 109 states and 112 transitions. [2021-11-09 09:44:38,005 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:44:38,005 INFO L681 BuchiCegarLoop]: Abstraction has 109 states and 112 transitions. [2021-11-09 09:44:38,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states and 112 transitions. [2021-11-09 09:44:38,006 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 108. [2021-11-09 09:44:38,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 108 states have (on average 1.0277777777777777) internal successors, (111), 107 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:44:38,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 111 transitions. [2021-11-09 09:44:38,012 INFO L704 BuchiCegarLoop]: Abstraction has 108 states and 111 transitions. [2021-11-09 09:44:38,012 INFO L587 BuchiCegarLoop]: Abstraction has 108 states and 111 transitions. [2021-11-09 09:44:38,013 INFO L425 BuchiCegarLoop]: ======== Iteration 52============ [2021-11-09 09:44:38,013 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108 states and 111 transitions. [2021-11-09 09:44:38,023 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:44:38,024 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:44:38,024 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:44:38,025 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [50, 50, 1, 1, 1, 1] [2021-11-09 09:44:38,025 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:44:38,025 INFO L791 eck$LassoCheckResult]: Stem: 15319#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 15320#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 15326#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15327#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15328#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15323#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15324#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15426#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15425#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15424#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15423#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15422#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15421#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15420#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15419#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15418#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15417#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15416#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15415#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15414#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15413#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15412#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15411#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15410#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15409#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15408#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15407#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15406#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15405#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15404#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15403#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15402#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15401#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15400#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15399#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15398#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15397#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15396#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15395#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15394#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15393#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15392#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15391#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15390#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15389#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15388#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15387#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15386#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15385#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15384#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15383#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15382#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15381#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15380#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15379#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15378#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15377#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15376#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15375#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15374#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15373#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15372#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15371#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15370#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15369#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15368#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15367#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15366#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15365#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15364#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15363#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15362#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15361#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15360#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15359#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15358#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15357#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15356#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15355#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15354#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15353#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15352#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15351#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15350#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15349#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15348#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15347#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15346#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15345#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15344#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15343#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15342#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15341#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15340#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15339#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15338#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15337#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15336#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15335#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15334#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15333#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15332#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15331#L18-3 assume !(main_~i~0 < 1048); 15329#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 15325#L23-2 [2021-11-09 09:44:38,025 INFO L793 eck$LassoCheckResult]: Loop: 15325#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 15321#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 15322#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 15330#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 15325#L23-2 [2021-11-09 09:44:38,025 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:44:38,026 INFO L85 PathProgramCache]: Analyzing trace with hash -1899115537, now seen corresponding path program 50 times [2021-11-09 09:44:38,026 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:44:38,026 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [212155593] [2021-11-09 09:44:38,026 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:44:38,027 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:44:38,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:44:39,512 INFO L134 CoverageAnalysis]: Checked inductivity of 2500 backedges. 0 proven. 2500 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:44:39,512 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:44:39,512 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [212155593] [2021-11-09 09:44:39,512 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [212155593] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:44:39,512 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [171592162] [2021-11-09 09:44:39,512 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:44:39,513 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:44:39,513 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:44:39,514 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:44:39,516 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Waiting until timeout for monitored process [2021-11-09 09:44:40,437 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:44:40,438 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:44:40,440 INFO L263 TraceCheckSpWp]: Trace formula consists of 427 conjuncts, 52 conjunts are in the unsatisfiable core [2021-11-09 09:44:40,442 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:44:40,716 INFO L134 CoverageAnalysis]: Checked inductivity of 2500 backedges. 0 proven. 2500 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:44:40,716 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [171592162] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:44:40,716 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:44:40,716 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 53] total 54 [2021-11-09 09:44:40,716 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1853777325] [2021-11-09 09:44:40,717 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:44:40,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:44:40,717 INFO L85 PathProgramCache]: Analyzing trace with hash 1573223, now seen corresponding path program 51 times [2021-11-09 09:44:40,717 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:44:40,718 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1544907126] [2021-11-09 09:44:40,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:44:40,718 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:44:40,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:44:40,728 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:44:40,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:44:40,731 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:44:40,817 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:44:40,819 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2021-11-09 09:44:40,820 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1431, Invalid=1431, Unknown=0, NotChecked=0, Total=2862 [2021-11-09 09:44:40,820 INFO L87 Difference]: Start difference. First operand 108 states and 111 transitions. cyclomatic complexity: 5 Second operand has 54 states, 54 states have (on average 1.9814814814814814) internal successors, (107), 54 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:44:40,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:44:40,935 INFO L93 Difference]: Finished difference Result 111 states and 114 transitions. [2021-11-09 09:44:40,935 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2021-11-09 09:44:40,935 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 111 states and 114 transitions. [2021-11-09 09:44:40,936 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:44:40,936 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 111 states to 111 states and 114 transitions. [2021-11-09 09:44:40,936 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:44:40,936 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:44:40,936 INFO L73 IsDeterministic]: Start isDeterministic. Operand 111 states and 114 transitions. [2021-11-09 09:44:40,936 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:44:40,936 INFO L681 BuchiCegarLoop]: Abstraction has 111 states and 114 transitions. [2021-11-09 09:44:40,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states and 114 transitions. [2021-11-09 09:44:40,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 110. [2021-11-09 09:44:40,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 110 states, 110 states have (on average 1.0272727272727273) internal successors, (113), 109 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:44:40,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 113 transitions. [2021-11-09 09:44:40,939 INFO L704 BuchiCegarLoop]: Abstraction has 110 states and 113 transitions. [2021-11-09 09:44:40,939 INFO L587 BuchiCegarLoop]: Abstraction has 110 states and 113 transitions. [2021-11-09 09:44:40,939 INFO L425 BuchiCegarLoop]: ======== Iteration 53============ [2021-11-09 09:44:40,939 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 110 states and 113 transitions. [2021-11-09 09:44:40,939 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:44:40,939 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:44:40,939 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:44:40,940 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [51, 51, 1, 1, 1, 1] [2021-11-09 09:44:40,940 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:44:40,940 INFO L791 eck$LassoCheckResult]: Stem: 15906#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier; 15907#L-1 havoc main_#res;havoc main_#t~malloc1.base, main_#t~malloc1.offset, main_#t~nondet3, main_#t~post2, main_~i~0, main_#t~nondet6, main_#t~post7.base, main_#t~post7.offset, main_#t~mem8, main_#t~post9, main_#t~mem4, main_#t~short5, main_~p~0.base, main_~p~0.offset, main_~q~0.base, main_~q~0.offset;call main_#t~malloc1.base, main_#t~malloc1.offset := #Ultimate.allocOnHeap(4192);main_~p~0.base, main_~p~0.offset := main_#t~malloc1.base, main_#t~malloc1.offset;havoc main_#t~malloc1.base, main_#t~malloc1.offset;main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset;main_~i~0 := 0; 15911#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15912#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15913#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15908#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15909#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 16013#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16012#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 16011#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16010#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 16009#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16008#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 16007#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16006#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 16005#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16004#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 16003#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16002#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 16001#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 16000#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15999#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15998#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15997#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15996#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15995#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15994#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15993#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15992#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15991#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15990#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15989#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15988#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15987#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15986#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15985#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15984#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15983#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15982#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15981#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15980#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15979#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15978#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15977#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15976#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15975#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15974#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15973#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15972#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15971#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15970#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15969#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15968#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15967#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15966#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15965#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15964#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15963#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15962#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15961#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15960#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15959#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15958#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15957#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15956#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15955#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15954#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15953#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15952#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15951#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15950#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15949#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15948#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15947#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15946#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15945#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15944#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15943#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15942#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15941#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15940#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15939#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15938#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15937#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15936#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15935#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15934#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15933#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15932#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15931#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15930#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15929#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15928#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15927#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15926#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15925#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15924#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15923#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15922#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15921#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15920#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15919#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15918#L18-3 assume !!(main_~i~0 < 1048);call write~int(main_#t~nondet3, main_~q~0.base, main_~q~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet3; 15917#L18-2 main_#t~post2 := main_~i~0;main_~i~0 := 1 + main_#t~post2;havoc main_#t~post2; 15916#L18-3 assume !(main_~i~0 < 1048); 15914#L18-4 main_~q~0.base, main_~q~0.offset := main_~p~0.base, main_~p~0.offset; 15910#L23-2 [2021-11-09 09:44:40,941 INFO L793 eck$LassoCheckResult]: Loop: 15910#L23-2 assume main_~q~0.base == main_~p~0.base;main_#t~short5 := main_~q~0.offset < 4192 + main_~p~0.offset; 15904#L22-1 assume main_#t~short5;call main_#t~mem4 := read~int(main_~q~0.base, main_~q~0.offset, 4);main_#t~short5 := main_#t~mem4 >= 0; 15905#L22-3 assume !!main_#t~short5;havoc main_#t~mem4;havoc main_#t~short5; 15915#L23 assume 0 != main_#t~nondet6;havoc main_#t~nondet6;main_#t~post7.base, main_#t~post7.offset := main_~q~0.base, main_~q~0.offset;main_~q~0.base, main_~q~0.offset := main_#t~post7.base, 4 + main_#t~post7.offset;havoc main_#t~post7.base, main_#t~post7.offset; 15910#L23-2 [2021-11-09 09:44:40,941 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:44:40,941 INFO L85 PathProgramCache]: Analyzing trace with hash 311125745, now seen corresponding path program 51 times [2021-11-09 09:44:40,941 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:44:40,941 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1069662507] [2021-11-09 09:44:40,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:44:40,941 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:44:41,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:44:42,313 INFO L134 CoverageAnalysis]: Checked inductivity of 2601 backedges. 0 proven. 2601 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:44:42,313 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:44:42,313 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1069662507] [2021-11-09 09:44:42,313 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1069662507] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:44:42,313 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1505585469] [2021-11-09 09:44:42,314 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:44:42,314 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:44:42,314 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:44:42,320 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:44:42,335 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_a500d6ee-270d-4487-b28b-f9f7207d8b35/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Waiting until timeout for monitored process