./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/termination-crafted-lit/Urban-WST2013-Fig2-modified1000.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f8e1c903 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/termination-crafted-lit/Urban-WST2013-Fig2-modified1000.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 0b3c6d5b6497aa5ff0eb68154ec5345da59cc3565c3dc280e241d196cfa0cbf4 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-f8e1c90 [2021-11-09 09:33:12,239 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-09 09:33:12,241 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-09 09:33:12,295 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-09 09:33:12,296 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-09 09:33:12,304 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-09 09:33:12,306 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-09 09:33:12,311 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-09 09:33:12,314 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-09 09:33:12,320 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-09 09:33:12,321 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-09 09:33:12,323 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-09 09:33:12,324 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-09 09:33:12,327 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-09 09:33:12,330 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-09 09:33:12,338 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-09 09:33:12,340 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-09 09:33:12,341 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-09 09:33:12,343 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-09 09:33:12,352 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-09 09:33:12,354 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-09 09:33:12,355 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-09 09:33:12,359 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-09 09:33:12,360 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-09 09:33:12,369 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-09 09:33:12,370 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-09 09:33:12,370 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-09 09:33:12,373 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-09 09:33:12,373 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-09 09:33:12,375 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-09 09:33:12,377 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-09 09:33:12,378 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-09 09:33:12,379 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-09 09:33:12,381 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-09 09:33:12,382 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-09 09:33:12,382 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-09 09:33:12,383 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-09 09:33:12,384 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-09 09:33:12,384 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-09 09:33:12,385 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-09 09:33:12,386 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-09 09:33:12,386 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/config/svcomp-Termination-64bit-Automizer_Default.epf [2021-11-09 09:33:12,433 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-09 09:33:12,434 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-09 09:33:12,434 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-09 09:33:12,434 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-09 09:33:12,436 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-09 09:33:12,436 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-09 09:33:12,436 INFO L138 SettingsManager]: * Use SBE=true [2021-11-09 09:33:12,436 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-09 09:33:12,437 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-09 09:33:12,437 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-09 09:33:12,437 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-09 09:33:12,437 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-09 09:33:12,437 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-09 09:33:12,438 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-09 09:33:12,438 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-09 09:33:12,438 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-09 09:33:12,438 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-09 09:33:12,438 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-09 09:33:12,439 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-09 09:33:12,439 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-09 09:33:12,439 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-09 09:33:12,439 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-09 09:33:12,439 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-09 09:33:12,440 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-09 09:33:12,440 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-09 09:33:12,440 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-09 09:33:12,440 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-09 09:33:12,441 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-09 09:33:12,441 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-09 09:33:12,442 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-09 09:33:12,442 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0b3c6d5b6497aa5ff0eb68154ec5345da59cc3565c3dc280e241d196cfa0cbf4 [2021-11-09 09:33:12,833 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-09 09:33:12,860 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-09 09:33:12,863 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-09 09:33:12,864 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-09 09:33:12,866 INFO L275 PluginConnector]: CDTParser initialized [2021-11-09 09:33:12,867 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/../../sv-benchmarks/c/termination-crafted-lit/Urban-WST2013-Fig2-modified1000.c [2021-11-09 09:33:12,940 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/data/6636623a1/cfea3118a6294eea8bc083da31b2faf7/FLAG047f4df25 [2021-11-09 09:33:13,488 INFO L306 CDTParser]: Found 1 translation units. [2021-11-09 09:33:13,489 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/sv-benchmarks/c/termination-crafted-lit/Urban-WST2013-Fig2-modified1000.c [2021-11-09 09:33:13,500 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/data/6636623a1/cfea3118a6294eea8bc083da31b2faf7/FLAG047f4df25 [2021-11-09 09:33:13,852 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/data/6636623a1/cfea3118a6294eea8bc083da31b2faf7 [2021-11-09 09:33:13,855 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-09 09:33:13,856 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-09 09:33:13,858 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-09 09:33:13,859 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-09 09:33:13,863 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-09 09:33:13,864 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 09:33:13" (1/1) ... [2021-11-09 09:33:13,865 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@21609b80 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:13, skipping insertion in model container [2021-11-09 09:33:13,866 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 09:33:13" (1/1) ... [2021-11-09 09:33:13,874 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-09 09:33:13,887 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-09 09:33:14,016 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-09 09:33:14,021 INFO L203 MainTranslator]: Completed pre-run [2021-11-09 09:33:14,035 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-09 09:33:14,048 INFO L208 MainTranslator]: Completed translation [2021-11-09 09:33:14,049 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:14 WrapperNode [2021-11-09 09:33:14,049 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-09 09:33:14,050 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-09 09:33:14,051 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-09 09:33:14,051 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-09 09:33:14,059 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:14" (1/1) ... [2021-11-09 09:33:14,064 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:14" (1/1) ... [2021-11-09 09:33:14,082 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-09 09:33:14,083 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-09 09:33:14,084 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-09 09:33:14,084 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-09 09:33:14,093 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:14" (1/1) ... [2021-11-09 09:33:14,093 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:14" (1/1) ... [2021-11-09 09:33:14,094 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:14" (1/1) ... [2021-11-09 09:33:14,094 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:14" (1/1) ... [2021-11-09 09:33:14,096 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:14" (1/1) ... [2021-11-09 09:33:14,101 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:14" (1/1) ... [2021-11-09 09:33:14,102 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:14" (1/1) ... [2021-11-09 09:33:14,103 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-09 09:33:14,104 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-09 09:33:14,105 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-09 09:33:14,105 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-09 09:33:14,106 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:14" (1/1) ... [2021-11-09 09:33:14,116 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:33:14,129 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:14,150 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:33:14,171 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-09 09:33:14,203 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-09 09:33:14,203 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-09 09:33:14,379 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-09 09:33:14,380 INFO L299 CfgBuilder]: Removed 6 assume(true) statements. [2021-11-09 09:33:14,383 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 09:33:14 BoogieIcfgContainer [2021-11-09 09:33:14,383 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-09 09:33:14,384 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-09 09:33:14,384 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-09 09:33:14,387 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-09 09:33:14,388 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-09 09:33:14,388 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 09.11 09:33:13" (1/3) ... [2021-11-09 09:33:14,390 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@a1e9ac0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 09:33:14, skipping insertion in model container [2021-11-09 09:33:14,391 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-09 09:33:14,391 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:33:14" (2/3) ... [2021-11-09 09:33:14,391 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@a1e9ac0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 09:33:14, skipping insertion in model container [2021-11-09 09:33:14,391 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-09 09:33:14,392 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 09:33:14" (3/3) ... [2021-11-09 09:33:14,393 INFO L389 chiAutomizerObserver]: Analyzing ICFG Urban-WST2013-Fig2-modified1000.c [2021-11-09 09:33:14,454 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-09 09:33:14,454 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-09 09:33:14,454 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-09 09:33:14,455 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-09 09:33:14,455 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-09 09:33:14,455 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-09 09:33:14,455 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-09 09:33:14,455 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-09 09:33:14,471 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 8 states, 7 states have (on average 1.5714285714285714) internal successors, (11), 7 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:14,491 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:33:14,491 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:14,491 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:14,497 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:14,497 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:33:14,497 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-09 09:33:14,498 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 8 states, 7 states have (on average 1.5714285714285714) internal successors, (11), 7 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:14,499 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:33:14,499 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:14,500 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:14,500 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:14,500 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:33:14,507 INFO L791 eck$LassoCheckResult]: Stem: 6#ULTIMATE.startENTRYtrue havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 3#L19-2true [2021-11-09 09:33:14,507 INFO L793 eck$LassoCheckResult]: Loop: 3#L19-2true assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 7#L21-2true assume !(main_~x2~0 > 1); 5#L21-3true main_~x1~0 := 1 + main_~x1~0; 3#L19-2true [2021-11-09 09:33:14,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:14,513 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 1 times [2021-11-09 09:33:14,526 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:14,527 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [268325127] [2021-11-09 09:33:14,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:14,529 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:14,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:14,613 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:14,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:14,640 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:14,643 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:14,644 INFO L85 PathProgramCache]: Analyzing trace with hash 39951, now seen corresponding path program 1 times [2021-11-09 09:33:14,644 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:14,645 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1625496249] [2021-11-09 09:33:14,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:14,645 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:14,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:14,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:14,766 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:14,766 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1625496249] [2021-11-09 09:33:14,767 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1625496249] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:33:14,767 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:33:14,767 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-09 09:33:14,768 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [330988200] [2021-11-09 09:33:14,773 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:14,774 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:14,813 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:33:14,815 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:33:14,817 INFO L87 Difference]: Start difference. First operand has 8 states, 7 states have (on average 1.5714285714285714) internal successors, (11), 7 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.0) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:14,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:14,880 INFO L93 Difference]: Finished difference Result 9 states and 10 transitions. [2021-11-09 09:33:14,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:33:14,882 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9 states and 10 transitions. [2021-11-09 09:33:14,890 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:14,893 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9 states to 5 states and 6 transitions. [2021-11-09 09:33:14,895 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5 [2021-11-09 09:33:14,895 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5 [2021-11-09 09:33:14,896 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5 states and 6 transitions. [2021-11-09 09:33:14,904 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:14,904 INFO L681 BuchiCegarLoop]: Abstraction has 5 states and 6 transitions. [2021-11-09 09:33:14,921 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5 states and 6 transitions. [2021-11-09 09:33:14,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5 to 5. [2021-11-09 09:33:14,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 1.2) internal successors, (6), 4 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:14,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 6 transitions. [2021-11-09 09:33:14,932 INFO L704 BuchiCegarLoop]: Abstraction has 5 states and 6 transitions. [2021-11-09 09:33:14,932 INFO L587 BuchiCegarLoop]: Abstraction has 5 states and 6 transitions. [2021-11-09 09:33:14,932 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-09 09:33:14,932 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5 states and 6 transitions. [2021-11-09 09:33:14,933 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 4 [2021-11-09 09:33:14,933 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:14,933 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:14,934 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:14,934 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1] [2021-11-09 09:33:14,934 INFO L791 eck$LassoCheckResult]: Stem: 29#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 26#L19-2 [2021-11-09 09:33:14,934 INFO L793 eck$LassoCheckResult]: Loop: 26#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 27#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30#L21-2 assume !(main_~x2~0 > 1); 28#L21-3 main_~x1~0 := 1 + main_~x1~0; 26#L19-2 [2021-11-09 09:33:14,935 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:14,935 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 2 times [2021-11-09 09:33:14,935 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:14,936 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1088146811] [2021-11-09 09:33:14,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:14,936 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:14,940 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:14,941 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:14,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:14,945 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:14,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:14,945 INFO L85 PathProgramCache]: Analyzing trace with hash 1240240, now seen corresponding path program 1 times [2021-11-09 09:33:14,946 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:14,946 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [143397964] [2021-11-09 09:33:14,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:14,947 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:14,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:14,994 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:14,994 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:14,994 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [143397964] [2021-11-09 09:33:14,995 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [143397964] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:14,995 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [686187978] [2021-11-09 09:33:14,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:14,996 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:14,996 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:15,020 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:15,047 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2021-11-09 09:33:15,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:15,077 INFO L263 TraceCheckSpWp]: Trace formula consists of 11 conjuncts, 3 conjunts are in the unsatisfiable core [2021-11-09 09:33:15,079 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:15,129 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:15,130 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [686187978] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:15,130 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:15,130 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3] total 3 [2021-11-09 09:33:15,131 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1338759580] [2021-11-09 09:33:15,131 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:15,132 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:15,132 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-09 09:33:15,133 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2021-11-09 09:33:15,133 INFO L87 Difference]: Start difference. First operand 5 states and 6 transitions. cyclomatic complexity: 2 Second operand has 4 states, 4 states have (on average 1.0) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:15,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:15,144 INFO L93 Difference]: Finished difference Result 6 states and 7 transitions. [2021-11-09 09:33:15,145 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-09 09:33:15,145 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6 states and 7 transitions. [2021-11-09 09:33:15,146 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-11-09 09:33:15,146 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6 states to 6 states and 7 transitions. [2021-11-09 09:33:15,147 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2021-11-09 09:33:15,147 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6 [2021-11-09 09:33:15,147 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6 states and 7 transitions. [2021-11-09 09:33:15,147 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:15,148 INFO L681 BuchiCegarLoop]: Abstraction has 6 states and 7 transitions. [2021-11-09 09:33:15,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6 states and 7 transitions. [2021-11-09 09:33:15,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6 to 6. [2021-11-09 09:33:15,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 1.1666666666666667) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:15,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 7 transitions. [2021-11-09 09:33:15,149 INFO L704 BuchiCegarLoop]: Abstraction has 6 states and 7 transitions. [2021-11-09 09:33:15,149 INFO L587 BuchiCegarLoop]: Abstraction has 6 states and 7 transitions. [2021-11-09 09:33:15,150 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-09 09:33:15,150 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6 states and 7 transitions. [2021-11-09 09:33:15,150 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 5 [2021-11-09 09:33:15,151 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:15,151 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:15,151 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:15,151 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [2, 1, 1, 1] [2021-11-09 09:33:15,152 INFO L791 eck$LassoCheckResult]: Stem: 56#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 53#L19-2 [2021-11-09 09:33:15,152 INFO L793 eck$LassoCheckResult]: Loop: 53#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 54#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 57#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 58#L21-2 assume !(main_~x2~0 > 1); 55#L21-3 main_~x1~0 := 1 + main_~x1~0; 53#L19-2 [2021-11-09 09:33:15,152 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:15,152 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 3 times [2021-11-09 09:33:15,153 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:15,153 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [594989955] [2021-11-09 09:33:15,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:15,154 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:15,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:15,158 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:15,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:15,162 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:15,163 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:15,163 INFO L85 PathProgramCache]: Analyzing trace with hash 38449199, now seen corresponding path program 2 times [2021-11-09 09:33:15,163 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:15,164 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [536526945] [2021-11-09 09:33:15,164 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:15,164 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:15,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:15,201 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:15,202 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:15,202 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [536526945] [2021-11-09 09:33:15,203 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [536526945] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:15,203 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2019119529] [2021-11-09 09:33:15,203 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:33:15,203 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:15,204 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:15,205 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:15,227 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2021-11-09 09:33:15,239 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:33:15,240 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:15,240 INFO L263 TraceCheckSpWp]: Trace formula consists of 14 conjuncts, 4 conjunts are in the unsatisfiable core [2021-11-09 09:33:15,241 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:15,263 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:15,264 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2019119529] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:15,264 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:15,264 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 4 [2021-11-09 09:33:15,264 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [556310266] [2021-11-09 09:33:15,265 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:15,265 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:15,266 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-09 09:33:15,266 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2021-11-09 09:33:15,266 INFO L87 Difference]: Start difference. First operand 6 states and 7 transitions. cyclomatic complexity: 2 Second operand has 5 states, 5 states have (on average 1.0) internal successors, (5), 4 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:15,298 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:15,298 INFO L93 Difference]: Finished difference Result 7 states and 8 transitions. [2021-11-09 09:33:15,298 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-11-09 09:33:15,298 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7 states and 8 transitions. [2021-11-09 09:33:15,299 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6 [2021-11-09 09:33:15,299 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7 states to 7 states and 8 transitions. [2021-11-09 09:33:15,300 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7 [2021-11-09 09:33:15,300 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2021-11-09 09:33:15,300 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7 states and 8 transitions. [2021-11-09 09:33:15,300 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:15,300 INFO L681 BuchiCegarLoop]: Abstraction has 7 states and 8 transitions. [2021-11-09 09:33:15,300 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7 states and 8 transitions. [2021-11-09 09:33:15,301 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7 to 7. [2021-11-09 09:33:15,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 1.1428571428571428) internal successors, (8), 6 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:15,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 8 transitions. [2021-11-09 09:33:15,302 INFO L704 BuchiCegarLoop]: Abstraction has 7 states and 8 transitions. [2021-11-09 09:33:15,302 INFO L587 BuchiCegarLoop]: Abstraction has 7 states and 8 transitions. [2021-11-09 09:33:15,302 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-09 09:33:15,302 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7 states and 8 transitions. [2021-11-09 09:33:15,303 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 6 [2021-11-09 09:33:15,303 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:15,303 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:15,303 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:15,303 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [3, 1, 1, 1] [2021-11-09 09:33:15,304 INFO L791 eck$LassoCheckResult]: Stem: 89#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 86#L19-2 [2021-11-09 09:33:15,304 INFO L793 eck$LassoCheckResult]: Loop: 86#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 87#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 90#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 92#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 91#L21-2 assume !(main_~x2~0 > 1); 88#L21-3 main_~x1~0 := 1 + main_~x1~0; 86#L19-2 [2021-11-09 09:33:15,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:15,304 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 4 times [2021-11-09 09:33:15,305 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:15,305 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [122323151] [2021-11-09 09:33:15,305 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:15,305 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:15,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:15,309 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:15,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:15,328 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:15,329 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:15,329 INFO L85 PathProgramCache]: Analyzing trace with hash 1191926928, now seen corresponding path program 3 times [2021-11-09 09:33:15,329 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:15,330 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203772352] [2021-11-09 09:33:15,330 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:15,330 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:15,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:15,397 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:15,397 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:15,397 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1203772352] [2021-11-09 09:33:15,399 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1203772352] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:15,402 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1163071188] [2021-11-09 09:33:15,402 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:33:15,403 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:15,403 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:15,438 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:15,455 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2021-11-09 09:33:15,473 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2021-11-09 09:33:15,474 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:15,474 INFO L263 TraceCheckSpWp]: Trace formula consists of 17 conjuncts, 5 conjunts are in the unsatisfiable core [2021-11-09 09:33:15,475 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:15,528 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:15,528 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1163071188] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:15,529 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:15,529 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2021-11-09 09:33:15,529 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [105399101] [2021-11-09 09:33:15,529 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:15,530 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:15,530 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-11-09 09:33:15,531 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2021-11-09 09:33:15,531 INFO L87 Difference]: Start difference. First operand 7 states and 8 transitions. cyclomatic complexity: 2 Second operand has 6 states, 6 states have (on average 1.0) internal successors, (6), 5 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:15,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:15,542 INFO L93 Difference]: Finished difference Result 8 states and 9 transitions. [2021-11-09 09:33:15,543 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-09 09:33:15,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8 states and 9 transitions. [2021-11-09 09:33:15,543 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 7 [2021-11-09 09:33:15,544 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8 states to 8 states and 9 transitions. [2021-11-09 09:33:15,544 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2021-11-09 09:33:15,544 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2021-11-09 09:33:15,544 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8 states and 9 transitions. [2021-11-09 09:33:15,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:15,545 INFO L681 BuchiCegarLoop]: Abstraction has 8 states and 9 transitions. [2021-11-09 09:33:15,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8 states and 9 transitions. [2021-11-09 09:33:15,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8 to 8. [2021-11-09 09:33:15,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 1.125) internal successors, (9), 7 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:15,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 9 transitions. [2021-11-09 09:33:15,546 INFO L704 BuchiCegarLoop]: Abstraction has 8 states and 9 transitions. [2021-11-09 09:33:15,546 INFO L587 BuchiCegarLoop]: Abstraction has 8 states and 9 transitions. [2021-11-09 09:33:15,547 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-09 09:33:15,547 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8 states and 9 transitions. [2021-11-09 09:33:15,547 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 7 [2021-11-09 09:33:15,547 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:15,547 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:15,548 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:15,548 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [4, 1, 1, 1] [2021-11-09 09:33:15,548 INFO L791 eck$LassoCheckResult]: Stem: 128#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 125#L19-2 [2021-11-09 09:33:15,548 INFO L793 eck$LassoCheckResult]: Loop: 125#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 126#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 129#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 132#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 131#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 130#L21-2 assume !(main_~x2~0 > 1); 127#L21-3 main_~x1~0 := 1 + main_~x1~0; 125#L19-2 [2021-11-09 09:33:15,549 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:15,549 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 5 times [2021-11-09 09:33:15,549 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:15,549 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [999738909] [2021-11-09 09:33:15,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:15,550 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:15,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:15,554 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:15,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:15,557 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:15,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:15,558 INFO L85 PathProgramCache]: Analyzing trace with hash -1704969137, now seen corresponding path program 4 times [2021-11-09 09:33:15,558 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:15,558 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1700176433] [2021-11-09 09:33:15,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:15,559 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:15,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:15,647 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:15,648 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:15,648 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1700176433] [2021-11-09 09:33:15,648 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1700176433] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:15,648 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1416464821] [2021-11-09 09:33:15,648 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:33:15,649 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:15,649 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:15,650 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:15,669 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2021-11-09 09:33:15,704 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:33:15,704 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:15,705 INFO L263 TraceCheckSpWp]: Trace formula consists of 20 conjuncts, 6 conjunts are in the unsatisfiable core [2021-11-09 09:33:15,705 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:15,753 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:15,753 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1416464821] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:15,753 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:15,754 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2021-11-09 09:33:15,754 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [109289019] [2021-11-09 09:33:15,754 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:15,755 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:15,755 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2021-11-09 09:33:15,755 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2021-11-09 09:33:15,756 INFO L87 Difference]: Start difference. First operand 8 states and 9 transitions. cyclomatic complexity: 2 Second operand has 7 states, 7 states have (on average 1.0) internal successors, (7), 6 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:15,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:15,779 INFO L93 Difference]: Finished difference Result 9 states and 10 transitions. [2021-11-09 09:33:15,779 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-11-09 09:33:15,779 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9 states and 10 transitions. [2021-11-09 09:33:15,781 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 8 [2021-11-09 09:33:15,782 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9 states to 9 states and 10 transitions. [2021-11-09 09:33:15,783 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2021-11-09 09:33:15,783 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2021-11-09 09:33:15,784 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9 states and 10 transitions. [2021-11-09 09:33:15,784 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:15,785 INFO L681 BuchiCegarLoop]: Abstraction has 9 states and 10 transitions. [2021-11-09 09:33:15,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states and 10 transitions. [2021-11-09 09:33:15,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 9. [2021-11-09 09:33:15,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 8 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:15,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 10 transitions. [2021-11-09 09:33:15,787 INFO L704 BuchiCegarLoop]: Abstraction has 9 states and 10 transitions. [2021-11-09 09:33:15,787 INFO L587 BuchiCegarLoop]: Abstraction has 9 states and 10 transitions. [2021-11-09 09:33:15,788 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-09 09:33:15,788 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9 states and 10 transitions. [2021-11-09 09:33:15,789 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 8 [2021-11-09 09:33:15,789 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:15,790 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:15,791 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:15,791 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [5, 1, 1, 1] [2021-11-09 09:33:15,791 INFO L791 eck$LassoCheckResult]: Stem: 173#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 170#L19-2 [2021-11-09 09:33:15,792 INFO L793 eck$LassoCheckResult]: Loop: 170#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 171#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 174#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 178#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 177#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 176#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 175#L21-2 assume !(main_~x2~0 > 1); 172#L21-3 main_~x1~0 := 1 + main_~x1~0; 170#L19-2 [2021-11-09 09:33:15,792 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:15,793 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 6 times [2021-11-09 09:33:15,793 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:15,793 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1106729880] [2021-11-09 09:33:15,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:15,794 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:15,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:15,805 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:15,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:15,808 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:15,808 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:15,809 INFO L85 PathProgramCache]: Analyzing trace with hash -1314433936, now seen corresponding path program 5 times [2021-11-09 09:33:15,809 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:15,809 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [198535048] [2021-11-09 09:33:15,809 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:15,809 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:15,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:15,970 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:15,970 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:15,970 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [198535048] [2021-11-09 09:33:15,971 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [198535048] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:15,971 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1117661292] [2021-11-09 09:33:15,972 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:33:15,972 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:15,972 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:15,977 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:15,996 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2021-11-09 09:33:16,027 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2021-11-09 09:33:16,027 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:16,028 INFO L263 TraceCheckSpWp]: Trace formula consists of 23 conjuncts, 7 conjunts are in the unsatisfiable core [2021-11-09 09:33:16,028 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:16,086 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:16,087 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1117661292] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:16,088 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:16,088 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 7 [2021-11-09 09:33:16,089 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1606485967] [2021-11-09 09:33:16,093 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:16,093 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:16,094 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2021-11-09 09:33:16,094 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2021-11-09 09:33:16,095 INFO L87 Difference]: Start difference. First operand 9 states and 10 transitions. cyclomatic complexity: 2 Second operand has 8 states, 8 states have (on average 1.0) internal successors, (8), 7 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:16,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:16,107 INFO L93 Difference]: Finished difference Result 10 states and 11 transitions. [2021-11-09 09:33:16,107 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2021-11-09 09:33:16,107 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10 states and 11 transitions. [2021-11-09 09:33:16,108 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 9 [2021-11-09 09:33:16,108 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10 states to 10 states and 11 transitions. [2021-11-09 09:33:16,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2021-11-09 09:33:16,108 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2021-11-09 09:33:16,109 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10 states and 11 transitions. [2021-11-09 09:33:16,109 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:16,109 INFO L681 BuchiCegarLoop]: Abstraction has 10 states and 11 transitions. [2021-11-09 09:33:16,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10 states and 11 transitions. [2021-11-09 09:33:16,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10 to 10. [2021-11-09 09:33:16,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 1.1) internal successors, (11), 9 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:16,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 11 transitions. [2021-11-09 09:33:16,111 INFO L704 BuchiCegarLoop]: Abstraction has 10 states and 11 transitions. [2021-11-09 09:33:16,111 INFO L587 BuchiCegarLoop]: Abstraction has 10 states and 11 transitions. [2021-11-09 09:33:16,111 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-09 09:33:16,111 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10 states and 11 transitions. [2021-11-09 09:33:16,111 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 9 [2021-11-09 09:33:16,111 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:16,112 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:16,112 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:16,112 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [6, 1, 1, 1] [2021-11-09 09:33:16,112 INFO L791 eck$LassoCheckResult]: Stem: 224#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 221#L19-2 [2021-11-09 09:33:16,112 INFO L793 eck$LassoCheckResult]: Loop: 221#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 222#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 225#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 230#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 229#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 228#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 227#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 226#L21-2 assume !(main_~x2~0 > 1); 223#L21-3 main_~x1~0 := 1 + main_~x1~0; 221#L19-2 [2021-11-09 09:33:16,113 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:16,113 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 7 times [2021-11-09 09:33:16,113 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:16,113 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [481104521] [2021-11-09 09:33:16,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:16,114 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:16,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:16,117 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:16,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:16,120 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:16,120 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:16,120 INFO L85 PathProgramCache]: Analyzing trace with hash -2092744593, now seen corresponding path program 6 times [2021-11-09 09:33:16,120 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:16,121 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [137664282] [2021-11-09 09:33:16,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:16,121 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:16,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:16,266 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:16,280 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:16,280 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [137664282] [2021-11-09 09:33:16,280 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [137664282] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:16,281 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [604477527] [2021-11-09 09:33:16,281 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:33:16,281 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:16,281 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:16,308 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:16,320 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2021-11-09 09:33:16,378 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 4 check-sat command(s) [2021-11-09 09:33:16,378 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:16,379 INFO L263 TraceCheckSpWp]: Trace formula consists of 26 conjuncts, 8 conjunts are in the unsatisfiable core [2021-11-09 09:33:16,379 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:16,452 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:16,453 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [604477527] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:16,453 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:16,453 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 8 [2021-11-09 09:33:16,453 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2072980006] [2021-11-09 09:33:16,454 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:16,454 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:16,454 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2021-11-09 09:33:16,455 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2021-11-09 09:33:16,455 INFO L87 Difference]: Start difference. First operand 10 states and 11 transitions. cyclomatic complexity: 2 Second operand has 9 states, 9 states have (on average 1.0) internal successors, (9), 8 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:16,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:16,471 INFO L93 Difference]: Finished difference Result 11 states and 12 transitions. [2021-11-09 09:33:16,471 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2021-11-09 09:33:16,471 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11 states and 12 transitions. [2021-11-09 09:33:16,472 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 10 [2021-11-09 09:33:16,472 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11 states to 11 states and 12 transitions. [2021-11-09 09:33:16,473 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2021-11-09 09:33:16,473 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2021-11-09 09:33:16,473 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11 states and 12 transitions. [2021-11-09 09:33:16,473 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:16,473 INFO L681 BuchiCegarLoop]: Abstraction has 11 states and 12 transitions. [2021-11-09 09:33:16,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11 states and 12 transitions. [2021-11-09 09:33:16,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11 to 11. [2021-11-09 09:33:16,474 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 1.0909090909090908) internal successors, (12), 10 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:16,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 12 transitions. [2021-11-09 09:33:16,475 INFO L704 BuchiCegarLoop]: Abstraction has 11 states and 12 transitions. [2021-11-09 09:33:16,475 INFO L587 BuchiCegarLoop]: Abstraction has 11 states and 12 transitions. [2021-11-09 09:33:16,475 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-09 09:33:16,475 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11 states and 12 transitions. [2021-11-09 09:33:16,476 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 10 [2021-11-09 09:33:16,476 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:16,476 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:16,476 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:16,476 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [7, 1, 1, 1] [2021-11-09 09:33:16,476 INFO L791 eck$LassoCheckResult]: Stem: 281#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 278#L19-2 [2021-11-09 09:33:16,477 INFO L793 eck$LassoCheckResult]: Loop: 278#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 279#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 282#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 288#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 287#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 286#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 285#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 284#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 283#L21-2 assume !(main_~x2~0 > 1); 280#L21-3 main_~x1~0 := 1 + main_~x1~0; 278#L19-2 [2021-11-09 09:33:16,477 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:16,477 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 8 times [2021-11-09 09:33:16,477 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:16,477 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1441230729] [2021-11-09 09:33:16,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:16,478 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:16,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:16,486 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:16,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:16,495 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:16,496 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:16,496 INFO L85 PathProgramCache]: Analyzing trace with hash -450571184, now seen corresponding path program 7 times [2021-11-09 09:33:16,496 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:16,497 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1929848185] [2021-11-09 09:33:16,497 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:16,497 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:16,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:16,613 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:16,614 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:16,615 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1929848185] [2021-11-09 09:33:16,615 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1929848185] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:16,615 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2073369708] [2021-11-09 09:33:16,615 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:33:16,615 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:16,616 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:16,618 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:16,641 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2021-11-09 09:33:16,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:16,670 INFO L263 TraceCheckSpWp]: Trace formula consists of 29 conjuncts, 9 conjunts are in the unsatisfiable core [2021-11-09 09:33:16,670 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:16,732 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:16,732 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2073369708] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:16,732 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:16,732 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 9 [2021-11-09 09:33:16,733 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1924256313] [2021-11-09 09:33:16,733 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:16,733 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:16,734 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2021-11-09 09:33:16,734 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2021-11-09 09:33:16,734 INFO L87 Difference]: Start difference. First operand 11 states and 12 transitions. cyclomatic complexity: 2 Second operand has 10 states, 10 states have (on average 1.0) internal successors, (10), 9 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:16,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:16,757 INFO L93 Difference]: Finished difference Result 12 states and 13 transitions. [2021-11-09 09:33:16,758 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-11-09 09:33:16,758 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12 states and 13 transitions. [2021-11-09 09:33:16,758 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 11 [2021-11-09 09:33:16,759 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12 states to 12 states and 13 transitions. [2021-11-09 09:33:16,759 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12 [2021-11-09 09:33:16,759 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12 [2021-11-09 09:33:16,759 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 13 transitions. [2021-11-09 09:33:16,760 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:16,760 INFO L681 BuchiCegarLoop]: Abstraction has 12 states and 13 transitions. [2021-11-09 09:33:16,760 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 13 transitions. [2021-11-09 09:33:16,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 12. [2021-11-09 09:33:16,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 1.0833333333333333) internal successors, (13), 11 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:16,761 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 13 transitions. [2021-11-09 09:33:16,762 INFO L704 BuchiCegarLoop]: Abstraction has 12 states and 13 transitions. [2021-11-09 09:33:16,762 INFO L587 BuchiCegarLoop]: Abstraction has 12 states and 13 transitions. [2021-11-09 09:33:16,762 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-09 09:33:16,762 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12 states and 13 transitions. [2021-11-09 09:33:16,762 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 11 [2021-11-09 09:33:16,763 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:16,763 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:16,763 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:16,763 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [8, 1, 1, 1] [2021-11-09 09:33:16,763 INFO L791 eck$LassoCheckResult]: Stem: 344#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 341#L19-2 [2021-11-09 09:33:16,763 INFO L793 eck$LassoCheckResult]: Loop: 341#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 342#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 345#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 352#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 351#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 350#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 349#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 348#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 347#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 346#L21-2 assume !(main_~x2~0 > 1); 343#L21-3 main_~x1~0 := 1 + main_~x1~0; 341#L19-2 [2021-11-09 09:33:16,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:16,764 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 9 times [2021-11-09 09:33:16,764 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:16,764 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1295746084] [2021-11-09 09:33:16,765 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:16,765 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:16,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:16,772 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:16,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:16,775 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:16,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:16,776 INFO L85 PathProgramCache]: Analyzing trace with hash -1082803057, now seen corresponding path program 8 times [2021-11-09 09:33:16,776 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:16,776 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [174011631] [2021-11-09 09:33:16,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:16,776 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:16,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:16,898 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:16,898 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:16,898 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [174011631] [2021-11-09 09:33:16,899 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [174011631] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:16,899 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [879766405] [2021-11-09 09:33:16,899 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:33:16,899 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:16,899 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:16,901 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:16,912 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2021-11-09 09:33:16,965 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:33:16,965 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:16,966 INFO L263 TraceCheckSpWp]: Trace formula consists of 32 conjuncts, 10 conjunts are in the unsatisfiable core [2021-11-09 09:33:16,967 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:17,016 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:17,016 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [879766405] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:17,016 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:17,016 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 10 [2021-11-09 09:33:17,016 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1381321481] [2021-11-09 09:33:17,017 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:17,017 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:17,018 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2021-11-09 09:33:17,018 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2021-11-09 09:33:17,018 INFO L87 Difference]: Start difference. First operand 12 states and 13 transitions. cyclomatic complexity: 2 Second operand has 11 states, 11 states have (on average 1.0) internal successors, (11), 10 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:17,042 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:17,043 INFO L93 Difference]: Finished difference Result 13 states and 14 transitions. [2021-11-09 09:33:17,043 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-11-09 09:33:17,043 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13 states and 14 transitions. [2021-11-09 09:33:17,044 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 12 [2021-11-09 09:33:17,044 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13 states to 13 states and 14 transitions. [2021-11-09 09:33:17,044 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-11-09 09:33:17,045 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-11-09 09:33:17,045 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13 states and 14 transitions. [2021-11-09 09:33:17,045 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:17,045 INFO L681 BuchiCegarLoop]: Abstraction has 13 states and 14 transitions. [2021-11-09 09:33:17,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states and 14 transitions. [2021-11-09 09:33:17,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2021-11-09 09:33:17,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13 states, 13 states have (on average 1.0769230769230769) internal successors, (14), 12 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:17,047 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 14 transitions. [2021-11-09 09:33:17,047 INFO L704 BuchiCegarLoop]: Abstraction has 13 states and 14 transitions. [2021-11-09 09:33:17,047 INFO L587 BuchiCegarLoop]: Abstraction has 13 states and 14 transitions. [2021-11-09 09:33:17,049 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-09 09:33:17,049 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13 states and 14 transitions. [2021-11-09 09:33:17,049 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 12 [2021-11-09 09:33:17,050 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:17,050 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:17,050 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:17,050 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [9, 1, 1, 1] [2021-11-09 09:33:17,050 INFO L791 eck$LassoCheckResult]: Stem: 413#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 410#L19-2 [2021-11-09 09:33:17,051 INFO L793 eck$LassoCheckResult]: Loop: 410#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 411#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 414#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 422#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 421#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 420#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 419#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 418#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 417#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 416#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 415#L21-2 assume !(main_~x2~0 > 1); 412#L21-3 main_~x1~0 := 1 + main_~x1~0; 410#L19-2 [2021-11-09 09:33:17,051 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:17,051 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 10 times [2021-11-09 09:33:17,051 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:17,051 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052795826] [2021-11-09 09:33:17,052 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:17,052 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:17,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:17,055 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:17,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:17,057 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:17,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:17,058 INFO L85 PathProgramCache]: Analyzing trace with hash 792845360, now seen corresponding path program 9 times [2021-11-09 09:33:17,058 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:17,058 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1283860431] [2021-11-09 09:33:17,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:17,059 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:17,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:17,190 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:17,190 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:17,190 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1283860431] [2021-11-09 09:33:17,191 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1283860431] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:17,191 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1410470636] [2021-11-09 09:33:17,191 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:33:17,191 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:17,191 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:17,197 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:17,220 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2021-11-09 09:33:17,255 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2021-11-09 09:33:17,255 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:17,256 INFO L263 TraceCheckSpWp]: Trace formula consists of 35 conjuncts, 11 conjunts are in the unsatisfiable core [2021-11-09 09:33:17,257 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:17,324 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:17,325 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1410470636] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:17,325 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:17,325 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 11 [2021-11-09 09:33:17,325 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2083623716] [2021-11-09 09:33:17,326 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:17,326 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:17,332 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2021-11-09 09:33:17,333 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2021-11-09 09:33:17,333 INFO L87 Difference]: Start difference. First operand 13 states and 14 transitions. cyclomatic complexity: 2 Second operand has 12 states, 12 states have (on average 1.0) internal successors, (12), 11 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:17,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:17,350 INFO L93 Difference]: Finished difference Result 14 states and 15 transitions. [2021-11-09 09:33:17,350 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2021-11-09 09:33:17,351 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14 states and 15 transitions. [2021-11-09 09:33:17,351 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 13 [2021-11-09 09:33:17,352 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14 states to 14 states and 15 transitions. [2021-11-09 09:33:17,352 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2021-11-09 09:33:17,352 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2021-11-09 09:33:17,353 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14 states and 15 transitions. [2021-11-09 09:33:17,353 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:17,353 INFO L681 BuchiCegarLoop]: Abstraction has 14 states and 15 transitions. [2021-11-09 09:33:17,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states and 15 transitions. [2021-11-09 09:33:17,354 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 14. [2021-11-09 09:33:17,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.0714285714285714) internal successors, (15), 13 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:17,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 15 transitions. [2021-11-09 09:33:17,355 INFO L704 BuchiCegarLoop]: Abstraction has 14 states and 15 transitions. [2021-11-09 09:33:17,355 INFO L587 BuchiCegarLoop]: Abstraction has 14 states and 15 transitions. [2021-11-09 09:33:17,356 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-09 09:33:17,356 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14 states and 15 transitions. [2021-11-09 09:33:17,356 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 13 [2021-11-09 09:33:17,356 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:17,357 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:17,357 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:17,357 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [10, 1, 1, 1] [2021-11-09 09:33:17,357 INFO L791 eck$LassoCheckResult]: Stem: 488#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 485#L19-2 [2021-11-09 09:33:17,358 INFO L793 eck$LassoCheckResult]: Loop: 485#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 486#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 489#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 498#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 497#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 496#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 495#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 494#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 493#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 492#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 491#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 490#L21-2 assume !(main_~x2~0 > 1); 487#L21-3 main_~x1~0 := 1 + main_~x1~0; 485#L19-2 [2021-11-09 09:33:17,358 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:17,358 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 11 times [2021-11-09 09:33:17,358 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:17,359 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1778654418] [2021-11-09 09:33:17,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:17,359 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:17,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:17,362 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:17,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:17,365 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:17,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:17,365 INFO L85 PathProgramCache]: Analyzing trace with hash -1191595857, now seen corresponding path program 10 times [2021-11-09 09:33:17,366 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:17,366 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1686763489] [2021-11-09 09:33:17,366 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:17,366 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:17,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:17,468 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:17,468 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:17,468 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1686763489] [2021-11-09 09:33:17,468 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1686763489] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:17,469 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1227236906] [2021-11-09 09:33:17,469 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:33:17,469 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:17,469 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:17,472 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:17,496 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2021-11-09 09:33:17,534 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:33:17,534 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:17,535 INFO L263 TraceCheckSpWp]: Trace formula consists of 38 conjuncts, 12 conjunts are in the unsatisfiable core [2021-11-09 09:33:17,536 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:17,601 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:17,601 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1227236906] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:17,601 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:17,601 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 12 [2021-11-09 09:33:17,602 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1464123320] [2021-11-09 09:33:17,602 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:17,602 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:17,603 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2021-11-09 09:33:17,603 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2021-11-09 09:33:17,603 INFO L87 Difference]: Start difference. First operand 14 states and 15 transitions. cyclomatic complexity: 2 Second operand has 13 states, 13 states have (on average 1.0) internal successors, (13), 12 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:17,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:17,628 INFO L93 Difference]: Finished difference Result 15 states and 16 transitions. [2021-11-09 09:33:17,629 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2021-11-09 09:33:17,629 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 16 transitions. [2021-11-09 09:33:17,629 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 14 [2021-11-09 09:33:17,630 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 15 states and 16 transitions. [2021-11-09 09:33:17,630 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2021-11-09 09:33:17,630 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2021-11-09 09:33:17,630 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15 states and 16 transitions. [2021-11-09 09:33:17,630 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:17,631 INFO L681 BuchiCegarLoop]: Abstraction has 15 states and 16 transitions. [2021-11-09 09:33:17,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states and 16 transitions. [2021-11-09 09:33:17,632 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 15. [2021-11-09 09:33:17,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 1.0666666666666667) internal successors, (16), 14 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:17,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 16 transitions. [2021-11-09 09:33:17,633 INFO L704 BuchiCegarLoop]: Abstraction has 15 states and 16 transitions. [2021-11-09 09:33:17,633 INFO L587 BuchiCegarLoop]: Abstraction has 15 states and 16 transitions. [2021-11-09 09:33:17,633 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-09 09:33:17,633 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15 states and 16 transitions. [2021-11-09 09:33:17,633 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 14 [2021-11-09 09:33:17,634 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:17,634 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:17,634 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:17,634 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [11, 1, 1, 1] [2021-11-09 09:33:17,634 INFO L791 eck$LassoCheckResult]: Stem: 569#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 566#L19-2 [2021-11-09 09:33:17,634 INFO L793 eck$LassoCheckResult]: Loop: 566#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 567#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 570#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 580#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 579#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 578#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 577#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 576#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 575#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 574#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 573#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 572#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 571#L21-2 assume !(main_~x2~0 > 1); 568#L21-3 main_~x1~0 := 1 + main_~x1~0; 566#L19-2 [2021-11-09 09:33:17,635 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:17,635 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 12 times [2021-11-09 09:33:17,635 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:17,635 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [272751094] [2021-11-09 09:33:17,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:17,636 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:17,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:17,639 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:17,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:17,642 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:17,642 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:17,642 INFO L85 PathProgramCache]: Analyzing trace with hash 1715235856, now seen corresponding path program 11 times [2021-11-09 09:33:17,643 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:17,643 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2093129131] [2021-11-09 09:33:17,643 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:17,643 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:17,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:17,758 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:17,759 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:17,759 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2093129131] [2021-11-09 09:33:17,759 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2093129131] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:17,760 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1275173729] [2021-11-09 09:33:17,760 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:33:17,760 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:17,760 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:17,762 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:17,793 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2021-11-09 09:33:17,839 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2021-11-09 09:33:17,839 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:17,840 INFO L263 TraceCheckSpWp]: Trace formula consists of 41 conjuncts, 13 conjunts are in the unsatisfiable core [2021-11-09 09:33:17,841 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:17,916 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:17,917 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1275173729] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:17,917 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:17,917 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 13 [2021-11-09 09:33:17,917 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [84214469] [2021-11-09 09:33:17,917 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:17,918 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:17,918 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2021-11-09 09:33:17,918 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2021-11-09 09:33:17,919 INFO L87 Difference]: Start difference. First operand 15 states and 16 transitions. cyclomatic complexity: 2 Second operand has 14 states, 14 states have (on average 1.0) internal successors, (14), 13 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:17,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:17,946 INFO L93 Difference]: Finished difference Result 16 states and 17 transitions. [2021-11-09 09:33:17,946 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2021-11-09 09:33:17,947 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16 states and 17 transitions. [2021-11-09 09:33:17,952 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 15 [2021-11-09 09:33:17,955 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16 states to 16 states and 17 transitions. [2021-11-09 09:33:17,955 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2021-11-09 09:33:17,956 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2021-11-09 09:33:17,956 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16 states and 17 transitions. [2021-11-09 09:33:17,956 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:17,956 INFO L681 BuchiCegarLoop]: Abstraction has 16 states and 17 transitions. [2021-11-09 09:33:17,956 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states and 17 transitions. [2021-11-09 09:33:17,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 16. [2021-11-09 09:33:17,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.0625) internal successors, (17), 15 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:17,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 17 transitions. [2021-11-09 09:33:17,959 INFO L704 BuchiCegarLoop]: Abstraction has 16 states and 17 transitions. [2021-11-09 09:33:17,960 INFO L587 BuchiCegarLoop]: Abstraction has 16 states and 17 transitions. [2021-11-09 09:33:17,960 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-09 09:33:17,960 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16 states and 17 transitions. [2021-11-09 09:33:17,960 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 15 [2021-11-09 09:33:17,960 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:17,960 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:17,962 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:17,962 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [12, 1, 1, 1] [2021-11-09 09:33:17,963 INFO L791 eck$LassoCheckResult]: Stem: 656#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 653#L19-2 [2021-11-09 09:33:17,963 INFO L793 eck$LassoCheckResult]: Loop: 653#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 654#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 657#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 668#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 667#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 666#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 665#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 664#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 663#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 662#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 661#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 660#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 659#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 658#L21-2 assume !(main_~x2~0 > 1); 655#L21-3 main_~x1~0 := 1 + main_~x1~0; 653#L19-2 [2021-11-09 09:33:17,963 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:17,963 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 13 times [2021-11-09 09:33:17,963 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:17,966 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [804686645] [2021-11-09 09:33:17,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:17,966 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:17,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:17,970 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:17,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:17,973 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:17,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:17,974 INFO L85 PathProgramCache]: Analyzing trace with hash 1632705743, now seen corresponding path program 12 times [2021-11-09 09:33:17,974 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:17,974 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [637958089] [2021-11-09 09:33:17,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:17,974 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:18,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:18,144 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:18,144 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:18,144 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [637958089] [2021-11-09 09:33:18,144 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [637958089] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:18,144 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1890394448] [2021-11-09 09:33:18,144 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:33:18,145 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:18,145 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:18,148 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:18,172 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2021-11-09 09:33:18,220 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2021-11-09 09:33:18,220 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:18,220 INFO L263 TraceCheckSpWp]: Trace formula consists of 44 conjuncts, 14 conjunts are in the unsatisfiable core [2021-11-09 09:33:18,221 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:18,284 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:18,284 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1890394448] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:18,284 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:18,285 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 14 [2021-11-09 09:33:18,285 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1712172524] [2021-11-09 09:33:18,289 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:18,290 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:18,290 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2021-11-09 09:33:18,291 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2021-11-09 09:33:18,293 INFO L87 Difference]: Start difference. First operand 16 states and 17 transitions. cyclomatic complexity: 2 Second operand has 15 states, 15 states have (on average 1.0) internal successors, (15), 14 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:18,309 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:18,310 INFO L93 Difference]: Finished difference Result 17 states and 18 transitions. [2021-11-09 09:33:18,310 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-11-09 09:33:18,310 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17 states and 18 transitions. [2021-11-09 09:33:18,310 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 16 [2021-11-09 09:33:18,311 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17 states to 17 states and 18 transitions. [2021-11-09 09:33:18,311 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17 [2021-11-09 09:33:18,311 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2021-11-09 09:33:18,311 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17 states and 18 transitions. [2021-11-09 09:33:18,311 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:18,311 INFO L681 BuchiCegarLoop]: Abstraction has 17 states and 18 transitions. [2021-11-09 09:33:18,311 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states and 18 transitions. [2021-11-09 09:33:18,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 17. [2021-11-09 09:33:18,313 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.0588235294117647) internal successors, (18), 16 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:18,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 18 transitions. [2021-11-09 09:33:18,313 INFO L704 BuchiCegarLoop]: Abstraction has 17 states and 18 transitions. [2021-11-09 09:33:18,313 INFO L587 BuchiCegarLoop]: Abstraction has 17 states and 18 transitions. [2021-11-09 09:33:18,313 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-09 09:33:18,313 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17 states and 18 transitions. [2021-11-09 09:33:18,314 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 16 [2021-11-09 09:33:18,314 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:18,314 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:18,314 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:18,314 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [13, 1, 1, 1] [2021-11-09 09:33:18,314 INFO L791 eck$LassoCheckResult]: Stem: 749#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 746#L19-2 [2021-11-09 09:33:18,314 INFO L793 eck$LassoCheckResult]: Loop: 746#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 747#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 750#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 762#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 761#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 760#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 759#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 758#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 757#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 756#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 755#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 754#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 753#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 752#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 751#L21-2 assume !(main_~x2~0 > 1); 748#L21-3 main_~x1~0 := 1 + main_~x1~0; 746#L19-2 [2021-11-09 09:33:18,315 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:18,315 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 14 times [2021-11-09 09:33:18,315 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:18,315 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [393690620] [2021-11-09 09:33:18,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:18,315 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:18,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:18,318 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:18,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:18,320 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:18,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:18,321 INFO L85 PathProgramCache]: Analyzing trace with hash -925727760, now seen corresponding path program 13 times [2021-11-09 09:33:18,321 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:18,321 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1314708631] [2021-11-09 09:33:18,321 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:18,321 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:18,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:18,468 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:18,468 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:18,468 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1314708631] [2021-11-09 09:33:18,468 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1314708631] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:18,469 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [137543903] [2021-11-09 09:33:18,469 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:33:18,469 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:18,469 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:18,470 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:18,495 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2021-11-09 09:33:18,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:18,553 INFO L263 TraceCheckSpWp]: Trace formula consists of 47 conjuncts, 15 conjunts are in the unsatisfiable core [2021-11-09 09:33:18,554 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:18,613 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:18,614 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [137543903] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:18,614 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:18,614 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 15 [2021-11-09 09:33:18,614 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [237829457] [2021-11-09 09:33:18,615 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:18,615 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:18,615 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2021-11-09 09:33:18,615 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2021-11-09 09:33:18,616 INFO L87 Difference]: Start difference. First operand 17 states and 18 transitions. cyclomatic complexity: 2 Second operand has 16 states, 16 states have (on average 1.0) internal successors, (16), 15 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:18,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:18,637 INFO L93 Difference]: Finished difference Result 18 states and 19 transitions. [2021-11-09 09:33:18,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2021-11-09 09:33:18,638 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18 states and 19 transitions. [2021-11-09 09:33:18,638 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 17 [2021-11-09 09:33:18,639 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18 states to 18 states and 19 transitions. [2021-11-09 09:33:18,639 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18 [2021-11-09 09:33:18,639 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18 [2021-11-09 09:33:18,639 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18 states and 19 transitions. [2021-11-09 09:33:18,639 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:18,640 INFO L681 BuchiCegarLoop]: Abstraction has 18 states and 19 transitions. [2021-11-09 09:33:18,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states and 19 transitions. [2021-11-09 09:33:18,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 18. [2021-11-09 09:33:18,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 18 states have (on average 1.0555555555555556) internal successors, (19), 17 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:18,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 19 transitions. [2021-11-09 09:33:18,642 INFO L704 BuchiCegarLoop]: Abstraction has 18 states and 19 transitions. [2021-11-09 09:33:18,642 INFO L587 BuchiCegarLoop]: Abstraction has 18 states and 19 transitions. [2021-11-09 09:33:18,642 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-09 09:33:18,642 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18 states and 19 transitions. [2021-11-09 09:33:18,642 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 17 [2021-11-09 09:33:18,643 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:18,643 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:18,643 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:18,643 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [14, 1, 1, 1] [2021-11-09 09:33:18,643 INFO L791 eck$LassoCheckResult]: Stem: 848#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 845#L19-2 [2021-11-09 09:33:18,643 INFO L793 eck$LassoCheckResult]: Loop: 845#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 846#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 849#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 862#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 861#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 860#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 859#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 858#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 857#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 856#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 855#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 854#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 853#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 852#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 851#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 850#L21-2 assume !(main_~x2~0 > 1); 847#L21-3 main_~x1~0 := 1 + main_~x1~0; 845#L19-2 [2021-11-09 09:33:18,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:18,644 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 15 times [2021-11-09 09:33:18,644 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:18,644 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1126724911] [2021-11-09 09:33:18,644 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:18,644 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:18,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:18,648 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:18,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:18,650 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:18,650 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:18,651 INFO L85 PathProgramCache]: Analyzing trace with hash 1367212271, now seen corresponding path program 14 times [2021-11-09 09:33:18,651 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:18,651 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [746539790] [2021-11-09 09:33:18,651 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:18,651 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:18,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:18,835 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:18,835 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:18,835 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [746539790] [2021-11-09 09:33:18,836 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [746539790] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:18,836 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [312983251] [2021-11-09 09:33:18,836 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:33:18,836 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:18,837 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:18,844 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:18,864 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2021-11-09 09:33:18,933 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:33:18,933 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:18,934 INFO L263 TraceCheckSpWp]: Trace formula consists of 50 conjuncts, 16 conjunts are in the unsatisfiable core [2021-11-09 09:33:18,935 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:19,018 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:19,018 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [312983251] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:19,018 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:19,019 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 16 [2021-11-09 09:33:19,019 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1120608243] [2021-11-09 09:33:19,019 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:19,020 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:19,020 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2021-11-09 09:33:19,021 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=136, Invalid=136, Unknown=0, NotChecked=0, Total=272 [2021-11-09 09:33:19,021 INFO L87 Difference]: Start difference. First operand 18 states and 19 transitions. cyclomatic complexity: 2 Second operand has 17 states, 17 states have (on average 1.0) internal successors, (17), 16 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:19,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:19,049 INFO L93 Difference]: Finished difference Result 19 states and 20 transitions. [2021-11-09 09:33:19,049 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2021-11-09 09:33:19,049 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19 states and 20 transitions. [2021-11-09 09:33:19,050 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 18 [2021-11-09 09:33:19,051 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19 states to 19 states and 20 transitions. [2021-11-09 09:33:19,051 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2021-11-09 09:33:19,051 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2021-11-09 09:33:19,051 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19 states and 20 transitions. [2021-11-09 09:33:19,052 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:19,052 INFO L681 BuchiCegarLoop]: Abstraction has 19 states and 20 transitions. [2021-11-09 09:33:19,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states and 20 transitions. [2021-11-09 09:33:19,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 19. [2021-11-09 09:33:19,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.0526315789473684) internal successors, (20), 18 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:19,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 20 transitions. [2021-11-09 09:33:19,054 INFO L704 BuchiCegarLoop]: Abstraction has 19 states and 20 transitions. [2021-11-09 09:33:19,054 INFO L587 BuchiCegarLoop]: Abstraction has 19 states and 20 transitions. [2021-11-09 09:33:19,054 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-09 09:33:19,054 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19 states and 20 transitions. [2021-11-09 09:33:19,055 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 18 [2021-11-09 09:33:19,055 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:19,055 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:19,056 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:19,056 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [15, 1, 1, 1] [2021-11-09 09:33:19,057 INFO L791 eck$LassoCheckResult]: Stem: 953#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 950#L19-2 [2021-11-09 09:33:19,058 INFO L793 eck$LassoCheckResult]: Loop: 950#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 951#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 954#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 968#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 967#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 966#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 965#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 964#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 963#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 962#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 961#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 960#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 959#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 958#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 957#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 956#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 955#L21-2 assume !(main_~x2~0 > 1); 952#L21-3 main_~x1~0 := 1 + main_~x1~0; 950#L19-2 [2021-11-09 09:33:19,058 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:19,058 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 16 times [2021-11-09 09:33:19,058 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:19,059 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1183003182] [2021-11-09 09:33:19,059 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:19,059 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:19,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:19,067 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:19,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:19,071 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:19,072 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:19,072 INFO L85 PathProgramCache]: Analyzing trace with hash -566090800, now seen corresponding path program 15 times [2021-11-09 09:33:19,072 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:19,072 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [692954726] [2021-11-09 09:33:19,072 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:19,072 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:19,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:19,302 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:19,302 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:19,302 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [692954726] [2021-11-09 09:33:19,302 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [692954726] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:19,303 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [141203401] [2021-11-09 09:33:19,303 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:33:19,303 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:19,303 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:19,308 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:19,318 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2021-11-09 09:33:19,407 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2021-11-09 09:33:19,408 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:19,409 INFO L263 TraceCheckSpWp]: Trace formula consists of 53 conjuncts, 17 conjunts are in the unsatisfiable core [2021-11-09 09:33:19,410 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:19,483 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:19,484 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [141203401] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:19,484 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:19,484 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 17 [2021-11-09 09:33:19,484 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1585830323] [2021-11-09 09:33:19,485 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:19,485 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:19,485 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2021-11-09 09:33:19,486 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2021-11-09 09:33:19,486 INFO L87 Difference]: Start difference. First operand 19 states and 20 transitions. cyclomatic complexity: 2 Second operand has 18 states, 18 states have (on average 1.0) internal successors, (18), 17 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:19,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:19,526 INFO L93 Difference]: Finished difference Result 20 states and 21 transitions. [2021-11-09 09:33:19,526 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2021-11-09 09:33:19,527 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20 states and 21 transitions. [2021-11-09 09:33:19,528 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 19 [2021-11-09 09:33:19,529 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20 states to 20 states and 21 transitions. [2021-11-09 09:33:19,529 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20 [2021-11-09 09:33:19,530 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20 [2021-11-09 09:33:19,530 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20 states and 21 transitions. [2021-11-09 09:33:19,530 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:19,530 INFO L681 BuchiCegarLoop]: Abstraction has 20 states and 21 transitions. [2021-11-09 09:33:19,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states and 21 transitions. [2021-11-09 09:33:19,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2021-11-09 09:33:19,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.05) internal successors, (21), 19 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:19,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 21 transitions. [2021-11-09 09:33:19,537 INFO L704 BuchiCegarLoop]: Abstraction has 20 states and 21 transitions. [2021-11-09 09:33:19,537 INFO L587 BuchiCegarLoop]: Abstraction has 20 states and 21 transitions. [2021-11-09 09:33:19,538 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-09 09:33:19,538 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20 states and 21 transitions. [2021-11-09 09:33:19,538 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 19 [2021-11-09 09:33:19,538 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:19,538 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:19,540 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:19,540 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [16, 1, 1, 1] [2021-11-09 09:33:19,540 INFO L791 eck$LassoCheckResult]: Stem: 1064#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 1061#L19-2 [2021-11-09 09:33:19,540 INFO L793 eck$LassoCheckResult]: Loop: 1061#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 1062#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1065#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1080#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1079#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1078#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1077#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1076#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1075#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1074#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1073#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1072#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1071#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1070#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1069#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1068#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1067#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1066#L21-2 assume !(main_~x2~0 > 1); 1063#L21-3 main_~x1~0 := 1 + main_~x1~0; 1061#L19-2 [2021-11-09 09:33:19,541 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:19,541 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 17 times [2021-11-09 09:33:19,541 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:19,541 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [230107255] [2021-11-09 09:33:19,542 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:19,542 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:19,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:19,545 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:19,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:19,549 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:19,549 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:19,550 INFO L85 PathProgramCache]: Analyzing trace with hash -368943857, now seen corresponding path program 16 times [2021-11-09 09:33:19,550 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:19,550 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1452713063] [2021-11-09 09:33:19,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:19,551 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:19,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:19,757 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:19,758 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:19,758 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1452713063] [2021-11-09 09:33:19,758 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1452713063] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:19,758 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1412751532] [2021-11-09 09:33:19,758 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:33:19,758 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:19,758 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:19,760 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:19,768 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2021-11-09 09:33:19,851 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:33:19,851 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:19,852 INFO L263 TraceCheckSpWp]: Trace formula consists of 56 conjuncts, 18 conjunts are in the unsatisfiable core [2021-11-09 09:33:19,853 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:19,923 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:19,923 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1412751532] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:19,923 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:19,923 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 18 [2021-11-09 09:33:19,923 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1923384206] [2021-11-09 09:33:19,924 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:19,924 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:19,924 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2021-11-09 09:33:19,925 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2021-11-09 09:33:19,925 INFO L87 Difference]: Start difference. First operand 20 states and 21 transitions. cyclomatic complexity: 2 Second operand has 19 states, 19 states have (on average 1.0) internal successors, (19), 18 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:19,951 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:19,951 INFO L93 Difference]: Finished difference Result 21 states and 22 transitions. [2021-11-09 09:33:19,951 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2021-11-09 09:33:19,952 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21 states and 22 transitions. [2021-11-09 09:33:19,952 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 20 [2021-11-09 09:33:19,952 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21 states to 21 states and 22 transitions. [2021-11-09 09:33:19,953 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2021-11-09 09:33:19,953 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21 [2021-11-09 09:33:19,953 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21 states and 22 transitions. [2021-11-09 09:33:19,953 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:19,953 INFO L681 BuchiCegarLoop]: Abstraction has 21 states and 22 transitions. [2021-11-09 09:33:19,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states and 22 transitions. [2021-11-09 09:33:19,954 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2021-11-09 09:33:19,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.0476190476190477) internal successors, (22), 20 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:19,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 22 transitions. [2021-11-09 09:33:19,958 INFO L704 BuchiCegarLoop]: Abstraction has 21 states and 22 transitions. [2021-11-09 09:33:19,958 INFO L587 BuchiCegarLoop]: Abstraction has 21 states and 22 transitions. [2021-11-09 09:33:19,958 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-09 09:33:19,958 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 22 transitions. [2021-11-09 09:33:19,958 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 20 [2021-11-09 09:33:19,958 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:19,958 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:19,959 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:19,959 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [17, 1, 1, 1] [2021-11-09 09:33:19,960 INFO L791 eck$LassoCheckResult]: Stem: 1181#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 1178#L19-2 [2021-11-09 09:33:19,960 INFO L793 eck$LassoCheckResult]: Loop: 1178#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 1179#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1182#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1198#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1197#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1196#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1195#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1194#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1193#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1192#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1191#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1190#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1189#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1188#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1187#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1186#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1185#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1184#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1183#L21-2 assume !(main_~x2~0 > 1); 1180#L21-3 main_~x1~0 := 1 + main_~x1~0; 1178#L19-2 [2021-11-09 09:33:19,961 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:19,961 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 18 times [2021-11-09 09:33:19,961 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:19,961 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [335715341] [2021-11-09 09:33:19,961 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:19,961 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:19,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:19,970 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:19,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:19,972 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:19,972 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:19,972 INFO L85 PathProgramCache]: Analyzing trace with hash 1447644080, now seen corresponding path program 17 times [2021-11-09 09:33:19,973 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:19,973 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2033038045] [2021-11-09 09:33:19,973 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:19,973 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:19,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:20,210 INFO L134 CoverageAnalysis]: Checked inductivity of 153 backedges. 0 proven. 153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:20,211 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:20,211 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2033038045] [2021-11-09 09:33:20,211 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2033038045] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:20,211 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1366838632] [2021-11-09 09:33:20,211 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:33:20,211 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:20,211 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:20,213 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:20,213 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2021-11-09 09:33:20,309 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2021-11-09 09:33:20,309 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:20,309 INFO L263 TraceCheckSpWp]: Trace formula consists of 59 conjuncts, 19 conjunts are in the unsatisfiable core [2021-11-09 09:33:20,311 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:20,393 INFO L134 CoverageAnalysis]: Checked inductivity of 153 backedges. 0 proven. 153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:20,393 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1366838632] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:20,394 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:20,394 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 19 [2021-11-09 09:33:20,394 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [131618933] [2021-11-09 09:33:20,394 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:20,395 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:20,395 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2021-11-09 09:33:20,395 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2021-11-09 09:33:20,396 INFO L87 Difference]: Start difference. First operand 21 states and 22 transitions. cyclomatic complexity: 2 Second operand has 20 states, 20 states have (on average 1.0) internal successors, (20), 19 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:20,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:20,424 INFO L93 Difference]: Finished difference Result 22 states and 23 transitions. [2021-11-09 09:33:20,424 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2021-11-09 09:33:20,424 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22 states and 23 transitions. [2021-11-09 09:33:20,425 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 21 [2021-11-09 09:33:20,425 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22 states to 22 states and 23 transitions. [2021-11-09 09:33:20,426 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2021-11-09 09:33:20,426 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2021-11-09 09:33:20,426 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22 states and 23 transitions. [2021-11-09 09:33:20,426 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:20,426 INFO L681 BuchiCegarLoop]: Abstraction has 22 states and 23 transitions. [2021-11-09 09:33:20,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states and 23 transitions. [2021-11-09 09:33:20,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2021-11-09 09:33:20,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 22 states have (on average 1.0454545454545454) internal successors, (23), 21 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:20,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 23 transitions. [2021-11-09 09:33:20,428 INFO L704 BuchiCegarLoop]: Abstraction has 22 states and 23 transitions. [2021-11-09 09:33:20,429 INFO L587 BuchiCegarLoop]: Abstraction has 22 states and 23 transitions. [2021-11-09 09:33:20,429 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-09 09:33:20,429 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22 states and 23 transitions. [2021-11-09 09:33:20,429 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 21 [2021-11-09 09:33:20,429 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:20,429 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:20,430 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:20,430 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [18, 1, 1, 1] [2021-11-09 09:33:20,430 INFO L791 eck$LassoCheckResult]: Stem: 1304#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 1301#L19-2 [2021-11-09 09:33:20,430 INFO L793 eck$LassoCheckResult]: Loop: 1301#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 1302#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1305#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1322#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1321#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1320#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1319#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1318#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1317#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1316#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1315#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1314#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1313#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1312#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1311#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1310#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1309#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1308#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1307#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1306#L21-2 assume !(main_~x2~0 > 1); 1303#L21-3 main_~x1~0 := 1 + main_~x1~0; 1301#L19-2 [2021-11-09 09:33:20,431 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:20,431 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 19 times [2021-11-09 09:33:20,431 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:20,431 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [103151062] [2021-11-09 09:33:20,431 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:20,432 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:20,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:20,435 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:20,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:20,436 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:20,437 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:20,437 INFO L85 PathProgramCache]: Analyzing trace with hash 1927295279, now seen corresponding path program 18 times [2021-11-09 09:33:20,437 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:20,437 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1342867878] [2021-11-09 09:33:20,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:20,438 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:20,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:20,667 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 0 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:20,667 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:20,667 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1342867878] [2021-11-09 09:33:20,667 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1342867878] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:20,667 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [194746934] [2021-11-09 09:33:20,667 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:33:20,668 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:20,668 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:20,669 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:20,690 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2021-11-09 09:33:20,781 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2021-11-09 09:33:20,782 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:20,783 INFO L263 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 20 conjunts are in the unsatisfiable core [2021-11-09 09:33:20,784 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:20,880 INFO L134 CoverageAnalysis]: Checked inductivity of 171 backedges. 0 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:20,880 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [194746934] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:20,880 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:20,880 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 20 [2021-11-09 09:33:20,881 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [577222221] [2021-11-09 09:33:20,882 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:20,882 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:20,883 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-11-09 09:33:20,883 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2021-11-09 09:33:20,884 INFO L87 Difference]: Start difference. First operand 22 states and 23 transitions. cyclomatic complexity: 2 Second operand has 21 states, 21 states have (on average 1.0) internal successors, (21), 20 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:20,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:20,911 INFO L93 Difference]: Finished difference Result 23 states and 24 transitions. [2021-11-09 09:33:20,912 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2021-11-09 09:33:20,912 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23 states and 24 transitions. [2021-11-09 09:33:20,912 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 22 [2021-11-09 09:33:20,914 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23 states to 23 states and 24 transitions. [2021-11-09 09:33:20,915 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23 [2021-11-09 09:33:20,916 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 23 [2021-11-09 09:33:20,916 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23 states and 24 transitions. [2021-11-09 09:33:20,922 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:20,922 INFO L681 BuchiCegarLoop]: Abstraction has 23 states and 24 transitions. [2021-11-09 09:33:20,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states and 24 transitions. [2021-11-09 09:33:20,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 23. [2021-11-09 09:33:20,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23 states, 23 states have (on average 1.0434782608695652) internal successors, (24), 22 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:20,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 24 transitions. [2021-11-09 09:33:20,930 INFO L704 BuchiCegarLoop]: Abstraction has 23 states and 24 transitions. [2021-11-09 09:33:20,931 INFO L587 BuchiCegarLoop]: Abstraction has 23 states and 24 transitions. [2021-11-09 09:33:20,931 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-09 09:33:20,931 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23 states and 24 transitions. [2021-11-09 09:33:20,931 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 22 [2021-11-09 09:33:20,931 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:20,932 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:20,934 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:20,934 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [19, 1, 1, 1] [2021-11-09 09:33:20,934 INFO L791 eck$LassoCheckResult]: Stem: 1433#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 1430#L19-2 [2021-11-09 09:33:20,935 INFO L793 eck$LassoCheckResult]: Loop: 1430#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 1431#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1434#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1452#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1451#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1450#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1449#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1448#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1447#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1446#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1445#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1444#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1443#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1442#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1441#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1440#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1439#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1438#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1437#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1436#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1435#L21-2 assume !(main_~x2~0 > 1); 1432#L21-3 main_~x1~0 := 1 + main_~x1~0; 1430#L19-2 [2021-11-09 09:33:20,935 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:20,935 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 20 times [2021-11-09 09:33:20,935 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:20,935 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1448090853] [2021-11-09 09:33:20,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:20,936 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:20,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:20,942 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:20,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:20,944 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:20,945 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:20,945 INFO L85 PathProgramCache]: Analyzing trace with hash -383386736, now seen corresponding path program 19 times [2021-11-09 09:33:20,945 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:20,945 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1769697727] [2021-11-09 09:33:20,946 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:20,946 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:20,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:21,221 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:21,222 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:21,222 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1769697727] [2021-11-09 09:33:21,222 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1769697727] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:21,222 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [13062696] [2021-11-09 09:33:21,223 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:33:21,223 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:21,223 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:21,228 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:21,247 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2021-11-09 09:33:21,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:21,347 INFO L263 TraceCheckSpWp]: Trace formula consists of 65 conjuncts, 21 conjunts are in the unsatisfiable core [2021-11-09 09:33:21,348 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:21,457 INFO L134 CoverageAnalysis]: Checked inductivity of 190 backedges. 0 proven. 190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:21,457 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [13062696] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:21,457 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:21,457 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 21 [2021-11-09 09:33:21,458 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1318880564] [2021-11-09 09:33:21,458 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:21,458 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:21,458 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2021-11-09 09:33:21,459 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2021-11-09 09:33:21,459 INFO L87 Difference]: Start difference. First operand 23 states and 24 transitions. cyclomatic complexity: 2 Second operand has 22 states, 22 states have (on average 1.0) internal successors, (22), 21 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:21,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:21,497 INFO L93 Difference]: Finished difference Result 24 states and 25 transitions. [2021-11-09 09:33:21,497 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2021-11-09 09:33:21,497 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24 states and 25 transitions. [2021-11-09 09:33:21,498 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 23 [2021-11-09 09:33:21,498 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24 states to 24 states and 25 transitions. [2021-11-09 09:33:21,498 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24 [2021-11-09 09:33:21,499 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24 [2021-11-09 09:33:21,499 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24 states and 25 transitions. [2021-11-09 09:33:21,499 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:21,499 INFO L681 BuchiCegarLoop]: Abstraction has 24 states and 25 transitions. [2021-11-09 09:33:21,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states and 25 transitions. [2021-11-09 09:33:21,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 24. [2021-11-09 09:33:21,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.0416666666666667) internal successors, (25), 23 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:21,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 25 transitions. [2021-11-09 09:33:21,502 INFO L704 BuchiCegarLoop]: Abstraction has 24 states and 25 transitions. [2021-11-09 09:33:21,502 INFO L587 BuchiCegarLoop]: Abstraction has 24 states and 25 transitions. [2021-11-09 09:33:21,502 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-09 09:33:21,502 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 25 transitions. [2021-11-09 09:33:21,502 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 23 [2021-11-09 09:33:21,502 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:21,503 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:21,503 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:21,503 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [20, 1, 1, 1] [2021-11-09 09:33:21,503 INFO L791 eck$LassoCheckResult]: Stem: 1568#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 1565#L19-2 [2021-11-09 09:33:21,504 INFO L793 eck$LassoCheckResult]: Loop: 1565#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 1566#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1569#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1588#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1587#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1586#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1585#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1584#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1583#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1582#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1581#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1580#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1579#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1578#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1577#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1576#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1575#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1574#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1573#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1572#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1571#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1570#L21-2 assume !(main_~x2~0 > 1); 1567#L21-3 main_~x1~0 := 1 + main_~x1~0; 1565#L19-2 [2021-11-09 09:33:21,504 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:21,504 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 21 times [2021-11-09 09:33:21,504 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:21,505 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1518794108] [2021-11-09 09:33:21,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:21,505 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:21,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:21,509 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:21,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:21,511 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:21,511 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:21,511 INFO L85 PathProgramCache]: Analyzing trace with hash 999914831, now seen corresponding path program 20 times [2021-11-09 09:33:21,512 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:21,512 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [715392796] [2021-11-09 09:33:21,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:21,512 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:21,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:21,776 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:21,776 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:21,776 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [715392796] [2021-11-09 09:33:21,776 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [715392796] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:21,776 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [105330844] [2021-11-09 09:33:21,776 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:33:21,777 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:21,777 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:21,783 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:21,784 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2021-11-09 09:33:21,893 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:33:21,893 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:21,894 INFO L263 TraceCheckSpWp]: Trace formula consists of 68 conjuncts, 22 conjunts are in the unsatisfiable core [2021-11-09 09:33:21,895 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:21,984 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:21,984 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [105330844] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:21,984 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:21,984 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 22 [2021-11-09 09:33:21,986 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [166486743] [2021-11-09 09:33:21,988 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:21,988 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:21,989 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2021-11-09 09:33:21,989 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=253, Unknown=0, NotChecked=0, Total=506 [2021-11-09 09:33:21,989 INFO L87 Difference]: Start difference. First operand 24 states and 25 transitions. cyclomatic complexity: 2 Second operand has 23 states, 23 states have (on average 1.0) internal successors, (23), 22 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:22,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:22,021 INFO L93 Difference]: Finished difference Result 25 states and 26 transitions. [2021-11-09 09:33:22,021 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2021-11-09 09:33:22,021 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25 states and 26 transitions. [2021-11-09 09:33:22,022 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 24 [2021-11-09 09:33:22,022 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25 states to 25 states and 26 transitions. [2021-11-09 09:33:22,022 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2021-11-09 09:33:22,022 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2021-11-09 09:33:22,023 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25 states and 26 transitions. [2021-11-09 09:33:22,023 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:22,023 INFO L681 BuchiCegarLoop]: Abstraction has 25 states and 26 transitions. [2021-11-09 09:33:22,023 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states and 26 transitions. [2021-11-09 09:33:22,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2021-11-09 09:33:22,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 25 states have (on average 1.04) internal successors, (26), 24 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:22,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 26 transitions. [2021-11-09 09:33:22,025 INFO L704 BuchiCegarLoop]: Abstraction has 25 states and 26 transitions. [2021-11-09 09:33:22,025 INFO L587 BuchiCegarLoop]: Abstraction has 25 states and 26 transitions. [2021-11-09 09:33:22,025 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-09 09:33:22,025 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 26 transitions. [2021-11-09 09:33:22,026 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 24 [2021-11-09 09:33:22,027 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:22,027 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:22,028 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:22,028 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [21, 1, 1, 1] [2021-11-09 09:33:22,028 INFO L791 eck$LassoCheckResult]: Stem: 1709#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 1706#L19-2 [2021-11-09 09:33:22,028 INFO L793 eck$LassoCheckResult]: Loop: 1706#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 1707#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1710#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1730#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1729#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1728#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1727#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1726#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1725#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1724#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1723#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1722#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1721#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1720#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1719#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1718#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1717#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1716#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1715#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1714#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1713#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1712#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1711#L21-2 assume !(main_~x2~0 > 1); 1708#L21-3 main_~x1~0 := 1 + main_~x1~0; 1706#L19-2 [2021-11-09 09:33:22,028 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:22,029 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 22 times [2021-11-09 09:33:22,029 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:22,029 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [511100300] [2021-11-09 09:33:22,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:22,029 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:22,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:22,040 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:22,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:22,042 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:22,043 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:22,043 INFO L85 PathProgramCache]: Analyzing trace with hash 932590448, now seen corresponding path program 21 times [2021-11-09 09:33:22,043 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:22,043 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [137315709] [2021-11-09 09:33:22,043 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:22,044 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:22,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:22,311 INFO L134 CoverageAnalysis]: Checked inductivity of 231 backedges. 0 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:22,312 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:22,313 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [137315709] [2021-11-09 09:33:22,313 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [137315709] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:22,313 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2031342381] [2021-11-09 09:33:22,313 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:33:22,313 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:22,313 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:22,322 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:22,324 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2021-11-09 09:33:22,448 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2021-11-09 09:33:22,448 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:22,449 INFO L263 TraceCheckSpWp]: Trace formula consists of 71 conjuncts, 23 conjunts are in the unsatisfiable core [2021-11-09 09:33:22,450 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:22,555 INFO L134 CoverageAnalysis]: Checked inductivity of 231 backedges. 0 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:22,555 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2031342381] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:22,555 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:22,555 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23] total 23 [2021-11-09 09:33:22,555 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1742323994] [2021-11-09 09:33:22,556 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:22,556 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:22,556 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2021-11-09 09:33:22,557 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2021-11-09 09:33:22,557 INFO L87 Difference]: Start difference. First operand 25 states and 26 transitions. cyclomatic complexity: 2 Second operand has 24 states, 24 states have (on average 1.0) internal successors, (24), 23 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:22,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:22,589 INFO L93 Difference]: Finished difference Result 26 states and 27 transitions. [2021-11-09 09:33:22,589 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2021-11-09 09:33:22,589 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26 states and 27 transitions. [2021-11-09 09:33:22,589 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 25 [2021-11-09 09:33:22,590 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26 states to 26 states and 27 transitions. [2021-11-09 09:33:22,590 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26 [2021-11-09 09:33:22,590 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26 [2021-11-09 09:33:22,590 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26 states and 27 transitions. [2021-11-09 09:33:22,590 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:22,591 INFO L681 BuchiCegarLoop]: Abstraction has 26 states and 27 transitions. [2021-11-09 09:33:22,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states and 27 transitions. [2021-11-09 09:33:22,594 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 26. [2021-11-09 09:33:22,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 1.0384615384615385) internal successors, (27), 25 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:22,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 27 transitions. [2021-11-09 09:33:22,595 INFO L704 BuchiCegarLoop]: Abstraction has 26 states and 27 transitions. [2021-11-09 09:33:22,595 INFO L587 BuchiCegarLoop]: Abstraction has 26 states and 27 transitions. [2021-11-09 09:33:22,595 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-11-09 09:33:22,595 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26 states and 27 transitions. [2021-11-09 09:33:22,596 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 25 [2021-11-09 09:33:22,596 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:22,596 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:22,596 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:22,596 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [22, 1, 1, 1] [2021-11-09 09:33:22,596 INFO L791 eck$LassoCheckResult]: Stem: 1856#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 1853#L19-2 [2021-11-09 09:33:22,596 INFO L793 eck$LassoCheckResult]: Loop: 1853#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 1854#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1857#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1878#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1877#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1876#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1875#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1874#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1873#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1872#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1871#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1870#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1869#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1868#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1867#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1866#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1865#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1864#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1863#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1862#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1861#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1860#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1859#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 1858#L21-2 assume !(main_~x2~0 > 1); 1855#L21-3 main_~x1~0 := 1 + main_~x1~0; 1853#L19-2 [2021-11-09 09:33:22,597 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:22,597 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 23 times [2021-11-09 09:33:22,597 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:22,597 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2069660191] [2021-11-09 09:33:22,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:22,597 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:22,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:22,601 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:22,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:22,603 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:22,604 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:22,604 INFO L85 PathProgramCache]: Analyzing trace with hash -1154465425, now seen corresponding path program 22 times [2021-11-09 09:33:22,604 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:22,604 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1258183296] [2021-11-09 09:33:22,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:22,605 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:22,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:22,968 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:22,969 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:22,969 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1258183296] [2021-11-09 09:33:22,969 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1258183296] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:22,969 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [361514408] [2021-11-09 09:33:22,969 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:33:22,969 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:22,970 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:22,977 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:22,995 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2021-11-09 09:33:23,117 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:33:23,118 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:23,119 INFO L263 TraceCheckSpWp]: Trace formula consists of 74 conjuncts, 24 conjunts are in the unsatisfiable core [2021-11-09 09:33:23,120 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:23,209 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:23,209 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [361514408] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:23,209 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:23,210 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 24 [2021-11-09 09:33:23,210 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [425728777] [2021-11-09 09:33:23,210 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:23,210 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:23,211 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2021-11-09 09:33:23,211 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2021-11-09 09:33:23,211 INFO L87 Difference]: Start difference. First operand 26 states and 27 transitions. cyclomatic complexity: 2 Second operand has 25 states, 25 states have (on average 1.0) internal successors, (25), 24 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:23,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:23,237 INFO L93 Difference]: Finished difference Result 27 states and 28 transitions. [2021-11-09 09:33:23,237 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2021-11-09 09:33:23,237 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27 states and 28 transitions. [2021-11-09 09:33:23,238 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 26 [2021-11-09 09:33:23,238 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27 states to 27 states and 28 transitions. [2021-11-09 09:33:23,238 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2021-11-09 09:33:23,238 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2021-11-09 09:33:23,238 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 28 transitions. [2021-11-09 09:33:23,239 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:23,239 INFO L681 BuchiCegarLoop]: Abstraction has 27 states and 28 transitions. [2021-11-09 09:33:23,239 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 28 transitions. [2021-11-09 09:33:23,240 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27. [2021-11-09 09:33:23,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.037037037037037) internal successors, (28), 26 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:23,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 28 transitions. [2021-11-09 09:33:23,241 INFO L704 BuchiCegarLoop]: Abstraction has 27 states and 28 transitions. [2021-11-09 09:33:23,241 INFO L587 BuchiCegarLoop]: Abstraction has 27 states and 28 transitions. [2021-11-09 09:33:23,241 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-11-09 09:33:23,241 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 28 transitions. [2021-11-09 09:33:23,241 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 26 [2021-11-09 09:33:23,241 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:23,241 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:23,242 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:23,242 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [23, 1, 1, 1] [2021-11-09 09:33:23,242 INFO L791 eck$LassoCheckResult]: Stem: 2009#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 2006#L19-2 [2021-11-09 09:33:23,242 INFO L793 eck$LassoCheckResult]: Loop: 2006#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 2007#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2010#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2032#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2031#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2030#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2029#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2028#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2027#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2026#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2025#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2024#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2023#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2022#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2021#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2020#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2019#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2018#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2017#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2016#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2015#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2014#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2013#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2012#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2011#L21-2 assume !(main_~x2~0 > 1); 2008#L21-3 main_~x1~0 := 1 + main_~x1~0; 2006#L19-2 [2021-11-09 09:33:23,242 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:23,242 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 24 times [2021-11-09 09:33:23,242 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:23,242 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [74403240] [2021-11-09 09:33:23,243 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:23,243 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:23,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:23,246 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:23,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:23,247 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:23,248 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:23,248 INFO L85 PathProgramCache]: Analyzing trace with hash -1428688048, now seen corresponding path program 23 times [2021-11-09 09:33:23,248 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:23,248 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1845590318] [2021-11-09 09:33:23,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:23,249 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:23,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:23,556 INFO L134 CoverageAnalysis]: Checked inductivity of 276 backedges. 0 proven. 276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:23,557 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:23,557 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1845590318] [2021-11-09 09:33:23,557 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1845590318] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:23,557 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1955363188] [2021-11-09 09:33:23,557 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:33:23,557 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:23,558 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:23,564 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:23,577 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2021-11-09 09:33:23,700 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2021-11-09 09:33:23,700 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:23,701 INFO L263 TraceCheckSpWp]: Trace formula consists of 77 conjuncts, 25 conjunts are in the unsatisfiable core [2021-11-09 09:33:23,702 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:23,788 INFO L134 CoverageAnalysis]: Checked inductivity of 276 backedges. 0 proven. 276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:23,788 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1955363188] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:23,788 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:23,789 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 25 [2021-11-09 09:33:23,789 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2026937241] [2021-11-09 09:33:23,789 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:23,789 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:23,790 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2021-11-09 09:33:23,790 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2021-11-09 09:33:23,790 INFO L87 Difference]: Start difference. First operand 27 states and 28 transitions. cyclomatic complexity: 2 Second operand has 26 states, 26 states have (on average 1.0) internal successors, (26), 25 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:23,827 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:23,827 INFO L93 Difference]: Finished difference Result 28 states and 29 transitions. [2021-11-09 09:33:23,827 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2021-11-09 09:33:23,827 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28 states and 29 transitions. [2021-11-09 09:33:23,828 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 27 [2021-11-09 09:33:23,831 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28 states to 28 states and 29 transitions. [2021-11-09 09:33:23,831 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28 [2021-11-09 09:33:23,831 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28 [2021-11-09 09:33:23,831 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28 states and 29 transitions. [2021-11-09 09:33:23,833 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:23,833 INFO L681 BuchiCegarLoop]: Abstraction has 28 states and 29 transitions. [2021-11-09 09:33:23,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states and 29 transitions. [2021-11-09 09:33:23,841 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 28. [2021-11-09 09:33:23,841 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.0357142857142858) internal successors, (29), 27 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:23,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 29 transitions. [2021-11-09 09:33:23,841 INFO L704 BuchiCegarLoop]: Abstraction has 28 states and 29 transitions. [2021-11-09 09:33:23,841 INFO L587 BuchiCegarLoop]: Abstraction has 28 states and 29 transitions. [2021-11-09 09:33:23,842 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-11-09 09:33:23,842 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 29 transitions. [2021-11-09 09:33:23,842 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 27 [2021-11-09 09:33:23,842 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:23,842 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:23,842 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:23,842 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [24, 1, 1, 1] [2021-11-09 09:33:23,843 INFO L791 eck$LassoCheckResult]: Stem: 2168#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 2165#L19-2 [2021-11-09 09:33:23,843 INFO L793 eck$LassoCheckResult]: Loop: 2165#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 2166#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2169#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2192#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2191#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2190#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2189#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2188#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2187#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2186#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2185#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2184#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2183#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2182#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2181#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2180#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2179#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2178#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2177#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2176#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2175#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2174#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2173#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2172#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2171#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2170#L21-2 assume !(main_~x2~0 > 1); 2167#L21-3 main_~x1~0 := 1 + main_~x1~0; 2165#L19-2 [2021-11-09 09:33:23,843 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:23,843 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 25 times [2021-11-09 09:33:23,843 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:23,843 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1813774831] [2021-11-09 09:33:23,844 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:23,844 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:23,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:23,846 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:23,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:23,848 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:23,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:23,848 INFO L85 PathProgramCache]: Analyzing trace with hash -1339654769, now seen corresponding path program 24 times [2021-11-09 09:33:23,848 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:23,848 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1300174065] [2021-11-09 09:33:23,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:23,849 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:23,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:24,192 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:24,192 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:24,193 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1300174065] [2021-11-09 09:33:24,193 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1300174065] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:24,193 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1575041286] [2021-11-09 09:33:24,193 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:33:24,193 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:24,193 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:24,194 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:24,195 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2021-11-09 09:33:24,330 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2021-11-09 09:33:24,330 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:24,331 INFO L263 TraceCheckSpWp]: Trace formula consists of 80 conjuncts, 26 conjunts are in the unsatisfiable core [2021-11-09 09:33:24,333 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:24,418 INFO L134 CoverageAnalysis]: Checked inductivity of 300 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:24,418 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1575041286] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:24,419 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:24,419 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26] total 26 [2021-11-09 09:33:24,419 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1104181334] [2021-11-09 09:33:24,419 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:24,419 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:24,420 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2021-11-09 09:33:24,420 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2021-11-09 09:33:24,420 INFO L87 Difference]: Start difference. First operand 28 states and 29 transitions. cyclomatic complexity: 2 Second operand has 27 states, 27 states have (on average 1.0) internal successors, (27), 26 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:24,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:24,446 INFO L93 Difference]: Finished difference Result 29 states and 30 transitions. [2021-11-09 09:33:24,446 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2021-11-09 09:33:24,446 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29 states and 30 transitions. [2021-11-09 09:33:24,447 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 28 [2021-11-09 09:33:24,447 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29 states to 29 states and 30 transitions. [2021-11-09 09:33:24,447 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29 [2021-11-09 09:33:24,447 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29 [2021-11-09 09:33:24,448 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29 states and 30 transitions. [2021-11-09 09:33:24,448 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:24,448 INFO L681 BuchiCegarLoop]: Abstraction has 29 states and 30 transitions. [2021-11-09 09:33:24,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states and 30 transitions. [2021-11-09 09:33:24,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2021-11-09 09:33:24,449 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 29 states have (on average 1.0344827586206897) internal successors, (30), 28 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:24,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 30 transitions. [2021-11-09 09:33:24,450 INFO L704 BuchiCegarLoop]: Abstraction has 29 states and 30 transitions. [2021-11-09 09:33:24,450 INFO L587 BuchiCegarLoop]: Abstraction has 29 states and 30 transitions. [2021-11-09 09:33:24,450 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-11-09 09:33:24,450 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29 states and 30 transitions. [2021-11-09 09:33:24,450 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 28 [2021-11-09 09:33:24,450 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:24,450 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:24,451 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:24,451 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [25, 1, 1, 1] [2021-11-09 09:33:24,451 INFO L791 eck$LassoCheckResult]: Stem: 2333#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 2330#L19-2 [2021-11-09 09:33:24,451 INFO L793 eck$LassoCheckResult]: Loop: 2330#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 2331#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2334#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2358#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2357#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2356#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2355#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2354#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2353#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2352#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2351#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2350#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2349#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2348#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2347#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2346#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2345#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2344#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2343#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2342#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2341#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2340#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2339#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2338#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2337#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2336#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2335#L21-2 assume !(main_~x2~0 > 1); 2332#L21-3 main_~x1~0 := 1 + main_~x1~0; 2330#L19-2 [2021-11-09 09:33:24,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:24,451 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 26 times [2021-11-09 09:33:24,451 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:24,452 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1402596909] [2021-11-09 09:33:24,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:24,452 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:24,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:24,455 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:24,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:24,456 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:24,457 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:24,457 INFO L85 PathProgramCache]: Analyzing trace with hash 1420376880, now seen corresponding path program 25 times [2021-11-09 09:33:24,457 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:24,457 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1332596773] [2021-11-09 09:33:24,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:24,457 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:24,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:24,832 INFO L134 CoverageAnalysis]: Checked inductivity of 325 backedges. 0 proven. 325 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:24,832 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:24,832 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1332596773] [2021-11-09 09:33:24,832 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1332596773] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:24,832 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1985648083] [2021-11-09 09:33:24,833 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:33:24,833 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:24,833 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:24,834 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:24,835 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2021-11-09 09:33:24,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:24,977 INFO L263 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 27 conjunts are in the unsatisfiable core [2021-11-09 09:33:24,978 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:25,081 INFO L134 CoverageAnalysis]: Checked inductivity of 325 backedges. 0 proven. 325 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:25,081 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1985648083] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:25,082 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:25,082 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27] total 27 [2021-11-09 09:33:25,082 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [921421082] [2021-11-09 09:33:25,083 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:25,084 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:25,085 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2021-11-09 09:33:25,085 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2021-11-09 09:33:25,085 INFO L87 Difference]: Start difference. First operand 29 states and 30 transitions. cyclomatic complexity: 2 Second operand has 28 states, 28 states have (on average 1.0) internal successors, (28), 27 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:25,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:25,122 INFO L93 Difference]: Finished difference Result 30 states and 31 transitions. [2021-11-09 09:33:25,122 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2021-11-09 09:33:25,123 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30 states and 31 transitions. [2021-11-09 09:33:25,123 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 29 [2021-11-09 09:33:25,124 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30 states to 30 states and 31 transitions. [2021-11-09 09:33:25,124 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30 [2021-11-09 09:33:25,125 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30 [2021-11-09 09:33:25,125 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30 states and 31 transitions. [2021-11-09 09:33:25,125 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:25,125 INFO L681 BuchiCegarLoop]: Abstraction has 30 states and 31 transitions. [2021-11-09 09:33:25,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states and 31 transitions. [2021-11-09 09:33:25,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 30. [2021-11-09 09:33:25,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30 states, 30 states have (on average 1.0333333333333334) internal successors, (31), 29 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:25,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 31 transitions. [2021-11-09 09:33:25,129 INFO L704 BuchiCegarLoop]: Abstraction has 30 states and 31 transitions. [2021-11-09 09:33:25,129 INFO L587 BuchiCegarLoop]: Abstraction has 30 states and 31 transitions. [2021-11-09 09:33:25,129 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-11-09 09:33:25,129 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30 states and 31 transitions. [2021-11-09 09:33:25,129 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 29 [2021-11-09 09:33:25,129 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:25,129 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:25,130 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:25,130 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [26, 1, 1, 1] [2021-11-09 09:33:25,130 INFO L791 eck$LassoCheckResult]: Stem: 2504#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 2501#L19-2 [2021-11-09 09:33:25,130 INFO L793 eck$LassoCheckResult]: Loop: 2501#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 2502#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2505#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2530#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2529#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2528#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2527#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2526#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2525#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2524#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2523#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2522#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2521#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2520#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2519#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2518#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2517#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2516#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2515#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2514#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2513#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2512#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2511#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2510#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2509#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2508#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2507#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2506#L21-2 assume !(main_~x2~0 > 1); 2503#L21-3 main_~x1~0 := 1 + main_~x1~0; 2501#L19-2 [2021-11-09 09:33:25,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:25,130 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 27 times [2021-11-09 09:33:25,131 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:25,131 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1675244892] [2021-11-09 09:33:25,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:25,131 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:25,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:25,134 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:25,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:25,137 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:25,138 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:25,138 INFO L85 PathProgramCache]: Analyzing trace with hash 1082012079, now seen corresponding path program 26 times [2021-11-09 09:33:25,138 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:25,138 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1570932069] [2021-11-09 09:33:25,138 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:25,139 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:25,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:25,512 INFO L134 CoverageAnalysis]: Checked inductivity of 351 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:25,512 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:25,512 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1570932069] [2021-11-09 09:33:25,512 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1570932069] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:25,512 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1246284341] [2021-11-09 09:33:25,512 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:33:25,513 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:25,513 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:25,514 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:25,540 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2021-11-09 09:33:25,697 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:33:25,697 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:25,698 INFO L263 TraceCheckSpWp]: Trace formula consists of 86 conjuncts, 28 conjunts are in the unsatisfiable core [2021-11-09 09:33:25,700 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:25,834 INFO L134 CoverageAnalysis]: Checked inductivity of 351 backedges. 0 proven. 351 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:25,834 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1246284341] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:25,834 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:25,834 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28] total 28 [2021-11-09 09:33:25,835 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1024630914] [2021-11-09 09:33:25,835 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:25,836 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:25,836 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2021-11-09 09:33:25,837 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2021-11-09 09:33:25,837 INFO L87 Difference]: Start difference. First operand 30 states and 31 transitions. cyclomatic complexity: 2 Second operand has 29 states, 29 states have (on average 1.0) internal successors, (29), 28 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:25,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:25,866 INFO L93 Difference]: Finished difference Result 31 states and 32 transitions. [2021-11-09 09:33:25,867 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2021-11-09 09:33:25,867 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31 states and 32 transitions. [2021-11-09 09:33:25,867 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 30 [2021-11-09 09:33:25,868 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31 states to 31 states and 32 transitions. [2021-11-09 09:33:25,868 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31 [2021-11-09 09:33:25,868 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31 [2021-11-09 09:33:25,868 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31 states and 32 transitions. [2021-11-09 09:33:25,868 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:25,868 INFO L681 BuchiCegarLoop]: Abstraction has 31 states and 32 transitions. [2021-11-09 09:33:25,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states and 32 transitions. [2021-11-09 09:33:25,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 31. [2021-11-09 09:33:25,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 31 states have (on average 1.032258064516129) internal successors, (32), 30 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:25,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 32 transitions. [2021-11-09 09:33:25,870 INFO L704 BuchiCegarLoop]: Abstraction has 31 states and 32 transitions. [2021-11-09 09:33:25,870 INFO L587 BuchiCegarLoop]: Abstraction has 31 states and 32 transitions. [2021-11-09 09:33:25,871 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-11-09 09:33:25,871 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31 states and 32 transitions. [2021-11-09 09:33:25,871 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 30 [2021-11-09 09:33:25,871 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:25,871 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:25,872 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:25,872 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [27, 1, 1, 1] [2021-11-09 09:33:25,872 INFO L791 eck$LassoCheckResult]: Stem: 2681#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 2678#L19-2 [2021-11-09 09:33:25,872 INFO L793 eck$LassoCheckResult]: Loop: 2678#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 2679#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2682#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2708#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2707#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2706#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2705#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2704#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2703#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2702#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2701#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2700#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2699#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2698#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2697#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2696#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2695#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2694#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2693#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2692#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2691#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2690#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2689#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2688#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2687#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2686#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2685#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2684#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2683#L21-2 assume !(main_~x2~0 > 1); 2680#L21-3 main_~x1~0 := 1 + main_~x1~0; 2678#L19-2 [2021-11-09 09:33:25,873 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:25,873 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 28 times [2021-11-09 09:33:25,873 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:25,873 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [210759527] [2021-11-09 09:33:25,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:25,873 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:25,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:25,877 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:25,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:25,878 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:25,879 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:25,879 INFO L85 PathProgramCache]: Analyzing trace with hash -817362160, now seen corresponding path program 27 times [2021-11-09 09:33:25,879 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:25,879 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [299615213] [2021-11-09 09:33:25,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:25,880 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:25,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:26,291 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:26,291 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:26,291 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [299615213] [2021-11-09 09:33:26,291 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [299615213] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:26,291 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1941717090] [2021-11-09 09:33:26,291 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:33:26,292 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:26,292 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:26,297 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:26,320 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2021-11-09 09:33:26,484 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2021-11-09 09:33:26,484 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:26,485 INFO L263 TraceCheckSpWp]: Trace formula consists of 89 conjuncts, 29 conjunts are in the unsatisfiable core [2021-11-09 09:33:26,485 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:26,595 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 0 proven. 378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:26,595 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1941717090] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:26,596 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:26,596 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29] total 29 [2021-11-09 09:33:26,596 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [50530132] [2021-11-09 09:33:26,596 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:26,596 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:26,597 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2021-11-09 09:33:26,598 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2021-11-09 09:33:26,598 INFO L87 Difference]: Start difference. First operand 31 states and 32 transitions. cyclomatic complexity: 2 Second operand has 30 states, 30 states have (on average 1.0) internal successors, (30), 29 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:26,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:26,626 INFO L93 Difference]: Finished difference Result 32 states and 33 transitions. [2021-11-09 09:33:26,626 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2021-11-09 09:33:26,626 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32 states and 33 transitions. [2021-11-09 09:33:26,627 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 31 [2021-11-09 09:33:26,632 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32 states to 32 states and 33 transitions. [2021-11-09 09:33:26,632 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32 [2021-11-09 09:33:26,632 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32 [2021-11-09 09:33:26,632 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 33 transitions. [2021-11-09 09:33:26,633 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:26,633 INFO L681 BuchiCegarLoop]: Abstraction has 32 states and 33 transitions. [2021-11-09 09:33:26,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 33 transitions. [2021-11-09 09:33:26,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 32. [2021-11-09 09:33:26,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 32 states have (on average 1.03125) internal successors, (33), 31 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:26,643 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 33 transitions. [2021-11-09 09:33:26,648 INFO L704 BuchiCegarLoop]: Abstraction has 32 states and 33 transitions. [2021-11-09 09:33:26,649 INFO L587 BuchiCegarLoop]: Abstraction has 32 states and 33 transitions. [2021-11-09 09:33:26,649 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-11-09 09:33:26,649 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32 states and 33 transitions. [2021-11-09 09:33:26,649 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 31 [2021-11-09 09:33:26,649 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:26,650 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:26,650 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:26,650 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [28, 1, 1, 1] [2021-11-09 09:33:26,650 INFO L791 eck$LassoCheckResult]: Stem: 2864#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 2861#L19-2 [2021-11-09 09:33:26,650 INFO L793 eck$LassoCheckResult]: Loop: 2861#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 2862#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2865#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2892#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2891#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2890#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2889#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2888#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2887#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2886#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2885#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2884#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2883#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2882#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2881#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2880#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2879#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2878#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2877#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2876#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2875#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2874#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2873#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2872#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2871#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2870#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2869#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2868#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2867#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 2866#L21-2 assume !(main_~x2~0 > 1); 2863#L21-3 main_~x1~0 := 1 + main_~x1~0; 2861#L19-2 [2021-11-09 09:33:26,652 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:26,652 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 29 times [2021-11-09 09:33:26,652 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:26,653 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1703647445] [2021-11-09 09:33:26,653 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:26,653 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:26,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:26,658 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:26,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:26,659 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:26,660 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:26,661 INFO L85 PathProgramCache]: Analyzing trace with hash 431578575, now seen corresponding path program 28 times [2021-11-09 09:33:26,661 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:26,661 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1468434782] [2021-11-09 09:33:26,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:26,662 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:26,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:27,124 INFO L134 CoverageAnalysis]: Checked inductivity of 406 backedges. 0 proven. 406 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:27,125 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:27,125 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1468434782] [2021-11-09 09:33:27,125 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1468434782] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:27,125 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1278555318] [2021-11-09 09:33:27,125 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:33:27,125 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:27,126 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:27,132 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:27,151 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2021-11-09 09:33:27,328 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:33:27,328 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:27,329 INFO L263 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 30 conjunts are in the unsatisfiable core [2021-11-09 09:33:27,330 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:27,469 INFO L134 CoverageAnalysis]: Checked inductivity of 406 backedges. 0 proven. 406 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:27,470 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1278555318] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:27,470 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:27,470 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 30 [2021-11-09 09:33:27,470 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [770014700] [2021-11-09 09:33:27,471 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:27,471 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:27,471 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2021-11-09 09:33:27,472 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2021-11-09 09:33:27,472 INFO L87 Difference]: Start difference. First operand 32 states and 33 transitions. cyclomatic complexity: 2 Second operand has 31 states, 31 states have (on average 1.0) internal successors, (31), 30 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:27,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:27,508 INFO L93 Difference]: Finished difference Result 33 states and 34 transitions. [2021-11-09 09:33:27,509 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2021-11-09 09:33:27,510 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33 states and 34 transitions. [2021-11-09 09:33:27,510 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 32 [2021-11-09 09:33:27,511 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33 states to 33 states and 34 transitions. [2021-11-09 09:33:27,511 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33 [2021-11-09 09:33:27,511 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33 [2021-11-09 09:33:27,512 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33 states and 34 transitions. [2021-11-09 09:33:27,512 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:27,512 INFO L681 BuchiCegarLoop]: Abstraction has 33 states and 34 transitions. [2021-11-09 09:33:27,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33 states and 34 transitions. [2021-11-09 09:33:27,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33 to 33. [2021-11-09 09:33:27,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33 states, 33 states have (on average 1.0303030303030303) internal successors, (34), 32 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:27,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 34 transitions. [2021-11-09 09:33:27,514 INFO L704 BuchiCegarLoop]: Abstraction has 33 states and 34 transitions. [2021-11-09 09:33:27,514 INFO L587 BuchiCegarLoop]: Abstraction has 33 states and 34 transitions. [2021-11-09 09:33:27,514 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-11-09 09:33:27,514 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33 states and 34 transitions. [2021-11-09 09:33:27,515 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 32 [2021-11-09 09:33:27,515 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:27,515 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:27,515 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:27,515 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [29, 1, 1, 1] [2021-11-09 09:33:27,516 INFO L791 eck$LassoCheckResult]: Stem: 3053#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 3050#L19-2 [2021-11-09 09:33:27,516 INFO L793 eck$LassoCheckResult]: Loop: 3050#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 3051#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3054#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3082#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3081#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3080#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3079#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3078#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3077#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3076#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3075#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3074#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3073#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3072#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3071#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3070#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3069#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3068#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3067#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3066#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3065#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3064#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3063#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3062#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3061#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3060#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3059#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3058#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3057#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3056#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3055#L21-2 assume !(main_~x2~0 > 1); 3052#L21-3 main_~x1~0 := 1 + main_~x1~0; 3050#L19-2 [2021-11-09 09:33:27,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:27,516 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 30 times [2021-11-09 09:33:27,517 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:27,517 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2081228855] [2021-11-09 09:33:27,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:27,517 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:27,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:27,521 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:27,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:27,523 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:27,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:27,523 INFO L85 PathProgramCache]: Analyzing trace with hash 494035696, now seen corresponding path program 29 times [2021-11-09 09:33:27,524 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:27,524 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1553776748] [2021-11-09 09:33:27,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:27,524 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:27,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:28,012 INFO L134 CoverageAnalysis]: Checked inductivity of 435 backedges. 0 proven. 435 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:28,013 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:28,013 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1553776748] [2021-11-09 09:33:28,013 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1553776748] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:28,013 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1631241516] [2021-11-09 09:33:28,013 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:33:28,013 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:28,013 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:28,017 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:28,042 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2021-11-09 09:33:28,256 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2021-11-09 09:33:28,269 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:28,271 INFO L263 TraceCheckSpWp]: Trace formula consists of 95 conjuncts, 31 conjunts are in the unsatisfiable core [2021-11-09 09:33:28,272 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:28,366 INFO L134 CoverageAnalysis]: Checked inductivity of 435 backedges. 0 proven. 435 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:28,367 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1631241516] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:28,367 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:28,367 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31] total 31 [2021-11-09 09:33:28,367 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1369668935] [2021-11-09 09:33:28,367 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:28,368 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:28,368 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2021-11-09 09:33:28,369 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2021-11-09 09:33:28,369 INFO L87 Difference]: Start difference. First operand 33 states and 34 transitions. cyclomatic complexity: 2 Second operand has 32 states, 32 states have (on average 1.0) internal successors, (32), 31 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:28,400 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:28,400 INFO L93 Difference]: Finished difference Result 34 states and 35 transitions. [2021-11-09 09:33:28,400 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2021-11-09 09:33:28,401 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34 states and 35 transitions. [2021-11-09 09:33:28,401 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 33 [2021-11-09 09:33:28,402 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34 states to 34 states and 35 transitions. [2021-11-09 09:33:28,402 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34 [2021-11-09 09:33:28,402 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34 [2021-11-09 09:33:28,402 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34 states and 35 transitions. [2021-11-09 09:33:28,402 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:28,402 INFO L681 BuchiCegarLoop]: Abstraction has 34 states and 35 transitions. [2021-11-09 09:33:28,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states and 35 transitions. [2021-11-09 09:33:28,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 34. [2021-11-09 09:33:28,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 34 states have (on average 1.0294117647058822) internal successors, (35), 33 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:28,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 35 transitions. [2021-11-09 09:33:28,404 INFO L704 BuchiCegarLoop]: Abstraction has 34 states and 35 transitions. [2021-11-09 09:33:28,404 INFO L587 BuchiCegarLoop]: Abstraction has 34 states and 35 transitions. [2021-11-09 09:33:28,404 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-11-09 09:33:28,404 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34 states and 35 transitions. [2021-11-09 09:33:28,405 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 33 [2021-11-09 09:33:28,405 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:28,405 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:28,406 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:28,406 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [30, 1, 1, 1] [2021-11-09 09:33:28,406 INFO L791 eck$LassoCheckResult]: Stem: 3248#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 3245#L19-2 [2021-11-09 09:33:28,407 INFO L793 eck$LassoCheckResult]: Loop: 3245#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 3246#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3249#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3278#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3277#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3276#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3275#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3274#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3273#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3272#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3271#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3270#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3269#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3268#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3267#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3266#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3265#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3264#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3263#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3262#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3261#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3260#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3259#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3258#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3257#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3256#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3255#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3254#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3253#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3252#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3251#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3250#L21-2 assume !(main_~x2~0 > 1); 3247#L21-3 main_~x1~0 := 1 + main_~x1~0; 3245#L19-2 [2021-11-09 09:33:28,407 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:28,407 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 31 times [2021-11-09 09:33:28,407 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:28,407 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1442625738] [2021-11-09 09:33:28,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:28,408 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:28,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:28,411 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:28,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:28,413 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:28,413 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:28,413 INFO L85 PathProgramCache]: Analyzing trace with hash -1864760849, now seen corresponding path program 30 times [2021-11-09 09:33:28,414 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:28,414 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1167022978] [2021-11-09 09:33:28,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:28,414 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:28,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:28,885 INFO L134 CoverageAnalysis]: Checked inductivity of 465 backedges. 0 proven. 465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:28,885 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:28,885 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1167022978] [2021-11-09 09:33:28,885 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1167022978] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:28,885 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [79513021] [2021-11-09 09:33:28,885 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:33:28,886 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:28,886 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:28,889 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:28,913 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2021-11-09 09:33:29,120 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 16 check-sat command(s) [2021-11-09 09:33:29,121 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:29,122 INFO L263 TraceCheckSpWp]: Trace formula consists of 98 conjuncts, 32 conjunts are in the unsatisfiable core [2021-11-09 09:33:29,127 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:29,236 INFO L134 CoverageAnalysis]: Checked inductivity of 465 backedges. 0 proven. 465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:29,237 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [79513021] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:29,237 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:29,237 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32] total 32 [2021-11-09 09:33:29,237 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [535546180] [2021-11-09 09:33:29,238 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:29,238 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:29,238 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2021-11-09 09:33:29,239 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2021-11-09 09:33:29,240 INFO L87 Difference]: Start difference. First operand 34 states and 35 transitions. cyclomatic complexity: 2 Second operand has 33 states, 33 states have (on average 1.0) internal successors, (33), 32 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:29,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:29,279 INFO L93 Difference]: Finished difference Result 35 states and 36 transitions. [2021-11-09 09:33:29,279 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2021-11-09 09:33:29,280 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 36 transitions. [2021-11-09 09:33:29,280 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 34 [2021-11-09 09:33:29,281 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 35 states and 36 transitions. [2021-11-09 09:33:29,281 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 35 [2021-11-09 09:33:29,281 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 35 [2021-11-09 09:33:29,281 INFO L73 IsDeterministic]: Start isDeterministic. Operand 35 states and 36 transitions. [2021-11-09 09:33:29,281 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:29,282 INFO L681 BuchiCegarLoop]: Abstraction has 35 states and 36 transitions. [2021-11-09 09:33:29,282 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states and 36 transitions. [2021-11-09 09:33:29,284 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 35. [2021-11-09 09:33:29,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35 states, 35 states have (on average 1.0285714285714285) internal successors, (36), 34 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:29,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 36 transitions. [2021-11-09 09:33:29,285 INFO L704 BuchiCegarLoop]: Abstraction has 35 states and 36 transitions. [2021-11-09 09:33:29,285 INFO L587 BuchiCegarLoop]: Abstraction has 35 states and 36 transitions. [2021-11-09 09:33:29,285 INFO L425 BuchiCegarLoop]: ======== Iteration 32============ [2021-11-09 09:33:29,286 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35 states and 36 transitions. [2021-11-09 09:33:29,286 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 34 [2021-11-09 09:33:29,286 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:29,286 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:29,287 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:29,287 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [31, 1, 1, 1] [2021-11-09 09:33:29,287 INFO L791 eck$LassoCheckResult]: Stem: 3449#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 3446#L19-2 [2021-11-09 09:33:29,287 INFO L793 eck$LassoCheckResult]: Loop: 3446#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 3447#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3450#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3480#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3479#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3478#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3477#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3476#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3475#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3474#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3473#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3472#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3471#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3470#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3469#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3468#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3467#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3466#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3465#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3464#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3463#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3462#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3461#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3460#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3459#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3458#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3457#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3456#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3455#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3454#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3453#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3452#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3451#L21-2 assume !(main_~x2~0 > 1); 3448#L21-3 main_~x1~0 := 1 + main_~x1~0; 3446#L19-2 [2021-11-09 09:33:29,288 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:29,288 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 32 times [2021-11-09 09:33:29,288 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:29,288 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [792004863] [2021-11-09 09:33:29,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:29,289 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:29,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:29,292 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:29,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:29,295 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:29,296 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:29,296 INFO L85 PathProgramCache]: Analyzing trace with hash -1973009712, now seen corresponding path program 31 times [2021-11-09 09:33:29,296 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:29,297 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1846853269] [2021-11-09 09:33:29,297 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:29,297 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:29,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:29,759 INFO L134 CoverageAnalysis]: Checked inductivity of 496 backedges. 0 proven. 496 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:29,760 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:29,760 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1846853269] [2021-11-09 09:33:29,760 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1846853269] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:29,760 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1505237852] [2021-11-09 09:33:29,760 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:33:29,760 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:29,760 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:29,762 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:29,762 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2021-11-09 09:33:29,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:29,974 INFO L263 TraceCheckSpWp]: Trace formula consists of 101 conjuncts, 33 conjunts are in the unsatisfiable core [2021-11-09 09:33:29,975 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:30,107 INFO L134 CoverageAnalysis]: Checked inductivity of 496 backedges. 0 proven. 496 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:30,107 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1505237852] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:30,108 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:30,108 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 33 [2021-11-09 09:33:30,108 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [905616514] [2021-11-09 09:33:30,109 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:30,109 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:30,110 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2021-11-09 09:33:30,111 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2021-11-09 09:33:30,111 INFO L87 Difference]: Start difference. First operand 35 states and 36 transitions. cyclomatic complexity: 2 Second operand has 34 states, 34 states have (on average 1.0) internal successors, (34), 33 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:30,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:30,150 INFO L93 Difference]: Finished difference Result 36 states and 37 transitions. [2021-11-09 09:33:30,151 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2021-11-09 09:33:30,151 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36 states and 37 transitions. [2021-11-09 09:33:30,152 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 35 [2021-11-09 09:33:30,152 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36 states to 36 states and 37 transitions. [2021-11-09 09:33:30,152 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36 [2021-11-09 09:33:30,153 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 36 [2021-11-09 09:33:30,153 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36 states and 37 transitions. [2021-11-09 09:33:30,153 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:30,153 INFO L681 BuchiCegarLoop]: Abstraction has 36 states and 37 transitions. [2021-11-09 09:33:30,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states and 37 transitions. [2021-11-09 09:33:30,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2021-11-09 09:33:30,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 36 states have (on average 1.0277777777777777) internal successors, (37), 35 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:30,156 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 37 transitions. [2021-11-09 09:33:30,156 INFO L704 BuchiCegarLoop]: Abstraction has 36 states and 37 transitions. [2021-11-09 09:33:30,156 INFO L587 BuchiCegarLoop]: Abstraction has 36 states and 37 transitions. [2021-11-09 09:33:30,156 INFO L425 BuchiCegarLoop]: ======== Iteration 33============ [2021-11-09 09:33:30,157 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36 states and 37 transitions. [2021-11-09 09:33:30,157 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 35 [2021-11-09 09:33:30,157 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:30,157 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:30,158 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:30,158 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [32, 1, 1, 1] [2021-11-09 09:33:30,158 INFO L791 eck$LassoCheckResult]: Stem: 3656#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 3653#L19-2 [2021-11-09 09:33:30,158 INFO L793 eck$LassoCheckResult]: Loop: 3653#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 3654#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3657#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3688#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3687#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3686#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3685#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3684#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3683#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3682#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3681#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3680#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3679#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3678#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3677#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3676#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3675#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3674#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3673#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3672#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3671#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3670#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3669#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3668#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3667#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3666#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3665#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3664#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3663#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3662#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3661#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3660#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3659#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3658#L21-2 assume !(main_~x2~0 > 1); 3655#L21-3 main_~x1~0 := 1 + main_~x1~0; 3653#L19-2 [2021-11-09 09:33:30,158 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:30,159 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 33 times [2021-11-09 09:33:30,159 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:30,159 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [630802091] [2021-11-09 09:33:30,159 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:30,159 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:30,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:30,169 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:30,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:30,171 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:30,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:30,171 INFO L85 PathProgramCache]: Analyzing trace with hash -1033757169, now seen corresponding path program 32 times [2021-11-09 09:33:30,172 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:30,172 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1636541019] [2021-11-09 09:33:30,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:30,172 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:30,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:30,673 INFO L134 CoverageAnalysis]: Checked inductivity of 528 backedges. 0 proven. 528 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:30,673 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:30,673 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1636541019] [2021-11-09 09:33:30,674 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1636541019] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:30,674 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1988258572] [2021-11-09 09:33:30,674 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:33:30,674 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:30,674 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:30,675 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:30,676 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2021-11-09 09:33:30,895 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:33:30,896 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:30,897 INFO L263 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 34 conjunts are in the unsatisfiable core [2021-11-09 09:33:30,898 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:31,029 INFO L134 CoverageAnalysis]: Checked inductivity of 528 backedges. 0 proven. 528 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:31,029 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1988258572] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:31,029 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:31,029 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34] total 34 [2021-11-09 09:33:31,029 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [99433272] [2021-11-09 09:33:31,030 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:31,030 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:31,030 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2021-11-09 09:33:31,031 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=595, Invalid=595, Unknown=0, NotChecked=0, Total=1190 [2021-11-09 09:33:31,031 INFO L87 Difference]: Start difference. First operand 36 states and 37 transitions. cyclomatic complexity: 2 Second operand has 35 states, 35 states have (on average 1.0) internal successors, (35), 34 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:31,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:31,064 INFO L93 Difference]: Finished difference Result 37 states and 38 transitions. [2021-11-09 09:33:31,064 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2021-11-09 09:33:31,065 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37 states and 38 transitions. [2021-11-09 09:33:31,065 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 36 [2021-11-09 09:33:31,066 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37 states to 37 states and 38 transitions. [2021-11-09 09:33:31,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37 [2021-11-09 09:33:31,066 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37 [2021-11-09 09:33:31,066 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37 states and 38 transitions. [2021-11-09 09:33:31,066 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:31,066 INFO L681 BuchiCegarLoop]: Abstraction has 37 states and 38 transitions. [2021-11-09 09:33:31,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states and 38 transitions. [2021-11-09 09:33:31,067 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 37. [2021-11-09 09:33:31,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 37 states have (on average 1.027027027027027) internal successors, (38), 36 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:31,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 38 transitions. [2021-11-09 09:33:31,068 INFO L704 BuchiCegarLoop]: Abstraction has 37 states and 38 transitions. [2021-11-09 09:33:31,068 INFO L587 BuchiCegarLoop]: Abstraction has 37 states and 38 transitions. [2021-11-09 09:33:31,068 INFO L425 BuchiCegarLoop]: ======== Iteration 34============ [2021-11-09 09:33:31,068 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37 states and 38 transitions. [2021-11-09 09:33:31,069 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 36 [2021-11-09 09:33:31,069 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:31,069 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:31,069 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:31,069 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [33, 1, 1, 1] [2021-11-09 09:33:31,070 INFO L791 eck$LassoCheckResult]: Stem: 3869#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 3866#L19-2 [2021-11-09 09:33:31,070 INFO L793 eck$LassoCheckResult]: Loop: 3866#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 3867#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3870#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3902#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3901#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3900#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3899#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3898#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3897#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3896#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3895#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3894#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3893#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3892#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3891#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3890#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3889#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3888#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3887#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3886#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3885#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3884#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3883#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3882#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3881#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3880#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3879#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3878#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3877#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3876#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3875#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3874#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3873#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3872#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 3871#L21-2 assume !(main_~x2~0 > 1); 3868#L21-3 main_~x1~0 := 1 + main_~x1~0; 3866#L19-2 [2021-11-09 09:33:31,070 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:31,070 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 34 times [2021-11-09 09:33:31,070 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:31,071 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [555833779] [2021-11-09 09:33:31,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:31,071 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:31,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:31,075 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:31,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:31,077 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:31,077 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:31,077 INFO L85 PathProgramCache]: Analyzing trace with hash -1981699408, now seen corresponding path program 33 times [2021-11-09 09:33:31,077 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:31,078 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1488211918] [2021-11-09 09:33:31,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:31,078 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:31,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:31,692 INFO L134 CoverageAnalysis]: Checked inductivity of 561 backedges. 0 proven. 561 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:31,692 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:31,692 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1488211918] [2021-11-09 09:33:31,692 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1488211918] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:31,692 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2018168020] [2021-11-09 09:33:31,693 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:33:31,693 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:31,693 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:31,695 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:31,698 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2021-11-09 09:33:31,932 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2021-11-09 09:33:31,933 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:31,934 INFO L263 TraceCheckSpWp]: Trace formula consists of 107 conjuncts, 35 conjunts are in the unsatisfiable core [2021-11-09 09:33:31,934 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:32,059 INFO L134 CoverageAnalysis]: Checked inductivity of 561 backedges. 0 proven. 561 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:32,059 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2018168020] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:32,060 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:32,060 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35] total 35 [2021-11-09 09:33:32,060 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [476810299] [2021-11-09 09:33:32,060 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:32,061 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:32,061 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2021-11-09 09:33:32,062 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2021-11-09 09:33:32,062 INFO L87 Difference]: Start difference. First operand 37 states and 38 transitions. cyclomatic complexity: 2 Second operand has 36 states, 36 states have (on average 1.0) internal successors, (36), 35 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:32,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:32,109 INFO L93 Difference]: Finished difference Result 38 states and 39 transitions. [2021-11-09 09:33:32,109 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2021-11-09 09:33:32,109 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38 states and 39 transitions. [2021-11-09 09:33:32,110 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 37 [2021-11-09 09:33:32,110 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38 states to 38 states and 39 transitions. [2021-11-09 09:33:32,111 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38 [2021-11-09 09:33:32,111 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38 [2021-11-09 09:33:32,111 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38 states and 39 transitions. [2021-11-09 09:33:32,111 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:32,111 INFO L681 BuchiCegarLoop]: Abstraction has 38 states and 39 transitions. [2021-11-09 09:33:32,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states and 39 transitions. [2021-11-09 09:33:32,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 38. [2021-11-09 09:33:32,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38 states, 38 states have (on average 1.0263157894736843) internal successors, (39), 37 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:32,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 39 transitions. [2021-11-09 09:33:32,113 INFO L704 BuchiCegarLoop]: Abstraction has 38 states and 39 transitions. [2021-11-09 09:33:32,113 INFO L587 BuchiCegarLoop]: Abstraction has 38 states and 39 transitions. [2021-11-09 09:33:32,113 INFO L425 BuchiCegarLoop]: ======== Iteration 35============ [2021-11-09 09:33:32,113 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38 states and 39 transitions. [2021-11-09 09:33:32,114 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 37 [2021-11-09 09:33:32,114 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:32,114 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:32,114 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:32,115 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [34, 1, 1, 1] [2021-11-09 09:33:32,115 INFO L791 eck$LassoCheckResult]: Stem: 4088#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 4085#L19-2 [2021-11-09 09:33:32,115 INFO L793 eck$LassoCheckResult]: Loop: 4085#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 4086#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4089#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4122#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4121#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4120#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4119#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4118#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4117#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4116#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4115#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4114#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4113#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4112#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4111#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4110#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4109#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4108#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4107#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4106#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4105#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4104#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4103#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4102#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4101#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4100#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4099#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4098#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4097#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4096#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4095#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4094#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4093#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4092#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4091#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4090#L21-2 assume !(main_~x2~0 > 1); 4087#L21-3 main_~x1~0 := 1 + main_~x1~0; 4085#L19-2 [2021-11-09 09:33:32,115 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:32,116 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 35 times [2021-11-09 09:33:32,116 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:32,116 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [838978434] [2021-11-09 09:33:32,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:32,116 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:32,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:32,122 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:32,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:32,125 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:32,126 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:32,126 INFO L85 PathProgramCache]: Analyzing trace with hash -1303137745, now seen corresponding path program 34 times [2021-11-09 09:33:32,126 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:32,126 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [310752140] [2021-11-09 09:33:32,126 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:32,126 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:32,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:32,738 INFO L134 CoverageAnalysis]: Checked inductivity of 595 backedges. 0 proven. 595 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:32,739 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:32,739 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [310752140] [2021-11-09 09:33:32,739 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [310752140] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:32,739 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1483897467] [2021-11-09 09:33:32,739 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:33:32,739 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:32,739 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:32,740 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:32,741 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2021-11-09 09:33:32,976 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:33:32,976 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:32,977 INFO L263 TraceCheckSpWp]: Trace formula consists of 110 conjuncts, 36 conjunts are in the unsatisfiable core [2021-11-09 09:33:32,978 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:33,091 INFO L134 CoverageAnalysis]: Checked inductivity of 595 backedges. 0 proven. 595 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:33,091 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1483897467] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:33,091 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:33,092 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36] total 36 [2021-11-09 09:33:33,092 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [517159276] [2021-11-09 09:33:33,093 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:33,093 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:33,094 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2021-11-09 09:33:33,094 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2021-11-09 09:33:33,094 INFO L87 Difference]: Start difference. First operand 38 states and 39 transitions. cyclomatic complexity: 2 Second operand has 37 states, 37 states have (on average 1.0) internal successors, (37), 36 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:33,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:33,131 INFO L93 Difference]: Finished difference Result 39 states and 40 transitions. [2021-11-09 09:33:33,131 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2021-11-09 09:33:33,131 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39 states and 40 transitions. [2021-11-09 09:33:33,132 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 38 [2021-11-09 09:33:33,132 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39 states to 39 states and 40 transitions. [2021-11-09 09:33:33,132 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39 [2021-11-09 09:33:33,132 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39 [2021-11-09 09:33:33,133 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 40 transitions. [2021-11-09 09:33:33,133 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:33,133 INFO L681 BuchiCegarLoop]: Abstraction has 39 states and 40 transitions. [2021-11-09 09:33:33,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 40 transitions. [2021-11-09 09:33:33,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 39. [2021-11-09 09:33:33,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 39 states have (on average 1.0256410256410255) internal successors, (40), 38 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:33,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 40 transitions. [2021-11-09 09:33:33,134 INFO L704 BuchiCegarLoop]: Abstraction has 39 states and 40 transitions. [2021-11-09 09:33:33,135 INFO L587 BuchiCegarLoop]: Abstraction has 39 states and 40 transitions. [2021-11-09 09:33:33,135 INFO L425 BuchiCegarLoop]: ======== Iteration 36============ [2021-11-09 09:33:33,135 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 40 transitions. [2021-11-09 09:33:33,135 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 38 [2021-11-09 09:33:33,135 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:33,135 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:33,136 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:33,136 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [35, 1, 1, 1] [2021-11-09 09:33:33,136 INFO L791 eck$LassoCheckResult]: Stem: 4313#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 4310#L19-2 [2021-11-09 09:33:33,136 INFO L793 eck$LassoCheckResult]: Loop: 4310#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 4311#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4314#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4348#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4347#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4346#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4345#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4344#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4343#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4342#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4341#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4340#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4339#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4338#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4337#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4336#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4335#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4334#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4333#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4332#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4331#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4330#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4329#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4328#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4327#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4326#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4325#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4324#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4323#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4322#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4321#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4320#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4319#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4318#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4317#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4316#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4315#L21-2 assume !(main_~x2~0 > 1); 4312#L21-3 main_~x1~0 := 1 + main_~x1~0; 4310#L19-2 [2021-11-09 09:33:33,137 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:33,137 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 36 times [2021-11-09 09:33:33,137 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:33,137 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1714925383] [2021-11-09 09:33:33,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:33,137 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:33,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:33,141 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:33,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:33,142 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:33,143 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:33,143 INFO L85 PathProgramCache]: Analyzing trace with hash -1742562672, now seen corresponding path program 35 times [2021-11-09 09:33:33,143 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:33,143 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135702695] [2021-11-09 09:33:33,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:33,144 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:33,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:33,751 INFO L134 CoverageAnalysis]: Checked inductivity of 630 backedges. 0 proven. 630 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:33,751 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:33,751 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2135702695] [2021-11-09 09:33:33,751 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2135702695] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:33,751 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1440593944] [2021-11-09 09:33:33,751 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:33:33,751 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:33,751 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:33,753 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:33,754 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2021-11-09 09:33:34,004 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2021-11-09 09:33:34,004 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:34,005 INFO L263 TraceCheckSpWp]: Trace formula consists of 113 conjuncts, 37 conjunts are in the unsatisfiable core [2021-11-09 09:33:34,006 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:34,172 INFO L134 CoverageAnalysis]: Checked inductivity of 630 backedges. 0 proven. 630 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:34,172 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1440593944] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:34,172 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:34,172 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37] total 37 [2021-11-09 09:33:34,172 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2082553788] [2021-11-09 09:33:34,173 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:34,173 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:34,173 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2021-11-09 09:33:34,174 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2021-11-09 09:33:34,174 INFO L87 Difference]: Start difference. First operand 39 states and 40 transitions. cyclomatic complexity: 2 Second operand has 38 states, 38 states have (on average 1.0) internal successors, (38), 37 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:34,215 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:34,215 INFO L93 Difference]: Finished difference Result 40 states and 41 transitions. [2021-11-09 09:33:34,216 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2021-11-09 09:33:34,216 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40 states and 41 transitions. [2021-11-09 09:33:34,216 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 39 [2021-11-09 09:33:34,217 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40 states to 40 states and 41 transitions. [2021-11-09 09:33:34,217 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40 [2021-11-09 09:33:34,217 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40 [2021-11-09 09:33:34,217 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40 states and 41 transitions. [2021-11-09 09:33:34,217 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:34,217 INFO L681 BuchiCegarLoop]: Abstraction has 40 states and 41 transitions. [2021-11-09 09:33:34,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states and 41 transitions. [2021-11-09 09:33:34,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 40. [2021-11-09 09:33:34,219 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40 states, 40 states have (on average 1.025) internal successors, (41), 39 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:34,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 41 transitions. [2021-11-09 09:33:34,219 INFO L704 BuchiCegarLoop]: Abstraction has 40 states and 41 transitions. [2021-11-09 09:33:34,219 INFO L587 BuchiCegarLoop]: Abstraction has 40 states and 41 transitions. [2021-11-09 09:33:34,219 INFO L425 BuchiCegarLoop]: ======== Iteration 37============ [2021-11-09 09:33:34,219 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40 states and 41 transitions. [2021-11-09 09:33:34,220 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 39 [2021-11-09 09:33:34,220 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:34,220 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:34,220 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:34,220 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [36, 1, 1, 1] [2021-11-09 09:33:34,221 INFO L791 eck$LassoCheckResult]: Stem: 4544#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 4541#L19-2 [2021-11-09 09:33:34,221 INFO L793 eck$LassoCheckResult]: Loop: 4541#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 4542#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4545#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4580#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4579#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4578#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4577#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4576#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4575#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4574#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4573#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4572#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4571#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4570#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4569#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4568#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4567#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4566#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4565#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4564#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4563#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4562#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4561#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4560#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4559#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4558#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4557#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4556#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4555#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4554#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4553#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4552#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4551#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4550#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4549#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4548#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4547#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4546#L21-2 assume !(main_~x2~0 > 1); 4543#L21-3 main_~x1~0 := 1 + main_~x1~0; 4541#L19-2 [2021-11-09 09:33:34,221 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:34,221 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 37 times [2021-11-09 09:33:34,221 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:34,221 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [50383812] [2021-11-09 09:33:34,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:34,222 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:34,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:34,226 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:34,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:34,227 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:34,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:34,228 INFO L85 PathProgramCache]: Analyzing trace with hash 1815133775, now seen corresponding path program 36 times [2021-11-09 09:33:34,228 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:34,228 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [482294025] [2021-11-09 09:33:34,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:34,228 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:34,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:34,896 INFO L134 CoverageAnalysis]: Checked inductivity of 666 backedges. 0 proven. 666 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:34,896 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:34,896 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [482294025] [2021-11-09 09:33:34,897 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [482294025] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:34,897 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [290728291] [2021-11-09 09:33:34,897 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:33:34,897 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:34,897 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:34,899 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:34,923 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2021-11-09 09:33:35,216 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2021-11-09 09:33:35,216 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:35,217 INFO L263 TraceCheckSpWp]: Trace formula consists of 116 conjuncts, 38 conjunts are in the unsatisfiable core [2021-11-09 09:33:35,218 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:35,379 INFO L134 CoverageAnalysis]: Checked inductivity of 666 backedges. 0 proven. 666 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:35,380 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [290728291] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:35,380 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:35,380 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38] total 38 [2021-11-09 09:33:35,381 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [629349119] [2021-11-09 09:33:35,381 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:35,381 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:35,403 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2021-11-09 09:33:35,403 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=741, Invalid=741, Unknown=0, NotChecked=0, Total=1482 [2021-11-09 09:33:35,404 INFO L87 Difference]: Start difference. First operand 40 states and 41 transitions. cyclomatic complexity: 2 Second operand has 39 states, 39 states have (on average 1.0) internal successors, (39), 38 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:35,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:35,458 INFO L93 Difference]: Finished difference Result 41 states and 42 transitions. [2021-11-09 09:33:35,458 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2021-11-09 09:33:35,458 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41 states and 42 transitions. [2021-11-09 09:33:35,459 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 40 [2021-11-09 09:33:35,459 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41 states to 41 states and 42 transitions. [2021-11-09 09:33:35,459 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41 [2021-11-09 09:33:35,459 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41 [2021-11-09 09:33:35,460 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41 states and 42 transitions. [2021-11-09 09:33:35,460 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:35,460 INFO L681 BuchiCegarLoop]: Abstraction has 41 states and 42 transitions. [2021-11-09 09:33:35,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states and 42 transitions. [2021-11-09 09:33:35,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 41. [2021-11-09 09:33:35,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 41 states have (on average 1.024390243902439) internal successors, (42), 40 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:35,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 42 transitions. [2021-11-09 09:33:35,461 INFO L704 BuchiCegarLoop]: Abstraction has 41 states and 42 transitions. [2021-11-09 09:33:35,461 INFO L587 BuchiCegarLoop]: Abstraction has 41 states and 42 transitions. [2021-11-09 09:33:35,461 INFO L425 BuchiCegarLoop]: ======== Iteration 38============ [2021-11-09 09:33:35,461 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41 states and 42 transitions. [2021-11-09 09:33:35,462 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 40 [2021-11-09 09:33:35,462 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:35,462 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:35,462 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:35,462 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [37, 1, 1, 1] [2021-11-09 09:33:35,462 INFO L791 eck$LassoCheckResult]: Stem: 4781#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 4778#L19-2 [2021-11-09 09:33:35,463 INFO L793 eck$LassoCheckResult]: Loop: 4778#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 4779#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4782#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4818#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4817#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4816#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4815#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4814#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4813#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4812#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4811#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4810#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4809#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4808#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4807#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4806#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4805#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4804#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4803#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4802#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4801#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4800#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4799#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4798#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4797#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4796#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4795#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4794#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4793#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4792#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4791#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4790#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4789#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4788#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4787#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4786#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4785#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4784#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 4783#L21-2 assume !(main_~x2~0 > 1); 4780#L21-3 main_~x1~0 := 1 + main_~x1~0; 4778#L19-2 [2021-11-09 09:33:35,463 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:35,463 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 38 times [2021-11-09 09:33:35,464 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:35,464 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [329713538] [2021-11-09 09:33:35,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:35,464 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:35,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:35,471 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:35,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:35,472 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:35,473 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:35,473 INFO L85 PathProgramCache]: Analyzing trace with hash 434573936, now seen corresponding path program 37 times [2021-11-09 09:33:35,473 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:35,473 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1320567443] [2021-11-09 09:33:35,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:35,474 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:35,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:36,153 INFO L134 CoverageAnalysis]: Checked inductivity of 703 backedges. 0 proven. 703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:36,153 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:36,153 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1320567443] [2021-11-09 09:33:36,153 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1320567443] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:36,153 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2141664284] [2021-11-09 09:33:36,154 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:33:36,154 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:36,154 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:36,155 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:36,164 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2021-11-09 09:33:36,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:36,454 INFO L263 TraceCheckSpWp]: Trace formula consists of 119 conjuncts, 39 conjunts are in the unsatisfiable core [2021-11-09 09:33:36,454 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:36,572 INFO L134 CoverageAnalysis]: Checked inductivity of 703 backedges. 0 proven. 703 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:36,572 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2141664284] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:36,572 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:36,572 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39] total 39 [2021-11-09 09:33:36,573 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1757570156] [2021-11-09 09:33:36,573 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:36,573 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:36,574 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2021-11-09 09:33:36,574 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2021-11-09 09:33:36,575 INFO L87 Difference]: Start difference. First operand 41 states and 42 transitions. cyclomatic complexity: 2 Second operand has 40 states, 40 states have (on average 1.0) internal successors, (40), 39 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:36,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:36,611 INFO L93 Difference]: Finished difference Result 42 states and 43 transitions. [2021-11-09 09:33:36,612 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2021-11-09 09:33:36,612 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42 states and 43 transitions. [2021-11-09 09:33:36,613 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 41 [2021-11-09 09:33:36,613 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42 states to 42 states and 43 transitions. [2021-11-09 09:33:36,613 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42 [2021-11-09 09:33:36,613 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42 [2021-11-09 09:33:36,614 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42 states and 43 transitions. [2021-11-09 09:33:36,614 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:36,614 INFO L681 BuchiCegarLoop]: Abstraction has 42 states and 43 transitions. [2021-11-09 09:33:36,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states and 43 transitions. [2021-11-09 09:33:36,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 42. [2021-11-09 09:33:36,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 42 states have (on average 1.0238095238095237) internal successors, (43), 41 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:36,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 43 transitions. [2021-11-09 09:33:36,616 INFO L704 BuchiCegarLoop]: Abstraction has 42 states and 43 transitions. [2021-11-09 09:33:36,616 INFO L587 BuchiCegarLoop]: Abstraction has 42 states and 43 transitions. [2021-11-09 09:33:36,616 INFO L425 BuchiCegarLoop]: ======== Iteration 39============ [2021-11-09 09:33:36,616 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42 states and 43 transitions. [2021-11-09 09:33:36,617 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 41 [2021-11-09 09:33:36,617 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:36,617 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:36,617 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:36,617 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [38, 1, 1, 1] [2021-11-09 09:33:36,618 INFO L791 eck$LassoCheckResult]: Stem: 5024#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 5021#L19-2 [2021-11-09 09:33:36,618 INFO L793 eck$LassoCheckResult]: Loop: 5021#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 5022#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5025#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5062#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5061#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5060#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5059#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5058#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5057#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5056#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5055#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5054#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5053#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5052#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5051#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5050#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5049#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5048#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5047#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5046#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5045#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5044#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5043#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5042#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5041#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5040#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5039#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5038#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5037#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5036#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5035#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5034#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5033#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5032#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5031#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5030#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5029#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5028#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5027#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5026#L21-2 assume !(main_~x2~0 > 1); 5023#L21-3 main_~x1~0 := 1 + main_~x1~0; 5021#L19-2 [2021-11-09 09:33:36,618 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:36,618 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 39 times [2021-11-09 09:33:36,618 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:36,619 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1572244868] [2021-11-09 09:33:36,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:36,619 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:36,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:36,625 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:36,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:36,627 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:36,628 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:36,628 INFO L85 PathProgramCache]: Analyzing trace with hash 586891887, now seen corresponding path program 38 times [2021-11-09 09:33:36,628 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:36,628 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2015756728] [2021-11-09 09:33:36,628 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:36,628 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:36,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:37,287 INFO L134 CoverageAnalysis]: Checked inductivity of 741 backedges. 0 proven. 741 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:37,288 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:37,288 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2015756728] [2021-11-09 09:33:37,288 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2015756728] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:37,288 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [563281141] [2021-11-09 09:33:37,288 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:33:37,288 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:37,288 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:37,289 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:37,291 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2021-11-09 09:33:37,581 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:33:37,581 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:37,582 INFO L263 TraceCheckSpWp]: Trace formula consists of 122 conjuncts, 40 conjunts are in the unsatisfiable core [2021-11-09 09:33:37,583 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:37,727 INFO L134 CoverageAnalysis]: Checked inductivity of 741 backedges. 0 proven. 741 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:37,727 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [563281141] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:37,727 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:37,727 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40] total 40 [2021-11-09 09:33:37,727 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [36891932] [2021-11-09 09:33:37,728 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:37,728 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:37,729 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2021-11-09 09:33:37,729 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=820, Invalid=820, Unknown=0, NotChecked=0, Total=1640 [2021-11-09 09:33:37,730 INFO L87 Difference]: Start difference. First operand 42 states and 43 transitions. cyclomatic complexity: 2 Second operand has 41 states, 41 states have (on average 1.0) internal successors, (41), 40 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:37,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:37,783 INFO L93 Difference]: Finished difference Result 43 states and 44 transitions. [2021-11-09 09:33:37,783 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2021-11-09 09:33:37,783 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 44 transitions. [2021-11-09 09:33:37,783 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 42 [2021-11-09 09:33:37,784 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 43 states and 44 transitions. [2021-11-09 09:33:37,784 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43 [2021-11-09 09:33:37,784 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43 [2021-11-09 09:33:37,784 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43 states and 44 transitions. [2021-11-09 09:33:37,785 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:37,785 INFO L681 BuchiCegarLoop]: Abstraction has 43 states and 44 transitions. [2021-11-09 09:33:37,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states and 44 transitions. [2021-11-09 09:33:37,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 43. [2021-11-09 09:33:37,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43 states, 43 states have (on average 1.0232558139534884) internal successors, (44), 42 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:37,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 44 transitions. [2021-11-09 09:33:37,786 INFO L704 BuchiCegarLoop]: Abstraction has 43 states and 44 transitions. [2021-11-09 09:33:37,787 INFO L587 BuchiCegarLoop]: Abstraction has 43 states and 44 transitions. [2021-11-09 09:33:37,787 INFO L425 BuchiCegarLoop]: ======== Iteration 40============ [2021-11-09 09:33:37,787 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43 states and 44 transitions. [2021-11-09 09:33:37,787 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 42 [2021-11-09 09:33:37,787 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:37,787 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:37,788 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:37,788 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [39, 1, 1, 1] [2021-11-09 09:33:37,788 INFO L791 eck$LassoCheckResult]: Stem: 5273#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 5270#L19-2 [2021-11-09 09:33:37,788 INFO L793 eck$LassoCheckResult]: Loop: 5270#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 5271#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5274#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5312#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5311#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5310#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5309#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5308#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5307#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5306#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5305#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5304#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5303#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5302#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5301#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5300#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5299#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5298#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5297#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5296#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5295#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5294#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5293#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5292#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5291#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5290#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5289#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5288#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5287#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5286#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5285#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5284#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5283#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5282#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5281#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5280#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5279#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5278#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5277#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5276#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5275#L21-2 assume !(main_~x2~0 > 1); 5272#L21-3 main_~x1~0 := 1 + main_~x1~0; 5270#L19-2 [2021-11-09 09:33:37,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:37,789 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 40 times [2021-11-09 09:33:37,789 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:37,789 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [496968848] [2021-11-09 09:33:37,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:37,789 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:37,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:37,793 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:37,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:37,794 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:37,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:37,795 INFO L85 PathProgramCache]: Analyzing trace with hash 1013781072, now seen corresponding path program 39 times [2021-11-09 09:33:37,795 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:37,795 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [132071933] [2021-11-09 09:33:37,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:37,795 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:37,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:38,419 INFO L134 CoverageAnalysis]: Checked inductivity of 780 backedges. 0 proven. 780 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:38,419 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:38,419 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [132071933] [2021-11-09 09:33:38,419 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [132071933] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:38,419 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [551660540] [2021-11-09 09:33:38,419 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:33:38,420 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:38,420 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:38,421 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:38,423 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2021-11-09 09:33:38,725 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2021-11-09 09:33:38,725 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:38,726 INFO L263 TraceCheckSpWp]: Trace formula consists of 125 conjuncts, 41 conjunts are in the unsatisfiable core [2021-11-09 09:33:38,727 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:38,868 INFO L134 CoverageAnalysis]: Checked inductivity of 780 backedges. 0 proven. 780 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:38,870 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [551660540] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:38,870 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:38,870 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41] total 41 [2021-11-09 09:33:38,870 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [44952267] [2021-11-09 09:33:38,871 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:38,871 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:38,871 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2021-11-09 09:33:38,872 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2021-11-09 09:33:38,872 INFO L87 Difference]: Start difference. First operand 43 states and 44 transitions. cyclomatic complexity: 2 Second operand has 42 states, 42 states have (on average 1.0) internal successors, (42), 41 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:38,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:38,922 INFO L93 Difference]: Finished difference Result 44 states and 45 transitions. [2021-11-09 09:33:38,922 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2021-11-09 09:33:38,923 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44 states and 45 transitions. [2021-11-09 09:33:38,923 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 43 [2021-11-09 09:33:38,924 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44 states to 44 states and 45 transitions. [2021-11-09 09:33:38,924 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44 [2021-11-09 09:33:38,924 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44 [2021-11-09 09:33:38,924 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44 states and 45 transitions. [2021-11-09 09:33:38,925 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:38,925 INFO L681 BuchiCegarLoop]: Abstraction has 44 states and 45 transitions. [2021-11-09 09:33:38,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states and 45 transitions. [2021-11-09 09:33:38,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 44. [2021-11-09 09:33:38,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 44 states have (on average 1.0227272727272727) internal successors, (45), 43 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:38,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 45 transitions. [2021-11-09 09:33:38,927 INFO L704 BuchiCegarLoop]: Abstraction has 44 states and 45 transitions. [2021-11-09 09:33:38,927 INFO L587 BuchiCegarLoop]: Abstraction has 44 states and 45 transitions. [2021-11-09 09:33:38,927 INFO L425 BuchiCegarLoop]: ======== Iteration 41============ [2021-11-09 09:33:38,927 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44 states and 45 transitions. [2021-11-09 09:33:38,930 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 43 [2021-11-09 09:33:38,930 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:38,931 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:38,931 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:38,931 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [40, 1, 1, 1] [2021-11-09 09:33:38,931 INFO L791 eck$LassoCheckResult]: Stem: 5528#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 5525#L19-2 [2021-11-09 09:33:38,932 INFO L793 eck$LassoCheckResult]: Loop: 5525#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 5526#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5529#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5568#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5567#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5566#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5565#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5564#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5563#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5562#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5561#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5560#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5559#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5558#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5557#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5556#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5555#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5554#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5553#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5552#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5551#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5550#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5549#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5548#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5547#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5546#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5545#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5544#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5543#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5542#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5541#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5540#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5539#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5538#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5537#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5536#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5535#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5534#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5533#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5532#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5531#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5530#L21-2 assume !(main_~x2~0 > 1); 5527#L21-3 main_~x1~0 := 1 + main_~x1~0; 5525#L19-2 [2021-11-09 09:33:38,932 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:38,932 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 41 times [2021-11-09 09:33:38,932 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:38,932 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [70802554] [2021-11-09 09:33:38,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:38,933 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:38,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:38,937 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:38,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:38,940 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:38,941 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:38,941 INFO L85 PathProgramCache]: Analyzing trace with hash 1362443919, now seen corresponding path program 40 times [2021-11-09 09:33:38,941 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:38,941 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1289203698] [2021-11-09 09:33:38,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:38,941 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:38,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:39,771 INFO L134 CoverageAnalysis]: Checked inductivity of 820 backedges. 0 proven. 820 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:39,771 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:39,771 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1289203698] [2021-11-09 09:33:39,771 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1289203698] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:39,771 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1720856786] [2021-11-09 09:33:39,771 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:33:39,771 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:39,772 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:39,773 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:39,775 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2021-11-09 09:33:40,146 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:33:40,146 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:40,148 INFO L263 TraceCheckSpWp]: Trace formula consists of 128 conjuncts, 42 conjunts are in the unsatisfiable core [2021-11-09 09:33:40,149 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:40,290 INFO L134 CoverageAnalysis]: Checked inductivity of 820 backedges. 0 proven. 820 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:40,290 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1720856786] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:40,291 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:40,291 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42] total 42 [2021-11-09 09:33:40,291 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1271760457] [2021-11-09 09:33:40,291 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:40,291 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:40,292 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2021-11-09 09:33:40,293 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=903, Invalid=903, Unknown=0, NotChecked=0, Total=1806 [2021-11-09 09:33:40,293 INFO L87 Difference]: Start difference. First operand 44 states and 45 transitions. cyclomatic complexity: 2 Second operand has 43 states, 43 states have (on average 1.0) internal successors, (43), 42 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:40,337 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:40,337 INFO L93 Difference]: Finished difference Result 45 states and 46 transitions. [2021-11-09 09:33:40,337 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2021-11-09 09:33:40,338 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45 states and 46 transitions. [2021-11-09 09:33:40,339 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 44 [2021-11-09 09:33:40,339 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45 states to 45 states and 46 transitions. [2021-11-09 09:33:40,340 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45 [2021-11-09 09:33:40,341 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45 [2021-11-09 09:33:40,341 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45 states and 46 transitions. [2021-11-09 09:33:40,341 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:40,342 INFO L681 BuchiCegarLoop]: Abstraction has 45 states and 46 transitions. [2021-11-09 09:33:40,342 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states and 46 transitions. [2021-11-09 09:33:40,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 45. [2021-11-09 09:33:40,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 45 states have (on average 1.0222222222222221) internal successors, (46), 44 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:40,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 46 transitions. [2021-11-09 09:33:40,343 INFO L704 BuchiCegarLoop]: Abstraction has 45 states and 46 transitions. [2021-11-09 09:33:40,343 INFO L587 BuchiCegarLoop]: Abstraction has 45 states and 46 transitions. [2021-11-09 09:33:40,344 INFO L425 BuchiCegarLoop]: ======== Iteration 42============ [2021-11-09 09:33:40,344 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45 states and 46 transitions. [2021-11-09 09:33:40,344 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 44 [2021-11-09 09:33:40,344 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:40,344 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:40,345 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:40,345 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [41, 1, 1, 1] [2021-11-09 09:33:40,345 INFO L791 eck$LassoCheckResult]: Stem: 5789#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 5786#L19-2 [2021-11-09 09:33:40,345 INFO L793 eck$LassoCheckResult]: Loop: 5786#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 5787#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5790#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5830#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5829#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5828#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5827#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5826#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5825#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5824#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5823#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5822#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5821#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5820#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5819#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5818#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5817#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5816#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5815#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5814#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5813#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5812#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5811#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5810#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5809#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5808#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5807#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5806#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5805#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5804#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5803#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5802#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5801#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5800#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5799#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5798#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5797#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5796#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5795#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5794#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5793#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5792#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 5791#L21-2 assume !(main_~x2~0 > 1); 5788#L21-3 main_~x1~0 := 1 + main_~x1~0; 5786#L19-2 [2021-11-09 09:33:40,346 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:40,346 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 42 times [2021-11-09 09:33:40,346 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:40,346 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1714942994] [2021-11-09 09:33:40,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:40,346 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:40,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:40,380 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:40,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:40,382 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:40,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:40,382 INFO L85 PathProgramCache]: Analyzing trace with hash -713909712, now seen corresponding path program 41 times [2021-11-09 09:33:40,382 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:40,382 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1146837473] [2021-11-09 09:33:40,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:40,382 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:40,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:41,085 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 0 proven. 861 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:41,086 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:41,086 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1146837473] [2021-11-09 09:33:41,086 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1146837473] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:41,086 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1808314507] [2021-11-09 09:33:41,086 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:33:41,086 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:41,086 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:41,088 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:41,088 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2021-11-09 09:33:41,423 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2021-11-09 09:33:41,423 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:41,424 INFO L263 TraceCheckSpWp]: Trace formula consists of 131 conjuncts, 43 conjunts are in the unsatisfiable core [2021-11-09 09:33:41,425 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:41,571 INFO L134 CoverageAnalysis]: Checked inductivity of 861 backedges. 0 proven. 861 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:41,572 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1808314507] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:41,572 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:41,572 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43] total 43 [2021-11-09 09:33:41,572 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [888163880] [2021-11-09 09:33:41,573 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:41,573 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:41,573 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2021-11-09 09:33:41,574 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2021-11-09 09:33:41,574 INFO L87 Difference]: Start difference. First operand 45 states and 46 transitions. cyclomatic complexity: 2 Second operand has 44 states, 44 states have (on average 1.0) internal successors, (44), 43 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:41,670 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:41,670 INFO L93 Difference]: Finished difference Result 46 states and 47 transitions. [2021-11-09 09:33:41,670 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2021-11-09 09:33:41,670 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 46 states and 47 transitions. [2021-11-09 09:33:41,672 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 45 [2021-11-09 09:33:41,673 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 46 states to 46 states and 47 transitions. [2021-11-09 09:33:41,673 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46 [2021-11-09 09:33:41,674 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46 [2021-11-09 09:33:41,674 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46 states and 47 transitions. [2021-11-09 09:33:41,674 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:41,674 INFO L681 BuchiCegarLoop]: Abstraction has 46 states and 47 transitions. [2021-11-09 09:33:41,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states and 47 transitions. [2021-11-09 09:33:41,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 46. [2021-11-09 09:33:41,681 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46 states, 46 states have (on average 1.0217391304347827) internal successors, (47), 45 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:41,682 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 47 transitions. [2021-11-09 09:33:41,682 INFO L704 BuchiCegarLoop]: Abstraction has 46 states and 47 transitions. [2021-11-09 09:33:41,682 INFO L587 BuchiCegarLoop]: Abstraction has 46 states and 47 transitions. [2021-11-09 09:33:41,682 INFO L425 BuchiCegarLoop]: ======== Iteration 43============ [2021-11-09 09:33:41,682 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46 states and 47 transitions. [2021-11-09 09:33:41,683 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 45 [2021-11-09 09:33:41,683 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:41,683 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:41,683 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:41,683 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [42, 1, 1, 1] [2021-11-09 09:33:41,684 INFO L791 eck$LassoCheckResult]: Stem: 6056#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 6053#L19-2 [2021-11-09 09:33:41,684 INFO L793 eck$LassoCheckResult]: Loop: 6053#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 6054#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6057#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6098#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6097#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6096#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6095#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6094#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6093#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6092#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6091#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6090#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6089#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6088#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6087#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6086#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6085#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6084#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6083#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6082#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6081#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6080#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6079#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6078#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6077#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6076#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6075#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6074#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6073#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6072#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6071#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6070#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6069#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6068#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6067#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6066#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6065#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6064#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6063#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6062#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6061#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6060#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6059#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6058#L21-2 assume !(main_~x2~0 > 1); 6055#L21-3 main_~x1~0 := 1 + main_~x1~0; 6053#L19-2 [2021-11-09 09:33:41,684 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:41,684 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 43 times [2021-11-09 09:33:41,685 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:41,685 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1652539009] [2021-11-09 09:33:41,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:41,685 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:41,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:41,706 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:41,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:41,709 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:41,710 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:41,710 INFO L85 PathProgramCache]: Analyzing trace with hash -656362833, now seen corresponding path program 42 times [2021-11-09 09:33:41,710 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:41,710 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1113699347] [2021-11-09 09:33:41,710 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:41,711 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:41,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:42,600 INFO L134 CoverageAnalysis]: Checked inductivity of 903 backedges. 0 proven. 903 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:42,600 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:42,600 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1113699347] [2021-11-09 09:33:42,600 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1113699347] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:42,600 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [381693792] [2021-11-09 09:33:42,600 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:33:42,601 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:42,601 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:42,604 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:42,604 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2021-11-09 09:33:42,970 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) [2021-11-09 09:33:42,970 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:42,972 INFO L263 TraceCheckSpWp]: Trace formula consists of 134 conjuncts, 44 conjunts are in the unsatisfiable core [2021-11-09 09:33:42,973 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:43,092 INFO L134 CoverageAnalysis]: Checked inductivity of 903 backedges. 0 proven. 903 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:43,092 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [381693792] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:43,092 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:43,093 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44] total 44 [2021-11-09 09:33:43,093 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1883230356] [2021-11-09 09:33:43,093 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:43,093 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:43,094 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2021-11-09 09:33:43,095 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=990, Invalid=990, Unknown=0, NotChecked=0, Total=1980 [2021-11-09 09:33:43,095 INFO L87 Difference]: Start difference. First operand 46 states and 47 transitions. cyclomatic complexity: 2 Second operand has 45 states, 45 states have (on average 1.0) internal successors, (45), 44 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:43,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:43,135 INFO L93 Difference]: Finished difference Result 47 states and 48 transitions. [2021-11-09 09:33:43,135 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2021-11-09 09:33:43,135 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 47 states and 48 transitions. [2021-11-09 09:33:43,136 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 46 [2021-11-09 09:33:43,136 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 47 states to 47 states and 48 transitions. [2021-11-09 09:33:43,136 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 47 [2021-11-09 09:33:43,136 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 47 [2021-11-09 09:33:43,137 INFO L73 IsDeterministic]: Start isDeterministic. Operand 47 states and 48 transitions. [2021-11-09 09:33:43,137 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:43,137 INFO L681 BuchiCegarLoop]: Abstraction has 47 states and 48 transitions. [2021-11-09 09:33:43,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states and 48 transitions. [2021-11-09 09:33:43,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 47. [2021-11-09 09:33:43,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.0212765957446808) internal successors, (48), 46 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:43,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 48 transitions. [2021-11-09 09:33:43,138 INFO L704 BuchiCegarLoop]: Abstraction has 47 states and 48 transitions. [2021-11-09 09:33:43,138 INFO L587 BuchiCegarLoop]: Abstraction has 47 states and 48 transitions. [2021-11-09 09:33:43,139 INFO L425 BuchiCegarLoop]: ======== Iteration 44============ [2021-11-09 09:33:43,139 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 48 transitions. [2021-11-09 09:33:43,139 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 46 [2021-11-09 09:33:43,139 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:43,139 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:43,140 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:43,140 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [43, 1, 1, 1] [2021-11-09 09:33:43,140 INFO L791 eck$LassoCheckResult]: Stem: 6329#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 6326#L19-2 [2021-11-09 09:33:43,140 INFO L793 eck$LassoCheckResult]: Loop: 6326#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 6327#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6330#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6372#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6371#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6370#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6369#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6368#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6367#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6366#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6365#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6364#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6363#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6362#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6361#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6360#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6359#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6358#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6357#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6356#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6355#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6354#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6353#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6352#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6351#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6350#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6349#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6348#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6347#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6346#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6345#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6344#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6343#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6342#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6341#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6340#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6339#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6338#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6337#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6336#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6335#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6334#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6333#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6332#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6331#L21-2 assume !(main_~x2~0 > 1); 6328#L21-3 main_~x1~0 := 1 + main_~x1~0; 6326#L19-2 [2021-11-09 09:33:43,141 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:43,141 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 44 times [2021-11-09 09:33:43,141 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:43,141 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [712045442] [2021-11-09 09:33:43,141 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:43,142 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:43,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:43,169 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:43,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:43,170 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:43,170 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:43,170 INFO L85 PathProgramCache]: Analyzing trace with hash 1127590416, now seen corresponding path program 43 times [2021-11-09 09:33:43,171 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:43,171 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [868412143] [2021-11-09 09:33:43,171 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:43,171 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:43,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:43,944 INFO L134 CoverageAnalysis]: Checked inductivity of 946 backedges. 0 proven. 946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:43,944 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:43,944 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [868412143] [2021-11-09 09:33:43,944 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [868412143] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:43,944 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1279679269] [2021-11-09 09:33:43,944 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:33:43,944 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:43,944 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:43,946 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:43,946 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2021-11-09 09:33:44,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:44,298 INFO L263 TraceCheckSpWp]: Trace formula consists of 137 conjuncts, 45 conjunts are in the unsatisfiable core [2021-11-09 09:33:44,299 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:44,451 INFO L134 CoverageAnalysis]: Checked inductivity of 946 backedges. 0 proven. 946 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:44,452 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1279679269] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:44,452 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:44,452 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45] total 45 [2021-11-09 09:33:44,452 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1652755453] [2021-11-09 09:33:44,453 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:44,453 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:44,453 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2021-11-09 09:33:44,454 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2021-11-09 09:33:44,454 INFO L87 Difference]: Start difference. First operand 47 states and 48 transitions. cyclomatic complexity: 2 Second operand has 46 states, 46 states have (on average 1.0) internal successors, (46), 45 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:44,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:44,509 INFO L93 Difference]: Finished difference Result 48 states and 49 transitions. [2021-11-09 09:33:44,509 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2021-11-09 09:33:44,509 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48 states and 49 transitions. [2021-11-09 09:33:44,510 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 47 [2021-11-09 09:33:44,510 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48 states to 48 states and 49 transitions. [2021-11-09 09:33:44,510 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48 [2021-11-09 09:33:44,511 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48 [2021-11-09 09:33:44,511 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48 states and 49 transitions. [2021-11-09 09:33:44,511 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:44,511 INFO L681 BuchiCegarLoop]: Abstraction has 48 states and 49 transitions. [2021-11-09 09:33:44,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states and 49 transitions. [2021-11-09 09:33:44,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 48. [2021-11-09 09:33:44,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 48 states, 48 states have (on average 1.0208333333333333) internal successors, (49), 47 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:44,513 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 49 transitions. [2021-11-09 09:33:44,513 INFO L704 BuchiCegarLoop]: Abstraction has 48 states and 49 transitions. [2021-11-09 09:33:44,513 INFO L587 BuchiCegarLoop]: Abstraction has 48 states and 49 transitions. [2021-11-09 09:33:44,513 INFO L425 BuchiCegarLoop]: ======== Iteration 45============ [2021-11-09 09:33:44,513 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 48 states and 49 transitions. [2021-11-09 09:33:44,514 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 47 [2021-11-09 09:33:44,514 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:44,514 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:44,514 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:44,515 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [44, 1, 1, 1] [2021-11-09 09:33:44,515 INFO L791 eck$LassoCheckResult]: Stem: 6608#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 6605#L19-2 [2021-11-09 09:33:44,515 INFO L793 eck$LassoCheckResult]: Loop: 6605#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 6606#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6609#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6652#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6651#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6650#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6649#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6648#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6647#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6646#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6645#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6644#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6643#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6642#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6641#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6640#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6639#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6638#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6637#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6636#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6635#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6634#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6633#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6632#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6631#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6630#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6629#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6628#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6627#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6626#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6625#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6624#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6623#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6622#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6621#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6620#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6619#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6618#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6617#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6616#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6615#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6614#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6613#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6612#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6611#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6610#L21-2 assume !(main_~x2~0 > 1); 6607#L21-3 main_~x1~0 := 1 + main_~x1~0; 6605#L19-2 [2021-11-09 09:33:44,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:44,515 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 45 times [2021-11-09 09:33:44,515 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:44,516 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [486472940] [2021-11-09 09:33:44,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:44,516 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:44,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:44,521 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:44,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:44,522 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:44,522 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:44,523 INFO L85 PathProgramCache]: Analyzing trace with hash 595566287, now seen corresponding path program 44 times [2021-11-09 09:33:44,544 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:44,544 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2142427649] [2021-11-09 09:33:44,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:44,545 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:44,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:45,483 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:45,483 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:45,484 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2142427649] [2021-11-09 09:33:45,484 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2142427649] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:45,484 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1912869953] [2021-11-09 09:33:45,484 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:33:45,484 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:45,484 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:45,485 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:45,486 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2021-11-09 09:33:45,857 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:33:45,857 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:45,858 INFO L263 TraceCheckSpWp]: Trace formula consists of 140 conjuncts, 46 conjunts are in the unsatisfiable core [2021-11-09 09:33:45,859 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:45,996 INFO L134 CoverageAnalysis]: Checked inductivity of 990 backedges. 0 proven. 990 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:45,997 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1912869953] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:45,997 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:45,997 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46] total 46 [2021-11-09 09:33:45,997 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [875896843] [2021-11-09 09:33:45,997 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:45,997 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:45,998 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2021-11-09 09:33:45,998 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1081, Invalid=1081, Unknown=0, NotChecked=0, Total=2162 [2021-11-09 09:33:45,999 INFO L87 Difference]: Start difference. First operand 48 states and 49 transitions. cyclomatic complexity: 2 Second operand has 47 states, 47 states have (on average 1.0) internal successors, (47), 46 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:46,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:46,054 INFO L93 Difference]: Finished difference Result 49 states and 50 transitions. [2021-11-09 09:33:46,055 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2021-11-09 09:33:46,055 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49 states and 50 transitions. [2021-11-09 09:33:46,055 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 48 [2021-11-09 09:33:46,056 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49 states to 49 states and 50 transitions. [2021-11-09 09:33:46,056 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49 [2021-11-09 09:33:46,056 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49 [2021-11-09 09:33:46,056 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49 states and 50 transitions. [2021-11-09 09:33:46,057 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:46,057 INFO L681 BuchiCegarLoop]: Abstraction has 49 states and 50 transitions. [2021-11-09 09:33:46,057 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states and 50 transitions. [2021-11-09 09:33:46,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 49. [2021-11-09 09:33:46,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49 states, 49 states have (on average 1.0204081632653061) internal successors, (50), 48 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:46,058 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 50 transitions. [2021-11-09 09:33:46,059 INFO L704 BuchiCegarLoop]: Abstraction has 49 states and 50 transitions. [2021-11-09 09:33:46,059 INFO L587 BuchiCegarLoop]: Abstraction has 49 states and 50 transitions. [2021-11-09 09:33:46,059 INFO L425 BuchiCegarLoop]: ======== Iteration 46============ [2021-11-09 09:33:46,059 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49 states and 50 transitions. [2021-11-09 09:33:46,059 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 48 [2021-11-09 09:33:46,060 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:46,060 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:46,060 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:46,060 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [45, 1, 1, 1] [2021-11-09 09:33:46,060 INFO L791 eck$LassoCheckResult]: Stem: 6893#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 6890#L19-2 [2021-11-09 09:33:46,061 INFO L793 eck$LassoCheckResult]: Loop: 6890#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 6891#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6894#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6938#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6937#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6936#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6935#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6934#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6933#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6932#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6931#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6930#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6929#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6928#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6927#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6926#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6925#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6924#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6923#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6922#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6921#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6920#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6919#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6918#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6917#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6916#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6915#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6914#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6913#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6912#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6911#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6910#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6909#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6908#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6907#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6906#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6905#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6904#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6903#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6902#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6901#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6900#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6899#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6898#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6897#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6896#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 6895#L21-2 assume !(main_~x2~0 > 1); 6892#L21-3 main_~x1~0 := 1 + main_~x1~0; 6890#L19-2 [2021-11-09 09:33:46,061 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:46,061 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 46 times [2021-11-09 09:33:46,061 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:46,061 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1633104948] [2021-11-09 09:33:46,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:46,062 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:46,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:46,104 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:46,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:46,106 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:46,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:46,107 INFO L85 PathProgramCache]: Analyzing trace with hash 1282687472, now seen corresponding path program 45 times [2021-11-09 09:33:46,107 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:46,107 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1788742239] [2021-11-09 09:33:46,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:46,107 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:46,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:47,150 INFO L134 CoverageAnalysis]: Checked inductivity of 1035 backedges. 0 proven. 1035 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:47,150 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:47,150 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1788742239] [2021-11-09 09:33:47,150 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1788742239] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:47,150 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [360129466] [2021-11-09 09:33:47,150 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:33:47,152 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:47,153 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:47,173 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:47,176 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2021-11-09 09:33:47,594 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2021-11-09 09:33:47,594 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:47,596 INFO L263 TraceCheckSpWp]: Trace formula consists of 143 conjuncts, 47 conjunts are in the unsatisfiable core [2021-11-09 09:33:47,597 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:47,772 INFO L134 CoverageAnalysis]: Checked inductivity of 1035 backedges. 0 proven. 1035 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:47,772 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [360129466] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:47,772 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:47,772 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47] total 47 [2021-11-09 09:33:47,772 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1637389504] [2021-11-09 09:33:47,773 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:47,773 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:47,773 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2021-11-09 09:33:47,774 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2021-11-09 09:33:47,774 INFO L87 Difference]: Start difference. First operand 49 states and 50 transitions. cyclomatic complexity: 2 Second operand has 48 states, 48 states have (on average 1.0) internal successors, (48), 47 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:47,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:47,834 INFO L93 Difference]: Finished difference Result 50 states and 51 transitions. [2021-11-09 09:33:47,834 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2021-11-09 09:33:47,834 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 50 states and 51 transitions. [2021-11-09 09:33:47,835 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49 [2021-11-09 09:33:47,835 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 50 states to 50 states and 51 transitions. [2021-11-09 09:33:47,835 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 50 [2021-11-09 09:33:47,835 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 50 [2021-11-09 09:33:47,836 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50 states and 51 transitions. [2021-11-09 09:33:47,836 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:47,836 INFO L681 BuchiCegarLoop]: Abstraction has 50 states and 51 transitions. [2021-11-09 09:33:47,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states and 51 transitions. [2021-11-09 09:33:47,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 50. [2021-11-09 09:33:47,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.02) internal successors, (51), 49 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:47,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 51 transitions. [2021-11-09 09:33:47,838 INFO L704 BuchiCegarLoop]: Abstraction has 50 states and 51 transitions. [2021-11-09 09:33:47,838 INFO L587 BuchiCegarLoop]: Abstraction has 50 states and 51 transitions. [2021-11-09 09:33:47,838 INFO L425 BuchiCegarLoop]: ======== Iteration 47============ [2021-11-09 09:33:47,838 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50 states and 51 transitions. [2021-11-09 09:33:47,839 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 49 [2021-11-09 09:33:47,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:47,839 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:47,839 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:47,839 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [46, 1, 1, 1] [2021-11-09 09:33:47,840 INFO L791 eck$LassoCheckResult]: Stem: 7184#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 7181#L19-2 [2021-11-09 09:33:47,840 INFO L793 eck$LassoCheckResult]: Loop: 7181#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 7182#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7185#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7230#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7229#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7228#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7227#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7226#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7225#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7224#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7223#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7222#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7221#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7220#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7219#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7218#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7217#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7216#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7215#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7214#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7213#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7212#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7211#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7210#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7209#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7208#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7207#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7206#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7205#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7204#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7203#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7202#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7201#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7200#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7199#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7198#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7197#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7196#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7195#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7194#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7193#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7192#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7191#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7190#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7189#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7188#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7187#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7186#L21-2 assume !(main_~x2~0 > 1); 7183#L21-3 main_~x1~0 := 1 + main_~x1~0; 7181#L19-2 [2021-11-09 09:33:47,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:47,840 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 47 times [2021-11-09 09:33:47,840 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:47,840 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021488577] [2021-11-09 09:33:47,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:47,841 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:47,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:47,847 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:47,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:47,850 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:47,850 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:47,850 INFO L85 PathProgramCache]: Analyzing trace with hash 1108607727, now seen corresponding path program 46 times [2021-11-09 09:33:47,850 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:47,851 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1203411649] [2021-11-09 09:33:47,851 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:47,851 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:47,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:48,961 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:48,961 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:48,961 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1203411649] [2021-11-09 09:33:48,961 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1203411649] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:48,961 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1589101790] [2021-11-09 09:33:48,961 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:33:48,961 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:48,962 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:48,963 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:48,965 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2021-11-09 09:33:49,358 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:33:49,359 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:49,360 INFO L263 TraceCheckSpWp]: Trace formula consists of 146 conjuncts, 48 conjunts are in the unsatisfiable core [2021-11-09 09:33:49,361 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:49,519 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:49,519 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1589101790] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:49,519 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:49,519 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48] total 48 [2021-11-09 09:33:49,519 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [700968010] [2021-11-09 09:33:49,520 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:49,520 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:49,520 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2021-11-09 09:33:49,521 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2021-11-09 09:33:49,522 INFO L87 Difference]: Start difference. First operand 50 states and 51 transitions. cyclomatic complexity: 2 Second operand has 49 states, 49 states have (on average 1.0) internal successors, (49), 48 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:49,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:49,568 INFO L93 Difference]: Finished difference Result 51 states and 52 transitions. [2021-11-09 09:33:49,568 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2021-11-09 09:33:49,568 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51 states and 52 transitions. [2021-11-09 09:33:49,569 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 50 [2021-11-09 09:33:49,569 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51 states to 51 states and 52 transitions. [2021-11-09 09:33:49,569 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51 [2021-11-09 09:33:49,569 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51 [2021-11-09 09:33:49,569 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51 states and 52 transitions. [2021-11-09 09:33:49,570 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:49,570 INFO L681 BuchiCegarLoop]: Abstraction has 51 states and 52 transitions. [2021-11-09 09:33:49,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states and 52 transitions. [2021-11-09 09:33:49,571 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2021-11-09 09:33:49,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.0196078431372548) internal successors, (52), 50 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:49,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 52 transitions. [2021-11-09 09:33:49,571 INFO L704 BuchiCegarLoop]: Abstraction has 51 states and 52 transitions. [2021-11-09 09:33:49,571 INFO L587 BuchiCegarLoop]: Abstraction has 51 states and 52 transitions. [2021-11-09 09:33:49,571 INFO L425 BuchiCegarLoop]: ======== Iteration 48============ [2021-11-09 09:33:49,571 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 52 transitions. [2021-11-09 09:33:49,572 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 50 [2021-11-09 09:33:49,572 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:49,572 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:49,572 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:49,572 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [47, 1, 1, 1] [2021-11-09 09:33:49,573 INFO L791 eck$LassoCheckResult]: Stem: 7481#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 7478#L19-2 [2021-11-09 09:33:49,573 INFO L793 eck$LassoCheckResult]: Loop: 7478#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 7479#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7482#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7528#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7527#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7526#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7525#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7524#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7523#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7522#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7521#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7520#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7519#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7518#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7517#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7516#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7515#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7514#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7513#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7512#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7511#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7510#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7509#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7508#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7507#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7506#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7505#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7504#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7503#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7502#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7501#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7500#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7499#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7498#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7497#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7496#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7495#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7494#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7493#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7492#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7491#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7490#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7489#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7488#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7487#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7486#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7485#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7484#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7483#L21-2 assume !(main_~x2~0 > 1); 7480#L21-3 main_~x1~0 := 1 + main_~x1~0; 7478#L19-2 [2021-11-09 09:33:49,573 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:49,573 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 48 times [2021-11-09 09:33:49,573 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:49,573 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [861829603] [2021-11-09 09:33:49,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:49,574 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:49,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:49,578 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:49,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:49,579 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:49,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:49,580 INFO L85 PathProgramCache]: Analyzing trace with hash 7102928, now seen corresponding path program 47 times [2021-11-09 09:33:49,580 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:49,580 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [322085293] [2021-11-09 09:33:49,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:49,580 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:49,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:50,607 INFO L134 CoverageAnalysis]: Checked inductivity of 1128 backedges. 0 proven. 1128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:50,607 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:50,607 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [322085293] [2021-11-09 09:33:50,608 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [322085293] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:50,608 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [414672787] [2021-11-09 09:33:50,608 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:33:50,608 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:50,608 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:50,609 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:50,610 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2021-11-09 09:33:51,039 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2021-11-09 09:33:51,040 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:51,041 INFO L263 TraceCheckSpWp]: Trace formula consists of 149 conjuncts, 49 conjunts are in the unsatisfiable core [2021-11-09 09:33:51,043 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:51,179 INFO L134 CoverageAnalysis]: Checked inductivity of 1128 backedges. 0 proven. 1128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:51,180 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [414672787] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:51,180 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:51,180 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49] total 49 [2021-11-09 09:33:51,180 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1770688298] [2021-11-09 09:33:51,180 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:51,180 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:51,181 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2021-11-09 09:33:51,181 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2021-11-09 09:33:51,182 INFO L87 Difference]: Start difference. First operand 51 states and 52 transitions. cyclomatic complexity: 2 Second operand has 50 states, 50 states have (on average 1.0) internal successors, (50), 49 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:51,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:51,226 INFO L93 Difference]: Finished difference Result 52 states and 53 transitions. [2021-11-09 09:33:51,227 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2021-11-09 09:33:51,227 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52 states and 53 transitions. [2021-11-09 09:33:51,227 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 51 [2021-11-09 09:33:51,228 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52 states to 52 states and 53 transitions. [2021-11-09 09:33:51,228 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 52 [2021-11-09 09:33:51,228 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 52 [2021-11-09 09:33:51,228 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52 states and 53 transitions. [2021-11-09 09:33:51,229 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:51,229 INFO L681 BuchiCegarLoop]: Abstraction has 52 states and 53 transitions. [2021-11-09 09:33:51,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states and 53 transitions. [2021-11-09 09:33:51,230 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 52. [2021-11-09 09:33:51,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.0192307692307692) internal successors, (53), 51 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:51,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 53 transitions. [2021-11-09 09:33:51,231 INFO L704 BuchiCegarLoop]: Abstraction has 52 states and 53 transitions. [2021-11-09 09:33:51,231 INFO L587 BuchiCegarLoop]: Abstraction has 52 states and 53 transitions. [2021-11-09 09:33:51,231 INFO L425 BuchiCegarLoop]: ======== Iteration 49============ [2021-11-09 09:33:51,231 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 53 transitions. [2021-11-09 09:33:51,231 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 51 [2021-11-09 09:33:51,232 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:51,232 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:51,232 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:51,232 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [48, 1, 1, 1] [2021-11-09 09:33:51,232 INFO L791 eck$LassoCheckResult]: Stem: 7784#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 7781#L19-2 [2021-11-09 09:33:51,233 INFO L793 eck$LassoCheckResult]: Loop: 7781#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 7782#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7785#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7832#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7831#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7830#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7829#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7828#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7827#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7826#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7825#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7824#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7823#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7822#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7821#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7820#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7819#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7818#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7817#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7816#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7815#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7814#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7813#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7812#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7811#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7810#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7809#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7808#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7807#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7806#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7805#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7804#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7803#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7802#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7801#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7800#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7799#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7798#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7797#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7796#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7795#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7794#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7793#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7792#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7791#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7790#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7789#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7788#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7787#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 7786#L21-2 assume !(main_~x2~0 > 1); 7783#L21-3 main_~x1~0 := 1 + main_~x1~0; 7781#L19-2 [2021-11-09 09:33:51,233 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:51,233 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 49 times [2021-11-09 09:33:51,233 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:51,233 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [7435790] [2021-11-09 09:33:51,234 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:51,234 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:51,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:51,239 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:51,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:51,240 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:51,240 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:51,241 INFO L85 PathProgramCache]: Analyzing trace with hash 220192527, now seen corresponding path program 48 times [2021-11-09 09:33:51,241 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:51,241 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1234012910] [2021-11-09 09:33:51,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:51,241 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:51,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:52,478 INFO L134 CoverageAnalysis]: Checked inductivity of 1176 backedges. 0 proven. 1176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:52,479 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:52,479 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1234012910] [2021-11-09 09:33:52,479 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1234012910] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:52,479 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [573820447] [2021-11-09 09:33:52,479 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:33:52,479 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:52,479 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:52,481 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:52,481 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Waiting until timeout for monitored process [2021-11-09 09:33:52,953 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) [2021-11-09 09:33:52,953 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:52,955 INFO L263 TraceCheckSpWp]: Trace formula consists of 152 conjuncts, 50 conjunts are in the unsatisfiable core [2021-11-09 09:33:52,956 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:53,085 INFO L134 CoverageAnalysis]: Checked inductivity of 1176 backedges. 0 proven. 1176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:53,085 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [573820447] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:53,086 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:53,086 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50] total 50 [2021-11-09 09:33:53,086 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [844370035] [2021-11-09 09:33:53,086 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:53,086 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:53,086 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2021-11-09 09:33:53,087 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1275, Invalid=1275, Unknown=0, NotChecked=0, Total=2550 [2021-11-09 09:33:53,087 INFO L87 Difference]: Start difference. First operand 52 states and 53 transitions. cyclomatic complexity: 2 Second operand has 51 states, 51 states have (on average 1.0) internal successors, (51), 50 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:53,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:53,142 INFO L93 Difference]: Finished difference Result 53 states and 54 transitions. [2021-11-09 09:33:53,143 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2021-11-09 09:33:53,143 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53 states and 54 transitions. [2021-11-09 09:33:53,144 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 52 [2021-11-09 09:33:53,144 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53 states to 53 states and 54 transitions. [2021-11-09 09:33:53,144 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53 [2021-11-09 09:33:53,144 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53 [2021-11-09 09:33:53,145 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53 states and 54 transitions. [2021-11-09 09:33:53,145 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:53,145 INFO L681 BuchiCegarLoop]: Abstraction has 53 states and 54 transitions. [2021-11-09 09:33:53,145 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states and 54 transitions. [2021-11-09 09:33:53,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 53. [2021-11-09 09:33:53,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53 states, 53 states have (on average 1.0188679245283019) internal successors, (54), 52 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:53,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 54 transitions. [2021-11-09 09:33:53,147 INFO L704 BuchiCegarLoop]: Abstraction has 53 states and 54 transitions. [2021-11-09 09:33:53,147 INFO L587 BuchiCegarLoop]: Abstraction has 53 states and 54 transitions. [2021-11-09 09:33:53,147 INFO L425 BuchiCegarLoop]: ======== Iteration 50============ [2021-11-09 09:33:53,147 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53 states and 54 transitions. [2021-11-09 09:33:53,148 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 52 [2021-11-09 09:33:53,148 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:53,148 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:53,148 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:53,148 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [49, 1, 1, 1] [2021-11-09 09:33:53,149 INFO L791 eck$LassoCheckResult]: Stem: 8093#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 8090#L19-2 [2021-11-09 09:33:53,149 INFO L793 eck$LassoCheckResult]: Loop: 8090#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 8091#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8094#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8142#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8141#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8140#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8139#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8138#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8137#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8136#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8135#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8134#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8133#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8132#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8131#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8130#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8129#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8128#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8127#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8126#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8125#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8124#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8123#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8122#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8121#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8120#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8119#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8118#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8117#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8116#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8115#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8114#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8113#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8112#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8111#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8110#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8109#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8108#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8107#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8106#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8105#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8104#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8103#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8102#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8101#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8100#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8099#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8098#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8097#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8096#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8095#L21-2 assume !(main_~x2~0 > 1); 8092#L21-3 main_~x1~0 := 1 + main_~x1~0; 8090#L19-2 [2021-11-09 09:33:53,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:53,149 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 50 times [2021-11-09 09:33:53,149 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:53,150 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1358208736] [2021-11-09 09:33:53,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:53,150 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:53,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:53,155 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:53,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:53,156 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:53,157 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:53,157 INFO L85 PathProgramCache]: Analyzing trace with hash -1763964496, now seen corresponding path program 49 times [2021-11-09 09:33:53,157 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:53,157 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1994856464] [2021-11-09 09:33:53,157 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:53,157 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:53,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:54,167 INFO L134 CoverageAnalysis]: Checked inductivity of 1225 backedges. 0 proven. 1225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:54,167 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:54,167 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1994856464] [2021-11-09 09:33:54,168 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1994856464] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:54,168 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [825845137] [2021-11-09 09:33:54,168 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:33:54,168 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:54,168 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:54,169 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:54,171 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Waiting until timeout for monitored process [2021-11-09 09:33:54,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:54,625 INFO L263 TraceCheckSpWp]: Trace formula consists of 155 conjuncts, 51 conjunts are in the unsatisfiable core [2021-11-09 09:33:54,626 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:54,786 INFO L134 CoverageAnalysis]: Checked inductivity of 1225 backedges. 0 proven. 1225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:54,787 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [825845137] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:54,787 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:54,787 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 51] total 51 [2021-11-09 09:33:54,787 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [296168021] [2021-11-09 09:33:54,787 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:54,787 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:54,788 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2021-11-09 09:33:54,789 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2021-11-09 09:33:54,792 INFO L87 Difference]: Start difference. First operand 53 states and 54 transitions. cyclomatic complexity: 2 Second operand has 52 states, 52 states have (on average 1.0) internal successors, (52), 51 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:54,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:54,834 INFO L93 Difference]: Finished difference Result 54 states and 55 transitions. [2021-11-09 09:33:54,834 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2021-11-09 09:33:54,834 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54 states and 55 transitions. [2021-11-09 09:33:54,834 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 53 [2021-11-09 09:33:54,835 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54 states to 54 states and 55 transitions. [2021-11-09 09:33:54,835 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54 [2021-11-09 09:33:54,835 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54 [2021-11-09 09:33:54,835 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54 states and 55 transitions. [2021-11-09 09:33:54,835 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:54,835 INFO L681 BuchiCegarLoop]: Abstraction has 54 states and 55 transitions. [2021-11-09 09:33:54,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states and 55 transitions. [2021-11-09 09:33:54,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2021-11-09 09:33:54,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 54 states, 54 states have (on average 1.0185185185185186) internal successors, (55), 53 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:54,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 55 transitions. [2021-11-09 09:33:54,837 INFO L704 BuchiCegarLoop]: Abstraction has 54 states and 55 transitions. [2021-11-09 09:33:54,837 INFO L587 BuchiCegarLoop]: Abstraction has 54 states and 55 transitions. [2021-11-09 09:33:54,837 INFO L425 BuchiCegarLoop]: ======== Iteration 51============ [2021-11-09 09:33:54,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54 states and 55 transitions. [2021-11-09 09:33:54,838 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 53 [2021-11-09 09:33:54,838 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:54,838 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:54,839 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:54,839 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [50, 1, 1, 1] [2021-11-09 09:33:54,839 INFO L791 eck$LassoCheckResult]: Stem: 8408#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 8405#L19-2 [2021-11-09 09:33:54,839 INFO L793 eck$LassoCheckResult]: Loop: 8405#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 8406#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8409#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8458#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8457#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8456#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8455#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8454#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8453#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8452#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8451#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8450#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8449#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8448#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8447#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8446#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8445#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8444#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8443#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8442#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8441#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8440#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8439#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8438#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8437#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8436#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8435#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8434#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8433#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8432#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8431#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8430#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8429#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8428#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8427#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8426#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8425#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8424#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8423#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8422#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8421#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8420#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8419#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8418#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8417#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8416#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8415#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8414#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8413#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8412#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8411#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8410#L21-2 assume !(main_~x2~0 > 1); 8407#L21-3 main_~x1~0 := 1 + main_~x1~0; 8405#L19-2 [2021-11-09 09:33:54,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:54,840 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 51 times [2021-11-09 09:33:54,840 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:54,840 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1954843394] [2021-11-09 09:33:54,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:54,841 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:54,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:54,849 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:54,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:54,850 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:54,850 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:54,850 INFO L85 PathProgramCache]: Analyzing trace with hash 1151677231, now seen corresponding path program 50 times [2021-11-09 09:33:54,851 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:54,851 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [316523374] [2021-11-09 09:33:54,851 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:54,851 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:54,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:56,090 INFO L134 CoverageAnalysis]: Checked inductivity of 1275 backedges. 0 proven. 1275 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:56,091 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:56,091 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [316523374] [2021-11-09 09:33:56,091 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [316523374] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:56,091 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2069783818] [2021-11-09 09:33:56,091 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:33:56,092 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:56,092 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:56,095 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:56,096 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Waiting until timeout for monitored process [2021-11-09 09:33:56,560 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:33:56,560 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:56,562 INFO L263 TraceCheckSpWp]: Trace formula consists of 158 conjuncts, 52 conjunts are in the unsatisfiable core [2021-11-09 09:33:56,562 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:56,725 INFO L134 CoverageAnalysis]: Checked inductivity of 1275 backedges. 0 proven. 1275 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:56,726 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2069783818] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:56,726 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:56,726 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 52] total 52 [2021-11-09 09:33:56,726 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1087575454] [2021-11-09 09:33:56,727 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:56,727 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:56,727 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2021-11-09 09:33:56,729 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1378, Invalid=1378, Unknown=0, NotChecked=0, Total=2756 [2021-11-09 09:33:56,729 INFO L87 Difference]: Start difference. First operand 54 states and 55 transitions. cyclomatic complexity: 2 Second operand has 53 states, 53 states have (on average 1.0) internal successors, (53), 52 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:56,788 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:56,789 INFO L93 Difference]: Finished difference Result 55 states and 56 transitions. [2021-11-09 09:33:56,789 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2021-11-09 09:33:56,789 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55 states and 56 transitions. [2021-11-09 09:33:56,789 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 54 [2021-11-09 09:33:56,790 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55 states to 55 states and 56 transitions. [2021-11-09 09:33:56,790 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55 [2021-11-09 09:33:56,790 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55 [2021-11-09 09:33:56,790 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55 states and 56 transitions. [2021-11-09 09:33:56,791 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:56,791 INFO L681 BuchiCegarLoop]: Abstraction has 55 states and 56 transitions. [2021-11-09 09:33:56,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states and 56 transitions. [2021-11-09 09:33:56,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 55. [2021-11-09 09:33:56,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 55 states have (on average 1.018181818181818) internal successors, (56), 54 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:56,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 56 transitions. [2021-11-09 09:33:56,793 INFO L704 BuchiCegarLoop]: Abstraction has 55 states and 56 transitions. [2021-11-09 09:33:56,793 INFO L587 BuchiCegarLoop]: Abstraction has 55 states and 56 transitions. [2021-11-09 09:33:56,793 INFO L425 BuchiCegarLoop]: ======== Iteration 52============ [2021-11-09 09:33:56,793 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55 states and 56 transitions. [2021-11-09 09:33:56,793 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 54 [2021-11-09 09:33:56,794 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:56,794 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:56,794 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:56,794 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [51, 1, 1, 1] [2021-11-09 09:33:56,794 INFO L791 eck$LassoCheckResult]: Stem: 8729#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 8726#L19-2 [2021-11-09 09:33:56,795 INFO L793 eck$LassoCheckResult]: Loop: 8726#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 8727#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8730#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8780#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8779#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8778#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8777#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8776#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8775#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8774#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8773#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8772#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8771#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8770#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8769#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8768#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8767#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8766#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8765#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8764#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8763#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8762#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8761#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8760#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8759#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8758#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8757#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8756#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8755#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8754#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8753#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8752#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8751#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8750#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8749#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8748#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8747#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8746#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8745#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8744#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8743#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8742#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8741#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8740#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8739#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8738#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8737#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8736#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8735#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8734#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8733#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8732#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 8731#L21-2 assume !(main_~x2~0 > 1); 8728#L21-3 main_~x1~0 := 1 + main_~x1~0; 8726#L19-2 [2021-11-09 09:33:56,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:56,795 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 52 times [2021-11-09 09:33:56,795 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:56,795 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1368246425] [2021-11-09 09:33:56,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:56,796 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:56,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:56,801 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:56,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:56,803 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:56,803 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:56,803 INFO L85 PathProgramCache]: Analyzing trace with hash 1342257552, now seen corresponding path program 51 times [2021-11-09 09:33:56,803 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:56,803 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1769207917] [2021-11-09 09:33:56,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:56,804 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:56,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:57,837 INFO L134 CoverageAnalysis]: Checked inductivity of 1326 backedges. 0 proven. 1326 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:57,837 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:57,837 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1769207917] [2021-11-09 09:33:57,837 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1769207917] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:57,837 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1182188557] [2021-11-09 09:33:57,838 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:33:57,838 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:57,838 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:57,839 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:57,842 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Waiting until timeout for monitored process [2021-11-09 09:33:58,333 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2021-11-09 09:33:58,334 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:33:58,335 INFO L263 TraceCheckSpWp]: Trace formula consists of 161 conjuncts, 53 conjunts are in the unsatisfiable core [2021-11-09 09:33:58,336 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:33:58,515 INFO L134 CoverageAnalysis]: Checked inductivity of 1326 backedges. 0 proven. 1326 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:58,515 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1182188557] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:58,515 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:33:58,515 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 53] total 53 [2021-11-09 09:33:58,515 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1648994759] [2021-11-09 09:33:58,516 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:33:58,516 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:33:58,517 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2021-11-09 09:33:58,518 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1431, Invalid=1431, Unknown=0, NotChecked=0, Total=2862 [2021-11-09 09:33:58,518 INFO L87 Difference]: Start difference. First operand 55 states and 56 transitions. cyclomatic complexity: 2 Second operand has 54 states, 54 states have (on average 1.0) internal successors, (54), 53 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:58,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:33:58,579 INFO L93 Difference]: Finished difference Result 56 states and 57 transitions. [2021-11-09 09:33:58,579 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2021-11-09 09:33:58,579 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 56 states and 57 transitions. [2021-11-09 09:33:58,580 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 55 [2021-11-09 09:33:58,581 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 56 states to 56 states and 57 transitions. [2021-11-09 09:33:58,581 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 56 [2021-11-09 09:33:58,581 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 56 [2021-11-09 09:33:58,581 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56 states and 57 transitions. [2021-11-09 09:33:58,581 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:33:58,581 INFO L681 BuchiCegarLoop]: Abstraction has 56 states and 57 transitions. [2021-11-09 09:33:58,582 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states and 57 transitions. [2021-11-09 09:33:58,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 56. [2021-11-09 09:33:58,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56 states, 56 states have (on average 1.0178571428571428) internal successors, (57), 55 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:33:58,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 57 transitions. [2021-11-09 09:33:58,583 INFO L704 BuchiCegarLoop]: Abstraction has 56 states and 57 transitions. [2021-11-09 09:33:58,583 INFO L587 BuchiCegarLoop]: Abstraction has 56 states and 57 transitions. [2021-11-09 09:33:58,583 INFO L425 BuchiCegarLoop]: ======== Iteration 53============ [2021-11-09 09:33:58,584 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 56 states and 57 transitions. [2021-11-09 09:33:58,584 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 55 [2021-11-09 09:33:58,584 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:33:58,584 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:33:58,585 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:33:58,585 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [52, 1, 1, 1] [2021-11-09 09:33:58,585 INFO L791 eck$LassoCheckResult]: Stem: 9056#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 9053#L19-2 [2021-11-09 09:33:58,585 INFO L793 eck$LassoCheckResult]: Loop: 9053#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 9054#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9057#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9108#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9107#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9106#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9105#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9104#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9103#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9102#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9101#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9100#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9099#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9098#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9097#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9096#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9095#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9094#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9093#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9092#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9091#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9090#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9089#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9088#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9087#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9086#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9085#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9084#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9083#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9082#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9081#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9080#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9079#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9078#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9077#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9076#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9075#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9074#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9073#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9072#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9071#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9070#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9069#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9068#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9067#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9066#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9065#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9064#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9063#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9062#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9061#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9060#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9059#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9058#L21-2 assume !(main_~x2~0 > 1); 9055#L21-3 main_~x1~0 := 1 + main_~x1~0; 9053#L19-2 [2021-11-09 09:33:58,585 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:58,586 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 53 times [2021-11-09 09:33:58,586 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:58,586 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [441679572] [2021-11-09 09:33:58,586 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:58,586 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:58,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:58,592 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:33:58,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:33:58,593 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:33:58,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:33:58,594 INFO L85 PathProgramCache]: Analyzing trace with hash -1339687089, now seen corresponding path program 52 times [2021-11-09 09:33:58,594 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:33:58,594 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [876395019] [2021-11-09 09:33:58,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:33:58,594 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:33:58,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:33:59,744 INFO L134 CoverageAnalysis]: Checked inductivity of 1378 backedges. 0 proven. 1378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:33:59,744 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:33:59,744 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [876395019] [2021-11-09 09:33:59,745 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [876395019] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:33:59,745 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1030972585] [2021-11-09 09:33:59,745 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:33:59,745 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:33:59,745 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:33:59,746 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:33:59,747 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Waiting until timeout for monitored process [2021-11-09 09:34:00,254 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:34:00,255 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:00,256 INFO L263 TraceCheckSpWp]: Trace formula consists of 164 conjuncts, 54 conjunts are in the unsatisfiable core [2021-11-09 09:34:00,257 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:00,440 INFO L134 CoverageAnalysis]: Checked inductivity of 1378 backedges. 0 proven. 1378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:00,440 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1030972585] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:00,440 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:00,440 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 54] total 54 [2021-11-09 09:34:00,440 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [748961350] [2021-11-09 09:34:00,441 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:34:00,441 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:00,442 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2021-11-09 09:34:00,443 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1485, Invalid=1485, Unknown=0, NotChecked=0, Total=2970 [2021-11-09 09:34:00,451 INFO L87 Difference]: Start difference. First operand 56 states and 57 transitions. cyclomatic complexity: 2 Second operand has 55 states, 55 states have (on average 1.0) internal successors, (55), 54 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:00,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:00,504 INFO L93 Difference]: Finished difference Result 57 states and 58 transitions. [2021-11-09 09:34:00,505 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2021-11-09 09:34:00,505 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 57 states and 58 transitions. [2021-11-09 09:34:00,506 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 [2021-11-09 09:34:00,506 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 57 states to 57 states and 58 transitions. [2021-11-09 09:34:00,506 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 57 [2021-11-09 09:34:00,507 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 57 [2021-11-09 09:34:00,507 INFO L73 IsDeterministic]: Start isDeterministic. Operand 57 states and 58 transitions. [2021-11-09 09:34:00,507 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:00,507 INFO L681 BuchiCegarLoop]: Abstraction has 57 states and 58 transitions. [2021-11-09 09:34:00,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states and 58 transitions. [2021-11-09 09:34:00,509 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 57. [2021-11-09 09:34:00,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 57 states have (on average 1.0175438596491229) internal successors, (58), 56 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:00,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 58 transitions. [2021-11-09 09:34:00,510 INFO L704 BuchiCegarLoop]: Abstraction has 57 states and 58 transitions. [2021-11-09 09:34:00,510 INFO L587 BuchiCegarLoop]: Abstraction has 57 states and 58 transitions. [2021-11-09 09:34:00,511 INFO L425 BuchiCegarLoop]: ======== Iteration 54============ [2021-11-09 09:34:00,511 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57 states and 58 transitions. [2021-11-09 09:34:00,511 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 56 [2021-11-09 09:34:00,511 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:00,512 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:00,512 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:34:00,512 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [53, 1, 1, 1] [2021-11-09 09:34:00,513 INFO L791 eck$LassoCheckResult]: Stem: 9389#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 9386#L19-2 [2021-11-09 09:34:00,513 INFO L793 eck$LassoCheckResult]: Loop: 9386#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 9387#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9390#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9442#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9441#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9440#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9439#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9438#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9437#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9436#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9435#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9434#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9433#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9432#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9431#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9430#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9429#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9428#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9427#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9426#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9425#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9424#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9423#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9422#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9421#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9420#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9419#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9418#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9417#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9416#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9415#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9414#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9413#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9412#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9411#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9410#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9409#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9408#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9407#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9406#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9405#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9404#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9403#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9402#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9401#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9400#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9399#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9398#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9397#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9396#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9395#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9394#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9393#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9392#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9391#L21-2 assume !(main_~x2~0 > 1); 9388#L21-3 main_~x1~0 := 1 + main_~x1~0; 9386#L19-2 [2021-11-09 09:34:00,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:00,513 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 54 times [2021-11-09 09:34:00,513 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:00,514 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1259092294] [2021-11-09 09:34:00,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:00,514 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:00,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:00,525 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:00,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:00,526 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:00,527 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:00,527 INFO L85 PathProgramCache]: Analyzing trace with hash 1419374960, now seen corresponding path program 53 times [2021-11-09 09:34:00,527 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:00,527 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [363028377] [2021-11-09 09:34:00,528 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:00,528 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:00,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:01,949 INFO L134 CoverageAnalysis]: Checked inductivity of 1431 backedges. 0 proven. 1431 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:01,950 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:01,950 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [363028377] [2021-11-09 09:34:01,950 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [363028377] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:01,950 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1578672180] [2021-11-09 09:34:01,950 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:34:01,950 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:01,950 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:01,954 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:01,971 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Waiting until timeout for monitored process [2021-11-09 09:34:02,635 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2021-11-09 09:34:02,635 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:02,637 INFO L263 TraceCheckSpWp]: Trace formula consists of 167 conjuncts, 55 conjunts are in the unsatisfiable core [2021-11-09 09:34:02,638 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:02,838 INFO L134 CoverageAnalysis]: Checked inductivity of 1431 backedges. 0 proven. 1431 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:02,838 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1578672180] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:02,838 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:02,839 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 55] total 55 [2021-11-09 09:34:02,839 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1175016301] [2021-11-09 09:34:02,839 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:34:02,839 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:02,840 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2021-11-09 09:34:02,841 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2021-11-09 09:34:02,841 INFO L87 Difference]: Start difference. First operand 57 states and 58 transitions. cyclomatic complexity: 2 Second operand has 56 states, 56 states have (on average 1.0) internal successors, (56), 55 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:02,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:02,887 INFO L93 Difference]: Finished difference Result 58 states and 59 transitions. [2021-11-09 09:34:02,888 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2021-11-09 09:34:02,888 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 58 states and 59 transitions. [2021-11-09 09:34:02,888 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 57 [2021-11-09 09:34:02,889 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 58 states to 58 states and 59 transitions. [2021-11-09 09:34:02,889 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 58 [2021-11-09 09:34:02,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 58 [2021-11-09 09:34:02,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 58 states and 59 transitions. [2021-11-09 09:34:02,890 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:02,890 INFO L681 BuchiCegarLoop]: Abstraction has 58 states and 59 transitions. [2021-11-09 09:34:02,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states and 59 transitions. [2021-11-09 09:34:02,891 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 58. [2021-11-09 09:34:02,891 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 58 states, 58 states have (on average 1.0172413793103448) internal successors, (59), 57 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:02,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 59 transitions. [2021-11-09 09:34:02,892 INFO L704 BuchiCegarLoop]: Abstraction has 58 states and 59 transitions. [2021-11-09 09:34:02,892 INFO L587 BuchiCegarLoop]: Abstraction has 58 states and 59 transitions. [2021-11-09 09:34:02,892 INFO L425 BuchiCegarLoop]: ======== Iteration 55============ [2021-11-09 09:34:02,892 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 58 states and 59 transitions. [2021-11-09 09:34:02,892 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 57 [2021-11-09 09:34:02,893 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:02,893 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:02,893 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:34:02,893 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [54, 1, 1, 1] [2021-11-09 09:34:02,894 INFO L791 eck$LassoCheckResult]: Stem: 9728#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 9725#L19-2 [2021-11-09 09:34:02,894 INFO L793 eck$LassoCheckResult]: Loop: 9725#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 9726#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9729#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9782#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9781#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9780#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9779#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9778#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9777#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9776#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9775#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9774#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9773#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9772#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9771#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9770#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9769#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9768#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9767#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9766#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9765#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9764#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9763#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9762#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9761#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9760#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9759#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9758#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9757#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9756#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9755#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9754#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9753#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9752#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9751#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9750#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9749#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9748#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9747#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9746#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9745#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9744#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9743#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9742#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9741#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9740#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9739#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9738#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9737#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9736#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9735#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9734#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9733#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9732#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9731#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 9730#L21-2 assume !(main_~x2~0 > 1); 9727#L21-3 main_~x1~0 := 1 + main_~x1~0; 9725#L19-2 [2021-11-09 09:34:02,894 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:02,894 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 55 times [2021-11-09 09:34:02,894 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:02,895 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [955571299] [2021-11-09 09:34:02,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:02,895 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:02,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:02,900 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:02,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:02,901 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:02,901 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:02,901 INFO L85 PathProgramCache]: Analyzing trace with hash 1050952559, now seen corresponding path program 54 times [2021-11-09 09:34:02,901 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:02,901 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [305554964] [2021-11-09 09:34:02,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:02,901 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:02,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:04,265 INFO L134 CoverageAnalysis]: Checked inductivity of 1485 backedges. 0 proven. 1485 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:04,265 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:04,265 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [305554964] [2021-11-09 09:34:04,265 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [305554964] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:04,265 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1297023069] [2021-11-09 09:34:04,265 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:34:04,266 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:04,266 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:04,267 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:04,268 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Waiting until timeout for monitored process [2021-11-09 09:34:04,808 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 28 check-sat command(s) [2021-11-09 09:34:04,808 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:04,810 INFO L263 TraceCheckSpWp]: Trace formula consists of 170 conjuncts, 56 conjunts are in the unsatisfiable core [2021-11-09 09:34:04,811 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:04,963 INFO L134 CoverageAnalysis]: Checked inductivity of 1485 backedges. 0 proven. 1485 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:04,963 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1297023069] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:04,963 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:04,963 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 56] total 56 [2021-11-09 09:34:04,963 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1671397019] [2021-11-09 09:34:04,964 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:34:04,964 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:04,964 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2021-11-09 09:34:04,965 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1596, Invalid=1596, Unknown=0, NotChecked=0, Total=3192 [2021-11-09 09:34:04,965 INFO L87 Difference]: Start difference. First operand 58 states and 59 transitions. cyclomatic complexity: 2 Second operand has 57 states, 57 states have (on average 1.0) internal successors, (57), 56 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:05,007 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:05,007 INFO L93 Difference]: Finished difference Result 59 states and 60 transitions. [2021-11-09 09:34:05,008 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2021-11-09 09:34:05,008 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59 states and 60 transitions. [2021-11-09 09:34:05,008 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 58 [2021-11-09 09:34:05,009 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59 states to 59 states and 60 transitions. [2021-11-09 09:34:05,009 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 59 [2021-11-09 09:34:05,009 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 59 [2021-11-09 09:34:05,009 INFO L73 IsDeterministic]: Start isDeterministic. Operand 59 states and 60 transitions. [2021-11-09 09:34:05,009 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:05,010 INFO L681 BuchiCegarLoop]: Abstraction has 59 states and 60 transitions. [2021-11-09 09:34:05,010 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states and 60 transitions. [2021-11-09 09:34:05,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 59. [2021-11-09 09:34:05,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 59 states have (on average 1.0169491525423728) internal successors, (60), 58 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:05,011 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 60 transitions. [2021-11-09 09:34:05,011 INFO L704 BuchiCegarLoop]: Abstraction has 59 states and 60 transitions. [2021-11-09 09:34:05,012 INFO L587 BuchiCegarLoop]: Abstraction has 59 states and 60 transitions. [2021-11-09 09:34:05,012 INFO L425 BuchiCegarLoop]: ======== Iteration 56============ [2021-11-09 09:34:05,012 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59 states and 60 transitions. [2021-11-09 09:34:05,012 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 58 [2021-11-09 09:34:05,012 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:05,012 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:05,013 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:34:05,013 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [55, 1, 1, 1] [2021-11-09 09:34:05,013 INFO L791 eck$LassoCheckResult]: Stem: 10073#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 10070#L19-2 [2021-11-09 09:34:05,013 INFO L793 eck$LassoCheckResult]: Loop: 10070#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 10071#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10074#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10128#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10127#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10126#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10125#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10124#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10123#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10122#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10121#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10120#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10119#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10118#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10117#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10116#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10115#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10114#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10113#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10112#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10111#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10110#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10109#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10108#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10107#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10106#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10105#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10104#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10103#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10102#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10101#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10100#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10099#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10098#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10097#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10096#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10095#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10094#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10093#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10092#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10091#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10090#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10089#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10088#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10087#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10086#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10085#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10084#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10083#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10082#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10081#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10080#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10079#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10078#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10077#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10076#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10075#L21-2 assume !(main_~x2~0 > 1); 10072#L21-3 main_~x1~0 := 1 + main_~x1~0; 10070#L19-2 [2021-11-09 09:34:05,014 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:05,014 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 56 times [2021-11-09 09:34:05,014 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:05,014 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1356285133] [2021-11-09 09:34:05,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:05,014 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:05,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:05,021 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:05,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:05,022 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:05,022 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:05,022 INFO L85 PathProgramCache]: Analyzing trace with hash -1780207280, now seen corresponding path program 55 times [2021-11-09 09:34:05,022 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:05,023 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [672522264] [2021-11-09 09:34:05,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:05,023 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:05,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:06,485 INFO L134 CoverageAnalysis]: Checked inductivity of 1540 backedges. 0 proven. 1540 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:06,486 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:06,486 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [672522264] [2021-11-09 09:34:06,486 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [672522264] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:06,486 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [732339561] [2021-11-09 09:34:06,486 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:34:06,486 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:06,486 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:06,488 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:06,511 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Waiting until timeout for monitored process [2021-11-09 09:34:07,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:07,069 INFO L263 TraceCheckSpWp]: Trace formula consists of 173 conjuncts, 57 conjunts are in the unsatisfiable core [2021-11-09 09:34:07,070 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:07,251 INFO L134 CoverageAnalysis]: Checked inductivity of 1540 backedges. 0 proven. 1540 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:07,251 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [732339561] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:07,251 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:07,251 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [57, 57] total 57 [2021-11-09 09:34:07,252 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [899874457] [2021-11-09 09:34:07,252 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:34:07,252 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:07,253 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2021-11-09 09:34:07,253 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2021-11-09 09:34:07,254 INFO L87 Difference]: Start difference. First operand 59 states and 60 transitions. cyclomatic complexity: 2 Second operand has 58 states, 58 states have (on average 1.0) internal successors, (58), 57 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:07,306 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:07,307 INFO L93 Difference]: Finished difference Result 60 states and 61 transitions. [2021-11-09 09:34:07,307 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2021-11-09 09:34:07,307 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60 states and 61 transitions. [2021-11-09 09:34:07,307 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 59 [2021-11-09 09:34:07,308 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60 states to 60 states and 61 transitions. [2021-11-09 09:34:07,308 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60 [2021-11-09 09:34:07,308 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60 [2021-11-09 09:34:07,308 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60 states and 61 transitions. [2021-11-09 09:34:07,309 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:07,309 INFO L681 BuchiCegarLoop]: Abstraction has 60 states and 61 transitions. [2021-11-09 09:34:07,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states and 61 transitions. [2021-11-09 09:34:07,310 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 60. [2021-11-09 09:34:07,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 60 states have (on average 1.0166666666666666) internal successors, (61), 59 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:07,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 61 transitions. [2021-11-09 09:34:07,311 INFO L704 BuchiCegarLoop]: Abstraction has 60 states and 61 transitions. [2021-11-09 09:34:07,311 INFO L587 BuchiCegarLoop]: Abstraction has 60 states and 61 transitions. [2021-11-09 09:34:07,311 INFO L425 BuchiCegarLoop]: ======== Iteration 57============ [2021-11-09 09:34:07,311 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60 states and 61 transitions. [2021-11-09 09:34:07,311 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 59 [2021-11-09 09:34:07,312 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:07,312 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:07,312 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:34:07,312 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [56, 1, 1, 1] [2021-11-09 09:34:07,312 INFO L791 eck$LassoCheckResult]: Stem: 10424#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 10421#L19-2 [2021-11-09 09:34:07,313 INFO L793 eck$LassoCheckResult]: Loop: 10421#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 10422#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10425#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10480#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10479#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10478#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10477#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10476#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10475#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10474#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10473#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10472#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10471#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10470#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10469#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10468#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10467#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10466#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10465#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10464#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10463#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10462#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10461#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10460#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10459#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10458#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10457#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10456#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10455#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10454#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10453#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10452#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10451#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10450#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10449#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10448#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10447#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10446#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10445#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10444#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10443#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10442#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10441#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10440#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10439#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10438#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10437#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10436#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10435#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10434#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10433#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10432#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10431#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10430#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10429#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10428#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10427#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10426#L21-2 assume !(main_~x2~0 > 1); 10423#L21-3 main_~x1~0 := 1 + main_~x1~0; 10421#L19-2 [2021-11-09 09:34:07,313 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:07,313 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 57 times [2021-11-09 09:34:07,313 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:07,313 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [564279215] [2021-11-09 09:34:07,314 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:07,314 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:07,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:07,320 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:07,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:07,321 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:07,322 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:07,322 INFO L85 PathProgramCache]: Analyzing trace with hash 648150927, now seen corresponding path program 56 times [2021-11-09 09:34:07,322 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:07,322 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1505058247] [2021-11-09 09:34:07,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:07,322 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:07,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:08,788 INFO L134 CoverageAnalysis]: Checked inductivity of 1596 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:08,788 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:08,789 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1505058247] [2021-11-09 09:34:08,789 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1505058247] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:08,789 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1335509900] [2021-11-09 09:34:08,789 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:34:08,789 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:08,789 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:08,790 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:08,791 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Waiting until timeout for monitored process [2021-11-09 09:34:09,378 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:34:09,378 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:09,379 INFO L263 TraceCheckSpWp]: Trace formula consists of 176 conjuncts, 58 conjunts are in the unsatisfiable core [2021-11-09 09:34:09,380 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:09,540 INFO L134 CoverageAnalysis]: Checked inductivity of 1596 backedges. 0 proven. 1596 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:09,540 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1335509900] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:09,540 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:09,540 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 58] total 58 [2021-11-09 09:34:09,541 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2006724357] [2021-11-09 09:34:09,541 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:34:09,541 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:09,541 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2021-11-09 09:34:09,542 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1711, Invalid=1711, Unknown=0, NotChecked=0, Total=3422 [2021-11-09 09:34:09,542 INFO L87 Difference]: Start difference. First operand 60 states and 61 transitions. cyclomatic complexity: 2 Second operand has 59 states, 59 states have (on average 1.0) internal successors, (59), 58 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:09,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:09,588 INFO L93 Difference]: Finished difference Result 61 states and 62 transitions. [2021-11-09 09:34:09,588 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2021-11-09 09:34:09,588 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 61 states and 62 transitions. [2021-11-09 09:34:09,589 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 60 [2021-11-09 09:34:09,589 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 61 states to 61 states and 62 transitions. [2021-11-09 09:34:09,589 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61 [2021-11-09 09:34:09,590 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61 [2021-11-09 09:34:09,590 INFO L73 IsDeterministic]: Start isDeterministic. Operand 61 states and 62 transitions. [2021-11-09 09:34:09,590 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:09,590 INFO L681 BuchiCegarLoop]: Abstraction has 61 states and 62 transitions. [2021-11-09 09:34:09,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states and 62 transitions. [2021-11-09 09:34:09,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 61. [2021-11-09 09:34:09,592 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61 states, 61 states have (on average 1.0163934426229508) internal successors, (62), 60 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:09,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 62 transitions. [2021-11-09 09:34:09,592 INFO L704 BuchiCegarLoop]: Abstraction has 61 states and 62 transitions. [2021-11-09 09:34:09,592 INFO L587 BuchiCegarLoop]: Abstraction has 61 states and 62 transitions. [2021-11-09 09:34:09,592 INFO L425 BuchiCegarLoop]: ======== Iteration 58============ [2021-11-09 09:34:09,593 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61 states and 62 transitions. [2021-11-09 09:34:09,593 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 60 [2021-11-09 09:34:09,593 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:09,593 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:09,594 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:34:09,594 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [57, 1, 1, 1] [2021-11-09 09:34:09,594 INFO L791 eck$LassoCheckResult]: Stem: 10781#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 10778#L19-2 [2021-11-09 09:34:09,594 INFO L793 eck$LassoCheckResult]: Loop: 10778#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 10779#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10782#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10838#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10837#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10836#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10835#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10834#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10833#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10832#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10831#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10830#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10829#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10828#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10827#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10826#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10825#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10824#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10823#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10822#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10821#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10820#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10819#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10818#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10817#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10816#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10815#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10814#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10813#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10812#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10811#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10810#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10809#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10808#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10807#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10806#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10805#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10804#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10803#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10802#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10801#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10800#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10799#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10798#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10797#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10796#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10795#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10794#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10793#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10792#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10791#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10790#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10789#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10788#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10787#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10786#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10785#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10784#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 10783#L21-2 assume !(main_~x2~0 > 1); 10780#L21-3 main_~x1~0 := 1 + main_~x1~0; 10778#L19-2 [2021-11-09 09:34:09,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:09,595 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 58 times [2021-11-09 09:34:09,595 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:09,595 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1164961764] [2021-11-09 09:34:09,595 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:09,596 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:09,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:09,605 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:09,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:09,606 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:09,607 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:09,607 INFO L85 PathProgramCache]: Analyzing trace with hash -1382155984, now seen corresponding path program 57 times [2021-11-09 09:34:09,607 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:09,607 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [728670892] [2021-11-09 09:34:09,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:09,607 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:09,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:11,144 INFO L134 CoverageAnalysis]: Checked inductivity of 1653 backedges. 0 proven. 1653 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:11,144 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:11,144 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [728670892] [2021-11-09 09:34:11,144 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [728670892] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:11,144 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [228596942] [2021-11-09 09:34:11,145 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:34:11,145 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:11,145 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:11,148 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:11,168 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Waiting until timeout for monitored process [2021-11-09 09:34:12,021 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2021-11-09 09:34:12,021 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:12,023 INFO L263 TraceCheckSpWp]: Trace formula consists of 179 conjuncts, 59 conjunts are in the unsatisfiable core [2021-11-09 09:34:12,024 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:12,184 INFO L134 CoverageAnalysis]: Checked inductivity of 1653 backedges. 0 proven. 1653 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:12,184 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [228596942] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:12,184 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:12,184 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59] total 59 [2021-11-09 09:34:12,184 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1733799687] [2021-11-09 09:34:12,185 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:34:12,185 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:12,186 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2021-11-09 09:34:12,186 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1770, Invalid=1770, Unknown=0, NotChecked=0, Total=3540 [2021-11-09 09:34:12,186 INFO L87 Difference]: Start difference. First operand 61 states and 62 transitions. cyclomatic complexity: 2 Second operand has 60 states, 60 states have (on average 1.0) internal successors, (60), 59 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:12,241 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:12,241 INFO L93 Difference]: Finished difference Result 62 states and 63 transitions. [2021-11-09 09:34:12,241 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2021-11-09 09:34:12,242 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 62 states and 63 transitions. [2021-11-09 09:34:12,242 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 61 [2021-11-09 09:34:12,243 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 62 states to 62 states and 63 transitions. [2021-11-09 09:34:12,243 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62 [2021-11-09 09:34:12,243 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62 [2021-11-09 09:34:12,243 INFO L73 IsDeterministic]: Start isDeterministic. Operand 62 states and 63 transitions. [2021-11-09 09:34:12,243 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:12,244 INFO L681 BuchiCegarLoop]: Abstraction has 62 states and 63 transitions. [2021-11-09 09:34:12,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states and 63 transitions. [2021-11-09 09:34:12,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 62. [2021-11-09 09:34:12,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62 states, 62 states have (on average 1.0161290322580645) internal successors, (63), 61 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:12,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 63 transitions. [2021-11-09 09:34:12,245 INFO L704 BuchiCegarLoop]: Abstraction has 62 states and 63 transitions. [2021-11-09 09:34:12,245 INFO L587 BuchiCegarLoop]: Abstraction has 62 states and 63 transitions. [2021-11-09 09:34:12,246 INFO L425 BuchiCegarLoop]: ======== Iteration 59============ [2021-11-09 09:34:12,246 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62 states and 63 transitions. [2021-11-09 09:34:12,246 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 61 [2021-11-09 09:34:12,246 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:12,246 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:12,247 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:34:12,247 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [58, 1, 1, 1] [2021-11-09 09:34:12,247 INFO L791 eck$LassoCheckResult]: Stem: 11144#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 11141#L19-2 [2021-11-09 09:34:12,247 INFO L793 eck$LassoCheckResult]: Loop: 11141#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 11142#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11145#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11202#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11201#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11200#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11199#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11198#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11197#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11196#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11195#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11194#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11193#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11192#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11191#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11190#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11189#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11188#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11187#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11186#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11185#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11184#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11183#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11182#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11181#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11180#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11179#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11178#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11177#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11176#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11175#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11174#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11173#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11172#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11171#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11170#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11169#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11168#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11167#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11166#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11165#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11164#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11163#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11162#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11161#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11160#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11159#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11158#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11157#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11156#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11155#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11154#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11153#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11152#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11151#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11150#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11149#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11148#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11147#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11146#L21-2 assume !(main_~x2~0 > 1); 11143#L21-3 main_~x1~0 := 1 + main_~x1~0; 11141#L19-2 [2021-11-09 09:34:12,248 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:12,248 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 59 times [2021-11-09 09:34:12,248 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:12,248 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [311352743] [2021-11-09 09:34:12,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:12,248 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:12,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:12,255 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:12,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:12,257 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:12,257 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:12,257 INFO L85 PathProgramCache]: Analyzing trace with hash 102839215, now seen corresponding path program 58 times [2021-11-09 09:34:12,257 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:12,257 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [75921557] [2021-11-09 09:34:12,258 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:12,258 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:12,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:13,631 INFO L134 CoverageAnalysis]: Checked inductivity of 1711 backedges. 0 proven. 1711 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:13,631 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:13,631 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [75921557] [2021-11-09 09:34:13,631 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [75921557] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:13,631 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1860782555] [2021-11-09 09:34:13,631 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:34:13,632 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:13,632 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:13,633 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:13,634 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Waiting until timeout for monitored process [2021-11-09 09:34:14,253 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:34:14,253 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:14,254 INFO L263 TraceCheckSpWp]: Trace formula consists of 182 conjuncts, 60 conjunts are in the unsatisfiable core [2021-11-09 09:34:14,255 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:14,420 INFO L134 CoverageAnalysis]: Checked inductivity of 1711 backedges. 0 proven. 1711 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:14,420 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1860782555] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:14,420 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:14,420 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 60] total 60 [2021-11-09 09:34:14,420 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1570300355] [2021-11-09 09:34:14,421 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:34:14,421 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:14,421 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2021-11-09 09:34:14,422 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1830, Invalid=1830, Unknown=0, NotChecked=0, Total=3660 [2021-11-09 09:34:14,422 INFO L87 Difference]: Start difference. First operand 62 states and 63 transitions. cyclomatic complexity: 2 Second operand has 61 states, 61 states have (on average 1.0) internal successors, (61), 60 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:14,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:14,469 INFO L93 Difference]: Finished difference Result 63 states and 64 transitions. [2021-11-09 09:34:14,469 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2021-11-09 09:34:14,469 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63 states and 64 transitions. [2021-11-09 09:34:14,469 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 62 [2021-11-09 09:34:14,470 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63 states to 63 states and 64 transitions. [2021-11-09 09:34:14,470 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63 [2021-11-09 09:34:14,470 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63 [2021-11-09 09:34:14,470 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63 states and 64 transitions. [2021-11-09 09:34:14,471 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:14,471 INFO L681 BuchiCegarLoop]: Abstraction has 63 states and 64 transitions. [2021-11-09 09:34:14,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states and 64 transitions. [2021-11-09 09:34:14,472 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 63. [2021-11-09 09:34:14,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63 states, 63 states have (on average 1.0158730158730158) internal successors, (64), 62 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:14,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 64 transitions. [2021-11-09 09:34:14,472 INFO L704 BuchiCegarLoop]: Abstraction has 63 states and 64 transitions. [2021-11-09 09:34:14,473 INFO L587 BuchiCegarLoop]: Abstraction has 63 states and 64 transitions. [2021-11-09 09:34:14,473 INFO L425 BuchiCegarLoop]: ======== Iteration 60============ [2021-11-09 09:34:14,473 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63 states and 64 transitions. [2021-11-09 09:34:14,473 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 62 [2021-11-09 09:34:14,473 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:14,473 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:14,474 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:34:14,474 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [59, 1, 1, 1] [2021-11-09 09:34:14,474 INFO L791 eck$LassoCheckResult]: Stem: 11513#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 11510#L19-2 [2021-11-09 09:34:14,474 INFO L793 eck$LassoCheckResult]: Loop: 11510#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 11511#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11514#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11572#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11571#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11570#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11569#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11568#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11567#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11566#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11565#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11564#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11563#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11562#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11561#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11560#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11559#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11558#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11557#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11556#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11555#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11554#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11553#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11552#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11551#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11550#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11549#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11548#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11547#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11546#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11545#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11544#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11543#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11542#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11541#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11540#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11539#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11538#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11537#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11536#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11535#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11534#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11533#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11532#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11531#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11530#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11529#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11528#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11527#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11526#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11525#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11524#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11523#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11522#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11521#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11520#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11519#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11518#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11517#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11516#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11515#L21-2 assume !(main_~x2~0 > 1); 11512#L21-3 main_~x1~0 := 1 + main_~x1~0; 11510#L19-2 [2021-11-09 09:34:14,475 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:14,475 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 60 times [2021-11-09 09:34:14,475 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:14,475 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2028721840] [2021-11-09 09:34:14,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:14,476 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:14,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:14,521 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:14,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:14,522 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:14,522 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:14,522 INFO L85 PathProgramCache]: Analyzing trace with hash -1106949872, now seen corresponding path program 59 times [2021-11-09 09:34:14,523 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:14,523 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1336818163] [2021-11-09 09:34:14,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:14,523 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:14,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:16,044 INFO L134 CoverageAnalysis]: Checked inductivity of 1770 backedges. 0 proven. 1770 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:16,044 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:16,044 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1336818163] [2021-11-09 09:34:16,044 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1336818163] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:16,045 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1337001595] [2021-11-09 09:34:16,045 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:34:16,045 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:16,045 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:16,047 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:16,052 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Waiting until timeout for monitored process [2021-11-09 09:34:16,690 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 31 check-sat command(s) [2021-11-09 09:34:16,690 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:16,692 INFO L263 TraceCheckSpWp]: Trace formula consists of 185 conjuncts, 61 conjunts are in the unsatisfiable core [2021-11-09 09:34:16,694 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:16,853 INFO L134 CoverageAnalysis]: Checked inductivity of 1770 backedges. 0 proven. 1770 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:16,853 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1337001595] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:16,854 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:16,854 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [61, 61] total 61 [2021-11-09 09:34:16,854 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [311195580] [2021-11-09 09:34:16,854 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:34:16,854 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:16,855 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2021-11-09 09:34:16,855 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2021-11-09 09:34:16,855 INFO L87 Difference]: Start difference. First operand 63 states and 64 transitions. cyclomatic complexity: 2 Second operand has 62 states, 62 states have (on average 1.0) internal successors, (62), 61 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:16,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:16,900 INFO L93 Difference]: Finished difference Result 64 states and 65 transitions. [2021-11-09 09:34:16,901 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2021-11-09 09:34:16,901 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 64 states and 65 transitions. [2021-11-09 09:34:16,901 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2021-11-09 09:34:16,902 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 64 states to 64 states and 65 transitions. [2021-11-09 09:34:16,902 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64 [2021-11-09 09:34:16,902 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64 [2021-11-09 09:34:16,902 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64 states and 65 transitions. [2021-11-09 09:34:16,902 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:16,902 INFO L681 BuchiCegarLoop]: Abstraction has 64 states and 65 transitions. [2021-11-09 09:34:16,903 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states and 65 transitions. [2021-11-09 09:34:16,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 64. [2021-11-09 09:34:16,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64 states, 64 states have (on average 1.015625) internal successors, (65), 63 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:16,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 65 transitions. [2021-11-09 09:34:16,904 INFO L704 BuchiCegarLoop]: Abstraction has 64 states and 65 transitions. [2021-11-09 09:34:16,904 INFO L587 BuchiCegarLoop]: Abstraction has 64 states and 65 transitions. [2021-11-09 09:34:16,905 INFO L425 BuchiCegarLoop]: ======== Iteration 61============ [2021-11-09 09:34:16,905 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 64 states and 65 transitions. [2021-11-09 09:34:16,905 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 63 [2021-11-09 09:34:16,905 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:16,906 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:16,906 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:34:16,906 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [60, 1, 1, 1] [2021-11-09 09:34:16,906 INFO L791 eck$LassoCheckResult]: Stem: 11888#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 11885#L19-2 [2021-11-09 09:34:16,906 INFO L793 eck$LassoCheckResult]: Loop: 11885#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 11886#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11889#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11948#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11947#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11946#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11945#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11944#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11943#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11942#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11941#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11940#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11939#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11938#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11937#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11936#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11935#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11934#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11933#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11932#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11931#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11930#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11929#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11928#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11927#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11926#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11925#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11924#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11923#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11922#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11921#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11920#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11919#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11918#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11917#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11916#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11915#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11914#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11913#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11912#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11911#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11910#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11909#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11908#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11907#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11906#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11905#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11904#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11903#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11902#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11901#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11900#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11899#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11898#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11897#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11896#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11895#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11894#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11893#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11892#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11891#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 11890#L21-2 assume !(main_~x2~0 > 1); 11887#L21-3 main_~x1~0 := 1 + main_~x1~0; 11885#L19-2 [2021-11-09 09:34:16,907 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:16,907 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 61 times [2021-11-09 09:34:16,907 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:16,907 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [990156563] [2021-11-09 09:34:16,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:16,908 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:16,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:16,913 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:16,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:16,914 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:16,914 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:16,914 INFO L85 PathProgramCache]: Analyzing trace with hash 44294095, now seen corresponding path program 60 times [2021-11-09 09:34:16,915 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:16,915 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1921253478] [2021-11-09 09:34:16,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:16,915 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:16,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:18,358 INFO L134 CoverageAnalysis]: Checked inductivity of 1830 backedges. 0 proven. 1830 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:18,359 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:18,359 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1921253478] [2021-11-09 09:34:18,359 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1921253478] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:18,359 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [421767185] [2021-11-09 09:34:18,359 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:34:18,359 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:18,360 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:18,361 INFO L229 MonitoredProcess]: Starting monitored process 61 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:18,361 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (61)] Waiting until timeout for monitored process [2021-11-09 09:34:19,032 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 31 check-sat command(s) [2021-11-09 09:34:19,032 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:19,034 INFO L263 TraceCheckSpWp]: Trace formula consists of 188 conjuncts, 62 conjunts are in the unsatisfiable core [2021-11-09 09:34:19,035 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:19,239 INFO L134 CoverageAnalysis]: Checked inductivity of 1830 backedges. 0 proven. 1830 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:19,240 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [421767185] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:19,240 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:19,240 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 62] total 62 [2021-11-09 09:34:19,240 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [168449917] [2021-11-09 09:34:19,240 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:34:19,240 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:19,241 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2021-11-09 09:34:19,242 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1953, Invalid=1953, Unknown=0, NotChecked=0, Total=3906 [2021-11-09 09:34:19,242 INFO L87 Difference]: Start difference. First operand 64 states and 65 transitions. cyclomatic complexity: 2 Second operand has 63 states, 63 states have (on average 1.0) internal successors, (63), 62 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:19,297 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:19,297 INFO L93 Difference]: Finished difference Result 65 states and 66 transitions. [2021-11-09 09:34:19,298 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2021-11-09 09:34:19,298 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65 states and 66 transitions. [2021-11-09 09:34:19,299 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 64 [2021-11-09 09:34:19,299 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65 states to 65 states and 66 transitions. [2021-11-09 09:34:19,300 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65 [2021-11-09 09:34:19,300 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65 [2021-11-09 09:34:19,300 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65 states and 66 transitions. [2021-11-09 09:34:19,300 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:19,300 INFO L681 BuchiCegarLoop]: Abstraction has 65 states and 66 transitions. [2021-11-09 09:34:19,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states and 66 transitions. [2021-11-09 09:34:19,302 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 65. [2021-11-09 09:34:19,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 65 states have (on average 1.0153846153846153) internal successors, (66), 64 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:19,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 66 transitions. [2021-11-09 09:34:19,303 INFO L704 BuchiCegarLoop]: Abstraction has 65 states and 66 transitions. [2021-11-09 09:34:19,303 INFO L587 BuchiCegarLoop]: Abstraction has 65 states and 66 transitions. [2021-11-09 09:34:19,303 INFO L425 BuchiCegarLoop]: ======== Iteration 62============ [2021-11-09 09:34:19,303 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65 states and 66 transitions. [2021-11-09 09:34:19,304 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 64 [2021-11-09 09:34:19,304 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:19,304 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:19,305 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:34:19,305 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [61, 1, 1, 1] [2021-11-09 09:34:19,305 INFO L791 eck$LassoCheckResult]: Stem: 12269#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 12266#L19-2 [2021-11-09 09:34:19,305 INFO L793 eck$LassoCheckResult]: Loop: 12266#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 12267#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12270#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12330#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12329#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12328#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12327#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12326#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12325#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12324#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12323#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12322#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12321#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12320#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12319#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12318#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12317#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12316#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12315#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12314#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12313#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12312#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12311#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12310#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12309#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12308#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12307#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12306#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12305#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12304#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12303#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12302#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12301#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12300#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12299#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12298#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12297#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12296#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12295#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12294#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12293#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12292#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12291#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12290#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12289#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12288#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12287#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12286#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12285#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12284#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12283#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12282#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12281#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12280#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12279#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12278#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12277#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12276#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12275#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12274#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12273#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12272#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12271#L21-2 assume !(main_~x2~0 > 1); 12268#L21-3 main_~x1~0 := 1 + main_~x1~0; 12266#L19-2 [2021-11-09 09:34:19,306 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:19,306 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 62 times [2021-11-09 09:34:19,306 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:19,306 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1934830447] [2021-11-09 09:34:19,306 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:19,307 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:19,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:19,315 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:19,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:19,316 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:19,316 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:19,317 INFO L85 PathProgramCache]: Analyzing trace with hash 1373118704, now seen corresponding path program 61 times [2021-11-09 09:34:19,317 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:19,317 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1266404344] [2021-11-09 09:34:19,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:19,317 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:19,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:21,000 INFO L134 CoverageAnalysis]: Checked inductivity of 1891 backedges. 0 proven. 1891 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:21,000 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:21,000 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1266404344] [2021-11-09 09:34:21,000 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1266404344] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:21,000 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2096837999] [2021-11-09 09:34:21,000 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:34:21,000 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:21,001 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:21,003 INFO L229 MonitoredProcess]: Starting monitored process 62 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:21,003 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (62)] Waiting until timeout for monitored process [2021-11-09 09:34:21,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:21,694 INFO L263 TraceCheckSpWp]: Trace formula consists of 191 conjuncts, 63 conjunts are in the unsatisfiable core [2021-11-09 09:34:21,695 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:21,919 INFO L134 CoverageAnalysis]: Checked inductivity of 1891 backedges. 0 proven. 1891 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:21,919 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2096837999] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:21,919 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:21,920 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [63, 63] total 63 [2021-11-09 09:34:21,920 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [52002664] [2021-11-09 09:34:21,920 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:34:21,920 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:21,921 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2021-11-09 09:34:21,921 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2021-11-09 09:34:21,921 INFO L87 Difference]: Start difference. First operand 65 states and 66 transitions. cyclomatic complexity: 2 Second operand has 64 states, 64 states have (on average 1.0) internal successors, (64), 63 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:21,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:21,980 INFO L93 Difference]: Finished difference Result 66 states and 67 transitions. [2021-11-09 09:34:21,980 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2021-11-09 09:34:21,981 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 66 states and 67 transitions. [2021-11-09 09:34:21,981 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 65 [2021-11-09 09:34:21,981 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 66 states to 66 states and 67 transitions. [2021-11-09 09:34:21,981 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 66 [2021-11-09 09:34:21,982 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 66 [2021-11-09 09:34:21,982 INFO L73 IsDeterministic]: Start isDeterministic. Operand 66 states and 67 transitions. [2021-11-09 09:34:21,982 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:21,982 INFO L681 BuchiCegarLoop]: Abstraction has 66 states and 67 transitions. [2021-11-09 09:34:21,982 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states and 67 transitions. [2021-11-09 09:34:21,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 66. [2021-11-09 09:34:21,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 66 states have (on average 1.0151515151515151) internal successors, (67), 65 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:21,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 67 transitions. [2021-11-09 09:34:21,983 INFO L704 BuchiCegarLoop]: Abstraction has 66 states and 67 transitions. [2021-11-09 09:34:21,983 INFO L587 BuchiCegarLoop]: Abstraction has 66 states and 67 transitions. [2021-11-09 09:34:21,983 INFO L425 BuchiCegarLoop]: ======== Iteration 63============ [2021-11-09 09:34:21,983 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66 states and 67 transitions. [2021-11-09 09:34:21,984 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 65 [2021-11-09 09:34:21,984 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:21,984 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:21,984 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:34:21,984 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [62, 1, 1, 1] [2021-11-09 09:34:21,984 INFO L791 eck$LassoCheckResult]: Stem: 12656#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 12653#L19-2 [2021-11-09 09:34:21,985 INFO L793 eck$LassoCheckResult]: Loop: 12653#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 12654#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12657#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12718#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12717#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12716#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12715#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12714#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12713#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12712#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12711#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12710#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12709#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12708#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12707#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12706#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12705#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12704#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12703#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12702#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12701#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12700#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12699#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12698#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12697#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12696#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12695#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12694#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12693#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12692#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12691#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12690#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12689#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12688#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12687#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12686#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12685#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12684#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12683#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12682#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12681#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12680#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12679#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12678#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12677#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12676#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12675#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12674#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12673#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12672#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12671#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12670#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12669#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12668#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12667#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12666#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12665#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12664#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12663#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12662#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12661#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12660#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12659#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 12658#L21-2 assume !(main_~x2~0 > 1); 12655#L21-3 main_~x1~0 := 1 + main_~x1~0; 12653#L19-2 [2021-11-09 09:34:21,985 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:21,985 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 63 times [2021-11-09 09:34:21,985 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:21,986 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [367644631] [2021-11-09 09:34:21,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:21,986 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:21,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:21,996 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:21,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:21,997 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:21,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:21,998 INFO L85 PathProgramCache]: Analyzing trace with hash -382991377, now seen corresponding path program 62 times [2021-11-09 09:34:21,998 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:21,998 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1103613818] [2021-11-09 09:34:21,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:21,998 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:22,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:23,614 INFO L134 CoverageAnalysis]: Checked inductivity of 1953 backedges. 0 proven. 1953 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:23,614 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:23,614 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1103613818] [2021-11-09 09:34:23,614 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1103613818] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:23,614 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2111855507] [2021-11-09 09:34:23,614 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:34:23,614 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:23,614 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:23,616 INFO L229 MonitoredProcess]: Starting monitored process 63 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:23,617 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (63)] Waiting until timeout for monitored process [2021-11-09 09:34:24,311 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:34:24,311 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:24,312 INFO L263 TraceCheckSpWp]: Trace formula consists of 194 conjuncts, 64 conjunts are in the unsatisfiable core [2021-11-09 09:34:24,313 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:24,488 INFO L134 CoverageAnalysis]: Checked inductivity of 1953 backedges. 0 proven. 1953 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:24,489 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2111855507] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:24,489 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:24,489 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 64] total 64 [2021-11-09 09:34:24,489 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [977148488] [2021-11-09 09:34:24,490 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:34:24,490 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:24,491 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2021-11-09 09:34:24,491 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2080, Invalid=2080, Unknown=0, NotChecked=0, Total=4160 [2021-11-09 09:34:24,492 INFO L87 Difference]: Start difference. First operand 66 states and 67 transitions. cyclomatic complexity: 2 Second operand has 65 states, 65 states have (on average 1.0) internal successors, (65), 64 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:24,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:24,581 INFO L93 Difference]: Finished difference Result 67 states and 68 transitions. [2021-11-09 09:34:24,581 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2021-11-09 09:34:24,582 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67 states and 68 transitions. [2021-11-09 09:34:24,582 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 66 [2021-11-09 09:34:24,583 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67 states to 67 states and 68 transitions. [2021-11-09 09:34:24,583 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67 [2021-11-09 09:34:24,583 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67 [2021-11-09 09:34:24,583 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67 states and 68 transitions. [2021-11-09 09:34:24,583 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:24,583 INFO L681 BuchiCegarLoop]: Abstraction has 67 states and 68 transitions. [2021-11-09 09:34:24,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states and 68 transitions. [2021-11-09 09:34:24,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 67. [2021-11-09 09:34:24,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67 states, 67 states have (on average 1.0149253731343284) internal successors, (68), 66 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:24,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 68 transitions. [2021-11-09 09:34:24,587 INFO L704 BuchiCegarLoop]: Abstraction has 67 states and 68 transitions. [2021-11-09 09:34:24,587 INFO L587 BuchiCegarLoop]: Abstraction has 67 states and 68 transitions. [2021-11-09 09:34:24,588 INFO L425 BuchiCegarLoop]: ======== Iteration 64============ [2021-11-09 09:34:24,588 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67 states and 68 transitions. [2021-11-09 09:34:24,588 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 66 [2021-11-09 09:34:24,588 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:24,588 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:24,589 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:34:24,589 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [63, 1, 1, 1] [2021-11-09 09:34:24,589 INFO L791 eck$LassoCheckResult]: Stem: 13049#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 13046#L19-2 [2021-11-09 09:34:24,592 INFO L793 eck$LassoCheckResult]: Loop: 13046#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 13047#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13050#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13112#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13111#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13110#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13109#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13108#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13107#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13106#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13105#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13104#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13103#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13102#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13101#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13100#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13099#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13098#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13097#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13096#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13095#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13094#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13093#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13092#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13091#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13090#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13089#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13088#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13087#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13086#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13085#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13084#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13083#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13082#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13081#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13080#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13079#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13078#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13077#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13076#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13075#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13074#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13073#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13072#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13071#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13070#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13069#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13068#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13067#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13066#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13065#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13064#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13063#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13062#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13061#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13060#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13059#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13058#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13057#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13056#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13055#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13054#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13053#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13052#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13051#L21-2 assume !(main_~x2~0 > 1); 13048#L21-3 main_~x1~0 := 1 + main_~x1~0; 13046#L19-2 [2021-11-09 09:34:24,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:24,593 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 64 times [2021-11-09 09:34:24,593 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:24,593 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2033747299] [2021-11-09 09:34:24,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:24,593 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:24,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:24,601 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:24,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:24,614 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:24,615 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:24,615 INFO L85 PathProgramCache]: Analyzing trace with hash 1012170960, now seen corresponding path program 63 times [2021-11-09 09:34:24,615 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:24,616 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [781408578] [2021-11-09 09:34:24,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:24,617 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:24,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:26,162 INFO L134 CoverageAnalysis]: Checked inductivity of 2016 backedges. 0 proven. 2016 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:26,162 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:26,162 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [781408578] [2021-11-09 09:34:26,163 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [781408578] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:26,163 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [666390466] [2021-11-09 09:34:26,163 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:34:26,163 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:26,163 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:26,165 INFO L229 MonitoredProcess]: Starting monitored process 64 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:26,167 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (64)] Waiting until timeout for monitored process [2021-11-09 09:34:26,905 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 33 check-sat command(s) [2021-11-09 09:34:26,905 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:26,907 INFO L263 TraceCheckSpWp]: Trace formula consists of 197 conjuncts, 65 conjunts are in the unsatisfiable core [2021-11-09 09:34:26,909 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:27,075 INFO L134 CoverageAnalysis]: Checked inductivity of 2016 backedges. 0 proven. 2016 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:27,076 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [666390466] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:27,076 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:27,076 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [65, 65] total 65 [2021-11-09 09:34:27,076 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [550788476] [2021-11-09 09:34:27,076 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:34:27,077 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:27,077 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2021-11-09 09:34:27,078 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2145, Invalid=2145, Unknown=0, NotChecked=0, Total=4290 [2021-11-09 09:34:27,078 INFO L87 Difference]: Start difference. First operand 67 states and 68 transitions. cyclomatic complexity: 2 Second operand has 66 states, 66 states have (on average 1.0) internal successors, (66), 65 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:27,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:27,130 INFO L93 Difference]: Finished difference Result 68 states and 69 transitions. [2021-11-09 09:34:27,131 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2021-11-09 09:34:27,131 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68 states and 69 transitions. [2021-11-09 09:34:27,131 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 67 [2021-11-09 09:34:27,132 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68 states to 68 states and 69 transitions. [2021-11-09 09:34:27,132 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 68 [2021-11-09 09:34:27,132 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68 [2021-11-09 09:34:27,132 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68 states and 69 transitions. [2021-11-09 09:34:27,133 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:27,133 INFO L681 BuchiCegarLoop]: Abstraction has 68 states and 69 transitions. [2021-11-09 09:34:27,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states and 69 transitions. [2021-11-09 09:34:27,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 68. [2021-11-09 09:34:27,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.0147058823529411) internal successors, (69), 67 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:27,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 69 transitions. [2021-11-09 09:34:27,134 INFO L704 BuchiCegarLoop]: Abstraction has 68 states and 69 transitions. [2021-11-09 09:34:27,134 INFO L587 BuchiCegarLoop]: Abstraction has 68 states and 69 transitions. [2021-11-09 09:34:27,134 INFO L425 BuchiCegarLoop]: ======== Iteration 65============ [2021-11-09 09:34:27,135 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 69 transitions. [2021-11-09 09:34:27,135 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 67 [2021-11-09 09:34:27,135 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:27,135 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:27,136 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:34:27,136 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [64, 1, 1, 1] [2021-11-09 09:34:27,136 INFO L791 eck$LassoCheckResult]: Stem: 13448#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 13445#L19-2 [2021-11-09 09:34:27,136 INFO L793 eck$LassoCheckResult]: Loop: 13445#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 13446#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13449#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13512#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13511#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13510#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13509#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13508#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13507#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13506#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13505#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13504#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13503#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13502#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13501#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13500#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13499#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13498#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13497#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13496#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13495#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13494#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13493#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13492#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13491#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13490#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13489#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13488#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13487#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13486#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13485#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13484#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13483#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13482#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13481#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13480#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13479#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13478#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13477#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13476#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13475#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13474#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13473#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13472#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13471#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13470#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13469#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13468#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13467#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13466#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13465#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13464#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13463#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13462#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13461#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13460#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13459#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13458#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13457#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13456#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13455#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13454#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13453#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13452#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13451#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13450#L21-2 assume !(main_~x2~0 > 1); 13447#L21-3 main_~x1~0 := 1 + main_~x1~0; 13445#L19-2 [2021-11-09 09:34:27,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:27,136 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 65 times [2021-11-09 09:34:27,136 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:27,136 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1877653450] [2021-11-09 09:34:27,137 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:27,137 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:27,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:27,144 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:27,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:27,146 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:27,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:27,146 INFO L85 PathProgramCache]: Analyzing trace with hash 1312530447, now seen corresponding path program 64 times [2021-11-09 09:34:27,147 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:27,147 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1028510982] [2021-11-09 09:34:27,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:27,147 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:27,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:28,762 INFO L134 CoverageAnalysis]: Checked inductivity of 2080 backedges. 0 proven. 2080 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:28,762 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:28,762 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1028510982] [2021-11-09 09:34:28,762 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1028510982] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:28,762 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2118354448] [2021-11-09 09:34:28,762 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:34:28,763 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:28,763 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:28,764 INFO L229 MonitoredProcess]: Starting monitored process 65 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:28,765 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (65)] Waiting until timeout for monitored process [2021-11-09 09:34:29,516 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:34:29,517 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:29,518 INFO L263 TraceCheckSpWp]: Trace formula consists of 200 conjuncts, 66 conjunts are in the unsatisfiable core [2021-11-09 09:34:29,519 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:29,769 INFO L134 CoverageAnalysis]: Checked inductivity of 2080 backedges. 0 proven. 2080 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:29,770 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2118354448] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:29,770 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:29,771 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 66] total 66 [2021-11-09 09:34:29,772 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1288544821] [2021-11-09 09:34:29,772 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:34:29,773 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:29,773 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2021-11-09 09:34:29,774 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2211, Invalid=2211, Unknown=0, NotChecked=0, Total=4422 [2021-11-09 09:34:29,774 INFO L87 Difference]: Start difference. First operand 68 states and 69 transitions. cyclomatic complexity: 2 Second operand has 67 states, 67 states have (on average 1.0) internal successors, (67), 66 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:29,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:29,858 INFO L93 Difference]: Finished difference Result 69 states and 70 transitions. [2021-11-09 09:34:29,858 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2021-11-09 09:34:29,858 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69 states and 70 transitions. [2021-11-09 09:34:29,859 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 68 [2021-11-09 09:34:29,859 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69 states to 69 states and 70 transitions. [2021-11-09 09:34:29,860 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69 [2021-11-09 09:34:29,860 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69 [2021-11-09 09:34:29,860 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69 states and 70 transitions. [2021-11-09 09:34:29,860 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:29,860 INFO L681 BuchiCegarLoop]: Abstraction has 69 states and 70 transitions. [2021-11-09 09:34:29,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states and 70 transitions. [2021-11-09 09:34:29,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 69. [2021-11-09 09:34:29,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69 states, 69 states have (on average 1.0144927536231885) internal successors, (70), 68 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:29,862 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 70 transitions. [2021-11-09 09:34:29,863 INFO L704 BuchiCegarLoop]: Abstraction has 69 states and 70 transitions. [2021-11-09 09:34:29,863 INFO L587 BuchiCegarLoop]: Abstraction has 69 states and 70 transitions. [2021-11-09 09:34:29,863 INFO L425 BuchiCegarLoop]: ======== Iteration 66============ [2021-11-09 09:34:29,863 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69 states and 70 transitions. [2021-11-09 09:34:29,864 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 68 [2021-11-09 09:34:29,864 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:29,864 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:29,865 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:34:29,865 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [65, 1, 1, 1] [2021-11-09 09:34:29,866 INFO L791 eck$LassoCheckResult]: Stem: 13853#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 13850#L19-2 [2021-11-09 09:34:29,866 INFO L793 eck$LassoCheckResult]: Loop: 13850#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 13851#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13854#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13918#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13917#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13916#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13915#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13914#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13913#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13912#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13911#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13910#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13909#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13908#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13907#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13906#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13905#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13904#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13903#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13902#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13901#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13900#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13899#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13898#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13897#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13896#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13895#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13894#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13893#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13892#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13891#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13890#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13889#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13888#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13887#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13886#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13885#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13884#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13883#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13882#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13881#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13880#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13879#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13878#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13877#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13876#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13875#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13874#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13873#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13872#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13871#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13870#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13869#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13868#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13867#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13866#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13865#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13864#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13863#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13862#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13861#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13860#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13859#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13858#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13857#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13856#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 13855#L21-2 assume !(main_~x2~0 > 1); 13852#L21-3 main_~x1~0 := 1 + main_~x1~0; 13850#L19-2 [2021-11-09 09:34:29,866 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:29,866 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 66 times [2021-11-09 09:34:29,867 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:29,867 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [733464725] [2021-11-09 09:34:29,867 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:29,867 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:29,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:29,876 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:29,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:29,877 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:29,878 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:29,878 INFO L85 PathProgramCache]: Analyzing trace with hash 2033739952, now seen corresponding path program 65 times [2021-11-09 09:34:29,878 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:29,878 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1691641930] [2021-11-09 09:34:29,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:29,878 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:29,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:31,566 INFO L134 CoverageAnalysis]: Checked inductivity of 2145 backedges. 0 proven. 2145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:31,567 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:31,567 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1691641930] [2021-11-09 09:34:31,567 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1691641930] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:31,567 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1289262390] [2021-11-09 09:34:31,567 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:34:31,567 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:31,568 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:31,569 INFO L229 MonitoredProcess]: Starting monitored process 66 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:31,569 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (66)] Waiting until timeout for monitored process [2021-11-09 09:34:32,363 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 34 check-sat command(s) [2021-11-09 09:34:32,364 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:32,366 INFO L263 TraceCheckSpWp]: Trace formula consists of 203 conjuncts, 67 conjunts are in the unsatisfiable core [2021-11-09 09:34:32,367 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:32,564 INFO L134 CoverageAnalysis]: Checked inductivity of 2145 backedges. 0 proven. 2145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:32,564 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1289262390] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:32,564 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:32,564 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [67, 67] total 67 [2021-11-09 09:34:32,564 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [655752040] [2021-11-09 09:34:32,564 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:34:32,564 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:32,565 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2021-11-09 09:34:32,569 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2278, Invalid=2278, Unknown=0, NotChecked=0, Total=4556 [2021-11-09 09:34:32,569 INFO L87 Difference]: Start difference. First operand 69 states and 70 transitions. cyclomatic complexity: 2 Second operand has 68 states, 68 states have (on average 1.0) internal successors, (68), 67 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:32,629 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:32,629 INFO L93 Difference]: Finished difference Result 70 states and 71 transitions. [2021-11-09 09:34:32,629 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2021-11-09 09:34:32,629 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 70 states and 71 transitions. [2021-11-09 09:34:32,630 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2021-11-09 09:34:32,630 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 70 states to 70 states and 71 transitions. [2021-11-09 09:34:32,630 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 70 [2021-11-09 09:34:32,631 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 70 [2021-11-09 09:34:32,631 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70 states and 71 transitions. [2021-11-09 09:34:32,631 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:32,631 INFO L681 BuchiCegarLoop]: Abstraction has 70 states and 71 transitions. [2021-11-09 09:34:32,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states and 71 transitions. [2021-11-09 09:34:32,632 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 70. [2021-11-09 09:34:32,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 70 states, 70 states have (on average 1.0142857142857142) internal successors, (71), 69 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:32,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 70 states to 70 states and 71 transitions. [2021-11-09 09:34:32,633 INFO L704 BuchiCegarLoop]: Abstraction has 70 states and 71 transitions. [2021-11-09 09:34:32,633 INFO L587 BuchiCegarLoop]: Abstraction has 70 states and 71 transitions. [2021-11-09 09:34:32,633 INFO L425 BuchiCegarLoop]: ======== Iteration 67============ [2021-11-09 09:34:32,634 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 70 states and 71 transitions. [2021-11-09 09:34:32,634 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2021-11-09 09:34:32,634 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:32,634 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:32,635 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:34:32,635 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [66, 1, 1, 1] [2021-11-09 09:34:32,635 INFO L791 eck$LassoCheckResult]: Stem: 14264#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 14261#L19-2 [2021-11-09 09:34:32,635 INFO L793 eck$LassoCheckResult]: Loop: 14261#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 14262#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14265#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14330#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14329#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14328#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14327#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14326#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14325#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14324#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14323#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14322#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14321#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14320#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14319#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14318#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14317#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14316#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14315#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14314#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14313#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14312#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14311#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14310#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14309#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14308#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14307#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14306#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14305#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14304#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14303#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14302#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14301#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14300#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14299#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14298#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14297#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14296#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14295#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14294#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14293#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14292#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14291#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14290#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14289#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14288#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14287#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14286#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14285#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14284#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14283#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14282#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14281#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14280#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14279#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14278#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14277#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14276#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14275#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14274#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14273#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14272#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14271#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14270#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14269#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14268#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14267#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14266#L21-2 assume !(main_~x2~0 > 1); 14263#L21-3 main_~x1~0 := 1 + main_~x1~0; 14261#L19-2 [2021-11-09 09:34:32,636 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:32,636 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 67 times [2021-11-09 09:34:32,636 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:32,636 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1617114330] [2021-11-09 09:34:32,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:32,637 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:32,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:32,648 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:32,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:32,649 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:32,649 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:32,650 INFO L85 PathProgramCache]: Analyzing trace with hash -1378569169, now seen corresponding path program 66 times [2021-11-09 09:34:32,650 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:32,650 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1971308368] [2021-11-09 09:34:32,650 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:32,650 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:32,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:34,357 INFO L134 CoverageAnalysis]: Checked inductivity of 2211 backedges. 0 proven. 2211 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:34,357 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:34,357 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1971308368] [2021-11-09 09:34:34,357 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1971308368] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:34,357 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2099663949] [2021-11-09 09:34:34,358 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:34:34,358 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:34,358 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:34,359 INFO L229 MonitoredProcess]: Starting monitored process 67 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:34,360 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (67)] Waiting until timeout for monitored process [2021-11-09 09:34:35,173 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 34 check-sat command(s) [2021-11-09 09:34:35,173 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:35,176 INFO L263 TraceCheckSpWp]: Trace formula consists of 206 conjuncts, 68 conjunts are in the unsatisfiable core [2021-11-09 09:34:35,177 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:35,397 INFO L134 CoverageAnalysis]: Checked inductivity of 2211 backedges. 0 proven. 2211 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:35,397 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2099663949] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:35,397 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:35,398 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 68] total 68 [2021-11-09 09:34:35,398 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [579654910] [2021-11-09 09:34:35,398 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:34:35,398 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:35,399 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2021-11-09 09:34:35,400 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2346, Invalid=2346, Unknown=0, NotChecked=0, Total=4692 [2021-11-09 09:34:35,400 INFO L87 Difference]: Start difference. First operand 70 states and 71 transitions. cyclomatic complexity: 2 Second operand has 69 states, 69 states have (on average 1.0) internal successors, (69), 68 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:35,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:35,494 INFO L93 Difference]: Finished difference Result 71 states and 72 transitions. [2021-11-09 09:34:35,494 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2021-11-09 09:34:35,494 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71 states and 72 transitions. [2021-11-09 09:34:35,495 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 70 [2021-11-09 09:34:35,495 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71 states to 71 states and 72 transitions. [2021-11-09 09:34:35,496 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 71 [2021-11-09 09:34:35,496 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 71 [2021-11-09 09:34:35,496 INFO L73 IsDeterministic]: Start isDeterministic. Operand 71 states and 72 transitions. [2021-11-09 09:34:35,496 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:35,496 INFO L681 BuchiCegarLoop]: Abstraction has 71 states and 72 transitions. [2021-11-09 09:34:35,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states and 72 transitions. [2021-11-09 09:34:35,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 71. [2021-11-09 09:34:35,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 71 states, 71 states have (on average 1.0140845070422535) internal successors, (72), 70 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:35,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 72 transitions. [2021-11-09 09:34:35,498 INFO L704 BuchiCegarLoop]: Abstraction has 71 states and 72 transitions. [2021-11-09 09:34:35,498 INFO L587 BuchiCegarLoop]: Abstraction has 71 states and 72 transitions. [2021-11-09 09:34:35,498 INFO L425 BuchiCegarLoop]: ======== Iteration 68============ [2021-11-09 09:34:35,499 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71 states and 72 transitions. [2021-11-09 09:34:35,499 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 70 [2021-11-09 09:34:35,499 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:35,499 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:35,500 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:34:35,500 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [67, 1, 1, 1] [2021-11-09 09:34:35,500 INFO L791 eck$LassoCheckResult]: Stem: 14681#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 14678#L19-2 [2021-11-09 09:34:35,500 INFO L793 eck$LassoCheckResult]: Loop: 14678#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 14679#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14682#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14748#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14747#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14746#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14745#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14744#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14743#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14742#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14741#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14740#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14739#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14738#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14737#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14736#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14735#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14734#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14733#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14732#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14731#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14730#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14729#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14728#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14727#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14726#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14725#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14724#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14723#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14722#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14721#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14720#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14719#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14718#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14717#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14716#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14715#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14714#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14713#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14712#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14711#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14710#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14709#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14708#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14707#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14706#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14705#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14704#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14703#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14702#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14701#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14700#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14699#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14698#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14697#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14696#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14695#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14694#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14693#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14692#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14691#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14690#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14689#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14688#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14687#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14686#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14685#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14684#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 14683#L21-2 assume !(main_~x2~0 > 1); 14680#L21-3 main_~x1~0 := 1 + main_~x1~0; 14678#L19-2 [2021-11-09 09:34:35,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:35,501 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 68 times [2021-11-09 09:34:35,501 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:35,501 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [169390645] [2021-11-09 09:34:35,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:35,557 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:35,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:35,564 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:35,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:35,566 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:35,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:35,566 INFO L85 PathProgramCache]: Analyzing trace with hash 214030480, now seen corresponding path program 67 times [2021-11-09 09:34:35,566 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:35,567 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2102033182] [2021-11-09 09:34:35,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:35,567 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:35,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:37,228 INFO L134 CoverageAnalysis]: Checked inductivity of 2278 backedges. 0 proven. 2278 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:37,229 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:37,229 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2102033182] [2021-11-09 09:34:37,229 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2102033182] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:37,229 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1936747334] [2021-11-09 09:34:37,229 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:34:37,229 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:37,229 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:37,230 INFO L229 MonitoredProcess]: Starting monitored process 68 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:37,231 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (68)] Waiting until timeout for monitored process [2021-11-09 09:34:38,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:38,039 INFO L263 TraceCheckSpWp]: Trace formula consists of 209 conjuncts, 69 conjunts are in the unsatisfiable core [2021-11-09 09:34:38,040 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:38,248 INFO L134 CoverageAnalysis]: Checked inductivity of 2278 backedges. 0 proven. 2278 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:38,248 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1936747334] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:38,248 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:38,249 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [69, 69] total 69 [2021-11-09 09:34:38,249 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [566859114] [2021-11-09 09:34:38,249 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:34:38,249 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:38,250 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2021-11-09 09:34:38,251 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2415, Invalid=2415, Unknown=0, NotChecked=0, Total=4830 [2021-11-09 09:34:38,252 INFO L87 Difference]: Start difference. First operand 71 states and 72 transitions. cyclomatic complexity: 2 Second operand has 70 states, 70 states have (on average 1.0) internal successors, (70), 69 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:38,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:38,330 INFO L93 Difference]: Finished difference Result 72 states and 73 transitions. [2021-11-09 09:34:38,330 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2021-11-09 09:34:38,330 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72 states and 73 transitions. [2021-11-09 09:34:38,331 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2021-11-09 09:34:38,331 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72 states to 72 states and 73 transitions. [2021-11-09 09:34:38,332 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 72 [2021-11-09 09:34:38,332 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 72 [2021-11-09 09:34:38,332 INFO L73 IsDeterministic]: Start isDeterministic. Operand 72 states and 73 transitions. [2021-11-09 09:34:38,332 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:38,332 INFO L681 BuchiCegarLoop]: Abstraction has 72 states and 73 transitions. [2021-11-09 09:34:38,332 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states and 73 transitions. [2021-11-09 09:34:38,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 72. [2021-11-09 09:34:38,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72 states, 72 states have (on average 1.0138888888888888) internal successors, (73), 71 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:38,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 73 transitions. [2021-11-09 09:34:38,334 INFO L704 BuchiCegarLoop]: Abstraction has 72 states and 73 transitions. [2021-11-09 09:34:38,334 INFO L587 BuchiCegarLoop]: Abstraction has 72 states and 73 transitions. [2021-11-09 09:34:38,334 INFO L425 BuchiCegarLoop]: ======== Iteration 69============ [2021-11-09 09:34:38,335 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 72 states and 73 transitions. [2021-11-09 09:34:38,335 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2021-11-09 09:34:38,335 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:38,335 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:38,336 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:34:38,336 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [68, 1, 1, 1] [2021-11-09 09:34:38,337 INFO L791 eck$LassoCheckResult]: Stem: 15104#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 15101#L19-2 [2021-11-09 09:34:38,337 INFO L793 eck$LassoCheckResult]: Loop: 15101#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 15102#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15105#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15172#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15171#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15170#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15169#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15168#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15167#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15166#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15165#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15164#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15163#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15162#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15161#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15160#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15159#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15158#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15157#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15156#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15155#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15154#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15153#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15152#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15151#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15150#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15149#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15148#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15147#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15146#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15145#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15144#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15143#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15142#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15141#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15140#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15139#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15138#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15137#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15136#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15135#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15134#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15133#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15132#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15131#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15130#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15129#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15128#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15127#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15126#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15125#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15124#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15123#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15122#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15121#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15120#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15119#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15118#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15117#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15116#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15115#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15114#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15113#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15112#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15111#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15110#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15109#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15108#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15107#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15106#L21-2 assume !(main_~x2~0 > 1); 15103#L21-3 main_~x1~0 := 1 + main_~x1~0; 15101#L19-2 [2021-11-09 09:34:38,337 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:38,337 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 69 times [2021-11-09 09:34:38,338 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:38,340 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [958921048] [2021-11-09 09:34:38,341 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:38,341 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:38,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:38,349 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:38,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:38,350 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:38,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:38,351 INFO L85 PathProgramCache]: Analyzing trace with hash -1954987953, now seen corresponding path program 68 times [2021-11-09 09:34:38,351 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:38,351 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [195424355] [2021-11-09 09:34:38,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:38,351 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:38,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:40,169 INFO L134 CoverageAnalysis]: Checked inductivity of 2346 backedges. 0 proven. 2346 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:40,169 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:40,169 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [195424355] [2021-11-09 09:34:40,169 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [195424355] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:40,169 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1328137235] [2021-11-09 09:34:40,169 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:34:40,169 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:40,170 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:40,170 INFO L229 MonitoredProcess]: Starting monitored process 69 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:40,171 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (69)] Waiting until timeout for monitored process [2021-11-09 09:34:40,993 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:34:40,993 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:40,995 INFO L263 TraceCheckSpWp]: Trace formula consists of 212 conjuncts, 70 conjunts are in the unsatisfiable core [2021-11-09 09:34:40,996 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:41,204 INFO L134 CoverageAnalysis]: Checked inductivity of 2346 backedges. 0 proven. 2346 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:41,205 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1328137235] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:41,205 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:41,205 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 70] total 70 [2021-11-09 09:34:41,205 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [495386930] [2021-11-09 09:34:41,205 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:34:41,205 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:41,206 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2021-11-09 09:34:41,208 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2485, Invalid=2485, Unknown=0, NotChecked=0, Total=4970 [2021-11-09 09:34:41,209 INFO L87 Difference]: Start difference. First operand 72 states and 73 transitions. cyclomatic complexity: 2 Second operand has 71 states, 71 states have (on average 1.0) internal successors, (71), 70 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:41,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:41,267 INFO L93 Difference]: Finished difference Result 73 states and 74 transitions. [2021-11-09 09:34:41,268 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2021-11-09 09:34:41,268 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73 states and 74 transitions. [2021-11-09 09:34:41,268 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2021-11-09 09:34:41,269 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73 states to 73 states and 74 transitions. [2021-11-09 09:34:41,269 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 73 [2021-11-09 09:34:41,269 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 73 [2021-11-09 09:34:41,269 INFO L73 IsDeterministic]: Start isDeterministic. Operand 73 states and 74 transitions. [2021-11-09 09:34:41,269 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:41,269 INFO L681 BuchiCegarLoop]: Abstraction has 73 states and 74 transitions. [2021-11-09 09:34:41,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states and 74 transitions. [2021-11-09 09:34:41,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 73. [2021-11-09 09:34:41,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73 states, 73 states have (on average 1.0136986301369864) internal successors, (74), 72 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:41,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 74 transitions. [2021-11-09 09:34:41,270 INFO L704 BuchiCegarLoop]: Abstraction has 73 states and 74 transitions. [2021-11-09 09:34:41,270 INFO L587 BuchiCegarLoop]: Abstraction has 73 states and 74 transitions. [2021-11-09 09:34:41,270 INFO L425 BuchiCegarLoop]: ======== Iteration 70============ [2021-11-09 09:34:41,270 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73 states and 74 transitions. [2021-11-09 09:34:41,271 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2021-11-09 09:34:41,271 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:41,271 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:41,271 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:34:41,271 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [69, 1, 1, 1] [2021-11-09 09:34:41,272 INFO L791 eck$LassoCheckResult]: Stem: 15533#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 15530#L19-2 [2021-11-09 09:34:41,272 INFO L793 eck$LassoCheckResult]: Loop: 15530#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 15531#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15534#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15602#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15601#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15600#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15599#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15598#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15597#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15596#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15595#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15594#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15593#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15592#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15591#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15590#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15589#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15588#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15587#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15586#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15585#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15584#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15583#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15582#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15581#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15580#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15579#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15578#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15577#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15576#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15575#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15574#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15573#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15572#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15571#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15570#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15569#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15568#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15567#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15566#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15565#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15564#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15563#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15562#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15561#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15560#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15559#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15558#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15557#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15556#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15555#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15554#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15553#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15552#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15551#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15550#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15549#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15548#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15547#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15546#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15545#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15544#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15543#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15542#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15541#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15540#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15539#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15538#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15537#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15536#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15535#L21-2 assume !(main_~x2~0 > 1); 15532#L21-3 main_~x1~0 := 1 + main_~x1~0; 15530#L19-2 [2021-11-09 09:34:41,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:41,272 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 70 times [2021-11-09 09:34:41,272 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:41,273 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [801727464] [2021-11-09 09:34:41,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:41,273 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:41,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:41,282 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:41,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:41,283 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:41,283 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:41,283 INFO L85 PathProgramCache]: Analyzing trace with hash -475082640, now seen corresponding path program 69 times [2021-11-09 09:34:41,284 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:41,284 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [165548757] [2021-11-09 09:34:41,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:41,284 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:41,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:43,225 INFO L134 CoverageAnalysis]: Checked inductivity of 2415 backedges. 0 proven. 2415 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:43,225 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:43,225 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [165548757] [2021-11-09 09:34:43,225 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [165548757] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:43,225 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [725699759] [2021-11-09 09:34:43,226 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:34:43,226 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:43,226 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:43,233 INFO L229 MonitoredProcess]: Starting monitored process 70 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:43,236 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (70)] Waiting until timeout for monitored process [2021-11-09 09:34:44,097 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 36 check-sat command(s) [2021-11-09 09:34:44,097 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:44,098 INFO L263 TraceCheckSpWp]: Trace formula consists of 215 conjuncts, 71 conjunts are in the unsatisfiable core [2021-11-09 09:34:44,099 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:44,367 INFO L134 CoverageAnalysis]: Checked inductivity of 2415 backedges. 0 proven. 2415 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:44,367 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [725699759] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:44,367 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:44,367 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [71, 71] total 71 [2021-11-09 09:34:44,367 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2139573203] [2021-11-09 09:34:44,376 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:34:44,376 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:44,377 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 72 interpolants. [2021-11-09 09:34:44,378 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2556, Invalid=2556, Unknown=0, NotChecked=0, Total=5112 [2021-11-09 09:34:44,378 INFO L87 Difference]: Start difference. First operand 73 states and 74 transitions. cyclomatic complexity: 2 Second operand has 72 states, 72 states have (on average 1.0) internal successors, (72), 71 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:44,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:44,451 INFO L93 Difference]: Finished difference Result 74 states and 75 transitions. [2021-11-09 09:34:44,451 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 72 states. [2021-11-09 09:34:44,451 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 74 states and 75 transitions. [2021-11-09 09:34:44,451 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 73 [2021-11-09 09:34:44,452 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 74 states to 74 states and 75 transitions. [2021-11-09 09:34:44,452 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 74 [2021-11-09 09:34:44,452 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 74 [2021-11-09 09:34:44,452 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74 states and 75 transitions. [2021-11-09 09:34:44,452 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:44,452 INFO L681 BuchiCegarLoop]: Abstraction has 74 states and 75 transitions. [2021-11-09 09:34:44,452 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states and 75 transitions. [2021-11-09 09:34:44,456 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 74. [2021-11-09 09:34:44,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74 states, 74 states have (on average 1.0135135135135136) internal successors, (75), 73 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:44,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 75 transitions. [2021-11-09 09:34:44,457 INFO L704 BuchiCegarLoop]: Abstraction has 74 states and 75 transitions. [2021-11-09 09:34:44,457 INFO L587 BuchiCegarLoop]: Abstraction has 74 states and 75 transitions. [2021-11-09 09:34:44,458 INFO L425 BuchiCegarLoop]: ======== Iteration 71============ [2021-11-09 09:34:44,458 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74 states and 75 transitions. [2021-11-09 09:34:44,459 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 73 [2021-11-09 09:34:44,459 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:44,459 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:44,460 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:34:44,460 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [70, 1, 1, 1] [2021-11-09 09:34:44,460 INFO L791 eck$LassoCheckResult]: Stem: 15968#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 15965#L19-2 [2021-11-09 09:34:44,460 INFO L793 eck$LassoCheckResult]: Loop: 15965#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 15966#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15969#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16038#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16037#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16036#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16035#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16034#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16033#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16032#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16031#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16030#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16029#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16028#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16027#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16026#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16025#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16024#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16023#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16022#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16021#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16020#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16019#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16018#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16017#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16016#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16015#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16014#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16013#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16012#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16011#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16010#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16009#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16008#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16007#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16006#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16005#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16004#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16003#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16002#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16001#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16000#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15999#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15998#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15997#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15996#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15995#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15994#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15993#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15992#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15991#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15990#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15989#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15988#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15987#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15986#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15985#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15984#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15983#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15982#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15981#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15980#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15979#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15978#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15977#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15976#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15975#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15974#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15973#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15972#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15971#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 15970#L21-2 assume !(main_~x2~0 > 1); 15967#L21-3 main_~x1~0 := 1 + main_~x1~0; 15965#L19-2 [2021-11-09 09:34:44,461 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:44,461 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 71 times [2021-11-09 09:34:44,461 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:44,461 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [424226637] [2021-11-09 09:34:44,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:44,461 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:44,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:44,470 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:44,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:44,472 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:44,472 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:44,472 INFO L85 PathProgramCache]: Analyzing trace with hash -1842658193, now seen corresponding path program 70 times [2021-11-09 09:34:44,472 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:44,473 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1657924041] [2021-11-09 09:34:44,473 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:44,473 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:44,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:46,342 INFO L134 CoverageAnalysis]: Checked inductivity of 2485 backedges. 0 proven. 2485 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:46,342 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:46,343 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1657924041] [2021-11-09 09:34:46,343 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1657924041] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:46,343 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [522837804] [2021-11-09 09:34:46,343 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:34:46,343 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:46,343 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:46,344 INFO L229 MonitoredProcess]: Starting monitored process 71 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:46,345 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (71)] Waiting until timeout for monitored process [2021-11-09 09:34:47,222 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:34:47,222 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:47,224 INFO L263 TraceCheckSpWp]: Trace formula consists of 218 conjuncts, 72 conjunts are in the unsatisfiable core [2021-11-09 09:34:47,225 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:47,420 INFO L134 CoverageAnalysis]: Checked inductivity of 2485 backedges. 0 proven. 2485 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:47,420 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [522837804] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:47,420 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:47,420 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [72, 72] total 72 [2021-11-09 09:34:47,420 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [831335018] [2021-11-09 09:34:47,420 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:34:47,421 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:47,421 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2021-11-09 09:34:47,422 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2628, Invalid=2628, Unknown=0, NotChecked=0, Total=5256 [2021-11-09 09:34:47,422 INFO L87 Difference]: Start difference. First operand 74 states and 75 transitions. cyclomatic complexity: 2 Second operand has 73 states, 73 states have (on average 1.0) internal successors, (73), 72 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:47,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:47,479 INFO L93 Difference]: Finished difference Result 75 states and 76 transitions. [2021-11-09 09:34:47,480 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 73 states. [2021-11-09 09:34:47,480 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 75 states and 76 transitions. [2021-11-09 09:34:47,480 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 74 [2021-11-09 09:34:47,481 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 75 states to 75 states and 76 transitions. [2021-11-09 09:34:47,481 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75 [2021-11-09 09:34:47,481 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75 [2021-11-09 09:34:47,481 INFO L73 IsDeterministic]: Start isDeterministic. Operand 75 states and 76 transitions. [2021-11-09 09:34:47,481 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:47,481 INFO L681 BuchiCegarLoop]: Abstraction has 75 states and 76 transitions. [2021-11-09 09:34:47,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states and 76 transitions. [2021-11-09 09:34:47,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 75. [2021-11-09 09:34:47,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75 states, 75 states have (on average 1.0133333333333334) internal successors, (76), 74 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:47,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 76 transitions. [2021-11-09 09:34:47,484 INFO L704 BuchiCegarLoop]: Abstraction has 75 states and 76 transitions. [2021-11-09 09:34:47,484 INFO L587 BuchiCegarLoop]: Abstraction has 75 states and 76 transitions. [2021-11-09 09:34:47,484 INFO L425 BuchiCegarLoop]: ======== Iteration 72============ [2021-11-09 09:34:47,484 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75 states and 76 transitions. [2021-11-09 09:34:47,484 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 74 [2021-11-09 09:34:47,528 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:47,528 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:47,529 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:34:47,529 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [71, 1, 1, 1] [2021-11-09 09:34:47,529 INFO L791 eck$LassoCheckResult]: Stem: 16409#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 16406#L19-2 [2021-11-09 09:34:47,529 INFO L793 eck$LassoCheckResult]: Loop: 16406#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 16407#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16410#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16480#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16479#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16478#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16477#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16476#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16475#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16474#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16473#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16472#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16471#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16470#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16469#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16468#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16467#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16466#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16465#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16464#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16463#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16462#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16461#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16460#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16459#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16458#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16457#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16456#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16455#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16454#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16453#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16452#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16451#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16450#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16449#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16448#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16447#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16446#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16445#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16444#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16443#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16442#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16441#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16440#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16439#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16438#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16437#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16436#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16435#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16434#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16433#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16432#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16431#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16430#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16429#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16428#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16427#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16426#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16425#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16424#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16423#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16422#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16421#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16420#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16419#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16418#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16417#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16416#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16415#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16414#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16413#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16412#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16411#L21-2 assume !(main_~x2~0 > 1); 16408#L21-3 main_~x1~0 := 1 + main_~x1~0; 16406#L19-2 [2021-11-09 09:34:47,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:47,529 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 72 times [2021-11-09 09:34:47,530 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:47,530 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1094868819] [2021-11-09 09:34:47,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:47,530 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:47,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:47,548 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:47,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:47,549 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:47,550 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:47,550 INFO L85 PathProgramCache]: Analyzing trace with hash -1287827376, now seen corresponding path program 71 times [2021-11-09 09:34:47,550 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:47,550 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [939211357] [2021-11-09 09:34:47,550 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:47,551 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:47,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:49,534 INFO L134 CoverageAnalysis]: Checked inductivity of 2556 backedges. 0 proven. 2556 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:49,534 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:49,535 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [939211357] [2021-11-09 09:34:49,535 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [939211357] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:49,535 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1308938762] [2021-11-09 09:34:49,535 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:34:49,535 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:49,535 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:49,537 INFO L229 MonitoredProcess]: Starting monitored process 72 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:49,538 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (72)] Waiting until timeout for monitored process [2021-11-09 09:34:50,466 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 37 check-sat command(s) [2021-11-09 09:34:50,466 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:50,469 INFO L263 TraceCheckSpWp]: Trace formula consists of 221 conjuncts, 73 conjunts are in the unsatisfiable core [2021-11-09 09:34:50,470 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:50,681 INFO L134 CoverageAnalysis]: Checked inductivity of 2556 backedges. 0 proven. 2556 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:50,681 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1308938762] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:50,681 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:50,681 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [73, 73] total 73 [2021-11-09 09:34:50,682 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1080751627] [2021-11-09 09:34:50,682 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:34:50,682 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:50,683 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 74 interpolants. [2021-11-09 09:34:50,684 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2701, Invalid=2701, Unknown=0, NotChecked=0, Total=5402 [2021-11-09 09:34:50,684 INFO L87 Difference]: Start difference. First operand 75 states and 76 transitions. cyclomatic complexity: 2 Second operand has 74 states, 74 states have (on average 1.0) internal successors, (74), 73 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:50,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:50,751 INFO L93 Difference]: Finished difference Result 76 states and 77 transitions. [2021-11-09 09:34:50,751 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 74 states. [2021-11-09 09:34:50,751 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 76 states and 77 transitions. [2021-11-09 09:34:50,751 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 75 [2021-11-09 09:34:50,752 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 76 states to 76 states and 77 transitions. [2021-11-09 09:34:50,752 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 76 [2021-11-09 09:34:50,752 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 76 [2021-11-09 09:34:50,752 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76 states and 77 transitions. [2021-11-09 09:34:50,752 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:50,752 INFO L681 BuchiCegarLoop]: Abstraction has 76 states and 77 transitions. [2021-11-09 09:34:50,753 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states and 77 transitions. [2021-11-09 09:34:50,754 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 76. [2021-11-09 09:34:50,754 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76 states, 76 states have (on average 1.013157894736842) internal successors, (77), 75 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:50,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 77 transitions. [2021-11-09 09:34:50,754 INFO L704 BuchiCegarLoop]: Abstraction has 76 states and 77 transitions. [2021-11-09 09:34:50,754 INFO L587 BuchiCegarLoop]: Abstraction has 76 states and 77 transitions. [2021-11-09 09:34:50,755 INFO L425 BuchiCegarLoop]: ======== Iteration 73============ [2021-11-09 09:34:50,755 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76 states and 77 transitions. [2021-11-09 09:34:50,755 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 75 [2021-11-09 09:34:50,755 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:50,755 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:50,756 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:34:50,756 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [72, 1, 1, 1] [2021-11-09 09:34:50,756 INFO L791 eck$LassoCheckResult]: Stem: 16856#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 16853#L19-2 [2021-11-09 09:34:50,757 INFO L793 eck$LassoCheckResult]: Loop: 16853#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 16854#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16857#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16928#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16927#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16926#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16925#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16924#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16923#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16922#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16921#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16920#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16919#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16918#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16917#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16916#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16915#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16914#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16913#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16912#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16911#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16910#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16909#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16908#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16907#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16906#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16905#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16904#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16903#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16902#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16901#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16900#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16899#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16898#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16897#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16896#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16895#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16894#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16893#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16892#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16891#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16890#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16889#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16888#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16887#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16886#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16885#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16884#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16883#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16882#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16881#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16880#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16879#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16878#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16877#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16876#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16875#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16874#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16873#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16872#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16871#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16870#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16869#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16868#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16867#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16866#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16865#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16864#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16863#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16862#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16861#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16860#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16859#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 16858#L21-2 assume !(main_~x2~0 > 1); 16855#L21-3 main_~x1~0 := 1 + main_~x1~0; 16853#L19-2 [2021-11-09 09:34:50,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:50,757 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 73 times [2021-11-09 09:34:50,757 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:50,757 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1889584192] [2021-11-09 09:34:50,758 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:50,758 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:50,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:50,771 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:50,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:50,772 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:50,772 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:50,772 INFO L85 PathProgramCache]: Analyzing trace with hash -1267941233, now seen corresponding path program 72 times [2021-11-09 09:34:50,772 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:50,772 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [974622205] [2021-11-09 09:34:50,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:50,772 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:50,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:52,752 INFO L134 CoverageAnalysis]: Checked inductivity of 2628 backedges. 0 proven. 2628 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:52,752 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:52,753 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [974622205] [2021-11-09 09:34:52,753 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [974622205] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:52,753 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [50466983] [2021-11-09 09:34:52,753 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:34:52,753 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:52,753 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:52,754 INFO L229 MonitoredProcess]: Starting monitored process 73 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:52,755 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (73)] Waiting until timeout for monitored process [2021-11-09 09:34:53,752 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 37 check-sat command(s) [2021-11-09 09:34:53,752 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:34:53,754 INFO L263 TraceCheckSpWp]: Trace formula consists of 224 conjuncts, 74 conjunts are in the unsatisfiable core [2021-11-09 09:34:53,755 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:54,024 INFO L134 CoverageAnalysis]: Checked inductivity of 2628 backedges. 0 proven. 2628 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:54,025 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [50466983] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:54,025 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:54,025 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [74, 74] total 74 [2021-11-09 09:34:54,026 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1911980403] [2021-11-09 09:34:54,026 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:34:54,026 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:54,027 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 75 interpolants. [2021-11-09 09:34:54,028 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2775, Invalid=2775, Unknown=0, NotChecked=0, Total=5550 [2021-11-09 09:34:54,028 INFO L87 Difference]: Start difference. First operand 76 states and 77 transitions. cyclomatic complexity: 2 Second operand has 75 states, 75 states have (on average 1.0) internal successors, (75), 74 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:54,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:54,114 INFO L93 Difference]: Finished difference Result 77 states and 78 transitions. [2021-11-09 09:34:54,115 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 75 states. [2021-11-09 09:34:54,115 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 77 states and 78 transitions. [2021-11-09 09:34:54,115 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 76 [2021-11-09 09:34:54,116 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 77 states to 77 states and 78 transitions. [2021-11-09 09:34:54,116 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 77 [2021-11-09 09:34:54,116 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 77 [2021-11-09 09:34:54,116 INFO L73 IsDeterministic]: Start isDeterministic. Operand 77 states and 78 transitions. [2021-11-09 09:34:54,116 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:54,116 INFO L681 BuchiCegarLoop]: Abstraction has 77 states and 78 transitions. [2021-11-09 09:34:54,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states and 78 transitions. [2021-11-09 09:34:54,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 77. [2021-11-09 09:34:54,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77 states, 77 states have (on average 1.0129870129870129) internal successors, (78), 76 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:54,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 78 transitions. [2021-11-09 09:34:54,118 INFO L704 BuchiCegarLoop]: Abstraction has 77 states and 78 transitions. [2021-11-09 09:34:54,118 INFO L587 BuchiCegarLoop]: Abstraction has 77 states and 78 transitions. [2021-11-09 09:34:54,118 INFO L425 BuchiCegarLoop]: ======== Iteration 74============ [2021-11-09 09:34:54,118 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77 states and 78 transitions. [2021-11-09 09:34:54,118 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 76 [2021-11-09 09:34:54,118 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:54,119 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:54,119 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:34:54,119 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [73, 1, 1, 1] [2021-11-09 09:34:54,119 INFO L791 eck$LassoCheckResult]: Stem: 17309#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 17306#L19-2 [2021-11-09 09:34:54,119 INFO L793 eck$LassoCheckResult]: Loop: 17306#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 17307#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17310#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17382#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17381#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17380#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17379#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17378#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17377#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17376#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17375#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17374#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17373#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17372#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17371#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17370#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17369#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17368#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17367#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17366#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17365#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17364#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17363#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17362#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17361#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17360#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17359#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17358#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17357#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17356#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17355#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17354#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17353#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17352#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17351#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17350#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17349#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17348#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17347#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17346#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17345#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17344#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17343#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17342#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17341#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17340#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17339#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17338#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17337#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17336#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17335#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17334#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17333#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17332#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17331#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17330#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17329#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17328#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17327#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17326#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17325#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17324#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17323#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17322#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17321#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17320#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17319#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17318#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17317#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17316#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17315#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17314#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17313#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17312#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17311#L21-2 assume !(main_~x2~0 > 1); 17308#L21-3 main_~x1~0 := 1 + main_~x1~0; 17306#L19-2 [2021-11-09 09:34:54,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:54,119 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 74 times [2021-11-09 09:34:54,120 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:54,120 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1273858394] [2021-11-09 09:34:54,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:54,120 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:54,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:54,129 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:54,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:54,130 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:54,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:54,130 INFO L85 PathProgramCache]: Analyzing trace with hash -651470800, now seen corresponding path program 73 times [2021-11-09 09:34:54,130 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:54,130 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1938017600] [2021-11-09 09:34:54,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:54,131 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:54,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:56,236 INFO L134 CoverageAnalysis]: Checked inductivity of 2701 backedges. 0 proven. 2701 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:56,237 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:56,237 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1938017600] [2021-11-09 09:34:56,237 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1938017600] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:56,237 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1614825060] [2021-11-09 09:34:56,237 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:34:56,237 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:56,237 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:56,239 INFO L229 MonitoredProcess]: Starting monitored process 74 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:56,239 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (74)] Waiting until timeout for monitored process [2021-11-09 09:34:57,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:57,383 INFO L263 TraceCheckSpWp]: Trace formula consists of 227 conjuncts, 75 conjunts are in the unsatisfiable core [2021-11-09 09:34:57,385 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:34:57,630 INFO L134 CoverageAnalysis]: Checked inductivity of 2701 backedges. 0 proven. 2701 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:57,630 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1614825060] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:57,630 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:34:57,630 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [75, 75] total 75 [2021-11-09 09:34:57,630 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [420128079] [2021-11-09 09:34:57,631 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:34:57,631 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:34:57,631 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2021-11-09 09:34:57,631 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2850, Invalid=2850, Unknown=0, NotChecked=0, Total=5700 [2021-11-09 09:34:57,632 INFO L87 Difference]: Start difference. First operand 77 states and 78 transitions. cyclomatic complexity: 2 Second operand has 76 states, 76 states have (on average 1.0) internal successors, (76), 75 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:57,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:34:57,695 INFO L93 Difference]: Finished difference Result 78 states and 79 transitions. [2021-11-09 09:34:57,695 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2021-11-09 09:34:57,695 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 78 states and 79 transitions. [2021-11-09 09:34:57,695 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 77 [2021-11-09 09:34:57,696 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 78 states to 78 states and 79 transitions. [2021-11-09 09:34:57,696 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 78 [2021-11-09 09:34:57,696 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 78 [2021-11-09 09:34:57,696 INFO L73 IsDeterministic]: Start isDeterministic. Operand 78 states and 79 transitions. [2021-11-09 09:34:57,696 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:34:57,696 INFO L681 BuchiCegarLoop]: Abstraction has 78 states and 79 transitions. [2021-11-09 09:34:57,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states and 79 transitions. [2021-11-09 09:34:57,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 78. [2021-11-09 09:34:57,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78 states, 78 states have (on average 1.0128205128205128) internal successors, (79), 77 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:34:57,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 79 transitions. [2021-11-09 09:34:57,698 INFO L704 BuchiCegarLoop]: Abstraction has 78 states and 79 transitions. [2021-11-09 09:34:57,698 INFO L587 BuchiCegarLoop]: Abstraction has 78 states and 79 transitions. [2021-11-09 09:34:57,698 INFO L425 BuchiCegarLoop]: ======== Iteration 75============ [2021-11-09 09:34:57,698 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78 states and 79 transitions. [2021-11-09 09:34:57,698 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 77 [2021-11-09 09:34:57,699 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:34:57,699 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:34:57,699 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:34:57,699 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [74, 1, 1, 1] [2021-11-09 09:34:57,700 INFO L791 eck$LassoCheckResult]: Stem: 17768#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 17765#L19-2 [2021-11-09 09:34:57,700 INFO L793 eck$LassoCheckResult]: Loop: 17765#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 17766#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17769#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17842#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17841#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17840#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17839#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17838#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17837#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17836#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17835#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17834#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17833#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17832#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17831#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17830#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17829#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17828#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17827#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17826#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17825#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17824#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17823#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17822#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17821#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17820#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17819#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17818#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17817#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17816#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17815#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17814#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17813#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17812#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17811#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17810#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17809#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17808#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17807#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17806#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17805#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17804#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17803#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17802#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17801#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17800#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17799#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17798#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17797#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17796#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17795#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17794#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17793#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17792#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17791#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17790#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17789#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17788#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17787#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17786#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17785#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17784#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17783#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17782#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17781#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17780#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17779#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17778#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17777#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17776#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17775#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17774#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17773#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17772#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17771#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 17770#L21-2 assume !(main_~x2~0 > 1); 17767#L21-3 main_~x1~0 := 1 + main_~x1~0; 17765#L19-2 [2021-11-09 09:34:57,700 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:57,700 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 75 times [2021-11-09 09:34:57,700 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:57,701 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1386271982] [2021-11-09 09:34:57,701 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:57,701 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:57,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:57,709 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:34:57,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:34:57,710 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:34:57,710 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:34:57,710 INFO L85 PathProgramCache]: Analyzing trace with hash 1279243439, now seen corresponding path program 74 times [2021-11-09 09:34:57,711 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:34:57,711 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510861419] [2021-11-09 09:34:57,711 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:34:57,711 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:34:57,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:34:59,822 INFO L134 CoverageAnalysis]: Checked inductivity of 2775 backedges. 0 proven. 2775 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:34:59,822 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:34:59,822 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1510861419] [2021-11-09 09:34:59,822 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1510861419] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:34:59,822 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [438155910] [2021-11-09 09:34:59,822 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:34:59,822 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:34:59,823 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:59,824 INFO L229 MonitoredProcess]: Starting monitored process 75 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:34:59,825 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (75)] Waiting until timeout for monitored process [2021-11-09 09:35:00,825 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:35:00,825 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:35:00,827 INFO L263 TraceCheckSpWp]: Trace formula consists of 230 conjuncts, 76 conjunts are in the unsatisfiable core [2021-11-09 09:35:00,828 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:35:01,068 INFO L134 CoverageAnalysis]: Checked inductivity of 2775 backedges. 0 proven. 2775 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:01,068 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [438155910] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:01,068 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:35:01,069 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [76, 76] total 76 [2021-11-09 09:35:01,069 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1169350484] [2021-11-09 09:35:01,069 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:01,069 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:01,070 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2021-11-09 09:35:01,071 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2926, Invalid=2926, Unknown=0, NotChecked=0, Total=5852 [2021-11-09 09:35:01,072 INFO L87 Difference]: Start difference. First operand 78 states and 79 transitions. cyclomatic complexity: 2 Second operand has 77 states, 77 states have (on average 1.0) internal successors, (77), 76 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:01,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:01,162 INFO L93 Difference]: Finished difference Result 79 states and 80 transitions. [2021-11-09 09:35:01,162 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2021-11-09 09:35:01,162 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79 states and 80 transitions. [2021-11-09 09:35:01,163 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 78 [2021-11-09 09:35:01,163 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79 states to 79 states and 80 transitions. [2021-11-09 09:35:01,163 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 79 [2021-11-09 09:35:01,164 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 79 [2021-11-09 09:35:01,164 INFO L73 IsDeterministic]: Start isDeterministic. Operand 79 states and 80 transitions. [2021-11-09 09:35:01,164 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:01,164 INFO L681 BuchiCegarLoop]: Abstraction has 79 states and 80 transitions. [2021-11-09 09:35:01,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states and 80 transitions. [2021-11-09 09:35:01,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 79. [2021-11-09 09:35:01,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 79 states, 79 states have (on average 1.0126582278481013) internal successors, (80), 78 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:01,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 80 transitions. [2021-11-09 09:35:01,166 INFO L704 BuchiCegarLoop]: Abstraction has 79 states and 80 transitions. [2021-11-09 09:35:01,166 INFO L587 BuchiCegarLoop]: Abstraction has 79 states and 80 transitions. [2021-11-09 09:35:01,166 INFO L425 BuchiCegarLoop]: ======== Iteration 76============ [2021-11-09 09:35:01,166 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 79 states and 80 transitions. [2021-11-09 09:35:01,167 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 78 [2021-11-09 09:35:01,168 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:01,168 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:01,168 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:35:01,168 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [75, 1, 1, 1] [2021-11-09 09:35:01,169 INFO L791 eck$LassoCheckResult]: Stem: 18233#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 18230#L19-2 [2021-11-09 09:35:01,169 INFO L793 eck$LassoCheckResult]: Loop: 18230#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 18231#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18234#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18308#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18307#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18306#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18305#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18304#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18303#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18302#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18301#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18300#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18299#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18298#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18297#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18296#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18295#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18294#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18293#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18292#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18291#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18290#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18289#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18288#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18287#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18286#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18285#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18284#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18283#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18282#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18281#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18280#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18279#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18278#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18277#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18276#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18275#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18274#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18273#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18272#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18271#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18270#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18269#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18268#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18267#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18266#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18265#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18264#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18263#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18262#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18261#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18260#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18259#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18258#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18257#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18256#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18255#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18254#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18253#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18252#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18251#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18250#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18249#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18248#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18247#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18246#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18245#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18244#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18243#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18242#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18241#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18240#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18239#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18238#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18237#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18236#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18235#L21-2 assume !(main_~x2~0 > 1); 18232#L21-3 main_~x1~0 := 1 + main_~x1~0; 18230#L19-2 [2021-11-09 09:35:01,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:01,169 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 76 times [2021-11-09 09:35:01,170 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:01,170 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [48745227] [2021-11-09 09:35:01,170 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:01,170 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:01,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:01,239 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:01,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:01,240 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:01,240 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:01,241 INFO L85 PathProgramCache]: Analyzing trace with hash 1001842704, now seen corresponding path program 75 times [2021-11-09 09:35:01,241 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:01,241 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1999629949] [2021-11-09 09:35:01,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:01,241 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:01,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:03,433 INFO L134 CoverageAnalysis]: Checked inductivity of 2850 backedges. 0 proven. 2850 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:03,433 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:03,433 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1999629949] [2021-11-09 09:35:03,433 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1999629949] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:03,433 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [683173349] [2021-11-09 09:35:03,433 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:35:03,434 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:35:03,434 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:35:03,435 INFO L229 MonitoredProcess]: Starting monitored process 76 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:35:03,436 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (76)] Waiting until timeout for monitored process [2021-11-09 09:35:04,448 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 39 check-sat command(s) [2021-11-09 09:35:04,448 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:35:04,450 INFO L263 TraceCheckSpWp]: Trace formula consists of 233 conjuncts, 77 conjunts are in the unsatisfiable core [2021-11-09 09:35:04,451 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:35:04,675 INFO L134 CoverageAnalysis]: Checked inductivity of 2850 backedges. 0 proven. 2850 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:04,675 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [683173349] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:04,675 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:35:04,675 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [77, 77] total 77 [2021-11-09 09:35:04,676 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1689193545] [2021-11-09 09:35:04,676 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:04,676 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:04,677 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 78 interpolants. [2021-11-09 09:35:04,677 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3003, Invalid=3003, Unknown=0, NotChecked=0, Total=6006 [2021-11-09 09:35:04,677 INFO L87 Difference]: Start difference. First operand 79 states and 80 transitions. cyclomatic complexity: 2 Second operand has 78 states, 78 states have (on average 1.0) internal successors, (78), 77 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:04,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:04,743 INFO L93 Difference]: Finished difference Result 80 states and 81 transitions. [2021-11-09 09:35:04,743 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 78 states. [2021-11-09 09:35:04,744 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 80 states and 81 transitions. [2021-11-09 09:35:04,744 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 79 [2021-11-09 09:35:04,744 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 80 states to 80 states and 81 transitions. [2021-11-09 09:35:04,744 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 80 [2021-11-09 09:35:04,745 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 80 [2021-11-09 09:35:04,745 INFO L73 IsDeterministic]: Start isDeterministic. Operand 80 states and 81 transitions. [2021-11-09 09:35:04,745 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:04,745 INFO L681 BuchiCegarLoop]: Abstraction has 80 states and 81 transitions. [2021-11-09 09:35:04,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states and 81 transitions. [2021-11-09 09:35:04,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 80. [2021-11-09 09:35:04,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80 states, 80 states have (on average 1.0125) internal successors, (81), 79 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:04,746 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 81 transitions. [2021-11-09 09:35:04,746 INFO L704 BuchiCegarLoop]: Abstraction has 80 states and 81 transitions. [2021-11-09 09:35:04,746 INFO L587 BuchiCegarLoop]: Abstraction has 80 states and 81 transitions. [2021-11-09 09:35:04,746 INFO L425 BuchiCegarLoop]: ======== Iteration 77============ [2021-11-09 09:35:04,746 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80 states and 81 transitions. [2021-11-09 09:35:04,747 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 79 [2021-11-09 09:35:04,747 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:04,747 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:04,747 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:35:04,747 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [76, 1, 1, 1] [2021-11-09 09:35:04,747 INFO L791 eck$LassoCheckResult]: Stem: 18704#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 18701#L19-2 [2021-11-09 09:35:04,747 INFO L793 eck$LassoCheckResult]: Loop: 18701#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 18702#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18705#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18780#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18779#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18778#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18777#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18776#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18775#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18774#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18773#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18772#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18771#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18770#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18769#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18768#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18767#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18766#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18765#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18764#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18763#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18762#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18761#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18760#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18759#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18758#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18757#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18756#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18755#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18754#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18753#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18752#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18751#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18750#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18749#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18748#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18747#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18746#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18745#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18744#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18743#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18742#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18741#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18740#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18739#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18738#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18737#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18736#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18735#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18734#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18733#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18732#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18731#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18730#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18729#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18728#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18727#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18726#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18725#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18724#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18723#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18722#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18721#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18720#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18719#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18718#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18717#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18716#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18715#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18714#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18713#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18712#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18711#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18710#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18709#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18708#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18707#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 18706#L21-2 assume !(main_~x2~0 > 1); 18703#L21-3 main_~x1~0 := 1 + main_~x1~0; 18701#L19-2 [2021-11-09 09:35:04,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:04,747 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 77 times [2021-11-09 09:35:04,748 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:04,748 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1898929210] [2021-11-09 09:35:04,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:04,748 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:04,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:04,755 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:04,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:04,756 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:04,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:04,757 INFO L85 PathProgramCache]: Analyzing trace with hash 992354511, now seen corresponding path program 76 times [2021-11-09 09:35:04,757 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:04,757 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [42156802] [2021-11-09 09:35:04,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:04,757 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:04,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:06,997 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:06,998 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:06,998 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [42156802] [2021-11-09 09:35:06,998 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [42156802] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:06,998 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1349401131] [2021-11-09 09:35:06,998 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:35:06,998 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:35:06,999 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:35:07,000 INFO L229 MonitoredProcess]: Starting monitored process 77 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:35:07,001 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (77)] Waiting until timeout for monitored process [2021-11-09 09:35:08,023 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:35:08,023 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:35:08,025 INFO L263 TraceCheckSpWp]: Trace formula consists of 236 conjuncts, 78 conjunts are in the unsatisfiable core [2021-11-09 09:35:08,026 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:35:08,244 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:08,245 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1349401131] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:08,245 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:35:08,245 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [78, 78] total 78 [2021-11-09 09:35:08,245 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2137914409] [2021-11-09 09:35:08,245 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:08,245 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:08,246 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 79 interpolants. [2021-11-09 09:35:08,246 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3081, Invalid=3081, Unknown=0, NotChecked=0, Total=6162 [2021-11-09 09:35:08,247 INFO L87 Difference]: Start difference. First operand 80 states and 81 transitions. cyclomatic complexity: 2 Second operand has 79 states, 79 states have (on average 1.0) internal successors, (79), 78 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:08,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:08,342 INFO L93 Difference]: Finished difference Result 81 states and 82 transitions. [2021-11-09 09:35:08,342 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 79 states. [2021-11-09 09:35:08,343 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81 states and 82 transitions. [2021-11-09 09:35:08,343 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 80 [2021-11-09 09:35:08,343 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81 states to 81 states and 82 transitions. [2021-11-09 09:35:08,343 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 81 [2021-11-09 09:35:08,343 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 81 [2021-11-09 09:35:08,344 INFO L73 IsDeterministic]: Start isDeterministic. Operand 81 states and 82 transitions. [2021-11-09 09:35:08,344 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:08,344 INFO L681 BuchiCegarLoop]: Abstraction has 81 states and 82 transitions. [2021-11-09 09:35:08,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states and 82 transitions. [2021-11-09 09:35:08,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 81. [2021-11-09 09:35:08,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81 states, 81 states have (on average 1.0123456790123457) internal successors, (82), 80 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:08,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 82 transitions. [2021-11-09 09:35:08,349 INFO L704 BuchiCegarLoop]: Abstraction has 81 states and 82 transitions. [2021-11-09 09:35:08,350 INFO L587 BuchiCegarLoop]: Abstraction has 81 states and 82 transitions. [2021-11-09 09:35:08,350 INFO L425 BuchiCegarLoop]: ======== Iteration 78============ [2021-11-09 09:35:08,350 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81 states and 82 transitions. [2021-11-09 09:35:08,350 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 80 [2021-11-09 09:35:08,350 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:08,350 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:08,351 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:35:08,351 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [77, 1, 1, 1] [2021-11-09 09:35:08,351 INFO L791 eck$LassoCheckResult]: Stem: 19181#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 19178#L19-2 [2021-11-09 09:35:08,351 INFO L793 eck$LassoCheckResult]: Loop: 19178#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 19179#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19182#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19258#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19257#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19256#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19255#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19254#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19253#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19252#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19251#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19250#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19249#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19248#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19247#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19246#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19245#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19244#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19243#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19242#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19241#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19240#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19239#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19238#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19237#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19236#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19235#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19234#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19233#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19232#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19231#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19230#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19229#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19228#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19227#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19226#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19225#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19224#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19223#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19222#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19221#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19220#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19219#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19218#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19217#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19216#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19215#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19214#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19213#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19212#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19211#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19210#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19209#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19208#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19207#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19206#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19205#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19204#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19203#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19202#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19201#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19200#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19199#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19198#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19197#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19196#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19195#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19194#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19193#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19192#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19191#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19190#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19189#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19188#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19187#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19186#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19185#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19184#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19183#L21-2 assume !(main_~x2~0 > 1); 19180#L21-3 main_~x1~0 := 1 + main_~x1~0; 19178#L19-2 [2021-11-09 09:35:08,352 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:08,352 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 78 times [2021-11-09 09:35:08,352 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:08,352 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [173045139] [2021-11-09 09:35:08,352 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:08,353 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:08,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:08,418 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:08,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:08,421 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:08,422 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:08,422 INFO L85 PathProgramCache]: Analyzing trace with hash 698220528, now seen corresponding path program 77 times [2021-11-09 09:35:08,422 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:08,422 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1506369780] [2021-11-09 09:35:08,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:08,423 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:08,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:10,754 INFO L134 CoverageAnalysis]: Checked inductivity of 3003 backedges. 0 proven. 3003 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:10,755 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:10,755 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1506369780] [2021-11-09 09:35:10,755 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1506369780] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:10,755 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2104824750] [2021-11-09 09:35:10,755 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:35:10,755 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:35:10,755 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:35:10,757 INFO L229 MonitoredProcess]: Starting monitored process 78 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:35:10,757 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (78)] Waiting until timeout for monitored process [2021-11-09 09:35:11,836 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 40 check-sat command(s) [2021-11-09 09:35:11,836 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:35:11,839 INFO L263 TraceCheckSpWp]: Trace formula consists of 239 conjuncts, 79 conjunts are in the unsatisfiable core [2021-11-09 09:35:11,840 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:35:12,061 INFO L134 CoverageAnalysis]: Checked inductivity of 3003 backedges. 0 proven. 3003 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:12,061 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2104824750] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:12,061 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:35:12,061 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [79, 79] total 79 [2021-11-09 09:35:12,061 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [361648915] [2021-11-09 09:35:12,062 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:12,062 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:12,063 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 80 interpolants. [2021-11-09 09:35:12,063 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3160, Invalid=3160, Unknown=0, NotChecked=0, Total=6320 [2021-11-09 09:35:12,063 INFO L87 Difference]: Start difference. First operand 81 states and 82 transitions. cyclomatic complexity: 2 Second operand has 80 states, 80 states have (on average 1.0) internal successors, (80), 79 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:12,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:12,138 INFO L93 Difference]: Finished difference Result 82 states and 83 transitions. [2021-11-09 09:35:12,138 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 80 states. [2021-11-09 09:35:12,138 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 82 states and 83 transitions. [2021-11-09 09:35:12,138 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 81 [2021-11-09 09:35:12,139 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 82 states to 82 states and 83 transitions. [2021-11-09 09:35:12,139 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 82 [2021-11-09 09:35:12,139 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 82 [2021-11-09 09:35:12,139 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82 states and 83 transitions. [2021-11-09 09:35:12,139 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:12,140 INFO L681 BuchiCegarLoop]: Abstraction has 82 states and 83 transitions. [2021-11-09 09:35:12,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states and 83 transitions. [2021-11-09 09:35:12,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 82. [2021-11-09 09:35:12,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82 states, 82 states have (on average 1.0121951219512195) internal successors, (83), 81 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:12,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 83 transitions. [2021-11-09 09:35:12,142 INFO L704 BuchiCegarLoop]: Abstraction has 82 states and 83 transitions. [2021-11-09 09:35:12,142 INFO L587 BuchiCegarLoop]: Abstraction has 82 states and 83 transitions. [2021-11-09 09:35:12,142 INFO L425 BuchiCegarLoop]: ======== Iteration 79============ [2021-11-09 09:35:12,142 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82 states and 83 transitions. [2021-11-09 09:35:12,142 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 81 [2021-11-09 09:35:12,143 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:12,143 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:12,143 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:35:12,143 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [78, 1, 1, 1] [2021-11-09 09:35:12,143 INFO L791 eck$LassoCheckResult]: Stem: 19664#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 19661#L19-2 [2021-11-09 09:35:12,144 INFO L793 eck$LassoCheckResult]: Loop: 19661#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 19662#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19665#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19742#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19741#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19740#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19739#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19738#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19737#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19736#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19735#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19734#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19733#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19732#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19731#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19730#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19729#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19728#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19727#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19726#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19725#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19724#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19723#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19722#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19721#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19720#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19719#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19718#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19717#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19716#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19715#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19714#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19713#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19712#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19711#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19710#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19709#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19708#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19707#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19706#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19705#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19704#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19703#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19702#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19701#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19700#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19699#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19698#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19697#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19696#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19695#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19694#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19693#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19692#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19691#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19690#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19689#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19688#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19687#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19686#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19685#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19684#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19683#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19682#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19681#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19680#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19679#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19678#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19677#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19676#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19675#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19674#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19673#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19672#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19671#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19670#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19669#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19668#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19667#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 19666#L21-2 assume !(main_~x2~0 > 1); 19663#L21-3 main_~x1~0 := 1 + main_~x1~0; 19661#L19-2 [2021-11-09 09:35:12,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:12,144 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 79 times [2021-11-09 09:35:12,144 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:12,144 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [113070634] [2021-11-09 09:35:12,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:12,145 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:12,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:12,161 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:12,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:12,162 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:12,163 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:12,163 INFO L85 PathProgramCache]: Analyzing trace with hash 170001647, now seen corresponding path program 78 times [2021-11-09 09:35:12,163 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:12,163 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1895825652] [2021-11-09 09:35:12,163 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:12,163 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:12,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:14,731 INFO L134 CoverageAnalysis]: Checked inductivity of 3081 backedges. 0 proven. 3081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:14,731 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:14,731 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1895825652] [2021-11-09 09:35:14,731 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1895825652] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:14,731 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1858112957] [2021-11-09 09:35:14,731 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:35:14,731 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:35:14,732 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:35:14,733 INFO L229 MonitoredProcess]: Starting monitored process 79 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:35:14,734 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (79)] Waiting until timeout for monitored process [2021-11-09 09:35:15,984 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 40 check-sat command(s) [2021-11-09 09:35:15,985 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:35:15,987 INFO L263 TraceCheckSpWp]: Trace formula consists of 242 conjuncts, 80 conjunts are in the unsatisfiable core [2021-11-09 09:35:15,988 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:35:16,276 INFO L134 CoverageAnalysis]: Checked inductivity of 3081 backedges. 0 proven. 3081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:16,276 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1858112957] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:16,277 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:35:16,277 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [80, 80] total 80 [2021-11-09 09:35:16,277 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [445849040] [2021-11-09 09:35:16,278 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:16,278 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:16,279 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 81 interpolants. [2021-11-09 09:35:16,280 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3240, Invalid=3240, Unknown=0, NotChecked=0, Total=6480 [2021-11-09 09:35:16,280 INFO L87 Difference]: Start difference. First operand 82 states and 83 transitions. cyclomatic complexity: 2 Second operand has 81 states, 81 states have (on average 1.0) internal successors, (81), 80 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:16,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:16,403 INFO L93 Difference]: Finished difference Result 83 states and 84 transitions. [2021-11-09 09:35:16,403 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 81 states. [2021-11-09 09:35:16,403 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83 states and 84 transitions. [2021-11-09 09:35:16,404 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 82 [2021-11-09 09:35:16,405 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83 states to 83 states and 84 transitions. [2021-11-09 09:35:16,405 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 83 [2021-11-09 09:35:16,405 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 83 [2021-11-09 09:35:16,405 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83 states and 84 transitions. [2021-11-09 09:35:16,406 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:16,406 INFO L681 BuchiCegarLoop]: Abstraction has 83 states and 84 transitions. [2021-11-09 09:35:16,406 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states and 84 transitions. [2021-11-09 09:35:16,407 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 83. [2021-11-09 09:35:16,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83 states, 83 states have (on average 1.0120481927710843) internal successors, (84), 82 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:16,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 84 transitions. [2021-11-09 09:35:16,409 INFO L704 BuchiCegarLoop]: Abstraction has 83 states and 84 transitions. [2021-11-09 09:35:16,409 INFO L587 BuchiCegarLoop]: Abstraction has 83 states and 84 transitions. [2021-11-09 09:35:16,409 INFO L425 BuchiCegarLoop]: ======== Iteration 80============ [2021-11-09 09:35:16,409 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83 states and 84 transitions. [2021-11-09 09:35:16,410 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 82 [2021-11-09 09:35:16,410 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:16,410 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:16,411 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:35:16,411 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [79, 1, 1, 1] [2021-11-09 09:35:16,411 INFO L791 eck$LassoCheckResult]: Stem: 20153#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 20150#L19-2 [2021-11-09 09:35:16,411 INFO L793 eck$LassoCheckResult]: Loop: 20150#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 20151#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20154#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20232#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20231#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20230#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20229#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20228#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20227#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20226#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20225#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20224#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20223#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20222#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20221#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20220#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20219#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20218#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20217#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20216#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20215#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20214#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20213#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20212#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20211#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20210#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20209#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20208#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20207#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20206#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20205#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20204#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20203#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20202#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20201#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20200#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20199#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20198#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20197#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20196#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20195#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20194#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20193#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20192#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20191#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20190#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20189#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20188#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20187#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20186#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20185#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20184#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20183#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20182#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20181#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20180#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20179#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20178#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20177#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20176#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20175#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20174#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20173#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20172#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20171#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20170#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20169#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20168#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20167#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20166#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20165#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20164#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20163#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20162#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20161#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20160#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20159#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20158#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20157#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20156#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20155#L21-2 assume !(main_~x2~0 > 1); 20152#L21-3 main_~x1~0 := 1 + main_~x1~0; 20150#L19-2 [2021-11-09 09:35:16,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:16,412 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 80 times [2021-11-09 09:35:16,412 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:16,412 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2074124225] [2021-11-09 09:35:16,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:16,413 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:16,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:16,426 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:16,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:16,427 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:16,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:16,428 INFO L85 PathProgramCache]: Analyzing trace with hash 975085520, now seen corresponding path program 79 times [2021-11-09 09:35:16,428 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:16,429 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1386782871] [2021-11-09 09:35:16,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:16,429 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:16,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:18,862 INFO L134 CoverageAnalysis]: Checked inductivity of 3160 backedges. 0 proven. 3160 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:18,862 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:18,862 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1386782871] [2021-11-09 09:35:18,863 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1386782871] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:18,863 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [255308204] [2021-11-09 09:35:18,863 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:35:18,863 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:35:18,863 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:35:18,864 INFO L229 MonitoredProcess]: Starting monitored process 80 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:35:18,865 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (80)] Waiting until timeout for monitored process [2021-11-09 09:35:19,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:19,962 INFO L263 TraceCheckSpWp]: Trace formula consists of 245 conjuncts, 81 conjunts are in the unsatisfiable core [2021-11-09 09:35:19,963 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:35:20,185 INFO L134 CoverageAnalysis]: Checked inductivity of 3160 backedges. 0 proven. 3160 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:20,186 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [255308204] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:20,186 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:35:20,186 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [81, 81] total 81 [2021-11-09 09:35:20,186 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [976812994] [2021-11-09 09:35:20,187 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:20,187 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:20,188 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2021-11-09 09:35:20,189 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3321, Invalid=3321, Unknown=0, NotChecked=0, Total=6642 [2021-11-09 09:35:20,189 INFO L87 Difference]: Start difference. First operand 83 states and 84 transitions. cyclomatic complexity: 2 Second operand has 82 states, 82 states have (on average 1.0) internal successors, (82), 81 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:20,273 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:20,273 INFO L93 Difference]: Finished difference Result 84 states and 85 transitions. [2021-11-09 09:35:20,274 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 82 states. [2021-11-09 09:35:20,274 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 84 states and 85 transitions. [2021-11-09 09:35:20,274 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 83 [2021-11-09 09:35:20,275 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 84 states to 84 states and 85 transitions. [2021-11-09 09:35:20,275 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 84 [2021-11-09 09:35:20,275 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 84 [2021-11-09 09:35:20,275 INFO L73 IsDeterministic]: Start isDeterministic. Operand 84 states and 85 transitions. [2021-11-09 09:35:20,276 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:20,276 INFO L681 BuchiCegarLoop]: Abstraction has 84 states and 85 transitions. [2021-11-09 09:35:20,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states and 85 transitions. [2021-11-09 09:35:20,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 84. [2021-11-09 09:35:20,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84 states, 84 states have (on average 1.0119047619047619) internal successors, (85), 83 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:20,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 85 transitions. [2021-11-09 09:35:20,278 INFO L704 BuchiCegarLoop]: Abstraction has 84 states and 85 transitions. [2021-11-09 09:35:20,278 INFO L587 BuchiCegarLoop]: Abstraction has 84 states and 85 transitions. [2021-11-09 09:35:20,278 INFO L425 BuchiCegarLoop]: ======== Iteration 81============ [2021-11-09 09:35:20,278 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84 states and 85 transitions. [2021-11-09 09:35:20,278 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 83 [2021-11-09 09:35:20,278 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:20,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:20,279 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:35:20,279 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [80, 1, 1, 1] [2021-11-09 09:35:20,279 INFO L791 eck$LassoCheckResult]: Stem: 20648#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 20645#L19-2 [2021-11-09 09:35:20,280 INFO L793 eck$LassoCheckResult]: Loop: 20645#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 20646#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20649#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20728#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20727#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20726#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20725#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20724#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20723#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20722#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20721#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20720#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20719#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20718#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20717#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20716#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20715#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20714#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20713#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20712#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20711#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20710#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20709#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20708#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20707#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20706#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20705#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20704#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20703#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20702#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20701#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20700#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20699#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20698#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20697#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20696#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20695#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20694#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20693#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20692#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20691#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20690#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20689#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20688#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20687#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20686#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20685#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20684#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20683#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20682#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20681#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20680#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20679#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20678#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20677#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20676#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20675#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20674#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20673#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20672#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20671#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20670#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20669#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20668#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20667#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20666#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20665#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20664#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20663#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20662#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20661#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20660#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20659#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20658#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20657#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20656#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20655#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20654#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20653#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20652#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20651#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 20650#L21-2 assume !(main_~x2~0 > 1); 20647#L21-3 main_~x1~0 := 1 + main_~x1~0; 20645#L19-2 [2021-11-09 09:35:20,280 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:20,280 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 81 times [2021-11-09 09:35:20,280 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:20,280 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [160659637] [2021-11-09 09:35:20,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:20,281 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:20,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:20,291 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:20,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:20,293 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:20,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:20,293 INFO L85 PathProgramCache]: Analyzing trace with hash 162881807, now seen corresponding path program 80 times [2021-11-09 09:35:20,293 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:20,294 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1916463348] [2021-11-09 09:35:20,294 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:20,294 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:20,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:22,684 INFO L134 CoverageAnalysis]: Checked inductivity of 3240 backedges. 0 proven. 3240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:22,685 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:22,685 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1916463348] [2021-11-09 09:35:22,685 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1916463348] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:22,685 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [542498288] [2021-11-09 09:35:22,685 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:35:22,685 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:35:22,685 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:35:22,686 INFO L229 MonitoredProcess]: Starting monitored process 81 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:35:22,687 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (81)] Waiting until timeout for monitored process [2021-11-09 09:35:23,823 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:35:23,823 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:35:23,825 INFO L263 TraceCheckSpWp]: Trace formula consists of 248 conjuncts, 82 conjunts are in the unsatisfiable core [2021-11-09 09:35:23,826 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:35:24,036 INFO L134 CoverageAnalysis]: Checked inductivity of 3240 backedges. 0 proven. 3240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:24,036 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [542498288] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:24,036 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:35:24,036 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [82, 82] total 82 [2021-11-09 09:35:24,036 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1266669632] [2021-11-09 09:35:24,036 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:24,036 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:24,038 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2021-11-09 09:35:24,038 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3403, Invalid=3403, Unknown=0, NotChecked=0, Total=6806 [2021-11-09 09:35:24,038 INFO L87 Difference]: Start difference. First operand 84 states and 85 transitions. cyclomatic complexity: 2 Second operand has 83 states, 83 states have (on average 1.0) internal successors, (83), 82 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:24,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:24,106 INFO L93 Difference]: Finished difference Result 85 states and 86 transitions. [2021-11-09 09:35:24,106 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2021-11-09 09:35:24,106 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 85 states and 86 transitions. [2021-11-09 09:35:24,107 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 84 [2021-11-09 09:35:24,107 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 85 states to 85 states and 86 transitions. [2021-11-09 09:35:24,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 85 [2021-11-09 09:35:24,108 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 85 [2021-11-09 09:35:24,108 INFO L73 IsDeterministic]: Start isDeterministic. Operand 85 states and 86 transitions. [2021-11-09 09:35:24,108 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:24,108 INFO L681 BuchiCegarLoop]: Abstraction has 85 states and 86 transitions. [2021-11-09 09:35:24,108 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states and 86 transitions. [2021-11-09 09:35:24,109 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 85. [2021-11-09 09:35:24,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 85 states, 85 states have (on average 1.011764705882353) internal successors, (86), 84 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:24,110 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 86 transitions. [2021-11-09 09:35:24,110 INFO L704 BuchiCegarLoop]: Abstraction has 85 states and 86 transitions. [2021-11-09 09:35:24,110 INFO L587 BuchiCegarLoop]: Abstraction has 85 states and 86 transitions. [2021-11-09 09:35:24,110 INFO L425 BuchiCegarLoop]: ======== Iteration 82============ [2021-11-09 09:35:24,111 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 85 states and 86 transitions. [2021-11-09 09:35:24,111 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 84 [2021-11-09 09:35:24,111 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:24,111 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:24,112 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:35:24,112 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [81, 1, 1, 1] [2021-11-09 09:35:24,112 INFO L791 eck$LassoCheckResult]: Stem: 21149#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 21146#L19-2 [2021-11-09 09:35:24,112 INFO L793 eck$LassoCheckResult]: Loop: 21146#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 21147#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21150#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21230#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21229#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21228#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21227#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21226#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21225#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21224#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21223#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21222#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21221#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21220#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21219#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21218#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21217#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21216#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21215#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21214#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21213#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21212#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21211#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21210#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21209#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21208#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21207#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21206#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21205#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21204#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21203#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21202#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21201#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21200#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21199#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21198#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21197#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21196#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21195#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21194#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21193#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21192#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21191#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21190#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21189#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21188#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21187#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21186#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21185#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21184#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21183#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21182#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21181#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21180#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21179#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21178#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21177#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21176#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21175#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21174#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21173#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21172#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21171#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21170#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21169#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21168#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21167#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21166#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21165#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21164#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21163#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21162#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21161#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21160#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21159#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21158#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21157#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21156#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21155#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21154#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21153#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21152#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21151#L21-2 assume !(main_~x2~0 > 1); 21148#L21-3 main_~x1~0 := 1 + main_~x1~0; 21146#L19-2 [2021-11-09 09:35:24,113 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:24,113 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 82 times [2021-11-09 09:35:24,113 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:24,113 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1532993781] [2021-11-09 09:35:24,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:24,113 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:24,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:24,125 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:24,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:24,126 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:24,126 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:24,126 INFO L85 PathProgramCache]: Analyzing trace with hash 754370480, now seen corresponding path program 81 times [2021-11-09 09:35:24,126 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:24,127 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1656080738] [2021-11-09 09:35:24,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:24,127 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:24,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:26,703 INFO L134 CoverageAnalysis]: Checked inductivity of 3321 backedges. 0 proven. 3321 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:26,703 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:26,703 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1656080738] [2021-11-09 09:35:26,703 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1656080738] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:26,704 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [487943201] [2021-11-09 09:35:26,704 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:35:26,704 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:35:26,704 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:35:26,705 INFO L229 MonitoredProcess]: Starting monitored process 82 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:35:26,706 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (82)] Waiting until timeout for monitored process [2021-11-09 09:35:27,879 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 42 check-sat command(s) [2021-11-09 09:35:27,879 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:35:27,881 INFO L263 TraceCheckSpWp]: Trace formula consists of 251 conjuncts, 83 conjunts are in the unsatisfiable core [2021-11-09 09:35:27,884 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:35:28,161 INFO L134 CoverageAnalysis]: Checked inductivity of 3321 backedges. 0 proven. 3321 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:28,161 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [487943201] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:28,162 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:35:28,162 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [83, 83] total 83 [2021-11-09 09:35:28,162 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1436022503] [2021-11-09 09:35:28,162 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:28,162 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:28,163 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 84 interpolants. [2021-11-09 09:35:28,163 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3486, Invalid=3486, Unknown=0, NotChecked=0, Total=6972 [2021-11-09 09:35:28,163 INFO L87 Difference]: Start difference. First operand 85 states and 86 transitions. cyclomatic complexity: 2 Second operand has 84 states, 84 states have (on average 1.0) internal successors, (84), 83 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:28,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:28,244 INFO L93 Difference]: Finished difference Result 86 states and 87 transitions. [2021-11-09 09:35:28,244 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2021-11-09 09:35:28,244 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 86 states and 87 transitions. [2021-11-09 09:35:28,245 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 85 [2021-11-09 09:35:28,245 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 86 states to 86 states and 87 transitions. [2021-11-09 09:35:28,245 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 86 [2021-11-09 09:35:28,245 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 86 [2021-11-09 09:35:28,245 INFO L73 IsDeterministic]: Start isDeterministic. Operand 86 states and 87 transitions. [2021-11-09 09:35:28,246 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:28,246 INFO L681 BuchiCegarLoop]: Abstraction has 86 states and 87 transitions. [2021-11-09 09:35:28,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86 states and 87 transitions. [2021-11-09 09:35:28,246 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86 to 86. [2021-11-09 09:35:28,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 86 states, 86 states have (on average 1.0116279069767442) internal successors, (87), 85 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:28,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 87 transitions. [2021-11-09 09:35:28,247 INFO L704 BuchiCegarLoop]: Abstraction has 86 states and 87 transitions. [2021-11-09 09:35:28,247 INFO L587 BuchiCegarLoop]: Abstraction has 86 states and 87 transitions. [2021-11-09 09:35:28,247 INFO L425 BuchiCegarLoop]: ======== Iteration 83============ [2021-11-09 09:35:28,247 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 86 states and 87 transitions. [2021-11-09 09:35:28,247 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 85 [2021-11-09 09:35:28,247 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:28,247 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:28,247 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:35:28,248 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [82, 1, 1, 1] [2021-11-09 09:35:28,248 INFO L791 eck$LassoCheckResult]: Stem: 21656#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 21653#L19-2 [2021-11-09 09:35:28,248 INFO L793 eck$LassoCheckResult]: Loop: 21653#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 21654#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21657#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21738#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21737#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21736#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21735#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21734#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21733#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21732#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21731#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21730#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21729#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21728#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21727#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21726#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21725#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21724#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21723#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21722#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21721#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21720#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21719#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21718#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21717#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21716#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21715#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21714#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21713#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21712#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21711#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21710#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21709#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21708#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21707#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21706#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21705#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21704#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21703#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21702#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21701#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21700#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21699#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21698#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21697#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21696#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21695#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21694#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21693#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21692#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21691#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21690#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21689#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21688#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21687#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21686#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21685#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21684#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21683#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21682#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21681#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21680#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21679#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21678#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21677#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21676#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21675#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21674#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21673#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21672#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21671#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21670#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21669#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21668#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21667#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21666#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21665#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21664#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21663#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21662#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21661#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21660#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21659#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 21658#L21-2 assume !(main_~x2~0 > 1); 21655#L21-3 main_~x1~0 := 1 + main_~x1~0; 21653#L19-2 [2021-11-09 09:35:28,248 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:28,248 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 83 times [2021-11-09 09:35:28,249 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:28,249 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1272390971] [2021-11-09 09:35:28,249 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:28,249 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:28,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:28,260 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:28,261 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:28,262 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:28,262 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:28,262 INFO L85 PathProgramCache]: Analyzing trace with hash 1910650159, now seen corresponding path program 82 times [2021-11-09 09:35:28,262 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:28,262 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [976629273] [2021-11-09 09:35:28,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:28,263 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:28,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:30,871 INFO L134 CoverageAnalysis]: Checked inductivity of 3403 backedges. 0 proven. 3403 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:30,871 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:30,871 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [976629273] [2021-11-09 09:35:30,871 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [976629273] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:30,871 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1877939089] [2021-11-09 09:35:30,871 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:35:30,872 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:35:30,872 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:35:30,875 INFO L229 MonitoredProcess]: Starting monitored process 83 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:35:30,876 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (83)] Waiting until timeout for monitored process [2021-11-09 09:35:32,055 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:35:32,055 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:35:32,057 INFO L263 TraceCheckSpWp]: Trace formula consists of 254 conjuncts, 84 conjunts are in the unsatisfiable core [2021-11-09 09:35:32,059 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:35:32,337 INFO L134 CoverageAnalysis]: Checked inductivity of 3403 backedges. 0 proven. 3403 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:32,338 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1877939089] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:32,338 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:35:32,338 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [84, 84] total 84 [2021-11-09 09:35:32,338 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [916797879] [2021-11-09 09:35:32,339 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:32,339 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:32,340 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2021-11-09 09:35:32,341 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3570, Invalid=3570, Unknown=0, NotChecked=0, Total=7140 [2021-11-09 09:35:32,341 INFO L87 Difference]: Start difference. First operand 86 states and 87 transitions. cyclomatic complexity: 2 Second operand has 85 states, 85 states have (on average 1.0) internal successors, (85), 84 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:32,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:32,409 INFO L93 Difference]: Finished difference Result 87 states and 88 transitions. [2021-11-09 09:35:32,410 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 85 states. [2021-11-09 09:35:32,410 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 87 states and 88 transitions. [2021-11-09 09:35:32,410 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 86 [2021-11-09 09:35:32,411 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 87 states to 87 states and 88 transitions. [2021-11-09 09:35:32,411 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 87 [2021-11-09 09:35:32,411 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 87 [2021-11-09 09:35:32,411 INFO L73 IsDeterministic]: Start isDeterministic. Operand 87 states and 88 transitions. [2021-11-09 09:35:32,411 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:32,412 INFO L681 BuchiCegarLoop]: Abstraction has 87 states and 88 transitions. [2021-11-09 09:35:32,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states and 88 transitions. [2021-11-09 09:35:32,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 87. [2021-11-09 09:35:32,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87 states, 87 states have (on average 1.0114942528735633) internal successors, (88), 86 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:32,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 88 transitions. [2021-11-09 09:35:32,414 INFO L704 BuchiCegarLoop]: Abstraction has 87 states and 88 transitions. [2021-11-09 09:35:32,414 INFO L587 BuchiCegarLoop]: Abstraction has 87 states and 88 transitions. [2021-11-09 09:35:32,414 INFO L425 BuchiCegarLoop]: ======== Iteration 84============ [2021-11-09 09:35:32,414 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 87 states and 88 transitions. [2021-11-09 09:35:32,414 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 86 [2021-11-09 09:35:32,415 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:32,415 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:32,415 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:35:32,415 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [83, 1, 1, 1] [2021-11-09 09:35:32,416 INFO L791 eck$LassoCheckResult]: Stem: 22169#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 22166#L19-2 [2021-11-09 09:35:32,416 INFO L793 eck$LassoCheckResult]: Loop: 22166#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 22167#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22170#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22252#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22251#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22250#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22249#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22248#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22247#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22246#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22245#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22244#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22243#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22242#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22241#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22240#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22239#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22238#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22237#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22236#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22235#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22234#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22233#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22232#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22231#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22230#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22229#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22228#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22227#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22226#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22225#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22224#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22223#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22222#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22221#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22220#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22219#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22218#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22217#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22216#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22215#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22214#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22213#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22212#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22211#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22210#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22209#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22208#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22207#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22206#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22205#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22204#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22203#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22202#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22201#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22200#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22199#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22198#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22197#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22196#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22195#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22194#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22193#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22192#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22191#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22190#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22189#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22188#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22187#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22186#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22185#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22184#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22183#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22182#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22181#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22180#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22179#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22178#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22177#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22176#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22175#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22174#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22173#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22172#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22171#L21-2 assume !(main_~x2~0 > 1); 22168#L21-3 main_~x1~0 := 1 + main_~x1~0; 22166#L19-2 [2021-11-09 09:35:32,416 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:32,416 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 84 times [2021-11-09 09:35:32,416 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:32,416 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [953944354] [2021-11-09 09:35:32,417 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:32,417 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:32,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:32,427 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:32,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:32,428 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:32,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:32,428 INFO L85 PathProgramCache]: Analyzing trace with hash -899385456, now seen corresponding path program 83 times [2021-11-09 09:35:32,428 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:32,428 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1165858634] [2021-11-09 09:35:32,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:32,429 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:32,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:35,090 INFO L134 CoverageAnalysis]: Checked inductivity of 3486 backedges. 0 proven. 3486 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:35,090 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:35,090 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1165858634] [2021-11-09 09:35:35,090 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1165858634] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:35,090 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1045290639] [2021-11-09 09:35:35,091 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:35:35,091 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:35:35,091 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:35:35,100 INFO L229 MonitoredProcess]: Starting monitored process 84 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:35:35,119 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (84)] Waiting until timeout for monitored process [2021-11-09 09:35:36,331 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 43 check-sat command(s) [2021-11-09 09:35:36,331 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:35:36,333 INFO L263 TraceCheckSpWp]: Trace formula consists of 257 conjuncts, 85 conjunts are in the unsatisfiable core [2021-11-09 09:35:36,334 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:35:36,560 INFO L134 CoverageAnalysis]: Checked inductivity of 3486 backedges. 0 proven. 3486 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:36,561 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1045290639] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:36,561 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:35:36,561 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [85, 85] total 85 [2021-11-09 09:35:36,561 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1124666857] [2021-11-09 09:35:36,561 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:36,561 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:36,562 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2021-11-09 09:35:36,563 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3655, Invalid=3655, Unknown=0, NotChecked=0, Total=7310 [2021-11-09 09:35:36,563 INFO L87 Difference]: Start difference. First operand 87 states and 88 transitions. cyclomatic complexity: 2 Second operand has 86 states, 86 states have (on average 1.0) internal successors, (86), 85 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:36,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:36,632 INFO L93 Difference]: Finished difference Result 88 states and 89 transitions. [2021-11-09 09:35:36,656 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 86 states. [2021-11-09 09:35:36,656 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88 states and 89 transitions. [2021-11-09 09:35:36,657 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 87 [2021-11-09 09:35:36,657 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88 states to 88 states and 89 transitions. [2021-11-09 09:35:36,657 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 88 [2021-11-09 09:35:36,658 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 88 [2021-11-09 09:35:36,658 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88 states and 89 transitions. [2021-11-09 09:35:36,658 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:36,658 INFO L681 BuchiCegarLoop]: Abstraction has 88 states and 89 transitions. [2021-11-09 09:35:36,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states and 89 transitions. [2021-11-09 09:35:36,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 88. [2021-11-09 09:35:36,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 88 states, 88 states have (on average 1.0113636363636365) internal successors, (89), 87 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:36,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 89 transitions. [2021-11-09 09:35:36,660 INFO L704 BuchiCegarLoop]: Abstraction has 88 states and 89 transitions. [2021-11-09 09:35:36,660 INFO L587 BuchiCegarLoop]: Abstraction has 88 states and 89 transitions. [2021-11-09 09:35:36,660 INFO L425 BuchiCegarLoop]: ======== Iteration 85============ [2021-11-09 09:35:36,660 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 88 states and 89 transitions. [2021-11-09 09:35:36,660 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 87 [2021-11-09 09:35:36,660 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:36,661 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:36,662 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:35:36,662 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [84, 1, 1, 1] [2021-11-09 09:35:36,663 INFO L791 eck$LassoCheckResult]: Stem: 22688#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 22685#L19-2 [2021-11-09 09:35:36,663 INFO L793 eck$LassoCheckResult]: Loop: 22685#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 22686#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22689#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22772#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22771#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22770#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22769#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22768#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22767#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22766#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22765#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22764#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22763#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22762#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22761#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22760#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22759#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22758#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22757#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22756#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22755#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22754#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22753#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22752#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22751#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22750#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22749#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22748#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22747#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22746#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22745#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22744#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22743#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22742#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22741#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22740#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22739#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22738#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22737#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22736#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22735#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22734#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22733#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22732#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22731#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22730#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22729#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22728#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22727#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22726#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22725#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22724#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22723#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22722#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22721#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22720#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22719#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22718#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22717#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22716#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22715#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22714#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22713#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22712#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22711#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22710#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22709#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22708#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22707#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22706#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22705#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22704#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22703#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22702#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22701#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22700#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22699#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22698#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22697#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22696#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22695#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22694#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22693#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22692#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22691#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 22690#L21-2 assume !(main_~x2~0 > 1); 22687#L21-3 main_~x1~0 := 1 + main_~x1~0; 22685#L19-2 [2021-11-09 09:35:36,663 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:36,663 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 85 times [2021-11-09 09:35:36,663 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:36,663 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [892948391] [2021-11-09 09:35:36,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:36,664 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:36,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:36,758 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:36,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:36,759 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:36,759 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:36,760 INFO L85 PathProgramCache]: Analyzing trace with hash -2111143601, now seen corresponding path program 84 times [2021-11-09 09:35:36,760 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:36,760 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [639463820] [2021-11-09 09:35:36,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:36,760 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:36,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:39,480 INFO L134 CoverageAnalysis]: Checked inductivity of 3570 backedges. 0 proven. 3570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:39,480 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:39,480 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [639463820] [2021-11-09 09:35:39,480 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [639463820] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:39,480 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1907658846] [2021-11-09 09:35:39,480 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:35:39,481 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:35:39,481 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:35:39,483 INFO L229 MonitoredProcess]: Starting monitored process 85 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:35:39,483 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (85)] Waiting until timeout for monitored process [2021-11-09 09:35:40,834 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 43 check-sat command(s) [2021-11-09 09:35:40,834 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:35:40,837 INFO L263 TraceCheckSpWp]: Trace formula consists of 260 conjuncts, 86 conjunts are in the unsatisfiable core [2021-11-09 09:35:40,838 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:35:41,110 INFO L134 CoverageAnalysis]: Checked inductivity of 3570 backedges. 0 proven. 3570 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:41,110 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1907658846] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:41,110 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:35:41,110 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [86, 86] total 86 [2021-11-09 09:35:41,110 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1964058424] [2021-11-09 09:35:41,111 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:41,111 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:41,111 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 87 interpolants. [2021-11-09 09:35:41,112 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3741, Invalid=3741, Unknown=0, NotChecked=0, Total=7482 [2021-11-09 09:35:41,112 INFO L87 Difference]: Start difference. First operand 88 states and 89 transitions. cyclomatic complexity: 2 Second operand has 87 states, 87 states have (on average 1.0) internal successors, (87), 86 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:41,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:41,201 INFO L93 Difference]: Finished difference Result 89 states and 90 transitions. [2021-11-09 09:35:41,202 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 87 states. [2021-11-09 09:35:41,202 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 89 states and 90 transitions. [2021-11-09 09:35:41,202 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 88 [2021-11-09 09:35:41,203 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 89 states to 89 states and 90 transitions. [2021-11-09 09:35:41,203 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 89 [2021-11-09 09:35:41,203 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 89 [2021-11-09 09:35:41,203 INFO L73 IsDeterministic]: Start isDeterministic. Operand 89 states and 90 transitions. [2021-11-09 09:35:41,204 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:41,204 INFO L681 BuchiCegarLoop]: Abstraction has 89 states and 90 transitions. [2021-11-09 09:35:41,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states and 90 transitions. [2021-11-09 09:35:41,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 89. [2021-11-09 09:35:41,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 89 states, 89 states have (on average 1.0112359550561798) internal successors, (90), 88 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:41,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 90 transitions. [2021-11-09 09:35:41,206 INFO L704 BuchiCegarLoop]: Abstraction has 89 states and 90 transitions. [2021-11-09 09:35:41,206 INFO L587 BuchiCegarLoop]: Abstraction has 89 states and 90 transitions. [2021-11-09 09:35:41,206 INFO L425 BuchiCegarLoop]: ======== Iteration 86============ [2021-11-09 09:35:41,206 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 89 states and 90 transitions. [2021-11-09 09:35:41,206 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 88 [2021-11-09 09:35:41,207 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:41,207 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:41,207 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:35:41,207 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [85, 1, 1, 1] [2021-11-09 09:35:41,207 INFO L791 eck$LassoCheckResult]: Stem: 23213#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 23210#L19-2 [2021-11-09 09:35:41,207 INFO L793 eck$LassoCheckResult]: Loop: 23210#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 23211#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23214#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23298#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23297#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23296#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23295#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23294#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23293#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23292#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23291#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23290#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23289#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23288#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23287#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23286#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23285#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23284#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23283#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23282#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23281#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23280#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23279#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23278#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23277#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23276#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23275#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23274#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23273#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23272#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23271#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23270#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23269#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23268#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23267#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23266#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23265#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23264#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23263#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23262#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23261#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23260#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23259#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23258#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23257#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23256#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23255#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23254#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23253#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23252#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23251#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23250#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23249#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23248#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23247#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23246#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23245#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23244#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23243#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23242#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23241#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23240#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23239#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23238#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23237#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23236#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23235#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23234#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23233#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23232#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23231#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23230#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23229#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23228#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23227#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23226#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23225#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23224#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23223#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23222#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23221#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23220#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23219#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23218#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23217#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23216#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23215#L21-2 assume !(main_~x2~0 > 1); 23212#L21-3 main_~x1~0 := 1 + main_~x1~0; 23210#L19-2 [2021-11-09 09:35:41,208 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:41,208 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 86 times [2021-11-09 09:35:41,208 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:41,208 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1719209025] [2021-11-09 09:35:41,208 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:41,208 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:41,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:41,222 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:41,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:41,224 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:41,224 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:41,224 INFO L85 PathProgramCache]: Analyzing trace with hash -1020940432, now seen corresponding path program 85 times [2021-11-09 09:35:41,224 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:41,224 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [450379290] [2021-11-09 09:35:41,225 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:41,225 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:41,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:44,081 INFO L134 CoverageAnalysis]: Checked inductivity of 3655 backedges. 0 proven. 3655 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:44,082 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:44,082 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [450379290] [2021-11-09 09:35:44,084 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [450379290] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:44,085 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [180072945] [2021-11-09 09:35:44,085 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:35:44,085 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:35:44,085 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:35:44,089 INFO L229 MonitoredProcess]: Starting monitored process 86 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:35:44,108 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (86)] Waiting until timeout for monitored process [2021-11-09 09:35:45,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:45,432 INFO L263 TraceCheckSpWp]: Trace formula consists of 263 conjuncts, 87 conjunts are in the unsatisfiable core [2021-11-09 09:35:45,433 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:35:45,671 INFO L134 CoverageAnalysis]: Checked inductivity of 3655 backedges. 0 proven. 3655 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:45,672 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [180072945] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:45,672 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:35:45,672 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [87, 87] total 87 [2021-11-09 09:35:45,672 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1909553246] [2021-11-09 09:35:45,672 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:45,673 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:45,674 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 88 interpolants. [2021-11-09 09:35:45,674 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3828, Invalid=3828, Unknown=0, NotChecked=0, Total=7656 [2021-11-09 09:35:45,674 INFO L87 Difference]: Start difference. First operand 89 states and 90 transitions. cyclomatic complexity: 2 Second operand has 88 states, 88 states have (on average 1.0) internal successors, (88), 87 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:45,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:45,755 INFO L93 Difference]: Finished difference Result 90 states and 91 transitions. [2021-11-09 09:35:45,755 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 88 states. [2021-11-09 09:35:45,756 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 90 states and 91 transitions. [2021-11-09 09:35:45,756 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 89 [2021-11-09 09:35:45,757 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 90 states to 90 states and 91 transitions. [2021-11-09 09:35:45,757 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 90 [2021-11-09 09:35:45,757 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 90 [2021-11-09 09:35:45,757 INFO L73 IsDeterministic]: Start isDeterministic. Operand 90 states and 91 transitions. [2021-11-09 09:35:45,758 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:45,758 INFO L681 BuchiCegarLoop]: Abstraction has 90 states and 91 transitions. [2021-11-09 09:35:45,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states and 91 transitions. [2021-11-09 09:35:45,759 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 90. [2021-11-09 09:35:45,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 90 states, 90 states have (on average 1.011111111111111) internal successors, (91), 89 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:45,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 91 transitions. [2021-11-09 09:35:45,760 INFO L704 BuchiCegarLoop]: Abstraction has 90 states and 91 transitions. [2021-11-09 09:35:45,760 INFO L587 BuchiCegarLoop]: Abstraction has 90 states and 91 transitions. [2021-11-09 09:35:45,760 INFO L425 BuchiCegarLoop]: ======== Iteration 87============ [2021-11-09 09:35:45,761 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90 states and 91 transitions. [2021-11-09 09:35:45,761 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 89 [2021-11-09 09:35:45,761 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:45,761 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:45,762 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:35:45,762 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [86, 1, 1, 1] [2021-11-09 09:35:45,762 INFO L791 eck$LassoCheckResult]: Stem: 23744#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 23741#L19-2 [2021-11-09 09:35:45,762 INFO L793 eck$LassoCheckResult]: Loop: 23741#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 23742#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23745#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23830#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23829#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23828#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23827#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23826#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23825#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23824#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23823#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23822#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23821#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23820#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23819#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23818#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23817#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23816#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23815#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23814#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23813#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23812#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23811#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23810#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23809#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23808#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23807#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23806#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23805#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23804#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23803#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23802#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23801#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23800#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23799#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23798#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23797#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23796#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23795#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23794#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23793#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23792#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23791#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23790#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23789#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23788#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23787#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23786#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23785#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23784#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23783#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23782#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23781#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23780#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23779#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23778#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23777#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23776#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23775#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23774#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23773#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23772#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23771#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23770#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23769#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23768#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23767#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23766#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23765#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23764#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23763#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23762#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23761#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23760#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23759#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23758#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23757#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23756#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23755#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23754#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23753#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23752#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23751#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23750#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23749#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23748#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23747#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 23746#L21-2 assume !(main_~x2~0 > 1); 23743#L21-3 main_~x1~0 := 1 + main_~x1~0; 23741#L19-2 [2021-11-09 09:35:45,763 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:45,763 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 87 times [2021-11-09 09:35:45,763 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:45,763 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [900161127] [2021-11-09 09:35:45,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:45,764 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:45,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:45,775 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:45,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:45,776 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:45,776 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:45,776 INFO L85 PathProgramCache]: Analyzing trace with hash -1584380561, now seen corresponding path program 86 times [2021-11-09 09:35:45,776 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:45,776 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [84637250] [2021-11-09 09:35:45,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:45,776 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:45,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:48,523 INFO L134 CoverageAnalysis]: Checked inductivity of 3741 backedges. 0 proven. 3741 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:48,523 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:48,523 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [84637250] [2021-11-09 09:35:48,523 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [84637250] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:48,523 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [211203400] [2021-11-09 09:35:48,523 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:35:48,523 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:35:48,523 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:35:48,524 INFO L229 MonitoredProcess]: Starting monitored process 87 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:35:48,526 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (87)] Waiting until timeout for monitored process [2021-11-09 09:35:49,829 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:35:49,829 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:35:49,831 INFO L263 TraceCheckSpWp]: Trace formula consists of 266 conjuncts, 88 conjunts are in the unsatisfiable core [2021-11-09 09:35:49,833 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:35:50,062 INFO L134 CoverageAnalysis]: Checked inductivity of 3741 backedges. 0 proven. 3741 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:50,063 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [211203400] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:50,063 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:35:50,063 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [88, 88] total 88 [2021-11-09 09:35:50,063 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [465672210] [2021-11-09 09:35:50,063 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:50,063 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:50,064 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 89 interpolants. [2021-11-09 09:35:50,064 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3916, Invalid=3916, Unknown=0, NotChecked=0, Total=7832 [2021-11-09 09:35:50,064 INFO L87 Difference]: Start difference. First operand 90 states and 91 transitions. cyclomatic complexity: 2 Second operand has 89 states, 89 states have (on average 1.0) internal successors, (89), 88 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:50,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:50,136 INFO L93 Difference]: Finished difference Result 91 states and 92 transitions. [2021-11-09 09:35:50,137 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2021-11-09 09:35:50,137 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91 states and 92 transitions. [2021-11-09 09:35:50,138 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 90 [2021-11-09 09:35:50,138 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91 states to 91 states and 92 transitions. [2021-11-09 09:35:50,138 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 91 [2021-11-09 09:35:50,138 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 91 [2021-11-09 09:35:50,138 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91 states and 92 transitions. [2021-11-09 09:35:50,139 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:50,139 INFO L681 BuchiCegarLoop]: Abstraction has 91 states and 92 transitions. [2021-11-09 09:35:50,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states and 92 transitions. [2021-11-09 09:35:50,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 91. [2021-11-09 09:35:50,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91 states, 91 states have (on average 1.010989010989011) internal successors, (92), 90 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:50,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 92 transitions. [2021-11-09 09:35:50,140 INFO L704 BuchiCegarLoop]: Abstraction has 91 states and 92 transitions. [2021-11-09 09:35:50,140 INFO L587 BuchiCegarLoop]: Abstraction has 91 states and 92 transitions. [2021-11-09 09:35:50,140 INFO L425 BuchiCegarLoop]: ======== Iteration 88============ [2021-11-09 09:35:50,140 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 91 states and 92 transitions. [2021-11-09 09:35:50,141 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 90 [2021-11-09 09:35:50,141 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:50,141 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:50,141 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:35:50,141 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [87, 1, 1, 1] [2021-11-09 09:35:50,141 INFO L791 eck$LassoCheckResult]: Stem: 24281#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 24278#L19-2 [2021-11-09 09:35:50,141 INFO L793 eck$LassoCheckResult]: Loop: 24278#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 24279#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24282#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24368#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24367#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24366#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24365#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24364#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24363#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24362#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24361#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24360#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24359#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24358#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24357#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24356#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24355#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24354#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24353#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24352#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24351#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24350#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24349#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24348#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24347#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24346#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24345#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24344#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24343#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24342#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24341#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24340#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24339#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24338#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24337#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24336#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24335#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24334#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24333#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24332#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24331#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24330#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24329#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24328#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24327#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24326#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24325#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24324#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24323#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24322#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24321#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24320#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24319#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24318#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24317#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24316#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24315#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24314#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24313#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24312#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24311#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24310#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24309#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24308#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24307#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24306#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24305#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24304#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24303#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24302#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24301#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24300#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24299#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24298#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24297#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24296#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24295#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24294#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24293#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24292#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24291#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24290#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24289#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24288#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24287#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24286#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24285#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24284#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24283#L21-2 assume !(main_~x2~0 > 1); 24280#L21-3 main_~x1~0 := 1 + main_~x1~0; 24278#L19-2 [2021-11-09 09:35:50,142 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:50,142 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 88 times [2021-11-09 09:35:50,142 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:50,142 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1950190796] [2021-11-09 09:35:50,142 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:50,142 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:50,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:50,154 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:50,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:50,154 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:50,155 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:50,155 INFO L85 PathProgramCache]: Analyzing trace with hash -1871155376, now seen corresponding path program 87 times [2021-11-09 09:35:50,155 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:50,155 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1718748373] [2021-11-09 09:35:50,155 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:50,155 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:50,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:53,049 INFO L134 CoverageAnalysis]: Checked inductivity of 3828 backedges. 0 proven. 3828 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:53,050 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:53,050 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1718748373] [2021-11-09 09:35:53,050 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1718748373] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:53,050 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [57064678] [2021-11-09 09:35:53,050 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:35:53,050 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:35:53,050 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:35:53,052 INFO L229 MonitoredProcess]: Starting monitored process 88 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:35:53,052 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (88)] Waiting until timeout for monitored process [2021-11-09 09:35:54,396 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 45 check-sat command(s) [2021-11-09 09:35:54,397 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:35:54,399 INFO L263 TraceCheckSpWp]: Trace formula consists of 269 conjuncts, 89 conjunts are in the unsatisfiable core [2021-11-09 09:35:54,400 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:35:54,633 INFO L134 CoverageAnalysis]: Checked inductivity of 3828 backedges. 0 proven. 3828 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:54,633 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [57064678] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:54,633 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:35:54,633 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [89, 89] total 89 [2021-11-09 09:35:54,633 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [155552155] [2021-11-09 09:35:54,634 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:54,634 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:54,634 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 90 interpolants. [2021-11-09 09:35:54,635 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4005, Invalid=4005, Unknown=0, NotChecked=0, Total=8010 [2021-11-09 09:35:54,635 INFO L87 Difference]: Start difference. First operand 91 states and 92 transitions. cyclomatic complexity: 2 Second operand has 90 states, 90 states have (on average 1.0) internal successors, (90), 89 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:54,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:54,722 INFO L93 Difference]: Finished difference Result 92 states and 93 transitions. [2021-11-09 09:35:54,722 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 90 states. [2021-11-09 09:35:54,722 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 92 states and 93 transitions. [2021-11-09 09:35:54,723 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 91 [2021-11-09 09:35:54,723 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 92 states to 92 states and 93 transitions. [2021-11-09 09:35:54,723 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 92 [2021-11-09 09:35:54,723 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 92 [2021-11-09 09:35:54,723 INFO L73 IsDeterministic]: Start isDeterministic. Operand 92 states and 93 transitions. [2021-11-09 09:35:54,723 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:54,723 INFO L681 BuchiCegarLoop]: Abstraction has 92 states and 93 transitions. [2021-11-09 09:35:54,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92 states and 93 transitions. [2021-11-09 09:35:54,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92 to 92. [2021-11-09 09:35:54,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 92 states, 92 states have (on average 1.0108695652173914) internal successors, (93), 91 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:54,729 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 93 transitions. [2021-11-09 09:35:54,729 INFO L704 BuchiCegarLoop]: Abstraction has 92 states and 93 transitions. [2021-11-09 09:35:54,729 INFO L587 BuchiCegarLoop]: Abstraction has 92 states and 93 transitions. [2021-11-09 09:35:54,729 INFO L425 BuchiCegarLoop]: ======== Iteration 89============ [2021-11-09 09:35:54,730 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 92 states and 93 transitions. [2021-11-09 09:35:54,730 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 91 [2021-11-09 09:35:54,730 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:54,730 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:54,731 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:35:54,731 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [88, 1, 1, 1] [2021-11-09 09:35:54,731 INFO L791 eck$LassoCheckResult]: Stem: 24824#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 24821#L19-2 [2021-11-09 09:35:54,732 INFO L793 eck$LassoCheckResult]: Loop: 24821#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 24822#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24825#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24912#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24911#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24910#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24909#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24908#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24907#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24906#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24905#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24904#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24903#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24902#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24901#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24900#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24899#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24898#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24897#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24896#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24895#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24894#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24893#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24892#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24891#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24890#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24889#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24888#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24887#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24886#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24885#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24884#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24883#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24882#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24881#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24880#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24879#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24878#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24877#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24876#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24875#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24874#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24873#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24872#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24871#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24870#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24869#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24868#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24867#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24866#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24865#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24864#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24863#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24862#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24861#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24860#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24859#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24858#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24857#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24856#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24855#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24854#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24853#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24852#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24851#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24850#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24849#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24848#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24847#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24846#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24845#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24844#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24843#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24842#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24841#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24840#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24839#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24838#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24837#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24836#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24835#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24834#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24833#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24832#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24831#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24830#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24829#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24828#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24827#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 24826#L21-2 assume !(main_~x2~0 > 1); 24823#L21-3 main_~x1~0 := 1 + main_~x1~0; 24821#L19-2 [2021-11-09 09:35:54,732 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:54,732 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 89 times [2021-11-09 09:35:54,732 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:54,732 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [189685517] [2021-11-09 09:35:54,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:54,733 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:54,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:54,744 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:54,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:54,745 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:54,745 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:54,746 INFO L85 PathProgramCache]: Analyzing trace with hash 2123727247, now seen corresponding path program 88 times [2021-11-09 09:35:54,746 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:54,746 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1241898206] [2021-11-09 09:35:54,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:54,746 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:54,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:57,602 INFO L134 CoverageAnalysis]: Checked inductivity of 3916 backedges. 0 proven. 3916 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:57,602 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:57,602 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1241898206] [2021-11-09 09:35:57,602 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1241898206] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:57,602 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [103896857] [2021-11-09 09:35:57,602 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:35:57,603 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:35:57,603 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:35:57,604 INFO L229 MonitoredProcess]: Starting monitored process 89 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:35:57,605 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (89)] Waiting until timeout for monitored process [2021-11-09 09:35:59,041 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:35:59,042 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:35:59,044 INFO L263 TraceCheckSpWp]: Trace formula consists of 272 conjuncts, 90 conjunts are in the unsatisfiable core [2021-11-09 09:35:59,046 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:35:59,364 INFO L134 CoverageAnalysis]: Checked inductivity of 3916 backedges. 0 proven. 3916 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:59,365 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [103896857] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:35:59,365 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:35:59,365 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [90, 90] total 90 [2021-11-09 09:35:59,365 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1965314339] [2021-11-09 09:35:59,365 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:59,365 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:59,366 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2021-11-09 09:35:59,366 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4095, Invalid=4095, Unknown=0, NotChecked=0, Total=8190 [2021-11-09 09:35:59,367 INFO L87 Difference]: Start difference. First operand 92 states and 93 transitions. cyclomatic complexity: 2 Second operand has 91 states, 91 states have (on average 1.0) internal successors, (91), 90 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:59,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:59,461 INFO L93 Difference]: Finished difference Result 93 states and 94 transitions. [2021-11-09 09:35:59,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 91 states. [2021-11-09 09:35:59,461 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 93 states and 94 transitions. [2021-11-09 09:35:59,461 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 92 [2021-11-09 09:35:59,462 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 93 states to 93 states and 94 transitions. [2021-11-09 09:35:59,462 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 93 [2021-11-09 09:35:59,462 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 93 [2021-11-09 09:35:59,462 INFO L73 IsDeterministic]: Start isDeterministic. Operand 93 states and 94 transitions. [2021-11-09 09:35:59,463 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:59,463 INFO L681 BuchiCegarLoop]: Abstraction has 93 states and 94 transitions. [2021-11-09 09:35:59,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states and 94 transitions. [2021-11-09 09:35:59,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 93. [2021-11-09 09:35:59,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 93 states, 93 states have (on average 1.010752688172043) internal successors, (94), 92 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:59,464 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 94 transitions. [2021-11-09 09:35:59,464 INFO L704 BuchiCegarLoop]: Abstraction has 93 states and 94 transitions. [2021-11-09 09:35:59,464 INFO L587 BuchiCegarLoop]: Abstraction has 93 states and 94 transitions. [2021-11-09 09:35:59,464 INFO L425 BuchiCegarLoop]: ======== Iteration 90============ [2021-11-09 09:35:59,464 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 93 states and 94 transitions. [2021-11-09 09:35:59,465 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 92 [2021-11-09 09:35:59,465 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:59,465 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:59,465 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:35:59,465 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [89, 1, 1, 1] [2021-11-09 09:35:59,465 INFO L791 eck$LassoCheckResult]: Stem: 25373#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 25370#L19-2 [2021-11-09 09:35:59,465 INFO L793 eck$LassoCheckResult]: Loop: 25370#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 25371#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25374#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25462#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25461#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25460#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25459#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25458#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25457#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25456#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25455#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25454#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25453#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25452#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25451#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25450#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25449#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25448#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25447#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25446#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25445#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25444#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25443#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25442#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25441#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25440#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25439#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25438#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25437#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25436#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25435#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25434#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25433#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25432#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25431#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25430#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25429#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25428#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25427#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25426#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25425#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25424#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25423#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25422#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25421#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25420#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25419#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25418#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25417#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25416#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25415#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25414#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25413#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25412#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25411#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25410#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25409#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25408#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25407#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25406#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25405#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25404#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25403#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25402#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25401#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25400#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25399#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25398#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25397#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25396#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25395#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25394#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25393#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25392#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25391#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25390#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25389#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25388#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25387#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25386#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25385#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25384#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25383#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25382#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25381#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25380#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25379#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25378#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25377#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25376#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25375#L21-2 assume !(main_~x2~0 > 1); 25372#L21-3 main_~x1~0 := 1 + main_~x1~0; 25370#L19-2 [2021-11-09 09:35:59,466 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:59,466 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 90 times [2021-11-09 09:35:59,466 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:59,466 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [586751755] [2021-11-09 09:35:59,466 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:59,466 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:59,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:59,478 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:59,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:59,479 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:59,479 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:59,479 INFO L85 PathProgramCache]: Analyzing trace with hash 1411036976, now seen corresponding path program 89 times [2021-11-09 09:35:59,479 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:59,479 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2116966932] [2021-11-09 09:35:59,479 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:59,479 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:59,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:36:02,993 INFO L134 CoverageAnalysis]: Checked inductivity of 4005 backedges. 0 proven. 4005 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:36:02,993 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:36:02,993 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2116966932] [2021-11-09 09:36:02,993 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2116966932] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:36:02,994 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [312412906] [2021-11-09 09:36:02,994 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:36:02,994 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:36:02,994 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:36:03,000 INFO L229 MonitoredProcess]: Starting monitored process 90 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:36:03,016 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (90)] Waiting until timeout for monitored process [2021-11-09 09:36:04,833 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 46 check-sat command(s) [2021-11-09 09:36:04,833 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:36:04,836 INFO L263 TraceCheckSpWp]: Trace formula consists of 275 conjuncts, 91 conjunts are in the unsatisfiable core [2021-11-09 09:36:04,837 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:36:05,087 INFO L134 CoverageAnalysis]: Checked inductivity of 4005 backedges. 0 proven. 4005 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:36:05,087 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [312412906] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:36:05,087 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:36:05,087 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [91, 91] total 91 [2021-11-09 09:36:05,087 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [99165665] [2021-11-09 09:36:05,088 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:36:05,088 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:36:05,088 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 92 interpolants. [2021-11-09 09:36:05,089 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4186, Invalid=4186, Unknown=0, NotChecked=0, Total=8372 [2021-11-09 09:36:05,089 INFO L87 Difference]: Start difference. First operand 93 states and 94 transitions. cyclomatic complexity: 2 Second operand has 92 states, 92 states have (on average 1.0) internal successors, (92), 91 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:36:05,165 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:36:05,165 INFO L93 Difference]: Finished difference Result 94 states and 95 transitions. [2021-11-09 09:36:05,165 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 92 states. [2021-11-09 09:36:05,165 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 94 states and 95 transitions. [2021-11-09 09:36:05,165 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 93 [2021-11-09 09:36:05,166 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 94 states to 94 states and 95 transitions. [2021-11-09 09:36:05,166 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 94 [2021-11-09 09:36:05,166 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 94 [2021-11-09 09:36:05,166 INFO L73 IsDeterministic]: Start isDeterministic. Operand 94 states and 95 transitions. [2021-11-09 09:36:05,166 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:36:05,166 INFO L681 BuchiCegarLoop]: Abstraction has 94 states and 95 transitions. [2021-11-09 09:36:05,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states and 95 transitions. [2021-11-09 09:36:05,167 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 94. [2021-11-09 09:36:05,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 94 states, 94 states have (on average 1.0106382978723405) internal successors, (95), 93 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:36:05,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 95 transitions. [2021-11-09 09:36:05,168 INFO L704 BuchiCegarLoop]: Abstraction has 94 states and 95 transitions. [2021-11-09 09:36:05,168 INFO L587 BuchiCegarLoop]: Abstraction has 94 states and 95 transitions. [2021-11-09 09:36:05,168 INFO L425 BuchiCegarLoop]: ======== Iteration 91============ [2021-11-09 09:36:05,168 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 94 states and 95 transitions. [2021-11-09 09:36:05,168 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 93 [2021-11-09 09:36:05,168 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:36:05,168 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:36:05,168 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:36:05,168 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [90, 1, 1, 1] [2021-11-09 09:36:05,169 INFO L791 eck$LassoCheckResult]: Stem: 25928#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 25925#L19-2 [2021-11-09 09:36:05,169 INFO L793 eck$LassoCheckResult]: Loop: 25925#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 25926#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25929#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26018#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26017#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26016#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26015#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26014#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26013#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26012#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26011#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26010#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26009#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26008#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26007#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26006#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26005#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26004#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26003#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26002#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26001#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26000#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25999#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25998#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25997#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25996#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25995#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25994#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25993#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25992#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25991#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25990#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25989#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25988#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25987#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25986#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25985#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25984#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25983#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25982#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25981#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25980#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25979#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25978#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25977#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25976#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25975#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25974#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25973#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25972#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25971#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25970#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25969#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25968#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25967#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25966#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25965#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25964#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25963#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25962#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25961#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25960#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25959#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25958#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25957#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25956#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25955#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25954#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25953#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25952#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25951#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25950#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25949#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25948#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25947#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25946#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25945#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25944#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25943#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25942#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25941#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25940#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25939#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25938#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25937#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25936#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25935#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25934#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25933#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25932#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25931#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 25930#L21-2 assume !(main_~x2~0 > 1); 25927#L21-3 main_~x1~0 := 1 + main_~x1~0; 25925#L19-2 [2021-11-09 09:36:05,169 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:36:05,169 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 91 times [2021-11-09 09:36:05,169 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:36:05,169 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1459889573] [2021-11-09 09:36:05,169 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:36:05,169 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:36:05,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:36:05,179 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:36:05,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:36:05,180 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:36:05,180 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:36:05,180 INFO L85 PathProgramCache]: Analyzing trace with hash 792475055, now seen corresponding path program 90 times [2021-11-09 09:36:05,180 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:36:05,181 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1628217268] [2021-11-09 09:36:05,181 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:36:05,181 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:36:05,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:36:08,177 INFO L134 CoverageAnalysis]: Checked inductivity of 4095 backedges. 0 proven. 4095 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:36:08,177 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:36:08,177 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1628217268] [2021-11-09 09:36:08,177 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1628217268] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:36:08,177 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1020941422] [2021-11-09 09:36:08,177 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:36:08,178 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:36:08,178 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:36:08,179 INFO L229 MonitoredProcess]: Starting monitored process 91 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:36:08,180 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (91)] Waiting until timeout for monitored process [2021-11-09 09:36:09,646 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 46 check-sat command(s) [2021-11-09 09:36:09,647 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:36:09,649 INFO L263 TraceCheckSpWp]: Trace formula consists of 278 conjuncts, 92 conjunts are in the unsatisfiable core [2021-11-09 09:36:09,651 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:36:09,902 INFO L134 CoverageAnalysis]: Checked inductivity of 4095 backedges. 0 proven. 4095 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:36:09,902 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1020941422] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:36:09,902 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:36:09,903 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [92, 92] total 92 [2021-11-09 09:36:09,903 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1998503581] [2021-11-09 09:36:09,903 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:36:09,903 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:36:09,904 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 93 interpolants. [2021-11-09 09:36:09,905 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4278, Invalid=4278, Unknown=0, NotChecked=0, Total=8556 [2021-11-09 09:36:09,905 INFO L87 Difference]: Start difference. First operand 94 states and 95 transitions. cyclomatic complexity: 2 Second operand has 93 states, 93 states have (on average 1.0) internal successors, (93), 92 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:36:10,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:36:10,014 INFO L93 Difference]: Finished difference Result 95 states and 96 transitions. [2021-11-09 09:36:10,014 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 93 states. [2021-11-09 09:36:10,015 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 95 states and 96 transitions. [2021-11-09 09:36:10,015 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 94 [2021-11-09 09:36:10,016 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 95 states to 95 states and 96 transitions. [2021-11-09 09:36:10,016 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 95 [2021-11-09 09:36:10,016 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 95 [2021-11-09 09:36:10,016 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95 states and 96 transitions. [2021-11-09 09:36:10,016 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:36:10,016 INFO L681 BuchiCegarLoop]: Abstraction has 95 states and 96 transitions. [2021-11-09 09:36:10,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states and 96 transitions. [2021-11-09 09:36:10,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 95. [2021-11-09 09:36:10,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95 states, 95 states have (on average 1.0105263157894737) internal successors, (96), 94 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:36:10,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 96 transitions. [2021-11-09 09:36:10,018 INFO L704 BuchiCegarLoop]: Abstraction has 95 states and 96 transitions. [2021-11-09 09:36:10,019 INFO L587 BuchiCegarLoop]: Abstraction has 95 states and 96 transitions. [2021-11-09 09:36:10,019 INFO L425 BuchiCegarLoop]: ======== Iteration 92============ [2021-11-09 09:36:10,019 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95 states and 96 transitions. [2021-11-09 09:36:10,020 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 94 [2021-11-09 09:36:10,020 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:36:10,020 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:36:10,020 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:36:10,021 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [91, 1, 1, 1] [2021-11-09 09:36:10,021 INFO L791 eck$LassoCheckResult]: Stem: 26489#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 26486#L19-2 [2021-11-09 09:36:10,021 INFO L793 eck$LassoCheckResult]: Loop: 26486#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 26487#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26490#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26580#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26579#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26578#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26577#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26576#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26575#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26574#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26573#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26572#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26571#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26570#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26569#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26568#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26567#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26566#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26565#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26564#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26563#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26562#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26561#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26560#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26559#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26558#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26557#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26556#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26555#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26554#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26553#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26552#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26551#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26550#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26549#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26548#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26547#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26546#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26545#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26544#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26543#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26542#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26541#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26540#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26539#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26538#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26537#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26536#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26535#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26534#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26533#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26532#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26531#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26530#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26529#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26528#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26527#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26526#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26525#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26524#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26523#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26522#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26521#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26520#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26519#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26518#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26517#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26516#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26515#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26514#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26513#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26512#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26511#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26510#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26509#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26508#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26507#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26506#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26505#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26504#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26503#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26502#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26501#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26500#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26499#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26498#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26497#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26496#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26495#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26494#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26493#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26492#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 26491#L21-2 assume !(main_~x2~0 > 1); 26488#L21-3 main_~x1~0 := 1 + main_~x1~0; 26486#L19-2 [2021-11-09 09:36:10,021 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:36:10,021 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 92 times [2021-11-09 09:36:10,021 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:36:10,022 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1437069311] [2021-11-09 09:36:10,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:36:10,023 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:36:10,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:36:10,037 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:36:10,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:36:10,038 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:36:10,038 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:36:10,038 INFO L85 PathProgramCache]: Analyzing trace with hash -1203075312, now seen corresponding path program 91 times [2021-11-09 09:36:10,038 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:36:10,038 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [393549579] [2021-11-09 09:36:10,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:36:10,039 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:36:10,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:36:13,311 INFO L134 CoverageAnalysis]: Checked inductivity of 4186 backedges. 0 proven. 4186 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:36:13,311 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:36:13,311 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [393549579] [2021-11-09 09:36:13,311 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [393549579] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:36:13,311 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [408602385] [2021-11-09 09:36:13,311 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:36:13,311 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:36:13,312 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:36:13,313 INFO L229 MonitoredProcess]: Starting monitored process 92 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:36:13,314 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (92)] Waiting until timeout for monitored process [2021-11-09 09:36:14,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:36:14,777 INFO L263 TraceCheckSpWp]: Trace formula consists of 281 conjuncts, 93 conjunts are in the unsatisfiable core [2021-11-09 09:36:14,779 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:36:15,061 INFO L134 CoverageAnalysis]: Checked inductivity of 4186 backedges. 0 proven. 4186 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:36:15,061 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [408602385] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:36:15,061 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:36:15,061 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [93, 93] total 93 [2021-11-09 09:36:15,062 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [276988789] [2021-11-09 09:36:15,062 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:36:15,062 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:36:15,063 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 94 interpolants. [2021-11-09 09:36:15,063 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4371, Invalid=4371, Unknown=0, NotChecked=0, Total=8742 [2021-11-09 09:36:15,063 INFO L87 Difference]: Start difference. First operand 95 states and 96 transitions. cyclomatic complexity: 2 Second operand has 94 states, 94 states have (on average 1.0) internal successors, (94), 93 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:36:15,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:36:15,139 INFO L93 Difference]: Finished difference Result 96 states and 97 transitions. [2021-11-09 09:36:15,140 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2021-11-09 09:36:15,140 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 96 states and 97 transitions. [2021-11-09 09:36:15,140 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 95 [2021-11-09 09:36:15,141 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 96 states to 96 states and 97 transitions. [2021-11-09 09:36:15,141 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 96 [2021-11-09 09:36:15,141 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 96 [2021-11-09 09:36:15,141 INFO L73 IsDeterministic]: Start isDeterministic. Operand 96 states and 97 transitions. [2021-11-09 09:36:15,142 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:36:15,142 INFO L681 BuchiCegarLoop]: Abstraction has 96 states and 97 transitions. [2021-11-09 09:36:15,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states and 97 transitions. [2021-11-09 09:36:15,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 96. [2021-11-09 09:36:15,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 96 states, 96 states have (on average 1.0104166666666667) internal successors, (97), 95 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:36:15,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96 states to 96 states and 97 transitions. [2021-11-09 09:36:15,144 INFO L704 BuchiCegarLoop]: Abstraction has 96 states and 97 transitions. [2021-11-09 09:36:15,144 INFO L587 BuchiCegarLoop]: Abstraction has 96 states and 97 transitions. [2021-11-09 09:36:15,144 INFO L425 BuchiCegarLoop]: ======== Iteration 93============ [2021-11-09 09:36:15,144 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 96 states and 97 transitions. [2021-11-09 09:36:15,144 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 95 [2021-11-09 09:36:15,145 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:36:15,145 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:36:15,145 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:36:15,145 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [92, 1, 1, 1] [2021-11-09 09:36:15,145 INFO L791 eck$LassoCheckResult]: Stem: 27056#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 27053#L19-2 [2021-11-09 09:36:15,146 INFO L793 eck$LassoCheckResult]: Loop: 27053#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 27054#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27057#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27148#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27147#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27146#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27145#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27144#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27143#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27142#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27141#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27140#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27139#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27138#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27137#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27136#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27135#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27134#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27133#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27132#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27131#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27130#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27129#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27128#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27127#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27126#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27125#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27124#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27123#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27122#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27121#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27120#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27119#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27118#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27117#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27116#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27115#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27114#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27113#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27112#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27111#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27110#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27109#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27108#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27107#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27106#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27105#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27104#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27103#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27102#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27101#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27100#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27099#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27098#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27097#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27096#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27095#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27094#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27093#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27092#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27091#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27090#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27089#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27088#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27087#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27086#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27085#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27084#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27083#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27082#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27081#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27080#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27079#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27078#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27077#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27076#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27075#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27074#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27073#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27072#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27071#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27070#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27069#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27068#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27067#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27066#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27065#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27064#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27063#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27062#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27061#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27060#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27059#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27058#L21-2 assume !(main_~x2~0 > 1); 27055#L21-3 main_~x1~0 := 1 + main_~x1~0; 27053#L19-2 [2021-11-09 09:36:15,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:36:15,146 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 93 times [2021-11-09 09:36:15,146 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:36:15,146 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1103488444] [2021-11-09 09:36:15,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:36:15,147 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:36:15,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:36:15,160 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:36:15,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:36:15,161 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:36:15,161 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:36:15,162 INFO L85 PathProgramCache]: Analyzing trace with hash 1359372751, now seen corresponding path program 92 times [2021-11-09 09:36:15,162 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:36:15,162 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1592260993] [2021-11-09 09:36:15,162 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:36:15,162 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:36:15,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:36:18,450 INFO L134 CoverageAnalysis]: Checked inductivity of 4278 backedges. 0 proven. 4278 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:36:18,451 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:36:18,451 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1592260993] [2021-11-09 09:36:18,451 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1592260993] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:36:18,451 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [440544499] [2021-11-09 09:36:18,451 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:36:18,451 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:36:18,451 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:36:18,453 INFO L229 MonitoredProcess]: Starting monitored process 93 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:36:18,454 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (93)] Waiting until timeout for monitored process [2021-11-09 09:36:20,013 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:36:20,013 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:36:20,016 INFO L263 TraceCheckSpWp]: Trace formula consists of 284 conjuncts, 94 conjunts are in the unsatisfiable core [2021-11-09 09:36:20,019 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:36:20,283 INFO L134 CoverageAnalysis]: Checked inductivity of 4278 backedges. 0 proven. 4278 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:36:20,283 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [440544499] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:36:20,283 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:36:20,283 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [94, 94] total 94 [2021-11-09 09:36:20,283 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1857022472] [2021-11-09 09:36:20,284 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:36:20,284 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:36:20,285 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 95 interpolants. [2021-11-09 09:36:20,286 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4465, Invalid=4465, Unknown=0, NotChecked=0, Total=8930 [2021-11-09 09:36:20,286 INFO L87 Difference]: Start difference. First operand 96 states and 97 transitions. cyclomatic complexity: 2 Second operand has 95 states, 95 states have (on average 1.0) internal successors, (95), 94 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:36:20,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:36:20,404 INFO L93 Difference]: Finished difference Result 97 states and 98 transitions. [2021-11-09 09:36:20,404 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 95 states. [2021-11-09 09:36:20,404 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97 states and 98 transitions. [2021-11-09 09:36:20,405 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 96 [2021-11-09 09:36:20,406 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97 states to 97 states and 98 transitions. [2021-11-09 09:36:20,406 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97 [2021-11-09 09:36:20,406 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97 [2021-11-09 09:36:20,406 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97 states and 98 transitions. [2021-11-09 09:36:20,406 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:36:20,407 INFO L681 BuchiCegarLoop]: Abstraction has 97 states and 98 transitions. [2021-11-09 09:36:20,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states and 98 transitions. [2021-11-09 09:36:20,408 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 97. [2021-11-09 09:36:20,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97 states, 97 states have (on average 1.0103092783505154) internal successors, (98), 96 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:36:20,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 98 transitions. [2021-11-09 09:36:20,409 INFO L704 BuchiCegarLoop]: Abstraction has 97 states and 98 transitions. [2021-11-09 09:36:20,409 INFO L587 BuchiCegarLoop]: Abstraction has 97 states and 98 transitions. [2021-11-09 09:36:20,409 INFO L425 BuchiCegarLoop]: ======== Iteration 94============ [2021-11-09 09:36:20,409 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97 states and 98 transitions. [2021-11-09 09:36:20,409 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 96 [2021-11-09 09:36:20,410 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:36:20,410 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:36:20,410 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:36:20,410 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [93, 1, 1, 1] [2021-11-09 09:36:20,410 INFO L791 eck$LassoCheckResult]: Stem: 27629#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 27626#L19-2 [2021-11-09 09:36:20,411 INFO L793 eck$LassoCheckResult]: Loop: 27626#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 27627#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27630#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27722#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27721#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27720#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27719#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27718#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27717#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27716#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27715#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27714#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27713#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27712#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27711#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27710#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27709#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27708#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27707#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27706#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27705#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27704#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27703#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27702#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27701#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27700#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27699#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27698#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27697#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27696#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27695#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27694#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27693#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27692#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27691#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27690#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27689#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27688#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27687#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27686#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27685#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27684#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27683#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27682#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27681#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27680#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27679#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27678#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27677#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27676#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27675#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27674#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27673#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27672#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27671#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27670#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27669#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27668#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27667#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27666#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27665#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27664#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27663#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27662#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27661#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27660#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27659#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27658#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27657#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27656#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27655#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27654#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27653#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27652#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27651#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27650#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27649#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27648#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27647#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27646#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27645#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27644#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27643#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27642#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27641#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27640#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27639#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27638#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27637#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27636#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27635#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27634#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27633#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27632#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 27631#L21-2 assume !(main_~x2~0 > 1); 27628#L21-3 main_~x1~0 := 1 + main_~x1~0; 27626#L19-2 [2021-11-09 09:36:20,411 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:36:20,411 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 94 times [2021-11-09 09:36:20,411 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:36:20,411 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2016756760] [2021-11-09 09:36:20,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:36:20,412 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:36:20,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:36:20,426 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:36:20,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:36:20,427 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:36:20,427 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:36:20,427 INFO L85 PathProgramCache]: Analyzing trace with hash -809115920, now seen corresponding path program 93 times [2021-11-09 09:36:20,428 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:36:20,428 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1320041163] [2021-11-09 09:36:20,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:36:20,428 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:36:20,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:36:23,742 INFO L134 CoverageAnalysis]: Checked inductivity of 4371 backedges. 0 proven. 4371 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:36:23,742 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:36:23,743 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1320041163] [2021-11-09 09:36:23,743 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1320041163] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:36:23,743 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1386937993] [2021-11-09 09:36:23,743 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:36:23,743 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:36:23,743 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:36:23,744 INFO L229 MonitoredProcess]: Starting monitored process 94 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:36:23,745 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (94)] Waiting until timeout for monitored process [2021-11-09 09:36:25,264 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 48 check-sat command(s) [2021-11-09 09:36:25,264 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:36:25,266 INFO L263 TraceCheckSpWp]: Trace formula consists of 287 conjuncts, 95 conjunts are in the unsatisfiable core [2021-11-09 09:36:25,268 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:36:25,528 INFO L134 CoverageAnalysis]: Checked inductivity of 4371 backedges. 0 proven. 4371 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:36:25,528 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1386937993] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:36:25,528 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:36:25,528 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [95, 95] total 95 [2021-11-09 09:36:25,528 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [140840848] [2021-11-09 09:36:25,529 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:36:25,529 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:36:25,530 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 96 interpolants. [2021-11-09 09:36:25,531 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4560, Invalid=4560, Unknown=0, NotChecked=0, Total=9120 [2021-11-09 09:36:25,531 INFO L87 Difference]: Start difference. First operand 97 states and 98 transitions. cyclomatic complexity: 2 Second operand has 96 states, 96 states have (on average 1.0) internal successors, (96), 95 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:36:25,640 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:36:25,640 INFO L93 Difference]: Finished difference Result 98 states and 99 transitions. [2021-11-09 09:36:25,641 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2021-11-09 09:36:25,641 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 98 states and 99 transitions. [2021-11-09 09:36:25,641 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2021-11-09 09:36:25,642 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 98 states to 98 states and 99 transitions. [2021-11-09 09:36:25,642 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 98 [2021-11-09 09:36:25,642 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 98 [2021-11-09 09:36:25,642 INFO L73 IsDeterministic]: Start isDeterministic. Operand 98 states and 99 transitions. [2021-11-09 09:36:25,642 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:36:25,642 INFO L681 BuchiCegarLoop]: Abstraction has 98 states and 99 transitions. [2021-11-09 09:36:25,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states and 99 transitions. [2021-11-09 09:36:25,643 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 98. [2021-11-09 09:36:25,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98 states, 98 states have (on average 1.010204081632653) internal successors, (99), 97 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:36:25,643 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 99 transitions. [2021-11-09 09:36:25,643 INFO L704 BuchiCegarLoop]: Abstraction has 98 states and 99 transitions. [2021-11-09 09:36:25,643 INFO L587 BuchiCegarLoop]: Abstraction has 98 states and 99 transitions. [2021-11-09 09:36:25,643 INFO L425 BuchiCegarLoop]: ======== Iteration 95============ [2021-11-09 09:36:25,643 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98 states and 99 transitions. [2021-11-09 09:36:25,644 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2021-11-09 09:36:25,644 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:36:25,644 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:36:25,644 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:36:25,644 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [94, 1, 1, 1] [2021-11-09 09:36:25,644 INFO L791 eck$LassoCheckResult]: Stem: 28208#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 28205#L19-2 [2021-11-09 09:36:25,644 INFO L793 eck$LassoCheckResult]: Loop: 28205#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 28206#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28209#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28302#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28301#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28300#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28299#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28298#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28297#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28296#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28295#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28294#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28293#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28292#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28291#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28290#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28289#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28288#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28287#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28286#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28285#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28284#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28283#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28282#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28281#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28280#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28279#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28278#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28277#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28276#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28275#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28274#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28273#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28272#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28271#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28270#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28269#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28268#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28267#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28266#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28265#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28264#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28263#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28262#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28261#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28260#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28259#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28258#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28257#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28256#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28255#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28254#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28253#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28252#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28251#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28250#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28249#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28248#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28247#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28246#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28245#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28244#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28243#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28242#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28241#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28240#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28239#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28238#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28237#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28236#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28235#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28234#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28233#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28232#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28231#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28230#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28229#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28228#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28227#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28226#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28225#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28224#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28223#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28222#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28221#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28220#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28219#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28218#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28217#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28216#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28215#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28214#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28213#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28212#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28211#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28210#L21-2 assume !(main_~x2~0 > 1); 28207#L21-3 main_~x1~0 := 1 + main_~x1~0; 28205#L19-2 [2021-11-09 09:36:25,644 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:36:25,645 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 95 times [2021-11-09 09:36:25,645 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:36:25,645 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1081524987] [2021-11-09 09:36:25,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:36:25,645 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:36:25,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:36:25,656 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:36:25,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:36:25,657 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:36:25,657 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:36:25,657 INFO L85 PathProgramCache]: Analyzing trace with hash 687212015, now seen corresponding path program 94 times [2021-11-09 09:36:25,657 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:36:25,657 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1877001809] [2021-11-09 09:36:25,657 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:36:25,657 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:36:25,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:36:28,914 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:36:28,914 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:36:28,914 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1877001809] [2021-11-09 09:36:28,914 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1877001809] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:36:28,914 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [630946609] [2021-11-09 09:36:28,914 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:36:28,915 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:36:28,915 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:36:28,916 INFO L229 MonitoredProcess]: Starting monitored process 95 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:36:28,917 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (95)] Waiting until timeout for monitored process [2021-11-09 09:36:30,488 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:36:30,488 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:36:30,490 INFO L263 TraceCheckSpWp]: Trace formula consists of 290 conjuncts, 96 conjunts are in the unsatisfiable core [2021-11-09 09:36:30,492 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:36:30,791 INFO L134 CoverageAnalysis]: Checked inductivity of 4465 backedges. 0 proven. 4465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:36:30,791 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [630946609] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:36:30,791 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:36:30,791 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [96, 96] total 96 [2021-11-09 09:36:30,791 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [317698720] [2021-11-09 09:36:30,792 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:36:30,792 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:36:30,793 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2021-11-09 09:36:30,793 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4656, Invalid=4656, Unknown=0, NotChecked=0, Total=9312 [2021-11-09 09:36:30,794 INFO L87 Difference]: Start difference. First operand 98 states and 99 transitions. cyclomatic complexity: 2 Second operand has 97 states, 97 states have (on average 1.0) internal successors, (97), 96 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:36:30,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:36:30,887 INFO L93 Difference]: Finished difference Result 99 states and 100 transitions. [2021-11-09 09:36:30,887 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 97 states. [2021-11-09 09:36:30,887 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99 states and 100 transitions. [2021-11-09 09:36:30,887 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2021-11-09 09:36:30,888 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99 states to 99 states and 100 transitions. [2021-11-09 09:36:30,888 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99 [2021-11-09 09:36:30,892 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99 [2021-11-09 09:36:30,892 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99 states and 100 transitions. [2021-11-09 09:36:30,892 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:36:30,893 INFO L681 BuchiCegarLoop]: Abstraction has 99 states and 100 transitions. [2021-11-09 09:36:30,893 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states and 100 transitions. [2021-11-09 09:36:30,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 99. [2021-11-09 09:36:30,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99 states, 99 states have (on average 1.0101010101010102) internal successors, (100), 98 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:36:30,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 100 transitions. [2021-11-09 09:36:30,895 INFO L704 BuchiCegarLoop]: Abstraction has 99 states and 100 transitions. [2021-11-09 09:36:30,895 INFO L587 BuchiCegarLoop]: Abstraction has 99 states and 100 transitions. [2021-11-09 09:36:30,895 INFO L425 BuchiCegarLoop]: ======== Iteration 96============ [2021-11-09 09:36:30,895 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 100 transitions. [2021-11-09 09:36:30,896 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 98 [2021-11-09 09:36:30,896 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:36:30,896 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:36:30,896 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:36:30,896 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [95, 1, 1, 1] [2021-11-09 09:36:30,896 INFO L791 eck$LassoCheckResult]: Stem: 28793#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 28790#L19-2 [2021-11-09 09:36:30,897 INFO L793 eck$LassoCheckResult]: Loop: 28790#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 28791#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28794#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28888#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28887#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28886#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28885#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28884#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28883#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28882#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28881#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28880#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28879#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28878#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28877#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28876#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28875#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28874#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28873#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28872#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28871#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28870#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28869#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28868#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28867#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28866#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28865#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28864#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28863#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28862#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28861#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28860#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28859#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28858#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28857#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28856#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28855#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28854#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28853#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28852#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28851#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28850#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28849#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28848#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28847#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28846#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28845#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28844#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28843#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28842#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28841#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28840#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28839#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28838#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28837#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28836#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28835#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28834#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28833#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28832#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28831#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28830#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28829#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28828#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28827#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28826#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28825#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28824#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28823#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28822#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28821#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28820#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28819#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28818#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28817#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28816#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28815#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28814#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28813#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28812#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28811#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28810#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28809#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28808#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28807#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28806#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28805#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28804#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28803#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28802#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28801#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28800#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28799#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28798#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28797#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28796#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 28795#L21-2 assume !(main_~x2~0 > 1); 28792#L21-3 main_~x1~0 := 1 + main_~x1~0; 28790#L19-2 [2021-11-09 09:36:30,897 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:36:30,897 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 96 times [2021-11-09 09:36:30,897 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:36:30,897 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [262907976] [2021-11-09 09:36:30,897 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:36:30,897 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:36:30,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:36:30,943 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:36:30,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:36:30,944 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:36:30,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:36:30,944 INFO L85 PathProgramCache]: Analyzing trace with hash -171262256, now seen corresponding path program 95 times [2021-11-09 09:36:30,945 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:36:30,945 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1960783989] [2021-11-09 09:36:30,945 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:36:30,945 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:36:30,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:36:34,247 INFO L134 CoverageAnalysis]: Checked inductivity of 4560 backedges. 0 proven. 4560 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:36:34,247 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:36:34,248 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1960783989] [2021-11-09 09:36:34,248 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1960783989] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:36:34,248 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1248158213] [2021-11-09 09:36:34,248 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:36:34,248 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:36:34,248 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:36:34,251 INFO L229 MonitoredProcess]: Starting monitored process 96 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:36:34,251 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (96)] Waiting until timeout for monitored process [2021-11-09 09:36:35,838 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 49 check-sat command(s) [2021-11-09 09:36:35,839 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:36:35,842 INFO L263 TraceCheckSpWp]: Trace formula consists of 293 conjuncts, 97 conjunts are in the unsatisfiable core [2021-11-09 09:36:35,843 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:36:36,095 INFO L134 CoverageAnalysis]: Checked inductivity of 4560 backedges. 0 proven. 4560 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:36:36,095 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1248158213] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:36:36,095 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:36:36,095 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [97, 97] total 97 [2021-11-09 09:36:36,096 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2066461276] [2021-11-09 09:36:36,096 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:36:36,096 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:36:36,097 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2021-11-09 09:36:36,097 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4753, Invalid=4753, Unknown=0, NotChecked=0, Total=9506 [2021-11-09 09:36:36,097 INFO L87 Difference]: Start difference. First operand 99 states and 100 transitions. cyclomatic complexity: 2 Second operand has 98 states, 98 states have (on average 1.0) internal successors, (98), 97 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:36:36,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:36:36,190 INFO L93 Difference]: Finished difference Result 100 states and 101 transitions. [2021-11-09 09:36:36,190 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 98 states. [2021-11-09 09:36:36,190 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100 states and 101 transitions. [2021-11-09 09:36:36,191 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 99 [2021-11-09 09:36:36,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100 states to 100 states and 101 transitions. [2021-11-09 09:36:36,191 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 100 [2021-11-09 09:36:36,192 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 100 [2021-11-09 09:36:36,192 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100 states and 101 transitions. [2021-11-09 09:36:36,192 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:36:36,192 INFO L681 BuchiCegarLoop]: Abstraction has 100 states and 101 transitions. [2021-11-09 09:36:36,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states and 101 transitions. [2021-11-09 09:36:36,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 100. [2021-11-09 09:36:36,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 100 states, 100 states have (on average 1.01) internal successors, (101), 99 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:36:36,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 101 transitions. [2021-11-09 09:36:36,193 INFO L704 BuchiCegarLoop]: Abstraction has 100 states and 101 transitions. [2021-11-09 09:36:36,193 INFO L587 BuchiCegarLoop]: Abstraction has 100 states and 101 transitions. [2021-11-09 09:36:36,194 INFO L425 BuchiCegarLoop]: ======== Iteration 97============ [2021-11-09 09:36:36,194 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 100 states and 101 transitions. [2021-11-09 09:36:36,194 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 99 [2021-11-09 09:36:36,194 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:36:36,194 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:36:36,195 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:36:36,195 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [96, 1, 1, 1] [2021-11-09 09:36:36,195 INFO L791 eck$LassoCheckResult]: Stem: 29384#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 29381#L19-2 [2021-11-09 09:36:36,195 INFO L793 eck$LassoCheckResult]: Loop: 29381#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 29382#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29385#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29480#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29479#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29478#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29477#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29476#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29475#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29474#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29473#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29472#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29471#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29470#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29469#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29468#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29467#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29466#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29465#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29464#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29463#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29462#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29461#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29460#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29459#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29458#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29457#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29456#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29455#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29454#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29453#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29452#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29451#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29450#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29449#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29448#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29447#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29446#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29445#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29444#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29443#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29442#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29441#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29440#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29439#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29438#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29437#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29436#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29435#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29434#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29433#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29432#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29431#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29430#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29429#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29428#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29427#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29426#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29425#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29424#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29423#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29422#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29421#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29420#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29419#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29418#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29417#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29416#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29415#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29414#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29413#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29412#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29411#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29410#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29409#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29408#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29407#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29406#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29405#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29404#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29403#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29402#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29401#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29400#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29399#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29398#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29397#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29396#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29395#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29394#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29393#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29392#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29391#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29390#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29389#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29388#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29387#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29386#L21-2 assume !(main_~x2~0 > 1); 29383#L21-3 main_~x1~0 := 1 + main_~x1~0; 29381#L19-2 [2021-11-09 09:36:36,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:36:36,195 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 97 times [2021-11-09 09:36:36,195 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:36:36,196 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1471986608] [2021-11-09 09:36:36,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:36:36,196 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:36:36,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:36:36,209 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:36:36,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:36:36,213 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:36:36,214 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:36:36,214 INFO L85 PathProgramCache]: Analyzing trace with hash -1014160881, now seen corresponding path program 96 times [2021-11-09 09:36:36,214 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:36:36,214 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1657309846] [2021-11-09 09:36:36,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:36:36,215 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:36:36,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:36:40,013 INFO L134 CoverageAnalysis]: Checked inductivity of 4656 backedges. 0 proven. 4656 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:36:40,014 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:36:40,014 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1657309846] [2021-11-09 09:36:40,014 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1657309846] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:36:40,014 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1741667409] [2021-11-09 09:36:40,014 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:36:40,014 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:36:40,014 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:36:40,015 INFO L229 MonitoredProcess]: Starting monitored process 97 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:36:40,065 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (97)] Waiting until timeout for monitored process [2021-11-09 09:36:41,837 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2021-11-09 09:36:41,838 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:36:41,840 INFO L263 TraceCheckSpWp]: Trace formula consists of 296 conjuncts, 98 conjunts are in the unsatisfiable core [2021-11-09 09:36:41,842 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:36:42,115 INFO L134 CoverageAnalysis]: Checked inductivity of 4656 backedges. 0 proven. 4656 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:36:42,115 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1741667409] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:36:42,115 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:36:42,115 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [98, 98] total 98 [2021-11-09 09:36:42,115 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [426219604] [2021-11-09 09:36:42,116 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:36:42,116 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:36:42,117 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 99 interpolants. [2021-11-09 09:36:42,117 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4851, Invalid=4851, Unknown=0, NotChecked=0, Total=9702 [2021-11-09 09:36:42,117 INFO L87 Difference]: Start difference. First operand 100 states and 101 transitions. cyclomatic complexity: 2 Second operand has 99 states, 99 states have (on average 1.0) internal successors, (99), 98 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:36:42,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:36:42,200 INFO L93 Difference]: Finished difference Result 101 states and 102 transitions. [2021-11-09 09:36:42,201 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 99 states. [2021-11-09 09:36:42,201 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 101 states and 102 transitions. [2021-11-09 09:36:42,201 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 100 [2021-11-09 09:36:42,202 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 101 states to 101 states and 102 transitions. [2021-11-09 09:36:42,202 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 101 [2021-11-09 09:36:42,202 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 101 [2021-11-09 09:36:42,202 INFO L73 IsDeterministic]: Start isDeterministic. Operand 101 states and 102 transitions. [2021-11-09 09:36:42,202 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:36:42,202 INFO L681 BuchiCegarLoop]: Abstraction has 101 states and 102 transitions. [2021-11-09 09:36:42,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states and 102 transitions. [2021-11-09 09:36:42,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 101. [2021-11-09 09:36:42,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101 states, 101 states have (on average 1.00990099009901) internal successors, (102), 100 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:36:42,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 102 transitions. [2021-11-09 09:36:42,204 INFO L704 BuchiCegarLoop]: Abstraction has 101 states and 102 transitions. [2021-11-09 09:36:42,204 INFO L587 BuchiCegarLoop]: Abstraction has 101 states and 102 transitions. [2021-11-09 09:36:42,204 INFO L425 BuchiCegarLoop]: ======== Iteration 98============ [2021-11-09 09:36:42,204 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101 states and 102 transitions. [2021-11-09 09:36:42,204 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 100 [2021-11-09 09:36:42,204 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:36:42,205 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:36:42,205 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:36:42,205 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [97, 1, 1, 1] [2021-11-09 09:36:42,205 INFO L791 eck$LassoCheckResult]: Stem: 29981#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 29978#L19-2 [2021-11-09 09:36:42,206 INFO L793 eck$LassoCheckResult]: Loop: 29978#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 29979#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29982#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30078#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30077#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30076#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30075#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30074#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30073#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30072#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30071#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30070#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30069#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30068#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30067#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30066#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30065#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30064#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30063#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30062#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30061#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30060#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30059#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30058#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30057#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30056#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30055#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30054#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30053#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30052#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30051#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30050#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30049#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30048#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30047#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30046#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30045#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30044#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30043#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30042#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30041#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30040#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30039#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30038#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30037#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30036#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30035#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30034#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30033#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30032#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30031#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30030#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30029#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30028#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30027#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30026#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30025#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30024#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30023#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30022#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30021#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30020#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30019#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30018#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30017#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30016#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30015#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30014#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30013#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30012#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30011#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30010#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30009#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30008#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30007#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30006#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30005#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30004#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30003#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30002#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30001#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30000#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29999#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29998#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29997#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29996#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29995#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29994#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29993#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29992#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29991#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29990#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29989#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29988#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29987#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29986#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29985#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29984#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 29983#L21-2 assume !(main_~x2~0 > 1); 29980#L21-3 main_~x1~0 := 1 + main_~x1~0; 29978#L19-2 [2021-11-09 09:36:42,206 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:36:42,206 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 98 times [2021-11-09 09:36:42,206 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:36:42,206 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [259883672] [2021-11-09 09:36:42,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:36:42,207 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:36:42,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:36:42,221 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:36:42,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:36:42,221 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:36:42,222 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:36:42,222 INFO L85 PathProgramCache]: Analyzing trace with hash -1374214480, now seen corresponding path program 97 times [2021-11-09 09:36:42,222 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:36:42,222 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [288742205] [2021-11-09 09:36:42,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:36:42,222 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:36:42,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:36:45,707 INFO L134 CoverageAnalysis]: Checked inductivity of 4753 backedges. 0 proven. 4753 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:36:45,707 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:36:45,707 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [288742205] [2021-11-09 09:36:45,707 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [288742205] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:36:45,707 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [133634118] [2021-11-09 09:36:45,707 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:36:45,707 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:36:45,707 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:36:45,709 INFO L229 MonitoredProcess]: Starting monitored process 98 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:36:45,709 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (98)] Waiting until timeout for monitored process [2021-11-09 09:36:47,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:36:47,365 INFO L263 TraceCheckSpWp]: Trace formula consists of 299 conjuncts, 99 conjunts are in the unsatisfiable core [2021-11-09 09:36:47,367 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:36:47,628 INFO L134 CoverageAnalysis]: Checked inductivity of 4753 backedges. 0 proven. 4753 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:36:47,628 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [133634118] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:36:47,628 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:36:47,628 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [99, 99] total 99 [2021-11-09 09:36:47,628 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1985076686] [2021-11-09 09:36:47,628 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:36:47,628 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:36:47,629 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 100 interpolants. [2021-11-09 09:36:47,630 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4950, Invalid=4950, Unknown=0, NotChecked=0, Total=9900 [2021-11-09 09:36:47,630 INFO L87 Difference]: Start difference. First operand 101 states and 102 transitions. cyclomatic complexity: 2 Second operand has 100 states, 100 states have (on average 1.0) internal successors, (100), 99 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:36:47,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:36:47,750 INFO L93 Difference]: Finished difference Result 102 states and 103 transitions. [2021-11-09 09:36:47,750 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 100 states. [2021-11-09 09:36:47,750 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 102 states and 103 transitions. [2021-11-09 09:36:47,751 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 101 [2021-11-09 09:36:47,751 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 102 states to 102 states and 103 transitions. [2021-11-09 09:36:47,751 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 102 [2021-11-09 09:36:47,752 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 102 [2021-11-09 09:36:47,752 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102 states and 103 transitions. [2021-11-09 09:36:47,752 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:36:47,752 INFO L681 BuchiCegarLoop]: Abstraction has 102 states and 103 transitions. [2021-11-09 09:36:47,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states and 103 transitions. [2021-11-09 09:36:47,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 102. [2021-11-09 09:36:47,754 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 102 states, 102 states have (on average 1.0098039215686274) internal successors, (103), 101 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:36:47,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 103 transitions. [2021-11-09 09:36:47,754 INFO L704 BuchiCegarLoop]: Abstraction has 102 states and 103 transitions. [2021-11-09 09:36:47,754 INFO L587 BuchiCegarLoop]: Abstraction has 102 states and 103 transitions. [2021-11-09 09:36:47,754 INFO L425 BuchiCegarLoop]: ======== Iteration 99============ [2021-11-09 09:36:47,754 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 102 states and 103 transitions. [2021-11-09 09:36:47,755 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 101 [2021-11-09 09:36:47,755 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:36:47,755 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:36:47,757 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:36:47,758 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [98, 1, 1, 1] [2021-11-09 09:36:47,758 INFO L791 eck$LassoCheckResult]: Stem: 30584#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 30581#L19-2 [2021-11-09 09:36:47,758 INFO L793 eck$LassoCheckResult]: Loop: 30581#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 30582#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30585#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30682#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30681#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30680#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30679#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30678#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30677#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30676#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30675#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30674#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30673#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30672#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30671#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30670#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30669#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30668#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30667#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30666#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30665#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30664#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30663#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30662#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30661#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30660#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30659#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30658#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30657#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30656#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30655#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30654#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30653#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30652#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30651#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30650#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30649#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30648#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30647#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30646#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30645#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30644#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30643#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30642#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30641#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30640#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30639#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30638#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30637#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30636#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30635#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30634#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30633#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30632#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30631#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30630#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30629#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30628#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30627#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30626#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30625#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30624#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30623#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30622#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30621#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30620#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30619#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30618#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30617#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30616#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30615#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30614#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30613#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30612#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30611#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30610#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30609#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30608#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30607#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30606#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30605#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30604#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30603#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30602#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30601#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30600#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30599#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30598#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30597#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30596#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30595#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30594#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30593#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30592#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30591#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30590#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30589#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30588#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30587#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 30586#L21-2 assume !(main_~x2~0 > 1); 30583#L21-3 main_~x1~0 := 1 + main_~x1~0; 30581#L19-2 [2021-11-09 09:36:47,758 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:36:47,758 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 99 times [2021-11-09 09:36:47,759 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:36:47,759 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1120196725] [2021-11-09 09:36:47,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:36:47,759 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:36:47,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:36:47,774 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:36:47,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:36:47,775 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:36:47,775 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:36:47,775 INFO L85 PathProgramCache]: Analyzing trace with hash 349025839, now seen corresponding path program 98 times [2021-11-09 09:36:47,775 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:36:47,775 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1096739649] [2021-11-09 09:36:47,776 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:36:47,776 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:36:47,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:36:51,249 INFO L134 CoverageAnalysis]: Checked inductivity of 4851 backedges. 0 proven. 4851 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:36:51,250 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:36:51,250 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1096739649] [2021-11-09 09:36:51,250 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1096739649] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:36:51,250 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [165946768] [2021-11-09 09:36:51,250 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:36:51,250 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:36:51,250 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:36:51,252 INFO L229 MonitoredProcess]: Starting monitored process 99 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:36:51,252 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (99)] Waiting until timeout for monitored process [2021-11-09 09:36:53,068 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:36:53,068 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:36:53,071 INFO L263 TraceCheckSpWp]: Trace formula consists of 302 conjuncts, 100 conjunts are in the unsatisfiable core [2021-11-09 09:36:53,073 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:36:53,397 INFO L134 CoverageAnalysis]: Checked inductivity of 4851 backedges. 0 proven. 4851 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:36:53,398 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [165946768] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:36:53,398 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:36:53,398 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [100, 100] total 100 [2021-11-09 09:36:53,398 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1880891412] [2021-11-09 09:36:53,398 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:36:53,398 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:36:53,399 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 101 interpolants. [2021-11-09 09:36:53,400 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5050, Invalid=5050, Unknown=0, NotChecked=0, Total=10100 [2021-11-09 09:36:53,400 INFO L87 Difference]: Start difference. First operand 102 states and 103 transitions. cyclomatic complexity: 2 Second operand has 101 states, 101 states have (on average 1.0) internal successors, (101), 100 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:36:53,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:36:53,517 INFO L93 Difference]: Finished difference Result 103 states and 104 transitions. [2021-11-09 09:36:53,517 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 101 states. [2021-11-09 09:36:53,517 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 103 states and 104 transitions. [2021-11-09 09:36:53,518 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 102 [2021-11-09 09:36:53,518 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 103 states to 103 states and 104 transitions. [2021-11-09 09:36:53,519 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 103 [2021-11-09 09:36:53,519 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 103 [2021-11-09 09:36:53,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 103 states and 104 transitions. [2021-11-09 09:36:53,519 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:36:53,520 INFO L681 BuchiCegarLoop]: Abstraction has 103 states and 104 transitions. [2021-11-09 09:36:53,520 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states and 104 transitions. [2021-11-09 09:36:53,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 103. [2021-11-09 09:36:53,522 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 103 states, 103 states have (on average 1.0097087378640777) internal successors, (104), 102 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:36:53,523 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 104 transitions. [2021-11-09 09:36:53,523 INFO L704 BuchiCegarLoop]: Abstraction has 103 states and 104 transitions. [2021-11-09 09:36:53,523 INFO L587 BuchiCegarLoop]: Abstraction has 103 states and 104 transitions. [2021-11-09 09:36:53,523 INFO L425 BuchiCegarLoop]: ======== Iteration 100============ [2021-11-09 09:36:53,523 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 103 states and 104 transitions. [2021-11-09 09:36:53,524 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 102 [2021-11-09 09:36:53,524 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:36:53,524 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:36:53,525 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:36:53,525 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [99, 1, 1, 1] [2021-11-09 09:36:53,525 INFO L791 eck$LassoCheckResult]: Stem: 31193#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 31190#L19-2 [2021-11-09 09:36:53,525 INFO L793 eck$LassoCheckResult]: Loop: 31190#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 31191#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31194#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31292#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31291#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31290#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31289#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31288#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31287#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31286#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31285#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31284#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31283#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31282#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31281#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31280#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31279#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31278#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31277#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31276#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31275#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31274#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31273#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31272#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31271#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31270#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31269#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31268#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31267#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31266#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31265#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31264#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31263#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31262#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31261#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31260#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31259#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31258#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31257#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31256#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31255#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31254#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31253#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31252#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31251#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31250#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31249#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31248#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31247#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31246#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31245#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31244#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31243#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31242#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31241#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31240#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31239#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31238#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31237#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31236#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31235#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31234#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31233#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31232#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31231#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31230#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31229#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31228#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31227#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31226#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31225#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31224#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31223#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31222#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31221#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31220#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31219#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31218#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31217#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31216#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31215#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31214#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31213#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31212#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31211#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31210#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31209#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31208#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31207#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31206#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31205#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31204#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31203#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31202#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31201#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31200#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31199#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31198#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31197#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31196#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31195#L21-2 assume !(main_~x2~0 > 1); 31192#L21-3 main_~x1~0 := 1 + main_~x1~0; 31190#L19-2 [2021-11-09 09:36:53,526 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:36:53,526 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 100 times [2021-11-09 09:36:53,526 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:36:53,526 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [138385090] [2021-11-09 09:36:53,527 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:36:53,527 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:36:53,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:36:53,544 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:36:53,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:36:53,546 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:36:53,546 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:36:53,546 INFO L85 PathProgramCache]: Analyzing trace with hash -2065099120, now seen corresponding path program 99 times [2021-11-09 09:36:53,546 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:36:53,547 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1834316630] [2021-11-09 09:36:53,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:36:53,547 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:36:53,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:36:57,364 INFO L134 CoverageAnalysis]: Checked inductivity of 4950 backedges. 0 proven. 4950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:36:57,364 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:36:57,364 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1834316630] [2021-11-09 09:36:57,364 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1834316630] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:36:57,364 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2078277458] [2021-11-09 09:36:57,364 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:36:57,364 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:36:57,364 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:36:57,366 INFO L229 MonitoredProcess]: Starting monitored process 100 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:36:57,366 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (100)] Waiting until timeout for monitored process [2021-11-09 09:36:59,108 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 51 check-sat command(s) [2021-11-09 09:36:59,108 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:36:59,110 INFO L263 TraceCheckSpWp]: Trace formula consists of 305 conjuncts, 101 conjunts are in the unsatisfiable core [2021-11-09 09:36:59,111 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:36:59,414 INFO L134 CoverageAnalysis]: Checked inductivity of 4950 backedges. 0 proven. 4950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:36:59,414 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2078277458] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:36:59,414 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:36:59,414 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [101, 101] total 101 [2021-11-09 09:36:59,414 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1200484491] [2021-11-09 09:36:59,414 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:36:59,415 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:36:59,415 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 102 interpolants. [2021-11-09 09:36:59,416 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5151, Invalid=5151, Unknown=0, NotChecked=0, Total=10302 [2021-11-09 09:36:59,416 INFO L87 Difference]: Start difference. First operand 103 states and 104 transitions. cyclomatic complexity: 2 Second operand has 102 states, 102 states have (on average 1.0) internal successors, (102), 101 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:36:59,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:36:59,544 INFO L93 Difference]: Finished difference Result 104 states and 105 transitions. [2021-11-09 09:36:59,544 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 102 states. [2021-11-09 09:36:59,544 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 104 states and 105 transitions. [2021-11-09 09:36:59,545 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 103 [2021-11-09 09:36:59,546 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 104 states to 104 states and 105 transitions. [2021-11-09 09:36:59,546 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 104 [2021-11-09 09:36:59,546 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 104 [2021-11-09 09:36:59,546 INFO L73 IsDeterministic]: Start isDeterministic. Operand 104 states and 105 transitions. [2021-11-09 09:36:59,546 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:36:59,546 INFO L681 BuchiCegarLoop]: Abstraction has 104 states and 105 transitions. [2021-11-09 09:36:59,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states and 105 transitions. [2021-11-09 09:36:59,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 104. [2021-11-09 09:36:59,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 104 states, 104 states have (on average 1.0096153846153846) internal successors, (105), 103 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:36:59,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 105 transitions. [2021-11-09 09:36:59,549 INFO L704 BuchiCegarLoop]: Abstraction has 104 states and 105 transitions. [2021-11-09 09:36:59,549 INFO L587 BuchiCegarLoop]: Abstraction has 104 states and 105 transitions. [2021-11-09 09:36:59,549 INFO L425 BuchiCegarLoop]: ======== Iteration 101============ [2021-11-09 09:36:59,549 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 104 states and 105 transitions. [2021-11-09 09:36:59,549 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 103 [2021-11-09 09:36:59,549 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:36:59,550 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:36:59,550 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:36:59,550 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [100, 1, 1, 1] [2021-11-09 09:36:59,550 INFO L791 eck$LassoCheckResult]: Stem: 31808#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 31805#L19-2 [2021-11-09 09:36:59,550 INFO L793 eck$LassoCheckResult]: Loop: 31805#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 31806#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31809#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31908#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31907#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31906#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31905#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31904#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31903#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31902#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31901#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31900#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31899#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31898#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31897#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31896#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31895#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31894#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31893#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31892#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31891#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31890#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31889#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31888#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31887#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31886#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31885#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31884#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31883#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31882#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31881#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31880#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31879#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31878#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31877#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31876#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31875#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31874#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31873#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31872#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31871#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31870#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31869#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31868#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31867#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31866#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31865#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31864#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31863#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31862#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31861#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31860#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31859#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31858#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31857#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31856#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31855#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31854#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31853#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31852#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31851#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31850#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31849#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31848#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31847#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31846#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31845#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31844#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31843#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31842#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31841#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31840#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31839#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31838#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31837#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31836#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31835#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31834#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31833#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31832#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31831#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31830#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31829#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31828#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31827#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31826#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31825#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31824#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31823#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31822#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31821#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31820#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31819#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31818#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31817#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31816#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31815#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31814#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31813#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31812#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31811#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 31810#L21-2 assume !(main_~x2~0 > 1); 31807#L21-3 main_~x1~0 := 1 + main_~x1~0; 31805#L19-2 [2021-11-09 09:36:59,551 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:36:59,551 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 101 times [2021-11-09 09:36:59,551 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:36:59,551 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2143329356] [2021-11-09 09:36:59,551 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:36:59,552 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:36:59,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:36:59,565 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:36:59,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:36:59,566 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:36:59,566 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:36:59,566 INFO L85 PathProgramCache]: Analyzing trace with hash 406438479, now seen corresponding path program 100 times [2021-11-09 09:36:59,566 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:36:59,566 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [745360953] [2021-11-09 09:36:59,566 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:36:59,566 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:36:59,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:37:03,262 INFO L134 CoverageAnalysis]: Checked inductivity of 5050 backedges. 0 proven. 5050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:03,262 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:37:03,262 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [745360953] [2021-11-09 09:37:03,262 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [745360953] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:03,262 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [134855009] [2021-11-09 09:37:03,262 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:37:03,263 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:37:03,263 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:37:03,268 INFO L229 MonitoredProcess]: Starting monitored process 101 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:37:03,287 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (101)] Waiting until timeout for monitored process [2021-11-09 09:37:05,055 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:37:05,056 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:37:05,059 INFO L263 TraceCheckSpWp]: Trace formula consists of 308 conjuncts, 102 conjunts are in the unsatisfiable core [2021-11-09 09:37:05,061 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:37:05,450 INFO L134 CoverageAnalysis]: Checked inductivity of 5050 backedges. 0 proven. 5050 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:05,450 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [134855009] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:05,450 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:37:05,450 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [102, 102] total 102 [2021-11-09 09:37:05,450 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [904725834] [2021-11-09 09:37:05,450 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:37:05,450 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:37:05,451 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2021-11-09 09:37:05,452 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5253, Invalid=5253, Unknown=0, NotChecked=0, Total=10506 [2021-11-09 09:37:05,452 INFO L87 Difference]: Start difference. First operand 104 states and 105 transitions. cyclomatic complexity: 2 Second operand has 103 states, 103 states have (on average 1.0) internal successors, (103), 102 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:37:05,573 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:37:05,573 INFO L93 Difference]: Finished difference Result 105 states and 106 transitions. [2021-11-09 09:37:05,574 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 103 states. [2021-11-09 09:37:05,574 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 105 states and 106 transitions. [2021-11-09 09:37:05,574 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 104 [2021-11-09 09:37:05,575 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 105 states to 105 states and 106 transitions. [2021-11-09 09:37:05,575 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 105 [2021-11-09 09:37:05,575 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 105 [2021-11-09 09:37:05,575 INFO L73 IsDeterministic]: Start isDeterministic. Operand 105 states and 106 transitions. [2021-11-09 09:37:05,575 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:37:05,576 INFO L681 BuchiCegarLoop]: Abstraction has 105 states and 106 transitions. [2021-11-09 09:37:05,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states and 106 transitions. [2021-11-09 09:37:05,577 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 105. [2021-11-09 09:37:05,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 105 states, 105 states have (on average 1.0095238095238095) internal successors, (106), 104 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:37:05,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 106 transitions. [2021-11-09 09:37:05,578 INFO L704 BuchiCegarLoop]: Abstraction has 105 states and 106 transitions. [2021-11-09 09:37:05,578 INFO L587 BuchiCegarLoop]: Abstraction has 105 states and 106 transitions. [2021-11-09 09:37:05,578 INFO L425 BuchiCegarLoop]: ======== Iteration 102============ [2021-11-09 09:37:05,578 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 105 states and 106 transitions. [2021-11-09 09:37:05,579 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 104 [2021-11-09 09:37:05,579 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:37:05,579 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:37:05,579 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:37:05,579 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [101, 1, 1, 1] [2021-11-09 09:37:05,580 INFO L791 eck$LassoCheckResult]: Stem: 32429#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 32426#L19-2 [2021-11-09 09:37:05,580 INFO L793 eck$LassoCheckResult]: Loop: 32426#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 32427#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32430#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32530#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32529#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32528#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32527#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32526#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32525#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32524#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32523#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32522#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32521#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32520#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32519#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32518#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32517#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32516#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32515#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32514#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32513#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32512#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32511#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32510#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32509#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32508#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32507#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32506#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32505#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32504#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32503#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32502#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32501#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32500#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32499#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32498#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32497#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32496#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32495#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32494#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32493#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32492#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32491#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32490#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32489#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32488#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32487#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32486#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32485#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32484#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32483#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32482#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32481#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32480#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32479#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32478#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32477#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32476#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32475#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32474#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32473#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32472#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32471#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32470#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32469#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32468#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32467#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32466#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32465#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32464#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32463#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32462#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32461#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32460#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32459#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32458#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32457#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32456#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32455#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32454#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32453#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32452#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32451#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32450#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32449#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32448#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32447#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32446#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32445#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32444#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32443#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32442#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32441#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32440#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32439#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32438#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32437#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32436#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32435#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32434#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32433#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32432#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 32431#L21-2 assume !(main_~x2~0 > 1); 32428#L21-3 main_~x1~0 := 1 + main_~x1~0; 32426#L19-2 [2021-11-09 09:37:05,580 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:37:05,580 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 102 times [2021-11-09 09:37:05,580 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:37:05,581 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1546489942] [2021-11-09 09:37:05,581 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:37:05,581 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:37:05,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:37:05,597 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:37:05,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:37:05,598 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:37:05,599 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:37:05,599 INFO L85 PathProgramCache]: Analyzing trace with hash -285307280, now seen corresponding path program 101 times [2021-11-09 09:37:05,599 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:37:05,599 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1798114432] [2021-11-09 09:37:05,599 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:37:05,599 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:37:05,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:37:09,333 INFO L134 CoverageAnalysis]: Checked inductivity of 5151 backedges. 0 proven. 5151 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:09,333 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:37:09,333 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1798114432] [2021-11-09 09:37:09,333 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1798114432] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:09,333 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1794583113] [2021-11-09 09:37:09,333 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:37:09,333 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:37:09,333 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:37:09,334 INFO L229 MonitoredProcess]: Starting monitored process 102 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:37:09,335 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (102)] Waiting until timeout for monitored process [2021-11-09 09:37:11,893 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 52 check-sat command(s) [2021-11-09 09:37:11,893 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:37:11,898 INFO L263 TraceCheckSpWp]: Trace formula consists of 311 conjuncts, 103 conjunts are in the unsatisfiable core [2021-11-09 09:37:11,900 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:37:12,401 INFO L134 CoverageAnalysis]: Checked inductivity of 5151 backedges. 0 proven. 5151 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:12,402 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1794583113] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:12,402 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:37:12,402 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [103, 103] total 103 [2021-11-09 09:37:12,402 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1259798658] [2021-11-09 09:37:12,403 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:37:12,403 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:37:12,405 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 104 interpolants. [2021-11-09 09:37:12,412 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5356, Invalid=5356, Unknown=0, NotChecked=0, Total=10712 [2021-11-09 09:37:12,413 INFO L87 Difference]: Start difference. First operand 105 states and 106 transitions. cyclomatic complexity: 2 Second operand has 104 states, 104 states have (on average 1.0) internal successors, (104), 103 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:37:12,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:37:12,643 INFO L93 Difference]: Finished difference Result 106 states and 107 transitions. [2021-11-09 09:37:12,644 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 104 states. [2021-11-09 09:37:12,644 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 106 states and 107 transitions. [2021-11-09 09:37:12,645 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 105 [2021-11-09 09:37:12,648 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 106 states to 106 states and 107 transitions. [2021-11-09 09:37:12,648 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 106 [2021-11-09 09:37:12,648 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 106 [2021-11-09 09:37:12,648 INFO L73 IsDeterministic]: Start isDeterministic. Operand 106 states and 107 transitions. [2021-11-09 09:37:12,649 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:37:12,650 INFO L681 BuchiCegarLoop]: Abstraction has 106 states and 107 transitions. [2021-11-09 09:37:12,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states and 107 transitions. [2021-11-09 09:37:12,669 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 106. [2021-11-09 09:37:12,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 106 states, 106 states have (on average 1.009433962264151) internal successors, (107), 105 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:37:12,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 107 transitions. [2021-11-09 09:37:12,670 INFO L704 BuchiCegarLoop]: Abstraction has 106 states and 107 transitions. [2021-11-09 09:37:12,670 INFO L587 BuchiCegarLoop]: Abstraction has 106 states and 107 transitions. [2021-11-09 09:37:12,670 INFO L425 BuchiCegarLoop]: ======== Iteration 103============ [2021-11-09 09:37:12,670 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 106 states and 107 transitions. [2021-11-09 09:37:12,671 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 105 [2021-11-09 09:37:12,671 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:37:12,671 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:37:12,671 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:37:12,671 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [102, 1, 1, 1] [2021-11-09 09:37:12,672 INFO L791 eck$LassoCheckResult]: Stem: 33056#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 33053#L19-2 [2021-11-09 09:37:12,672 INFO L793 eck$LassoCheckResult]: Loop: 33053#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 33054#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33057#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33158#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33157#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33156#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33155#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33154#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33153#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33152#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33151#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33150#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33149#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33148#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33147#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33146#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33145#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33144#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33143#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33142#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33141#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33140#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33139#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33138#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33137#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33136#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33135#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33134#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33133#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33132#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33131#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33130#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33129#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33128#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33127#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33126#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33125#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33124#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33123#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33122#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33121#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33120#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33119#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33118#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33117#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33116#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33115#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33114#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33113#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33112#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33111#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33110#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33109#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33108#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33107#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33106#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33105#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33104#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33103#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33102#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33101#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33100#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33099#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33098#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33097#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33096#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33095#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33094#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33093#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33092#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33091#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33090#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33089#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33088#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33087#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33086#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33085#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33084#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33083#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33082#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33081#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33080#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33079#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33078#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33077#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33076#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33075#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33074#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33073#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33072#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33071#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33070#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33069#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33068#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33067#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33066#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33065#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33064#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33063#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33062#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33061#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33060#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33059#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33058#L21-2 assume !(main_~x2~0 > 1); 33055#L21-3 main_~x1~0 := 1 + main_~x1~0; 33053#L19-2 [2021-11-09 09:37:12,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:37:12,672 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 103 times [2021-11-09 09:37:12,672 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:37:12,673 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1265639538] [2021-11-09 09:37:12,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:37:12,673 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:37:12,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:37:12,744 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:37:12,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:37:12,754 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:37:12,757 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:37:12,757 INFO L85 PathProgramCache]: Analyzing trace with hash -254589329, now seen corresponding path program 102 times [2021-11-09 09:37:12,757 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:37:12,757 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [827792955] [2021-11-09 09:37:12,757 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:37:12,758 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:37:12,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:37:16,951 INFO L134 CoverageAnalysis]: Checked inductivity of 5253 backedges. 0 proven. 5253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:16,951 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:37:16,951 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [827792955] [2021-11-09 09:37:16,951 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [827792955] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:16,951 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1120072699] [2021-11-09 09:37:16,951 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:37:16,951 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:37:16,952 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:37:16,953 INFO L229 MonitoredProcess]: Starting monitored process 103 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:37:16,954 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (103)] Waiting until timeout for monitored process [2021-11-09 09:37:18,827 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 52 check-sat command(s) [2021-11-09 09:37:18,827 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:37:18,830 INFO L263 TraceCheckSpWp]: Trace formula consists of 314 conjuncts, 104 conjunts are in the unsatisfiable core [2021-11-09 09:37:18,832 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:37:19,127 INFO L134 CoverageAnalysis]: Checked inductivity of 5253 backedges. 0 proven. 5253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:19,127 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1120072699] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:19,128 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:37:19,128 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [104, 104] total 104 [2021-11-09 09:37:19,128 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [282105061] [2021-11-09 09:37:19,128 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:37:19,128 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:37:19,129 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 105 interpolants. [2021-11-09 09:37:19,130 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5460, Invalid=5460, Unknown=0, NotChecked=0, Total=10920 [2021-11-09 09:37:19,130 INFO L87 Difference]: Start difference. First operand 106 states and 107 transitions. cyclomatic complexity: 2 Second operand has 105 states, 105 states have (on average 1.0) internal successors, (105), 104 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:37:19,220 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:37:19,220 INFO L93 Difference]: Finished difference Result 107 states and 108 transitions. [2021-11-09 09:37:19,220 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 105 states. [2021-11-09 09:37:19,220 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 107 states and 108 transitions. [2021-11-09 09:37:19,221 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 106 [2021-11-09 09:37:19,221 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 107 states to 107 states and 108 transitions. [2021-11-09 09:37:19,221 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 107 [2021-11-09 09:37:19,221 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 107 [2021-11-09 09:37:19,221 INFO L73 IsDeterministic]: Start isDeterministic. Operand 107 states and 108 transitions. [2021-11-09 09:37:19,221 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:37:19,221 INFO L681 BuchiCegarLoop]: Abstraction has 107 states and 108 transitions. [2021-11-09 09:37:19,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states and 108 transitions. [2021-11-09 09:37:19,223 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 107. [2021-11-09 09:37:19,223 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 107 states, 107 states have (on average 1.0093457943925233) internal successors, (108), 106 states have internal predecessors, (108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:37:19,223 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 108 transitions. [2021-11-09 09:37:19,223 INFO L704 BuchiCegarLoop]: Abstraction has 107 states and 108 transitions. [2021-11-09 09:37:19,224 INFO L587 BuchiCegarLoop]: Abstraction has 107 states and 108 transitions. [2021-11-09 09:37:19,224 INFO L425 BuchiCegarLoop]: ======== Iteration 104============ [2021-11-09 09:37:19,224 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 107 states and 108 transitions. [2021-11-09 09:37:19,224 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 106 [2021-11-09 09:37:19,224 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:37:19,224 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:37:19,225 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:37:19,225 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [103, 1, 1, 1] [2021-11-09 09:37:19,225 INFO L791 eck$LassoCheckResult]: Stem: 33689#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 33686#L19-2 [2021-11-09 09:37:19,225 INFO L793 eck$LassoCheckResult]: Loop: 33686#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 33687#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33690#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33792#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33791#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33790#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33789#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33788#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33787#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33786#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33785#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33784#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33783#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33782#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33781#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33780#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33779#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33778#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33777#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33776#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33775#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33774#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33773#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33772#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33771#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33770#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33769#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33768#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33767#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33766#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33765#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33764#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33763#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33762#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33761#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33760#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33759#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33758#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33757#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33756#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33755#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33754#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33753#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33752#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33751#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33750#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33749#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33748#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33747#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33746#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33745#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33744#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33743#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33742#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33741#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33740#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33739#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33738#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33737#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33736#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33735#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33734#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33733#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33732#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33731#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33730#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33729#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33728#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33727#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33726#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33725#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33724#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33723#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33722#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33721#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33720#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33719#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33718#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33717#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33716#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33715#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33714#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33713#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33712#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33711#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33710#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33709#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33708#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33707#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33706#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33705#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33704#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33703#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33702#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33701#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33700#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33699#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33698#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33697#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33696#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33695#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33694#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33693#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33692#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 33691#L21-2 assume !(main_~x2~0 > 1); 33688#L21-3 main_~x1~0 := 1 + main_~x1~0; 33686#L19-2 [2021-11-09 09:37:19,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:37:19,226 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 104 times [2021-11-09 09:37:19,226 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:37:19,226 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [432298735] [2021-11-09 09:37:19,226 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:37:19,226 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:37:19,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:37:19,284 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:37:19,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:37:19,285 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:37:19,285 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:37:19,285 INFO L85 PathProgramCache]: Analyzing trace with hash 697667152, now seen corresponding path program 103 times [2021-11-09 09:37:19,285 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:37:19,285 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [979080440] [2021-11-09 09:37:19,285 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:37:19,285 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:37:19,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:37:23,420 INFO L134 CoverageAnalysis]: Checked inductivity of 5356 backedges. 0 proven. 5356 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:23,420 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:37:23,420 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [979080440] [2021-11-09 09:37:23,420 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [979080440] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:23,420 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2076094322] [2021-11-09 09:37:23,420 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:37:23,420 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:37:23,421 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:37:23,422 INFO L229 MonitoredProcess]: Starting monitored process 104 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:37:23,428 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (104)] Waiting until timeout for monitored process [2021-11-09 09:37:25,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:37:25,363 INFO L263 TraceCheckSpWp]: Trace formula consists of 317 conjuncts, 105 conjunts are in the unsatisfiable core [2021-11-09 09:37:25,365 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:37:25,710 INFO L134 CoverageAnalysis]: Checked inductivity of 5356 backedges. 0 proven. 5356 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:25,710 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2076094322] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:25,710 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:37:25,711 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [105, 105] total 105 [2021-11-09 09:37:25,711 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1407341558] [2021-11-09 09:37:25,711 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:37:25,711 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:37:25,713 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 106 interpolants. [2021-11-09 09:37:25,713 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5565, Invalid=5565, Unknown=0, NotChecked=0, Total=11130 [2021-11-09 09:37:25,713 INFO L87 Difference]: Start difference. First operand 107 states and 108 transitions. cyclomatic complexity: 2 Second operand has 106 states, 106 states have (on average 1.0) internal successors, (106), 105 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:37:25,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:37:25,852 INFO L93 Difference]: Finished difference Result 108 states and 109 transitions. [2021-11-09 09:37:25,853 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 106 states. [2021-11-09 09:37:25,853 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 108 states and 109 transitions. [2021-11-09 09:37:25,853 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 107 [2021-11-09 09:37:25,854 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 108 states to 108 states and 109 transitions. [2021-11-09 09:37:25,854 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 108 [2021-11-09 09:37:25,854 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 108 [2021-11-09 09:37:25,854 INFO L73 IsDeterministic]: Start isDeterministic. Operand 108 states and 109 transitions. [2021-11-09 09:37:25,854 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:37:25,854 INFO L681 BuchiCegarLoop]: Abstraction has 108 states and 109 transitions. [2021-11-09 09:37:25,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states and 109 transitions. [2021-11-09 09:37:25,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 108. [2021-11-09 09:37:25,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 108 states have (on average 1.0092592592592593) internal successors, (109), 107 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:37:25,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 109 transitions. [2021-11-09 09:37:25,856 INFO L704 BuchiCegarLoop]: Abstraction has 108 states and 109 transitions. [2021-11-09 09:37:25,857 INFO L587 BuchiCegarLoop]: Abstraction has 108 states and 109 transitions. [2021-11-09 09:37:25,857 INFO L425 BuchiCegarLoop]: ======== Iteration 105============ [2021-11-09 09:37:25,857 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108 states and 109 transitions. [2021-11-09 09:37:25,857 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 107 [2021-11-09 09:37:25,857 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:37:25,857 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:37:25,858 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:37:25,858 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [104, 1, 1, 1] [2021-11-09 09:37:25,858 INFO L791 eck$LassoCheckResult]: Stem: 34328#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 34325#L19-2 [2021-11-09 09:37:25,858 INFO L793 eck$LassoCheckResult]: Loop: 34325#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 34326#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34329#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34432#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34431#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34430#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34429#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34428#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34427#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34426#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34425#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34424#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34423#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34422#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34421#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34420#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34419#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34418#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34417#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34416#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34415#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34414#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34413#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34412#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34411#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34410#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34409#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34408#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34407#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34406#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34405#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34404#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34403#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34402#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34401#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34400#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34399#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34398#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34397#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34396#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34395#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34394#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34393#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34392#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34391#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34390#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34389#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34388#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34387#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34386#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34385#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34384#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34383#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34382#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34381#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34380#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34379#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34378#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34377#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34376#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34375#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34374#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34373#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34372#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34371#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34370#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34369#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34368#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34367#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34366#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34365#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34364#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34363#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34362#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34361#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34360#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34359#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34358#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34357#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34356#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34355#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34354#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34353#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34352#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34351#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34350#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34349#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34348#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34347#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34346#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34345#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34344#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34343#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34342#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34341#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34340#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34339#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34338#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34337#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34336#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34335#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34334#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34333#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34332#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34331#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34330#L21-2 assume !(main_~x2~0 > 1); 34327#L21-3 main_~x1~0 := 1 + main_~x1~0; 34325#L19-2 [2021-11-09 09:37:25,859 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:37:25,859 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 105 times [2021-11-09 09:37:25,859 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:37:25,859 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [134980544] [2021-11-09 09:37:25,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:37:25,859 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:37:25,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:37:25,970 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:37:25,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:37:25,970 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:37:25,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:37:25,971 INFO L85 PathProgramCache]: Analyzing trace with hash 152846991, now seen corresponding path program 104 times [2021-11-09 09:37:25,971 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:37:25,971 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [267904803] [2021-11-09 09:37:25,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:37:25,971 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:37:26,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:37:29,847 INFO L134 CoverageAnalysis]: Checked inductivity of 5460 backedges. 0 proven. 5460 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:29,847 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:37:29,847 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [267904803] [2021-11-09 09:37:29,847 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [267904803] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:29,847 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1926656510] [2021-11-09 09:37:29,848 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:37:29,848 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:37:29,848 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:37:29,849 INFO L229 MonitoredProcess]: Starting monitored process 105 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:37:29,850 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (105)] Waiting until timeout for monitored process [2021-11-09 09:37:31,720 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:37:31,720 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:37:31,723 INFO L263 TraceCheckSpWp]: Trace formula consists of 320 conjuncts, 106 conjunts are in the unsatisfiable core [2021-11-09 09:37:31,724 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:37:32,096 INFO L134 CoverageAnalysis]: Checked inductivity of 5460 backedges. 0 proven. 5460 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:32,097 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1926656510] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:32,097 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:37:32,097 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [106, 106] total 106 [2021-11-09 09:37:32,097 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1306463921] [2021-11-09 09:37:32,097 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:37:32,097 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:37:32,098 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 107 interpolants. [2021-11-09 09:37:32,099 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5671, Invalid=5671, Unknown=0, NotChecked=0, Total=11342 [2021-11-09 09:37:32,099 INFO L87 Difference]: Start difference. First operand 108 states and 109 transitions. cyclomatic complexity: 2 Second operand has 107 states, 107 states have (on average 1.0) internal successors, (107), 106 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:37:32,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:37:32,189 INFO L93 Difference]: Finished difference Result 109 states and 110 transitions. [2021-11-09 09:37:32,190 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 107 states. [2021-11-09 09:37:32,190 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 109 states and 110 transitions. [2021-11-09 09:37:32,190 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 108 [2021-11-09 09:37:32,190 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 109 states to 109 states and 110 transitions. [2021-11-09 09:37:32,190 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 109 [2021-11-09 09:37:32,190 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 109 [2021-11-09 09:37:32,191 INFO L73 IsDeterministic]: Start isDeterministic. Operand 109 states and 110 transitions. [2021-11-09 09:37:32,191 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:37:32,191 INFO L681 BuchiCegarLoop]: Abstraction has 109 states and 110 transitions. [2021-11-09 09:37:32,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states and 110 transitions. [2021-11-09 09:37:32,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 109. [2021-11-09 09:37:32,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 109 states, 109 states have (on average 1.0091743119266054) internal successors, (110), 108 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:37:32,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 110 transitions. [2021-11-09 09:37:32,193 INFO L704 BuchiCegarLoop]: Abstraction has 109 states and 110 transitions. [2021-11-09 09:37:32,194 INFO L587 BuchiCegarLoop]: Abstraction has 109 states and 110 transitions. [2021-11-09 09:37:32,194 INFO L425 BuchiCegarLoop]: ======== Iteration 106============ [2021-11-09 09:37:32,194 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 109 states and 110 transitions. [2021-11-09 09:37:32,194 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 108 [2021-11-09 09:37:32,194 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:37:32,194 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:37:32,195 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:37:32,195 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [105, 1, 1, 1] [2021-11-09 09:37:32,195 INFO L791 eck$LassoCheckResult]: Stem: 34973#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 34970#L19-2 [2021-11-09 09:37:32,195 INFO L793 eck$LassoCheckResult]: Loop: 34970#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 34971#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34974#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35078#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35077#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35076#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35075#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35074#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35073#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35072#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35071#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35070#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35069#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35068#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35067#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35066#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35065#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35064#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35063#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35062#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35061#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35060#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35059#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35058#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35057#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35056#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35055#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35054#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35053#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35052#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35051#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35050#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35049#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35048#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35047#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35046#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35045#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35044#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35043#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35042#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35041#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35040#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35039#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35038#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35037#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35036#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35035#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35034#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35033#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35032#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35031#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35030#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35029#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35028#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35027#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35026#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35025#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35024#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35023#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35022#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35021#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35020#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35019#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35018#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35017#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35016#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35015#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35014#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35013#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35012#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35011#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35010#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35009#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35008#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35007#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35006#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35005#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35004#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35003#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35002#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35001#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35000#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34999#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34998#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34997#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34996#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34995#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34994#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34993#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34992#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34991#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34990#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34989#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34988#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34987#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34986#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34985#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34984#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34983#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34982#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34981#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34980#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34979#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34978#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34977#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34976#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 34975#L21-2 assume !(main_~x2~0 > 1); 34972#L21-3 main_~x1~0 := 1 + main_~x1~0; 34970#L19-2 [2021-11-09 09:37:32,196 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:37:32,196 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 106 times [2021-11-09 09:37:32,196 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:37:32,196 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1022539055] [2021-11-09 09:37:32,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:37:32,197 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:37:32,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:37:32,268 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:37:32,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:37:32,269 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:37:32,269 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:37:32,269 INFO L85 PathProgramCache]: Analyzing trace with hash 443291184, now seen corresponding path program 105 times [2021-11-09 09:37:32,269 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:37:32,269 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1608205997] [2021-11-09 09:37:32,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:37:32,270 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:37:32,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:37:36,406 INFO L134 CoverageAnalysis]: Checked inductivity of 5565 backedges. 0 proven. 5565 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:36,406 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:37:36,406 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1608205997] [2021-11-09 09:37:36,407 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1608205997] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:36,407 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1740097891] [2021-11-09 09:37:36,407 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:37:36,407 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:37:36,407 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:37:36,408 INFO L229 MonitoredProcess]: Starting monitored process 106 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:37:36,409 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (106)] Waiting until timeout for monitored process [2021-11-09 09:37:38,356 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 54 check-sat command(s) [2021-11-09 09:37:38,356 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:37:38,359 INFO L263 TraceCheckSpWp]: Trace formula consists of 323 conjuncts, 107 conjunts are in the unsatisfiable core [2021-11-09 09:37:38,360 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:37:38,783 INFO L134 CoverageAnalysis]: Checked inductivity of 5565 backedges. 0 proven. 5565 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:38,784 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1740097891] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:38,784 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:37:38,784 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [107, 107] total 107 [2021-11-09 09:37:38,784 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1108929661] [2021-11-09 09:37:38,785 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:37:38,785 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:37:38,785 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 108 interpolants. [2021-11-09 09:37:38,786 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5778, Invalid=5778, Unknown=0, NotChecked=0, Total=11556 [2021-11-09 09:37:38,786 INFO L87 Difference]: Start difference. First operand 109 states and 110 transitions. cyclomatic complexity: 2 Second operand has 108 states, 108 states have (on average 1.0) internal successors, (108), 107 states have internal predecessors, (108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:37:38,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:37:38,883 INFO L93 Difference]: Finished difference Result 110 states and 111 transitions. [2021-11-09 09:37:38,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 108 states. [2021-11-09 09:37:38,883 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 110 states and 111 transitions. [2021-11-09 09:37:38,883 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 109 [2021-11-09 09:37:38,884 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 110 states to 110 states and 111 transitions. [2021-11-09 09:37:38,884 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 110 [2021-11-09 09:37:38,884 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 110 [2021-11-09 09:37:38,884 INFO L73 IsDeterministic]: Start isDeterministic. Operand 110 states and 111 transitions. [2021-11-09 09:37:38,884 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:37:38,884 INFO L681 BuchiCegarLoop]: Abstraction has 110 states and 111 transitions. [2021-11-09 09:37:38,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110 states and 111 transitions. [2021-11-09 09:37:38,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110 to 110. [2021-11-09 09:37:38,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 110 states, 110 states have (on average 1.009090909090909) internal successors, (111), 109 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:37:38,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 111 transitions. [2021-11-09 09:37:38,885 INFO L704 BuchiCegarLoop]: Abstraction has 110 states and 111 transitions. [2021-11-09 09:37:38,885 INFO L587 BuchiCegarLoop]: Abstraction has 110 states and 111 transitions. [2021-11-09 09:37:38,885 INFO L425 BuchiCegarLoop]: ======== Iteration 107============ [2021-11-09 09:37:38,885 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 110 states and 111 transitions. [2021-11-09 09:37:38,885 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 109 [2021-11-09 09:37:38,885 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:37:38,886 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:37:38,886 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:37:38,886 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [106, 1, 1, 1] [2021-11-09 09:37:38,886 INFO L791 eck$LassoCheckResult]: Stem: 35624#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 35621#L19-2 [2021-11-09 09:37:38,886 INFO L793 eck$LassoCheckResult]: Loop: 35621#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 35622#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35625#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35730#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35729#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35728#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35727#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35726#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35725#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35724#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35723#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35722#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35721#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35720#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35719#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35718#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35717#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35716#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35715#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35714#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35713#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35712#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35711#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35710#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35709#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35708#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35707#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35706#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35705#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35704#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35703#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35702#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35701#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35700#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35699#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35698#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35697#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35696#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35695#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35694#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35693#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35692#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35691#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35690#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35689#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35688#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35687#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35686#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35685#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35684#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35683#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35682#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35681#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35680#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35679#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35678#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35677#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35676#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35675#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35674#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35673#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35672#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35671#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35670#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35669#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35668#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35667#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35666#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35665#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35664#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35663#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35662#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35661#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35660#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35659#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35658#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35657#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35656#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35655#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35654#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35653#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35652#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35651#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35650#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35649#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35648#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35647#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35646#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35645#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35644#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35643#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35642#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35641#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35640#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35639#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35638#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35637#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35636#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35635#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35634#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35633#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35632#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35631#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35630#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35629#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35628#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35627#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 35626#L21-2 assume !(main_~x2~0 > 1); 35623#L21-3 main_~x1~0 := 1 + main_~x1~0; 35621#L19-2 [2021-11-09 09:37:38,886 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:37:38,886 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 107 times [2021-11-09 09:37:38,886 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:37:38,886 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [919082122] [2021-11-09 09:37:38,886 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:37:38,887 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:37:38,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:37:38,901 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:37:38,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:37:38,901 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:37:38,902 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:37:38,902 INFO L85 PathProgramCache]: Analyzing trace with hash 857126575, now seen corresponding path program 106 times [2021-11-09 09:37:38,902 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:37:38,902 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [282130624] [2021-11-09 09:37:38,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:37:38,902 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:37:38,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:37:42,959 INFO L134 CoverageAnalysis]: Checked inductivity of 5671 backedges. 0 proven. 5671 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:42,959 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:37:42,959 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [282130624] [2021-11-09 09:37:42,959 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [282130624] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:42,959 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1753334822] [2021-11-09 09:37:42,959 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:37:42,959 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:37:42,959 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:37:42,961 INFO L229 MonitoredProcess]: Starting monitored process 107 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:37:42,961 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (107)] Waiting until timeout for monitored process [2021-11-09 09:37:44,932 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:37:44,932 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:37:44,934 INFO L263 TraceCheckSpWp]: Trace formula consists of 326 conjuncts, 108 conjunts are in the unsatisfiable core [2021-11-09 09:37:44,935 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:37:45,260 INFO L134 CoverageAnalysis]: Checked inductivity of 5671 backedges. 0 proven. 5671 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:45,260 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1753334822] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:45,260 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:37:45,260 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [108, 108] total 108 [2021-11-09 09:37:45,260 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [921652140] [2021-11-09 09:37:45,260 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:37:45,261 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:37:45,262 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 109 interpolants. [2021-11-09 09:37:45,262 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5886, Invalid=5886, Unknown=0, NotChecked=0, Total=11772 [2021-11-09 09:37:45,263 INFO L87 Difference]: Start difference. First operand 110 states and 111 transitions. cyclomatic complexity: 2 Second operand has 109 states, 109 states have (on average 1.0) internal successors, (109), 108 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:37:45,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:37:45,359 INFO L93 Difference]: Finished difference Result 111 states and 112 transitions. [2021-11-09 09:37:45,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 109 states. [2021-11-09 09:37:45,359 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 111 states and 112 transitions. [2021-11-09 09:37:45,359 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 110 [2021-11-09 09:37:45,359 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 111 states to 111 states and 112 transitions. [2021-11-09 09:37:45,360 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 111 [2021-11-09 09:37:45,360 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 111 [2021-11-09 09:37:45,360 INFO L73 IsDeterministic]: Start isDeterministic. Operand 111 states and 112 transitions. [2021-11-09 09:37:45,360 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:37:45,360 INFO L681 BuchiCegarLoop]: Abstraction has 111 states and 112 transitions. [2021-11-09 09:37:45,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states and 112 transitions. [2021-11-09 09:37:45,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 111. [2021-11-09 09:37:45,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 111 states, 111 states have (on average 1.009009009009009) internal successors, (112), 110 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:37:45,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 112 transitions. [2021-11-09 09:37:45,362 INFO L704 BuchiCegarLoop]: Abstraction has 111 states and 112 transitions. [2021-11-09 09:37:45,362 INFO L587 BuchiCegarLoop]: Abstraction has 111 states and 112 transitions. [2021-11-09 09:37:45,362 INFO L425 BuchiCegarLoop]: ======== Iteration 108============ [2021-11-09 09:37:45,362 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 111 states and 112 transitions. [2021-11-09 09:37:45,362 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 110 [2021-11-09 09:37:45,362 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:37:45,362 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:37:45,363 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:37:45,363 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [107, 1, 1, 1] [2021-11-09 09:37:45,363 INFO L791 eck$LassoCheckResult]: Stem: 36281#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 36278#L19-2 [2021-11-09 09:37:45,363 INFO L793 eck$LassoCheckResult]: Loop: 36278#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 36279#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36282#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36388#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36387#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36386#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36385#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36384#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36383#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36382#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36381#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36380#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36379#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36378#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36377#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36376#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36375#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36374#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36373#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36372#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36371#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36370#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36369#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36368#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36367#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36366#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36365#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36364#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36363#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36362#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36361#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36360#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36359#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36358#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36357#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36356#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36355#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36354#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36353#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36352#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36351#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36350#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36349#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36348#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36347#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36346#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36345#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36344#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36343#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36342#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36341#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36340#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36339#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36338#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36337#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36336#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36335#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36334#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36333#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36332#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36331#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36330#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36329#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36328#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36327#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36326#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36325#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36324#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36323#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36322#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36321#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36320#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36319#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36318#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36317#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36316#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36315#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36314#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36313#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36312#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36311#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36310#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36309#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36308#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36307#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36306#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36305#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36304#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36303#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36302#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36301#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36300#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36299#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36298#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36297#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36296#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36295#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36294#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36293#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36292#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36291#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36290#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36289#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36288#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36287#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36286#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36285#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36284#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36283#L21-2 assume !(main_~x2~0 > 1); 36280#L21-3 main_~x1~0 := 1 + main_~x1~0; 36278#L19-2 [2021-11-09 09:37:45,363 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:37:45,363 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 108 times [2021-11-09 09:37:45,363 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:37:45,363 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1422869696] [2021-11-09 09:37:45,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:37:45,364 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:37:45,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:37:45,382 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:37:45,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:37:45,383 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:37:45,383 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:37:45,383 INFO L85 PathProgramCache]: Analyzing trace with hash 801121808, now seen corresponding path program 107 times [2021-11-09 09:37:45,383 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:37:45,383 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1368563514] [2021-11-09 09:37:45,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:37:45,384 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:37:45,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:37:49,550 INFO L134 CoverageAnalysis]: Checked inductivity of 5778 backedges. 0 proven. 5778 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:49,551 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:37:49,551 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1368563514] [2021-11-09 09:37:49,551 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1368563514] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:49,551 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1353054895] [2021-11-09 09:37:49,551 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:37:49,551 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:37:49,552 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:37:49,553 INFO L229 MonitoredProcess]: Starting monitored process 108 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:37:49,554 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (108)] Waiting until timeout for monitored process [2021-11-09 09:37:51,747 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 55 check-sat command(s) [2021-11-09 09:37:51,747 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:37:51,752 INFO L263 TraceCheckSpWp]: Trace formula consists of 329 conjuncts, 109 conjunts are in the unsatisfiable core [2021-11-09 09:37:51,754 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:37:52,073 INFO L134 CoverageAnalysis]: Checked inductivity of 5778 backedges. 0 proven. 5778 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:52,073 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1353054895] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:52,073 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:37:52,073 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [109, 109] total 109 [2021-11-09 09:37:52,073 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1351236692] [2021-11-09 09:37:52,074 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:37:52,074 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:37:52,075 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 110 interpolants. [2021-11-09 09:37:52,075 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5995, Invalid=5995, Unknown=0, NotChecked=0, Total=11990 [2021-11-09 09:37:52,075 INFO L87 Difference]: Start difference. First operand 111 states and 112 transitions. cyclomatic complexity: 2 Second operand has 110 states, 110 states have (on average 1.0) internal successors, (110), 109 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:37:52,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:37:52,176 INFO L93 Difference]: Finished difference Result 112 states and 113 transitions. [2021-11-09 09:37:52,176 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 110 states. [2021-11-09 09:37:52,177 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 112 states and 113 transitions. [2021-11-09 09:37:52,177 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 111 [2021-11-09 09:37:52,177 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 112 states to 112 states and 113 transitions. [2021-11-09 09:37:52,177 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 112 [2021-11-09 09:37:52,177 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 112 [2021-11-09 09:37:52,177 INFO L73 IsDeterministic]: Start isDeterministic. Operand 112 states and 113 transitions. [2021-11-09 09:37:52,178 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:37:52,178 INFO L681 BuchiCegarLoop]: Abstraction has 112 states and 113 transitions. [2021-11-09 09:37:52,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states and 113 transitions. [2021-11-09 09:37:52,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 112. [2021-11-09 09:37:52,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 112 states, 112 states have (on average 1.0089285714285714) internal successors, (113), 111 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:37:52,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 113 transitions. [2021-11-09 09:37:52,179 INFO L704 BuchiCegarLoop]: Abstraction has 112 states and 113 transitions. [2021-11-09 09:37:52,179 INFO L587 BuchiCegarLoop]: Abstraction has 112 states and 113 transitions. [2021-11-09 09:37:52,179 INFO L425 BuchiCegarLoop]: ======== Iteration 109============ [2021-11-09 09:37:52,179 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 112 states and 113 transitions. [2021-11-09 09:37:52,179 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 111 [2021-11-09 09:37:52,179 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:37:52,179 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:37:52,180 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:37:52,180 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [108, 1, 1, 1] [2021-11-09 09:37:52,180 INFO L791 eck$LassoCheckResult]: Stem: 36944#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 36941#L19-2 [2021-11-09 09:37:52,180 INFO L793 eck$LassoCheckResult]: Loop: 36941#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 36942#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36945#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37052#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37051#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37050#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37049#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37048#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37047#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37046#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37045#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37044#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37043#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37042#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37041#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37040#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37039#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37038#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37037#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37036#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37035#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37034#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37033#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37032#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37031#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37030#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37029#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37028#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37027#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37026#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37025#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37024#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37023#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37022#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37021#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37020#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37019#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37018#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37017#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37016#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37015#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37014#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37013#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37012#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37011#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37010#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37009#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37008#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37007#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37006#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37005#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37004#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37003#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37002#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37001#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37000#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36999#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36998#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36997#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36996#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36995#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36994#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36993#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36992#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36991#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36990#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36989#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36988#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36987#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36986#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36985#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36984#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36983#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36982#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36981#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36980#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36979#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36978#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36977#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36976#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36975#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36974#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36973#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36972#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36971#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36970#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36969#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36968#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36967#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36966#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36965#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36964#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36963#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36962#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36961#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36960#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36959#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36958#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36957#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36956#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36955#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36954#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36953#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36952#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36951#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36950#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36949#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36948#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36947#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 36946#L21-2 assume !(main_~x2~0 > 1); 36943#L21-3 main_~x1~0 := 1 + main_~x1~0; 36941#L19-2 [2021-11-09 09:37:52,180 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:37:52,180 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 109 times [2021-11-09 09:37:52,181 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:37:52,181 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [53721848] [2021-11-09 09:37:52,181 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:37:52,181 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:37:52,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:37:52,239 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:37:52,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:37:52,240 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:37:52,240 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:37:52,240 INFO L85 PathProgramCache]: Analyzing trace with hash -935025969, now seen corresponding path program 108 times [2021-11-09 09:37:52,240 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:37:52,240 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1160260644] [2021-11-09 09:37:52,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:37:52,240 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:37:52,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:37:56,760 INFO L134 CoverageAnalysis]: Checked inductivity of 5886 backedges. 0 proven. 5886 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:56,760 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:37:56,760 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1160260644] [2021-11-09 09:37:56,760 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1160260644] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:56,760 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1012188516] [2021-11-09 09:37:56,760 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:37:56,760 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:37:56,760 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:37:56,766 INFO L229 MonitoredProcess]: Starting monitored process 109 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:37:56,780 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_64da1232-e26e-4ae6-adcf-fbf71245add3/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (109)] Waiting until timeout for monitored process [2021-11-09 09:37:59,643 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 55 check-sat command(s) [2021-11-09 09:37:59,643 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:37:59,646 INFO L263 TraceCheckSpWp]: Trace formula consists of 332 conjuncts, 110 conjunts are in the unsatisfiable core [2021-11-09 09:37:59,648 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:37:59,961 INFO L134 CoverageAnalysis]: Checked inductivity of 5886 backedges. 0 proven. 5886 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:37:59,962 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1012188516] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:37:59,962 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:37:59,962 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [110, 110] total 110 [2021-11-09 09:37:59,962 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1863441697] [2021-11-09 09:37:59,963 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:37:59,963 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:37:59,967 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 111 interpolants. [2021-11-09 09:37:59,968 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=6105, Invalid=6105, Unknown=0, NotChecked=0, Total=12210 [2021-11-09 09:37:59,969 INFO L87 Difference]: Start difference. First operand 112 states and 113 transitions. cyclomatic complexity: 2 Second operand has 111 states, 111 states have (on average 1.0) internal successors, (111), 110 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:38:00,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:38:00,172 INFO L93 Difference]: Finished difference Result 113 states and 114 transitions. [2021-11-09 09:38:00,172 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 111 states. [2021-11-09 09:38:00,172 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 113 states and 114 transitions. [2021-11-09 09:38:00,173 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 112 [2021-11-09 09:38:00,186 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 113 states to 113 states and 114 transitions. [2021-11-09 09:38:00,186 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 113 [2021-11-09 09:38:00,186 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 113 [2021-11-09 09:38:00,194 INFO L73 IsDeterministic]: Start isDeterministic. Operand 113 states and 114 transitions. [2021-11-09 09:38:00,194 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:38:00,194 INFO L681 BuchiCegarLoop]: Abstraction has 113 states and 114 transitions. [2021-11-09 09:38:00,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states and 114 transitions. [2021-11-09 09:38:00,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 113. [2021-11-09 09:38:00,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 113 states, 113 states have (on average 1.008849557522124) internal successors, (114), 112 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:38:00,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 114 transitions. [2021-11-09 09:38:00,196 INFO L704 BuchiCegarLoop]: Abstraction has 113 states and 114 transitions. [2021-11-09 09:38:00,196 INFO L587 BuchiCegarLoop]: Abstraction has 113 states and 114 transitions. [2021-11-09 09:38:00,196 INFO L425 BuchiCegarLoop]: ======== Iteration 110============ [2021-11-09 09:38:00,197 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 113 states and 114 transitions. [2021-11-09 09:38:00,197 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 112 [2021-11-09 09:38:00,197 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:38:00,197 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:38:00,198 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1] [2021-11-09 09:38:00,198 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [109, 1, 1, 1] [2021-11-09 09:38:00,198 INFO L791 eck$LassoCheckResult]: Stem: 37613#ULTIMATE.startENTRY havoc main_#res;havoc main_#t~nondet0, main_#t~nondet1, main_~x1~0, main_~x2~0;havoc main_~x1~0;havoc main_~x2~0;main_~x1~0 := main_#t~nondet0;havoc main_#t~nondet0;main_~x2~0 := main_#t~nondet1;havoc main_#t~nondet1; 37610#L19-2 [2021-11-09 09:38:00,198 INFO L793 eck$LassoCheckResult]: Loop: 37610#L19-2 assume !!(main_~x1~0 <= 10);main_~x2~0 := 1000; 37611#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37614#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37722#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37721#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37720#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37719#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37718#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37717#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37716#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37715#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37714#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37713#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37712#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37711#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37710#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37709#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37708#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37707#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37706#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37705#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37704#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37703#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37702#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37701#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37700#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37699#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37698#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37697#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37696#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37695#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37694#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37693#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37692#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37691#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37690#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37689#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37688#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37687#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37686#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37685#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37684#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37683#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37682#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37681#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37680#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37679#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37678#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37677#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37676#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37675#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37674#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37673#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37672#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37671#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37670#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37669#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37668#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37667#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37666#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37665#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37664#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37663#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37662#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37661#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37660#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37659#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37658#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37657#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37656#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37655#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37654#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37653#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37652#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37651#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37650#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37649#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37648#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37647#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37646#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37645#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37644#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37643#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37642#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37641#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37640#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37639#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37638#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37637#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37636#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37635#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37634#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37633#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37632#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37631#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37630#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37629#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37628#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37627#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37626#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37625#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37624#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37623#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37622#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37621#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37620#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37619#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37618#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37617#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37616#L21-2 assume !!(main_~x2~0 > 1);main_~x2~0 := main_~x2~0 - 1; 37615#L21-2 assume !(main_~x2~0 > 1); 37612#L21-3 main_~x1~0 := 1 + main_~x1~0; 37610#L19-2 [2021-11-09 09:38:00,198 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:38:00,199 INFO L85 PathProgramCache]: Analyzing trace with hash 32, now seen corresponding path program 110 times [2021-11-09 09:38:00,199 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:38:00,199 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1806422581] [2021-11-09 09:38:00,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:38:00,199 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:38:00,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:38:00,234 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:38:00,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:38:00,235 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:38:00,235 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:38:00,236 INFO L85 PathProgramCache]: Analyzing trace with hash 1078967792, now seen corresponding path program 109 times [2021-11-09 09:38:00,236 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:38:00,236 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [794517645] [2021-11-09 09:38:00,236 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:38:00,236 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:38:00,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat