./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/loop-acceleration/array_4.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f8e1c903 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/loop-acceleration/array_4.i -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e8c27e61ac5d5a22c0e00a5dbac1b872460567877a501387ed9d5bda89096498 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-f8e1c90 [2021-11-09 09:50:19,234 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-09 09:50:19,238 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-09 09:50:19,286 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-09 09:50:19,287 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-09 09:50:19,288 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-09 09:50:19,290 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-09 09:50:19,293 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-09 09:50:19,295 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-09 09:50:19,297 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-09 09:50:19,298 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-09 09:50:19,300 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-09 09:50:19,300 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-09 09:50:19,302 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-09 09:50:19,303 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-09 09:50:19,305 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-09 09:50:19,306 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-09 09:50:19,307 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-09 09:50:19,310 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-09 09:50:19,312 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-09 09:50:19,315 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-09 09:50:19,320 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-09 09:50:19,322 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-09 09:50:19,323 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-09 09:50:19,332 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-09 09:50:19,335 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-09 09:50:19,336 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-09 09:50:19,337 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-09 09:50:19,339 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-09 09:50:19,340 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-09 09:50:19,341 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-09 09:50:19,342 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-09 09:50:19,344 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-09 09:50:19,346 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-09 09:50:19,348 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-09 09:50:19,348 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-09 09:50:19,349 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-09 09:50:19,349 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-09 09:50:19,350 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-09 09:50:19,351 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-09 09:50:19,351 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-09 09:50:19,352 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-09 09:50:19,402 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-09 09:50:19,403 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-09 09:50:19,403 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-09 09:50:19,403 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-09 09:50:19,404 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-09 09:50:19,404 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-09 09:50:19,405 INFO L138 SettingsManager]: * Use SBE=true [2021-11-09 09:50:19,407 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-09 09:50:19,408 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-09 09:50:19,408 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-09 09:50:19,409 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-09 09:50:19,409 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-09 09:50:19,410 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-09 09:50:19,410 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-09 09:50:19,410 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-09 09:50:19,410 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-09 09:50:19,411 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-09 09:50:19,411 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-09 09:50:19,411 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-09 09:50:19,411 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-09 09:50:19,412 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-09 09:50:19,412 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-09 09:50:19,412 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-09 09:50:19,412 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-09 09:50:19,413 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-09 09:50:19,413 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-09 09:50:19,414 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-09 09:50:19,415 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-09 09:50:19,415 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-09 09:50:19,415 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-09 09:50:19,416 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-09 09:50:19,416 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-09 09:50:19,417 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-09 09:50:19,418 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e8c27e61ac5d5a22c0e00a5dbac1b872460567877a501387ed9d5bda89096498 [2021-11-09 09:50:19,691 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-09 09:50:19,713 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-09 09:50:19,716 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-09 09:50:19,718 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-09 09:50:19,719 INFO L275 PluginConnector]: CDTParser initialized [2021-11-09 09:50:19,720 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/../../sv-benchmarks/c/loop-acceleration/array_4.i [2021-11-09 09:50:19,795 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/data/bbe51cc67/f3420f31e739448f93c350a4904d385c/FLAG2c9c9e95b [2021-11-09 09:50:20,242 INFO L306 CDTParser]: Found 1 translation units. [2021-11-09 09:50:20,242 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/sv-benchmarks/c/loop-acceleration/array_4.i [2021-11-09 09:50:20,248 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/data/bbe51cc67/f3420f31e739448f93c350a4904d385c/FLAG2c9c9e95b [2021-11-09 09:50:20,641 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/data/bbe51cc67/f3420f31e739448f93c350a4904d385c [2021-11-09 09:50:20,648 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-09 09:50:20,650 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-09 09:50:20,651 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-09 09:50:20,651 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-09 09:50:20,655 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-09 09:50:20,656 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 09:50:20" (1/1) ... [2021-11-09 09:50:20,659 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@764988cb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:50:20, skipping insertion in model container [2021-11-09 09:50:20,659 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 09:50:20" (1/1) ... [2021-11-09 09:50:20,667 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-09 09:50:20,682 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-09 09:50:20,856 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/sv-benchmarks/c/loop-acceleration/array_4.i[848,861] [2021-11-09 09:50:20,867 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-09 09:50:20,874 INFO L203 MainTranslator]: Completed pre-run [2021-11-09 09:50:20,886 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/sv-benchmarks/c/loop-acceleration/array_4.i[848,861] [2021-11-09 09:50:20,891 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-09 09:50:20,905 INFO L208 MainTranslator]: Completed translation [2021-11-09 09:50:20,905 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:50:20 WrapperNode [2021-11-09 09:50:20,906 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-09 09:50:20,907 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-09 09:50:20,907 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-09 09:50:20,907 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-09 09:50:20,918 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:50:20" (1/1) ... [2021-11-09 09:50:20,927 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:50:20" (1/1) ... [2021-11-09 09:50:20,957 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-09 09:50:20,958 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-09 09:50:20,958 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-09 09:50:20,958 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-09 09:50:20,966 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:50:20" (1/1) ... [2021-11-09 09:50:20,967 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:50:20" (1/1) ... [2021-11-09 09:50:20,981 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:50:20" (1/1) ... [2021-11-09 09:50:20,982 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:50:20" (1/1) ... [2021-11-09 09:50:20,987 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:50:20" (1/1) ... [2021-11-09 09:50:20,991 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:50:20" (1/1) ... [2021-11-09 09:50:20,992 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:50:20" (1/1) ... [2021-11-09 09:50:21,002 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-09 09:50:21,003 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-09 09:50:21,004 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-09 09:50:21,004 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-09 09:50:21,006 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:50:20" (1/1) ... [2021-11-09 09:50:21,014 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:50:21,025 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:21,043 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:50:21,068 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-09 09:50:21,105 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-09 09:50:21,105 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-09 09:50:21,106 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2021-11-09 09:50:21,106 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-09 09:50:21,106 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-09 09:50:21,106 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2021-11-09 09:50:21,106 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2021-11-09 09:50:21,357 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-09 09:50:21,357 INFO L299 CfgBuilder]: Removed 8 assume(true) statements. [2021-11-09 09:50:21,359 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 09:50:21 BoogieIcfgContainer [2021-11-09 09:50:21,359 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-09 09:50:21,360 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-09 09:50:21,361 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-09 09:50:21,364 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-09 09:50:21,365 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-09 09:50:21,365 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 09.11 09:50:20" (1/3) ... [2021-11-09 09:50:21,366 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6394399b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 09:50:21, skipping insertion in model container [2021-11-09 09:50:21,367 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-09 09:50:21,367 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:50:20" (2/3) ... [2021-11-09 09:50:21,367 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6394399b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 09:50:21, skipping insertion in model container [2021-11-09 09:50:21,368 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-09 09:50:21,368 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 09:50:21" (3/3) ... [2021-11-09 09:50:21,369 INFO L389 chiAutomizerObserver]: Analyzing ICFG array_4.i [2021-11-09 09:50:21,416 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-09 09:50:21,417 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-09 09:50:21,418 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-09 09:50:21,418 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-09 09:50:21,418 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-09 09:50:21,418 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-09 09:50:21,419 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-09 09:50:21,419 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-09 09:50:21,470 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 14 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:21,489 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2021-11-09 09:50:21,490 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:21,490 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:21,496 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1] [2021-11-09 09:50:21,496 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-09 09:50:21,496 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-09 09:50:21,497 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 15 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 14 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:21,499 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2021-11-09 09:50:21,499 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:21,499 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:21,500 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1] [2021-11-09 09:50:21,500 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1] [2021-11-09 09:50:21,507 INFO L791 eck$LassoCheckResult]: Stem: 6#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 8#L-1true havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 7#L25-3true [2021-11-09 09:50:21,507 INFO L793 eck$LassoCheckResult]: Loop: 7#L25-3true assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10#L25-2true main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7#L25-3true [2021-11-09 09:50:21,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:21,514 INFO L85 PathProgramCache]: Analyzing trace with hash 963, now seen corresponding path program 1 times [2021-11-09 09:50:21,524 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:21,524 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2087343006] [2021-11-09 09:50:21,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:21,526 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:21,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:21,637 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:21,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:21,689 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:21,692 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:21,693 INFO L85 PathProgramCache]: Analyzing trace with hash 1283, now seen corresponding path program 1 times [2021-11-09 09:50:21,693 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:21,693 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [649213500] [2021-11-09 09:50:21,694 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:21,694 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:21,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:21,705 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:21,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:21,724 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:21,726 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:21,726 INFO L85 PathProgramCache]: Analyzing trace with hash 925765, now seen corresponding path program 1 times [2021-11-09 09:50:21,727 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:21,727 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [239158927] [2021-11-09 09:50:21,727 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:21,727 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:21,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:21,775 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:21,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:21,813 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:22,254 INFO L210 LassoAnalysis]: Preferences: [2021-11-09 09:50:22,255 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2021-11-09 09:50:22,255 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2021-11-09 09:50:22,255 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2021-11-09 09:50:22,256 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2021-11-09 09:50:22,256 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:50:22,256 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2021-11-09 09:50:22,256 INFO L132 ssoRankerPreferences]: Path of dumped script: [2021-11-09 09:50:22,256 INFO L133 ssoRankerPreferences]: Filename of dumped script: array_4.i_Iteration1_Lasso [2021-11-09 09:50:22,257 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2021-11-09 09:50:22,257 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2021-11-09 09:50:22,277 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-09 09:50:22,283 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-09 09:50:22,287 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-09 09:50:22,290 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-09 09:50:22,292 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-09 09:50:22,443 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-09 09:50:22,451 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-09 09:50:22,454 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2021-11-09 09:50:22,716 INFO L294 LassoAnalysis]: Preprocessing complete. [2021-11-09 09:50:22,721 INFO L490 LassoAnalysis]: Using template 'affine'. [2021-11-09 09:50:22,723 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:50:22,724 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:22,729 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:50:22,738 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-09 09:50:22,748 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-09 09:50:22,748 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-09 09:50:22,748 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-09 09:50:22,749 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-09 09:50:22,749 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-09 09:50:22,751 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-09 09:50:22,752 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-09 09:50:22,753 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2021-11-09 09:50:22,762 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-09 09:50:22,799 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2021-11-09 09:50:22,800 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:50:22,800 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:22,801 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:50:22,813 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-09 09:50:22,822 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-09 09:50:22,823 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-09 09:50:22,823 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-09 09:50:22,823 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-09 09:50:22,823 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2021-11-09 09:50:22,828 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-09 09:50:22,828 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-09 09:50:22,841 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-09 09:50:22,880 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2021-11-09 09:50:22,880 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:50:22,880 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:22,882 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:50:22,889 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-09 09:50:22,898 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-09 09:50:22,899 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-09 09:50:22,899 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-09 09:50:22,899 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-09 09:50:22,899 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-09 09:50:22,900 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-09 09:50:22,901 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-09 09:50:22,902 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2021-11-09 09:50:22,917 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-09 09:50:22,952 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2021-11-09 09:50:22,952 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:50:22,953 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:22,954 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:50:22,960 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-09 09:50:22,969 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-09 09:50:22,969 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-09 09:50:22,970 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-09 09:50:22,970 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-09 09:50:22,970 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-09 09:50:22,970 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-09 09:50:22,971 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-09 09:50:22,972 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2021-11-09 09:50:22,985 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-09 09:50:23,021 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2021-11-09 09:50:23,022 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:50:23,022 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:23,024 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:50:23,027 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2021-11-09 09:50:23,028 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-09 09:50:23,038 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-09 09:50:23,038 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-09 09:50:23,038 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-09 09:50:23,039 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-09 09:50:23,042 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-09 09:50:23,043 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-09 09:50:23,055 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-09 09:50:23,089 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2021-11-09 09:50:23,090 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:50:23,090 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:23,091 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:50:23,102 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-09 09:50:23,102 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2021-11-09 09:50:23,109 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-09 09:50:23,109 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-09 09:50:23,109 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-09 09:50:23,110 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-09 09:50:23,113 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-09 09:50:23,113 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-09 09:50:23,129 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-09 09:50:23,163 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2021-11-09 09:50:23,163 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:50:23,163 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:23,166 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:50:23,174 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-09 09:50:23,183 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-09 09:50:23,183 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-09 09:50:23,183 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-09 09:50:23,184 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-09 09:50:23,186 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-09 09:50:23,187 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-09 09:50:23,190 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2021-11-09 09:50:23,197 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-09 09:50:23,233 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2021-11-09 09:50:23,234 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:50:23,234 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:23,235 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:50:23,242 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-09 09:50:23,242 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2021-11-09 09:50:23,250 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-09 09:50:23,250 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2021-11-09 09:50:23,250 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-09 09:50:23,250 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-09 09:50:23,250 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-09 09:50:23,251 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2021-11-09 09:50:23,251 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2021-11-09 09:50:23,253 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-09 09:50:23,272 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2021-11-09 09:50:23,272 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:50:23,273 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:23,274 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:50:23,275 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2021-11-09 09:50:23,275 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-09 09:50:23,282 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-09 09:50:23,283 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-09 09:50:23,283 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-09 09:50:23,283 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-09 09:50:23,288 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-09 09:50:23,297 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-09 09:50:23,313 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2021-11-09 09:50:23,350 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2021-11-09 09:50:23,350 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:50:23,350 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:23,354 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:50:23,356 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2021-11-09 09:50:23,365 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2021-11-09 09:50:23,366 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2021-11-09 09:50:23,366 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2021-11-09 09:50:23,366 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2021-11-09 09:50:23,371 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2021-11-09 09:50:23,372 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2021-11-09 09:50:23,380 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2021-11-09 09:50:23,389 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2021-11-09 09:50:23,423 INFO L443 ModelExtractionUtils]: Simplification made 10 calls to the SMT solver. [2021-11-09 09:50:23,423 INFO L444 ModelExtractionUtils]: 0 out of 13 variables were initially zero. Simplification set additionally 10 variables to zero. [2021-11-09 09:50:23,425 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:50:23,425 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:23,436 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:50:23,467 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2021-11-09 09:50:23,467 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2021-11-09 09:50:23,491 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2021-11-09 09:50:23,491 INFO L513 LassoAnalysis]: Proved termination. [2021-11-09 09:50:23,492 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~i~0, v_rep(select #length ULTIMATE.start_main_~#A~0.base)_1) = -8*ULTIMATE.start_main_~i~0 + 2045*v_rep(select #length ULTIMATE.start_main_~#A~0.base)_1 Supporting invariants [] [2021-11-09 09:50:23,529 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2021-11-09 09:50:23,551 INFO L297 tatePredicateManager]: 7 out of 7 supporting invariants were superfluous and have been removed [2021-11-09 09:50:23,574 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:23,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:23,591 INFO L263 TraceCheckSpWp]: Trace formula consists of 35 conjuncts, 2 conjunts are in the unsatisfiable core [2021-11-09 09:50:23,593 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:23,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:23,609 WARN L261 TraceCheckSpWp]: Trace formula consists of 10 conjuncts, 6 conjunts are in the unsatisfiable core [2021-11-09 09:50:23,610 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:23,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:23,677 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2021-11-09 09:50:23,678 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 14 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:23,734 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 15 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 14 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 29 states and 39 transitions. Complement of second has 8 states. [2021-11-09 09:50:23,735 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 5 states 1 stem states 2 non-accepting loop states 1 accepting loop states [2021-11-09 09:50:23,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:23,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 19 transitions. [2021-11-09 09:50:23,745 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 19 transitions. Stem has 2 letters. Loop has 2 letters. [2021-11-09 09:50:23,746 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-09 09:50:23,746 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 19 transitions. Stem has 4 letters. Loop has 2 letters. [2021-11-09 09:50:23,746 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-09 09:50:23,746 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 5 states and 19 transitions. Stem has 2 letters. Loop has 4 letters. [2021-11-09 09:50:23,747 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2021-11-09 09:50:23,748 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29 states and 39 transitions. [2021-11-09 09:50:23,755 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:23,759 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29 states to 9 states and 11 transitions. [2021-11-09 09:50:23,760 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6 [2021-11-09 09:50:23,760 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7 [2021-11-09 09:50:23,760 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9 states and 11 transitions. [2021-11-09 09:50:23,761 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:23,761 INFO L681 BuchiCegarLoop]: Abstraction has 9 states and 11 transitions. [2021-11-09 09:50:23,777 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9 states and 11 transitions. [2021-11-09 09:50:23,785 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9 to 9. [2021-11-09 09:50:23,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 8 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:23,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 11 transitions. [2021-11-09 09:50:23,787 INFO L704 BuchiCegarLoop]: Abstraction has 9 states and 11 transitions. [2021-11-09 09:50:23,787 INFO L587 BuchiCegarLoop]: Abstraction has 9 states and 11 transitions. [2021-11-09 09:50:23,788 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-09 09:50:23,788 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9 states and 11 transitions. [2021-11-09 09:50:23,789 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:23,789 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:23,790 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:23,790 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2021-11-09 09:50:23,790 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:23,791 INFO L791 eck$LassoCheckResult]: Stem: 116#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 117#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 120#L25-3 assume !(main_~i~0 < 1023); 118#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 119#L30-4 [2021-11-09 09:50:23,791 INFO L793 eck$LassoCheckResult]: Loop: 119#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 112#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 113#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 119#L30-4 [2021-11-09 09:50:23,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:23,793 INFO L85 PathProgramCache]: Analyzing trace with hash 925707, now seen corresponding path program 1 times [2021-11-09 09:50:23,793 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:23,793 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [11237542] [2021-11-09 09:50:23,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:23,793 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:23,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:23,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:23,855 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:23,855 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [11237542] [2021-11-09 09:50:23,856 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [11237542] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:50:23,856 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:50:23,856 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:50:23,857 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1315643295] [2021-11-09 09:50:23,859 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:23,861 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:23,861 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 1 times [2021-11-09 09:50:23,862 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:23,862 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1922594237] [2021-11-09 09:50:23,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:23,863 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:23,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:23,874 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:23,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:23,881 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:23,937 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:23,940 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:50:23,940 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:50:23,942 INFO L87 Difference]: Start difference. First operand 9 states and 11 transitions. cyclomatic complexity: 4 Second operand has 3 states, 3 states have (on average 1.3333333333333333) internal successors, (4), 3 states have internal predecessors, (4), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:23,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:23,969 INFO L93 Difference]: Finished difference Result 13 states and 14 transitions. [2021-11-09 09:50:23,969 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:50:23,970 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13 states and 14 transitions. [2021-11-09 09:50:23,973 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:23,974 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13 states to 13 states and 14 transitions. [2021-11-09 09:50:23,975 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10 [2021-11-09 09:50:23,975 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2021-11-09 09:50:23,975 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13 states and 14 transitions. [2021-11-09 09:50:23,975 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:23,975 INFO L681 BuchiCegarLoop]: Abstraction has 13 states and 14 transitions. [2021-11-09 09:50:23,975 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states and 14 transitions. [2021-11-09 09:50:23,977 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 9. [2021-11-09 09:50:23,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 8 states have internal predecessors, (10), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:23,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 10 transitions. [2021-11-09 09:50:23,979 INFO L704 BuchiCegarLoop]: Abstraction has 9 states and 10 transitions. [2021-11-09 09:50:23,979 INFO L587 BuchiCegarLoop]: Abstraction has 9 states and 10 transitions. [2021-11-09 09:50:23,979 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-09 09:50:23,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9 states and 10 transitions. [2021-11-09 09:50:23,982 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:23,982 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:23,982 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:23,983 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2021-11-09 09:50:23,983 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:23,983 INFO L791 eck$LassoCheckResult]: Stem: 144#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 145#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 146#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 142#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 143#L25-3 assume !(main_~i~0 < 1023); 147#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 148#L30-4 [2021-11-09 09:50:23,983 INFO L793 eck$LassoCheckResult]: Loop: 148#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 140#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 141#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 148#L30-4 [2021-11-09 09:50:23,985 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:23,985 INFO L85 PathProgramCache]: Analyzing trace with hash 889660429, now seen corresponding path program 1 times [2021-11-09 09:50:23,985 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:23,985 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [488054576] [2021-11-09 09:50:23,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:23,986 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:23,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:24,022 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:24,022 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:24,022 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [488054576] [2021-11-09 09:50:24,022 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [488054576] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:24,023 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1197597377] [2021-11-09 09:50:24,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:24,023 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:24,023 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:24,024 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:24,041 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2021-11-09 09:50:24,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:24,070 INFO L263 TraceCheckSpWp]: Trace formula consists of 51 conjuncts, 3 conjunts are in the unsatisfiable core [2021-11-09 09:50:24,071 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:24,093 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:24,093 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1197597377] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:24,093 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:24,094 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 5 [2021-11-09 09:50:24,094 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [589451830] [2021-11-09 09:50:24,094 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:24,095 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:24,095 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 2 times [2021-11-09 09:50:24,095 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:24,095 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1326775044] [2021-11-09 09:50:24,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:24,095 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:24,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:24,103 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:24,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:24,118 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:24,165 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:24,165 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-09 09:50:24,168 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2021-11-09 09:50:24,169 INFO L87 Difference]: Start difference. First operand 9 states and 10 transitions. cyclomatic complexity: 3 Second operand has 5 states, 5 states have (on average 1.8) internal successors, (9), 5 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:24,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:24,205 INFO L93 Difference]: Finished difference Result 18 states and 19 transitions. [2021-11-09 09:50:24,208 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-09 09:50:24,208 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18 states and 19 transitions. [2021-11-09 09:50:24,209 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:24,211 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18 states to 18 states and 19 transitions. [2021-11-09 09:50:24,212 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13 [2021-11-09 09:50:24,213 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13 [2021-11-09 09:50:24,213 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18 states and 19 transitions. [2021-11-09 09:50:24,213 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:24,213 INFO L681 BuchiCegarLoop]: Abstraction has 18 states and 19 transitions. [2021-11-09 09:50:24,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states and 19 transitions. [2021-11-09 09:50:24,216 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 11. [2021-11-09 09:50:24,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 1.0909090909090908) internal successors, (12), 10 states have internal predecessors, (12), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:24,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 12 transitions. [2021-11-09 09:50:24,218 INFO L704 BuchiCegarLoop]: Abstraction has 11 states and 12 transitions. [2021-11-09 09:50:24,218 INFO L587 BuchiCegarLoop]: Abstraction has 11 states and 12 transitions. [2021-11-09 09:50:24,218 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-09 09:50:24,219 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11 states and 12 transitions. [2021-11-09 09:50:24,220 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:24,220 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:24,220 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:24,221 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1] [2021-11-09 09:50:24,221 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:24,221 INFO L791 eck$LassoCheckResult]: Stem: 194#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 195#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 196#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 197#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 198#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 192#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 193#L25-3 assume !(main_~i~0 < 1023); 199#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 200#L30-4 [2021-11-09 09:50:24,222 INFO L793 eck$LassoCheckResult]: Loop: 200#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 190#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 191#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 200#L30-4 [2021-11-09 09:50:24,222 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:24,224 INFO L85 PathProgramCache]: Analyzing trace with hash 265236367, now seen corresponding path program 2 times [2021-11-09 09:50:24,224 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:24,224 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1362683804] [2021-11-09 09:50:24,224 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:24,225 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:24,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:24,272 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:24,272 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:24,272 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1362683804] [2021-11-09 09:50:24,273 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1362683804] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:24,273 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1574102931] [2021-11-09 09:50:24,273 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:50:24,273 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:24,273 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:24,275 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:24,291 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2021-11-09 09:50:24,320 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:50:24,320 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:24,321 INFO L263 TraceCheckSpWp]: Trace formula consists of 59 conjuncts, 4 conjunts are in the unsatisfiable core [2021-11-09 09:50:24,322 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:24,354 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:24,355 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1574102931] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:24,355 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:24,355 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 6 [2021-11-09 09:50:24,355 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [20618036] [2021-11-09 09:50:24,356 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:24,356 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:24,356 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 3 times [2021-11-09 09:50:24,356 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:24,357 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1889824158] [2021-11-09 09:50:24,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:24,357 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:24,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:24,362 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:24,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:24,367 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:24,401 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:24,402 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2021-11-09 09:50:24,402 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2021-11-09 09:50:24,403 INFO L87 Difference]: Start difference. First operand 11 states and 12 transitions. cyclomatic complexity: 3 Second operand has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 6 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:24,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:24,432 INFO L93 Difference]: Finished difference Result 23 states and 24 transitions. [2021-11-09 09:50:24,433 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2021-11-09 09:50:24,433 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 23 states and 24 transitions. [2021-11-09 09:50:24,434 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:24,435 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 23 states to 23 states and 24 transitions. [2021-11-09 09:50:24,435 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2021-11-09 09:50:24,435 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16 [2021-11-09 09:50:24,435 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23 states and 24 transitions. [2021-11-09 09:50:24,435 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:24,436 INFO L681 BuchiCegarLoop]: Abstraction has 23 states and 24 transitions. [2021-11-09 09:50:24,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states and 24 transitions. [2021-11-09 09:50:24,437 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 13. [2021-11-09 09:50:24,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13 states, 13 states have (on average 1.0769230769230769) internal successors, (14), 12 states have internal predecessors, (14), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:24,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 14 transitions. [2021-11-09 09:50:24,438 INFO L704 BuchiCegarLoop]: Abstraction has 13 states and 14 transitions. [2021-11-09 09:50:24,438 INFO L587 BuchiCegarLoop]: Abstraction has 13 states and 14 transitions. [2021-11-09 09:50:24,438 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-09 09:50:24,438 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13 states and 14 transitions. [2021-11-09 09:50:24,439 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:24,439 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:24,439 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:24,439 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [3, 3, 1, 1, 1, 1] [2021-11-09 09:50:24,440 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:24,468 INFO L791 eck$LassoCheckResult]: Stem: 258#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 259#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 260#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 261#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 262#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 256#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 257#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 266#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 265#L25-3 assume !(main_~i~0 < 1023); 263#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 264#L30-4 [2021-11-09 09:50:24,469 INFO L793 eck$LassoCheckResult]: Loop: 264#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 254#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 255#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 264#L30-4 [2021-11-09 09:50:24,469 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:24,469 INFO L85 PathProgramCache]: Analyzing trace with hash 1489134225, now seen corresponding path program 3 times [2021-11-09 09:50:24,470 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:24,470 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1565856630] [2021-11-09 09:50:24,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:24,470 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:24,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:24,522 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2021-11-09 09:50:24,537 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:24,537 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:24,537 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1565856630] [2021-11-09 09:50:24,537 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1565856630] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:24,538 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [96701108] [2021-11-09 09:50:24,538 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:50:24,538 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:24,538 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:24,542 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:24,544 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2021-11-09 09:50:24,592 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2021-11-09 09:50:24,592 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:24,593 INFO L263 TraceCheckSpWp]: Trace formula consists of 67 conjuncts, 5 conjunts are in the unsatisfiable core [2021-11-09 09:50:24,594 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:24,643 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:24,643 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [96701108] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:24,644 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:24,644 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 7 [2021-11-09 09:50:24,644 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1355653155] [2021-11-09 09:50:24,645 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:24,645 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:24,646 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 4 times [2021-11-09 09:50:24,647 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:24,648 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1089185095] [2021-11-09 09:50:24,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:24,649 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:24,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:24,661 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:24,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:24,677 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:24,716 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:24,716 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2021-11-09 09:50:24,718 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=21, Unknown=0, NotChecked=0, Total=42 [2021-11-09 09:50:24,718 INFO L87 Difference]: Start difference. First operand 13 states and 14 transitions. cyclomatic complexity: 3 Second operand has 7 states, 7 states have (on average 1.8571428571428572) internal successors, (13), 7 states have internal predecessors, (13), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:24,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:24,761 INFO L93 Difference]: Finished difference Result 28 states and 29 transitions. [2021-11-09 09:50:24,761 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-09 09:50:24,761 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28 states and 29 transitions. [2021-11-09 09:50:24,764 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:24,768 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28 states to 28 states and 29 transitions. [2021-11-09 09:50:24,769 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19 [2021-11-09 09:50:24,769 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19 [2021-11-09 09:50:24,769 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28 states and 29 transitions. [2021-11-09 09:50:24,769 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:24,770 INFO L681 BuchiCegarLoop]: Abstraction has 28 states and 29 transitions. [2021-11-09 09:50:24,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states and 29 transitions. [2021-11-09 09:50:24,773 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 15. [2021-11-09 09:50:24,773 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 1.0666666666666667) internal successors, (16), 14 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:24,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 16 transitions. [2021-11-09 09:50:24,774 INFO L704 BuchiCegarLoop]: Abstraction has 15 states and 16 transitions. [2021-11-09 09:50:24,774 INFO L587 BuchiCegarLoop]: Abstraction has 15 states and 16 transitions. [2021-11-09 09:50:24,774 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-09 09:50:24,774 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15 states and 16 transitions. [2021-11-09 09:50:24,775 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:24,775 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:24,775 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:24,776 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [4, 4, 1, 1, 1, 1] [2021-11-09 09:50:24,776 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:24,776 INFO L791 eck$LassoCheckResult]: Stem: 336#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 337#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 338#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 339#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 340#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 334#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 335#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 346#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 345#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 344#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 343#L25-3 assume !(main_~i~0 < 1023); 341#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 342#L30-4 [2021-11-09 09:50:24,777 INFO L793 eck$LassoCheckResult]: Loop: 342#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 332#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 333#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 342#L30-4 [2021-11-09 09:50:24,777 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:24,777 INFO L85 PathProgramCache]: Analyzing trace with hash 833936659, now seen corresponding path program 4 times [2021-11-09 09:50:24,778 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:24,778 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1731110828] [2021-11-09 09:50:24,778 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:24,778 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:24,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:24,878 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:24,879 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:24,879 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1731110828] [2021-11-09 09:50:24,879 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1731110828] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:24,879 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2082843069] [2021-11-09 09:50:24,880 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:50:24,880 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:24,880 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:24,882 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:24,901 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2021-11-09 09:50:24,937 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:50:24,938 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:24,938 INFO L263 TraceCheckSpWp]: Trace formula consists of 75 conjuncts, 6 conjunts are in the unsatisfiable core [2021-11-09 09:50:24,939 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:24,992 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:24,993 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2082843069] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:24,993 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:24,993 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 8 [2021-11-09 09:50:24,993 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2061557679] [2021-11-09 09:50:24,994 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:24,994 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:24,994 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 5 times [2021-11-09 09:50:24,994 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:24,994 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [371129424] [2021-11-09 09:50:24,995 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:24,995 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:24,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:24,999 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:25,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:25,003 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:25,035 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:25,035 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2021-11-09 09:50:25,036 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2021-11-09 09:50:25,036 INFO L87 Difference]: Start difference. First operand 15 states and 16 transitions. cyclomatic complexity: 3 Second operand has 8 states, 8 states have (on average 1.875) internal successors, (15), 8 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:25,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:25,080 INFO L93 Difference]: Finished difference Result 33 states and 34 transitions. [2021-11-09 09:50:25,081 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-11-09 09:50:25,081 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33 states and 34 transitions. [2021-11-09 09:50:25,082 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:25,083 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33 states to 33 states and 34 transitions. [2021-11-09 09:50:25,083 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2021-11-09 09:50:25,083 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2021-11-09 09:50:25,083 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33 states and 34 transitions. [2021-11-09 09:50:25,084 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:25,084 INFO L681 BuchiCegarLoop]: Abstraction has 33 states and 34 transitions. [2021-11-09 09:50:25,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33 states and 34 transitions. [2021-11-09 09:50:25,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33 to 17. [2021-11-09 09:50:25,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.0588235294117647) internal successors, (18), 16 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:25,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 18 transitions. [2021-11-09 09:50:25,086 INFO L704 BuchiCegarLoop]: Abstraction has 17 states and 18 transitions. [2021-11-09 09:50:25,086 INFO L587 BuchiCegarLoop]: Abstraction has 17 states and 18 transitions. [2021-11-09 09:50:25,086 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-09 09:50:25,087 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17 states and 18 transitions. [2021-11-09 09:50:25,087 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:25,087 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:25,087 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:25,088 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [5, 5, 1, 1, 1, 1] [2021-11-09 09:50:25,088 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:25,088 INFO L791 eck$LassoCheckResult]: Stem: 428#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 429#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 430#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 431#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 432#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 426#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 427#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 440#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 439#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 438#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 437#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 436#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 435#L25-3 assume !(main_~i~0 < 1023); 433#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 434#L30-4 [2021-11-09 09:50:25,089 INFO L793 eck$LassoCheckResult]: Loop: 434#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 424#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 425#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 434#L30-4 [2021-11-09 09:50:25,089 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:25,089 INFO L85 PathProgramCache]: Analyzing trace with hash -1745699051, now seen corresponding path program 5 times [2021-11-09 09:50:25,089 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:25,089 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [93530955] [2021-11-09 09:50:25,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:25,090 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:25,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:25,148 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 0 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:25,148 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:25,148 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [93530955] [2021-11-09 09:50:25,148 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [93530955] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:25,149 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1685924680] [2021-11-09 09:50:25,149 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:50:25,149 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:25,149 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:25,151 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:25,155 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2021-11-09 09:50:25,210 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2021-11-09 09:50:25,210 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:25,211 INFO L263 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 7 conjunts are in the unsatisfiable core [2021-11-09 09:50:25,212 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:25,267 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 0 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:25,269 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1685924680] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:25,270 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:25,270 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 9 [2021-11-09 09:50:25,270 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [786703079] [2021-11-09 09:50:25,271 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:25,272 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:25,272 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 6 times [2021-11-09 09:50:25,273 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:25,273 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2088724007] [2021-11-09 09:50:25,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:25,273 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:25,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:25,279 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:25,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:25,287 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:25,320 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:25,321 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2021-11-09 09:50:25,321 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2021-11-09 09:50:25,321 INFO L87 Difference]: Start difference. First operand 17 states and 18 transitions. cyclomatic complexity: 3 Second operand has 9 states, 9 states have (on average 1.8888888888888888) internal successors, (17), 9 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:25,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:25,369 INFO L93 Difference]: Finished difference Result 38 states and 39 transitions. [2021-11-09 09:50:25,369 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2021-11-09 09:50:25,369 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38 states and 39 transitions. [2021-11-09 09:50:25,372 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:25,373 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38 states to 38 states and 39 transitions. [2021-11-09 09:50:25,374 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25 [2021-11-09 09:50:25,374 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25 [2021-11-09 09:50:25,374 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38 states and 39 transitions. [2021-11-09 09:50:25,375 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:25,375 INFO L681 BuchiCegarLoop]: Abstraction has 38 states and 39 transitions. [2021-11-09 09:50:25,375 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states and 39 transitions. [2021-11-09 09:50:25,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 19. [2021-11-09 09:50:25,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.0526315789473684) internal successors, (20), 18 states have internal predecessors, (20), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:25,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 20 transitions. [2021-11-09 09:50:25,380 INFO L704 BuchiCegarLoop]: Abstraction has 19 states and 20 transitions. [2021-11-09 09:50:25,380 INFO L587 BuchiCegarLoop]: Abstraction has 19 states and 20 transitions. [2021-11-09 09:50:25,380 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-09 09:50:25,380 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19 states and 20 transitions. [2021-11-09 09:50:25,383 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:25,383 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:25,383 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:25,384 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [6, 6, 1, 1, 1, 1] [2021-11-09 09:50:25,384 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:25,384 INFO L791 eck$LassoCheckResult]: Stem: 534#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 535#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 536#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 537#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 538#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 532#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 533#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 548#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 547#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 546#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 545#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 544#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 543#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 542#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 541#L25-3 assume !(main_~i~0 < 1023); 539#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 540#L30-4 [2021-11-09 09:50:25,385 INFO L793 eck$LassoCheckResult]: Loop: 540#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 530#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 531#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 540#L30-4 [2021-11-09 09:50:25,385 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:25,385 INFO L85 PathProgramCache]: Analyzing trace with hash 1715480727, now seen corresponding path program 6 times [2021-11-09 09:50:25,385 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:25,385 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1546779136] [2021-11-09 09:50:25,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:25,386 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:25,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:25,524 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:25,525 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:25,525 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1546779136] [2021-11-09 09:50:25,525 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1546779136] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:25,525 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1713491771] [2021-11-09 09:50:25,525 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:50:25,526 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:25,526 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:25,533 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:25,537 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2021-11-09 09:50:25,620 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2021-11-09 09:50:25,620 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:25,621 INFO L263 TraceCheckSpWp]: Trace formula consists of 91 conjuncts, 8 conjunts are in the unsatisfiable core [2021-11-09 09:50:25,622 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:25,692 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:25,692 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1713491771] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:25,693 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:25,693 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2021-11-09 09:50:25,694 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [337170074] [2021-11-09 09:50:25,694 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:25,694 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:25,695 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 7 times [2021-11-09 09:50:25,695 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:25,695 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [145568086] [2021-11-09 09:50:25,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:25,695 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:25,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:25,703 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:25,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:25,710 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:25,741 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:25,741 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2021-11-09 09:50:25,742 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2021-11-09 09:50:25,742 INFO L87 Difference]: Start difference. First operand 19 states and 20 transitions. cyclomatic complexity: 3 Second operand has 10 states, 10 states have (on average 1.9) internal successors, (19), 10 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:25,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:25,798 INFO L93 Difference]: Finished difference Result 43 states and 44 transitions. [2021-11-09 09:50:25,799 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2021-11-09 09:50:25,799 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43 states and 44 transitions. [2021-11-09 09:50:25,800 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:25,802 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43 states to 43 states and 44 transitions. [2021-11-09 09:50:25,803 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28 [2021-11-09 09:50:25,803 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28 [2021-11-09 09:50:25,803 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43 states and 44 transitions. [2021-11-09 09:50:25,803 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:25,803 INFO L681 BuchiCegarLoop]: Abstraction has 43 states and 44 transitions. [2021-11-09 09:50:25,804 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states and 44 transitions. [2021-11-09 09:50:25,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 21. [2021-11-09 09:50:25,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.0476190476190477) internal successors, (22), 20 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:25,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 22 transitions. [2021-11-09 09:50:25,807 INFO L704 BuchiCegarLoop]: Abstraction has 21 states and 22 transitions. [2021-11-09 09:50:25,807 INFO L587 BuchiCegarLoop]: Abstraction has 21 states and 22 transitions. [2021-11-09 09:50:25,807 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-09 09:50:25,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21 states and 22 transitions. [2021-11-09 09:50:25,809 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:25,809 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:25,809 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:25,810 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [7, 7, 1, 1, 1, 1] [2021-11-09 09:50:25,810 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:25,811 INFO L791 eck$LassoCheckResult]: Stem: 654#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 655#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 656#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 657#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 658#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 652#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 653#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 670#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 669#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 668#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 667#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 666#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 665#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 664#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 663#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 662#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 661#L25-3 assume !(main_~i~0 < 1023); 659#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 660#L30-4 [2021-11-09 09:50:25,811 INFO L793 eck$LassoCheckResult]: Loop: 660#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 650#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 651#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 660#L30-4 [2021-11-09 09:50:25,811 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:25,811 INFO L85 PathProgramCache]: Analyzing trace with hash -690407015, now seen corresponding path program 7 times [2021-11-09 09:50:25,811 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:25,812 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [192153016] [2021-11-09 09:50:25,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:25,812 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:25,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:25,904 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:25,904 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:25,905 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [192153016] [2021-11-09 09:50:25,905 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [192153016] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:25,906 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [208111569] [2021-11-09 09:50:25,906 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:50:25,907 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:25,907 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:25,913 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:25,933 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2021-11-09 09:50:25,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:25,992 INFO L263 TraceCheckSpWp]: Trace formula consists of 99 conjuncts, 9 conjunts are in the unsatisfiable core [2021-11-09 09:50:25,993 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:26,056 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:26,056 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [208111569] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:26,056 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:26,057 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 11 [2021-11-09 09:50:26,059 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1927720915] [2021-11-09 09:50:26,059 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:26,060 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:26,060 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 8 times [2021-11-09 09:50:26,060 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:26,060 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1794245468] [2021-11-09 09:50:26,060 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:26,060 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:26,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:26,065 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:26,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:26,071 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:26,102 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:26,102 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2021-11-09 09:50:26,103 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=55, Invalid=55, Unknown=0, NotChecked=0, Total=110 [2021-11-09 09:50:26,103 INFO L87 Difference]: Start difference. First operand 21 states and 22 transitions. cyclomatic complexity: 3 Second operand has 11 states, 11 states have (on average 1.9090909090909092) internal successors, (21), 11 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:26,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:26,181 INFO L93 Difference]: Finished difference Result 48 states and 49 transitions. [2021-11-09 09:50:26,181 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2021-11-09 09:50:26,182 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48 states and 49 transitions. [2021-11-09 09:50:26,184 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:26,188 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48 states to 48 states and 49 transitions. [2021-11-09 09:50:26,188 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31 [2021-11-09 09:50:26,189 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31 [2021-11-09 09:50:26,190 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48 states and 49 transitions. [2021-11-09 09:50:26,191 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:26,191 INFO L681 BuchiCegarLoop]: Abstraction has 48 states and 49 transitions. [2021-11-09 09:50:26,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states and 49 transitions. [2021-11-09 09:50:26,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 23. [2021-11-09 09:50:26,200 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23 states, 23 states have (on average 1.0434782608695652) internal successors, (24), 22 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:26,201 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 24 transitions. [2021-11-09 09:50:26,201 INFO L704 BuchiCegarLoop]: Abstraction has 23 states and 24 transitions. [2021-11-09 09:50:26,201 INFO L587 BuchiCegarLoop]: Abstraction has 23 states and 24 transitions. [2021-11-09 09:50:26,201 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-09 09:50:26,201 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23 states and 24 transitions. [2021-11-09 09:50:26,202 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:26,202 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:26,202 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:26,203 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [8, 8, 1, 1, 1, 1] [2021-11-09 09:50:26,203 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:26,204 INFO L791 eck$LassoCheckResult]: Stem: 788#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 789#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 790#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 791#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 792#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 786#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 787#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 806#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 805#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 804#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 803#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 802#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 801#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 800#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 799#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 798#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 797#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 796#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 795#L25-3 assume !(main_~i~0 < 1023); 793#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 794#L30-4 [2021-11-09 09:50:26,204 INFO L793 eck$LassoCheckResult]: Loop: 794#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 784#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 785#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 794#L30-4 [2021-11-09 09:50:26,207 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:26,207 INFO L85 PathProgramCache]: Analyzing trace with hash -2056121829, now seen corresponding path program 8 times [2021-11-09 09:50:26,207 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:26,207 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2119157694] [2021-11-09 09:50:26,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:26,208 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:26,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:26,322 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 0 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:26,322 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:26,322 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2119157694] [2021-11-09 09:50:26,323 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2119157694] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:26,323 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2035417905] [2021-11-09 09:50:26,323 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:50:26,323 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:26,323 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:26,330 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:26,352 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2021-11-09 09:50:26,413 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:50:26,413 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:26,414 INFO L263 TraceCheckSpWp]: Trace formula consists of 107 conjuncts, 10 conjunts are in the unsatisfiable core [2021-11-09 09:50:26,415 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:26,487 INFO L134 CoverageAnalysis]: Checked inductivity of 64 backedges. 0 proven. 64 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:26,487 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2035417905] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:26,487 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:26,488 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 12 [2021-11-09 09:50:26,488 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1411182861] [2021-11-09 09:50:26,488 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:26,489 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:26,489 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 9 times [2021-11-09 09:50:26,489 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:26,489 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1264917544] [2021-11-09 09:50:26,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:26,490 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:26,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:26,494 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:26,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:26,498 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:26,527 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:26,528 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2021-11-09 09:50:26,528 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2021-11-09 09:50:26,528 INFO L87 Difference]: Start difference. First operand 23 states and 24 transitions. cyclomatic complexity: 3 Second operand has 12 states, 12 states have (on average 1.9166666666666667) internal successors, (23), 12 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:26,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:26,593 INFO L93 Difference]: Finished difference Result 53 states and 54 transitions. [2021-11-09 09:50:26,594 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2021-11-09 09:50:26,594 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53 states and 54 transitions. [2021-11-09 09:50:26,596 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:26,598 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53 states to 53 states and 54 transitions. [2021-11-09 09:50:26,598 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34 [2021-11-09 09:50:26,598 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34 [2021-11-09 09:50:26,598 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53 states and 54 transitions. [2021-11-09 09:50:26,602 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:26,602 INFO L681 BuchiCegarLoop]: Abstraction has 53 states and 54 transitions. [2021-11-09 09:50:26,603 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states and 54 transitions. [2021-11-09 09:50:26,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 25. [2021-11-09 09:50:26,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 25 states have (on average 1.04) internal successors, (26), 24 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:26,609 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 26 transitions. [2021-11-09 09:50:26,609 INFO L704 BuchiCegarLoop]: Abstraction has 25 states and 26 transitions. [2021-11-09 09:50:26,609 INFO L587 BuchiCegarLoop]: Abstraction has 25 states and 26 transitions. [2021-11-09 09:50:26,609 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-09 09:50:26,610 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 26 transitions. [2021-11-09 09:50:26,610 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:26,610 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:26,610 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:26,611 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [9, 9, 1, 1, 1, 1] [2021-11-09 09:50:26,611 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:26,612 INFO L791 eck$LassoCheckResult]: Stem: 936#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 937#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 938#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 939#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 940#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 934#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 935#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 956#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 955#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 954#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 953#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 952#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 951#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 950#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 949#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 948#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 947#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 946#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 945#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 944#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 943#L25-3 assume !(main_~i~0 < 1023); 941#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 942#L30-4 [2021-11-09 09:50:26,612 INFO L793 eck$LassoCheckResult]: Loop: 942#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 932#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 933#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 942#L30-4 [2021-11-09 09:50:26,613 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:26,613 INFO L85 PathProgramCache]: Analyzing trace with hash -248065507, now seen corresponding path program 9 times [2021-11-09 09:50:26,613 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:26,613 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [958161971] [2021-11-09 09:50:26,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:26,614 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:26,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:26,712 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:26,713 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:26,713 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [958161971] [2021-11-09 09:50:26,713 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [958161971] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:26,713 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [693065631] [2021-11-09 09:50:26,713 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:50:26,715 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:26,716 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:26,718 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:26,741 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2021-11-09 09:50:26,893 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2021-11-09 09:50:26,893 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:26,895 INFO L263 TraceCheckSpWp]: Trace formula consists of 115 conjuncts, 11 conjunts are in the unsatisfiable core [2021-11-09 09:50:26,896 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:26,967 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 0 proven. 81 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:26,967 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [693065631] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:26,968 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:26,968 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 13 [2021-11-09 09:50:26,969 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1657007253] [2021-11-09 09:50:26,970 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:26,971 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:26,971 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 10 times [2021-11-09 09:50:26,971 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:26,971 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1154059947] [2021-11-09 09:50:26,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:26,971 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:26,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:26,979 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:26,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:27,010 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:27,040 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:27,040 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2021-11-09 09:50:27,041 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2021-11-09 09:50:27,041 INFO L87 Difference]: Start difference. First operand 25 states and 26 transitions. cyclomatic complexity: 3 Second operand has 13 states, 13 states have (on average 1.9230769230769231) internal successors, (25), 13 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:27,118 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:27,119 INFO L93 Difference]: Finished difference Result 58 states and 59 transitions. [2021-11-09 09:50:27,119 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2021-11-09 09:50:27,119 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 58 states and 59 transitions. [2021-11-09 09:50:27,120 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:27,120 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 58 states to 58 states and 59 transitions. [2021-11-09 09:50:27,121 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37 [2021-11-09 09:50:27,121 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37 [2021-11-09 09:50:27,121 INFO L73 IsDeterministic]: Start isDeterministic. Operand 58 states and 59 transitions. [2021-11-09 09:50:27,121 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:27,121 INFO L681 BuchiCegarLoop]: Abstraction has 58 states and 59 transitions. [2021-11-09 09:50:27,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states and 59 transitions. [2021-11-09 09:50:27,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 27. [2021-11-09 09:50:27,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.037037037037037) internal successors, (28), 26 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:27,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 28 transitions. [2021-11-09 09:50:27,125 INFO L704 BuchiCegarLoop]: Abstraction has 27 states and 28 transitions. [2021-11-09 09:50:27,125 INFO L587 BuchiCegarLoop]: Abstraction has 27 states and 28 transitions. [2021-11-09 09:50:27,126 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-09 09:50:27,126 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 28 transitions. [2021-11-09 09:50:27,126 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:27,126 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:27,126 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:27,127 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [10, 10, 1, 1, 1, 1] [2021-11-09 09:50:27,127 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:27,127 INFO L791 eck$LassoCheckResult]: Stem: 1098#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 1099#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 1100#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1101#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1102#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1096#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1097#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1120#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1119#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1118#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1117#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1116#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1115#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1114#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1113#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1112#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1111#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1110#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1109#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1108#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1107#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1106#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1105#L25-3 assume !(main_~i~0 < 1023); 1103#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 1104#L30-4 [2021-11-09 09:50:27,127 INFO L793 eck$LassoCheckResult]: Loop: 1104#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 1094#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 1095#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 1104#L30-4 [2021-11-09 09:50:27,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:27,128 INFO L85 PathProgramCache]: Analyzing trace with hash 2127272351, now seen corresponding path program 10 times [2021-11-09 09:50:27,128 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:27,128 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [121897178] [2021-11-09 09:50:27,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:27,129 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:27,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:27,252 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:27,252 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:27,252 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [121897178] [2021-11-09 09:50:27,252 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [121897178] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:27,252 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2146388837] [2021-11-09 09:50:27,253 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:50:27,253 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:27,253 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:27,256 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:27,271 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2021-11-09 09:50:27,350 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:50:27,350 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:27,351 INFO L263 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 12 conjunts are in the unsatisfiable core [2021-11-09 09:50:27,352 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:27,434 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:27,435 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2146388837] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:27,435 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:27,435 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 14 [2021-11-09 09:50:27,435 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1813702106] [2021-11-09 09:50:27,436 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:27,436 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:27,436 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 11 times [2021-11-09 09:50:27,436 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:27,436 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1849128559] [2021-11-09 09:50:27,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:27,437 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:27,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:27,440 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:27,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:27,443 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:27,473 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:27,474 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2021-11-09 09:50:27,474 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2021-11-09 09:50:27,474 INFO L87 Difference]: Start difference. First operand 27 states and 28 transitions. cyclomatic complexity: 3 Second operand has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 14 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:27,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:27,564 INFO L93 Difference]: Finished difference Result 63 states and 64 transitions. [2021-11-09 09:50:27,564 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2021-11-09 09:50:27,565 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63 states and 64 transitions. [2021-11-09 09:50:27,565 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:27,566 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63 states to 63 states and 64 transitions. [2021-11-09 09:50:27,566 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40 [2021-11-09 09:50:27,566 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40 [2021-11-09 09:50:27,566 INFO L73 IsDeterministic]: Start isDeterministic. Operand 63 states and 64 transitions. [2021-11-09 09:50:27,567 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:27,567 INFO L681 BuchiCegarLoop]: Abstraction has 63 states and 64 transitions. [2021-11-09 09:50:27,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states and 64 transitions. [2021-11-09 09:50:27,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 29. [2021-11-09 09:50:27,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 29 states have (on average 1.0344827586206897) internal successors, (30), 28 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:27,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 30 transitions. [2021-11-09 09:50:27,576 INFO L704 BuchiCegarLoop]: Abstraction has 29 states and 30 transitions. [2021-11-09 09:50:27,576 INFO L587 BuchiCegarLoop]: Abstraction has 29 states and 30 transitions. [2021-11-09 09:50:27,576 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-09 09:50:27,576 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29 states and 30 transitions. [2021-11-09 09:50:27,577 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:27,577 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:27,577 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:27,577 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [11, 11, 1, 1, 1, 1] [2021-11-09 09:50:27,578 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:27,578 INFO L791 eck$LassoCheckResult]: Stem: 1274#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 1275#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 1276#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1277#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1278#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1272#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1273#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1298#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1297#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1296#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1295#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1294#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1293#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1292#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1291#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1290#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1289#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1288#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1287#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1286#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1285#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1284#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1283#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1282#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1281#L25-3 assume !(main_~i~0 < 1023); 1279#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 1280#L30-4 [2021-11-09 09:50:27,578 INFO L793 eck$LassoCheckResult]: Loop: 1280#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 1270#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 1271#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 1280#L30-4 [2021-11-09 09:50:27,578 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:27,578 INFO L85 PathProgramCache]: Analyzing trace with hash -95647583, now seen corresponding path program 11 times [2021-11-09 09:50:27,579 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:27,579 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1418805824] [2021-11-09 09:50:27,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:27,579 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:27,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:27,706 INFO L134 CoverageAnalysis]: Checked inductivity of 121 backedges. 0 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:27,707 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:27,707 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1418805824] [2021-11-09 09:50:27,707 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1418805824] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:27,707 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [572781478] [2021-11-09 09:50:27,707 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:50:27,707 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:27,708 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:27,709 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:27,740 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2021-11-09 09:50:27,885 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2021-11-09 09:50:27,886 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:27,887 INFO L263 TraceCheckSpWp]: Trace formula consists of 131 conjuncts, 13 conjunts are in the unsatisfiable core [2021-11-09 09:50:27,889 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:27,987 INFO L134 CoverageAnalysis]: Checked inductivity of 121 backedges. 0 proven. 121 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:27,987 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [572781478] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:27,987 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:27,987 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 15 [2021-11-09 09:50:27,988 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1760676418] [2021-11-09 09:50:27,988 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:27,988 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:27,988 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 12 times [2021-11-09 09:50:27,988 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:27,989 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [880114459] [2021-11-09 09:50:27,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:27,989 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:27,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:27,993 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:27,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:27,996 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:28,028 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:28,029 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2021-11-09 09:50:28,029 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=105, Unknown=0, NotChecked=0, Total=210 [2021-11-09 09:50:28,030 INFO L87 Difference]: Start difference. First operand 29 states and 30 transitions. cyclomatic complexity: 3 Second operand has 15 states, 15 states have (on average 1.9333333333333333) internal successors, (29), 15 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:28,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:28,117 INFO L93 Difference]: Finished difference Result 68 states and 69 transitions. [2021-11-09 09:50:28,117 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2021-11-09 09:50:28,118 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68 states and 69 transitions. [2021-11-09 09:50:28,118 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:28,119 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68 states to 68 states and 69 transitions. [2021-11-09 09:50:28,119 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43 [2021-11-09 09:50:28,119 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43 [2021-11-09 09:50:28,120 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68 states and 69 transitions. [2021-11-09 09:50:28,120 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:28,120 INFO L681 BuchiCegarLoop]: Abstraction has 68 states and 69 transitions. [2021-11-09 09:50:28,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states and 69 transitions. [2021-11-09 09:50:28,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 31. [2021-11-09 09:50:28,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 31 states have (on average 1.032258064516129) internal successors, (32), 30 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:28,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 32 transitions. [2021-11-09 09:50:28,123 INFO L704 BuchiCegarLoop]: Abstraction has 31 states and 32 transitions. [2021-11-09 09:50:28,124 INFO L587 BuchiCegarLoop]: Abstraction has 31 states and 32 transitions. [2021-11-09 09:50:28,124 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-09 09:50:28,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31 states and 32 transitions. [2021-11-09 09:50:28,124 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:28,124 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:28,124 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:28,126 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [12, 12, 1, 1, 1, 1] [2021-11-09 09:50:28,126 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:28,129 INFO L791 eck$LassoCheckResult]: Stem: 1464#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 1465#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 1466#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1467#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1468#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1462#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1463#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1490#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1489#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1488#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1487#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1486#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1485#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1484#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1483#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1482#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1481#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1480#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1479#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1478#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1477#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1476#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1475#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1474#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1473#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1472#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1471#L25-3 assume !(main_~i~0 < 1023); 1469#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 1470#L30-4 [2021-11-09 09:50:28,129 INFO L793 eck$LassoCheckResult]: Loop: 1470#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 1460#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 1461#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 1470#L30-4 [2021-11-09 09:50:28,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:28,130 INFO L85 PathProgramCache]: Analyzing trace with hash -1722958045, now seen corresponding path program 12 times [2021-11-09 09:50:28,130 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:28,130 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2117634712] [2021-11-09 09:50:28,130 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:28,131 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:28,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:28,274 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:28,274 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:28,274 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2117634712] [2021-11-09 09:50:28,274 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2117634712] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:28,275 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1732086213] [2021-11-09 09:50:28,275 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:50:28,275 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:28,275 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:28,276 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:28,276 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2021-11-09 09:50:28,547 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2021-11-09 09:50:28,547 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:28,549 INFO L263 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 14 conjunts are in the unsatisfiable core [2021-11-09 09:50:28,551 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:28,644 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:28,644 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1732086213] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:28,644 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:28,644 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 16 [2021-11-09 09:50:28,645 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [209861794] [2021-11-09 09:50:28,645 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:28,645 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:28,645 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 13 times [2021-11-09 09:50:28,646 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:28,646 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [933661087] [2021-11-09 09:50:28,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:28,646 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:28,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:28,650 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:28,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:28,653 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:28,682 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:28,682 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2021-11-09 09:50:28,683 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2021-11-09 09:50:28,683 INFO L87 Difference]: Start difference. First operand 31 states and 32 transitions. cyclomatic complexity: 3 Second operand has 16 states, 16 states have (on average 1.9375) internal successors, (31), 16 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:28,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:28,781 INFO L93 Difference]: Finished difference Result 73 states and 74 transitions. [2021-11-09 09:50:28,782 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2021-11-09 09:50:28,782 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73 states and 74 transitions. [2021-11-09 09:50:28,783 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:28,783 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73 states to 73 states and 74 transitions. [2021-11-09 09:50:28,784 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46 [2021-11-09 09:50:28,784 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46 [2021-11-09 09:50:28,784 INFO L73 IsDeterministic]: Start isDeterministic. Operand 73 states and 74 transitions. [2021-11-09 09:50:28,784 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:28,784 INFO L681 BuchiCegarLoop]: Abstraction has 73 states and 74 transitions. [2021-11-09 09:50:28,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states and 74 transitions. [2021-11-09 09:50:28,786 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 33. [2021-11-09 09:50:28,786 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33 states, 33 states have (on average 1.0303030303030303) internal successors, (34), 32 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:28,787 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 34 transitions. [2021-11-09 09:50:28,787 INFO L704 BuchiCegarLoop]: Abstraction has 33 states and 34 transitions. [2021-11-09 09:50:28,787 INFO L587 BuchiCegarLoop]: Abstraction has 33 states and 34 transitions. [2021-11-09 09:50:28,787 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-09 09:50:28,787 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33 states and 34 transitions. [2021-11-09 09:50:28,787 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:28,788 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:28,788 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:28,788 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [13, 13, 1, 1, 1, 1] [2021-11-09 09:50:28,789 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:28,789 INFO L791 eck$LassoCheckResult]: Stem: 1668#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 1669#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 1670#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1671#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1672#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1666#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1667#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1696#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1695#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1694#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1693#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1692#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1691#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1690#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1689#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1688#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1687#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1686#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1685#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1684#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1683#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1682#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1681#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1680#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1679#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1678#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1677#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1676#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1675#L25-3 assume !(main_~i~0 < 1023); 1673#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 1674#L30-4 [2021-11-09 09:50:28,789 INFO L793 eck$LassoCheckResult]: Loop: 1674#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 1664#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 1665#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 1674#L30-4 [2021-11-09 09:50:28,789 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:28,789 INFO L85 PathProgramCache]: Analyzing trace with hash 2094751013, now seen corresponding path program 13 times [2021-11-09 09:50:28,790 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:28,790 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1090153782] [2021-11-09 09:50:28,790 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:28,790 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:28,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:28,926 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 0 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:28,926 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:28,926 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1090153782] [2021-11-09 09:50:28,926 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1090153782] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:28,926 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [855333675] [2021-11-09 09:50:28,926 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:50:28,927 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:28,927 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:28,929 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:28,953 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2021-11-09 09:50:29,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:29,062 INFO L263 TraceCheckSpWp]: Trace formula consists of 147 conjuncts, 15 conjunts are in the unsatisfiable core [2021-11-09 09:50:29,064 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:29,151 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 0 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:29,151 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [855333675] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:29,152 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:29,152 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 17 [2021-11-09 09:50:29,152 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [446666532] [2021-11-09 09:50:29,153 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:29,154 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:29,154 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 14 times [2021-11-09 09:50:29,154 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:29,154 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [198646202] [2021-11-09 09:50:29,154 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:29,155 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:29,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:29,159 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:29,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:29,161 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:29,194 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:29,195 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2021-11-09 09:50:29,195 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=136, Invalid=136, Unknown=0, NotChecked=0, Total=272 [2021-11-09 09:50:29,195 INFO L87 Difference]: Start difference. First operand 33 states and 34 transitions. cyclomatic complexity: 3 Second operand has 17 states, 17 states have (on average 1.9411764705882353) internal successors, (33), 17 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:29,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:29,296 INFO L93 Difference]: Finished difference Result 78 states and 79 transitions. [2021-11-09 09:50:29,296 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2021-11-09 09:50:29,296 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 78 states and 79 transitions. [2021-11-09 09:50:29,299 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:29,301 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 78 states to 78 states and 79 transitions. [2021-11-09 09:50:29,301 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49 [2021-11-09 09:50:29,301 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49 [2021-11-09 09:50:29,301 INFO L73 IsDeterministic]: Start isDeterministic. Operand 78 states and 79 transitions. [2021-11-09 09:50:29,301 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:29,302 INFO L681 BuchiCegarLoop]: Abstraction has 78 states and 79 transitions. [2021-11-09 09:50:29,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states and 79 transitions. [2021-11-09 09:50:29,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 35. [2021-11-09 09:50:29,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35 states, 35 states have (on average 1.0285714285714285) internal successors, (36), 34 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:29,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 36 transitions. [2021-11-09 09:50:29,305 INFO L704 BuchiCegarLoop]: Abstraction has 35 states and 36 transitions. [2021-11-09 09:50:29,305 INFO L587 BuchiCegarLoop]: Abstraction has 35 states and 36 transitions. [2021-11-09 09:50:29,305 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-09 09:50:29,305 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35 states and 36 transitions. [2021-11-09 09:50:29,306 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:29,306 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:29,306 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:29,309 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [14, 14, 1, 1, 1, 1] [2021-11-09 09:50:29,309 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:29,309 INFO L791 eck$LassoCheckResult]: Stem: 1886#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 1887#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 1888#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1889#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1890#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1884#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1885#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1916#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1915#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1914#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1913#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1912#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1911#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1910#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1909#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1908#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1907#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1906#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1905#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1904#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1903#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1902#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1901#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1900#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1899#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1898#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1897#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1896#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1895#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 1894#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 1893#L25-3 assume !(main_~i~0 < 1023); 1891#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 1892#L30-4 [2021-11-09 09:50:29,309 INFO L793 eck$LassoCheckResult]: Loop: 1892#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 1882#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 1883#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 1892#L30-4 [2021-11-09 09:50:29,309 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:29,309 INFO L85 PathProgramCache]: Analyzing trace with hash -1283882329, now seen corresponding path program 14 times [2021-11-09 09:50:29,310 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:29,310 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [497489289] [2021-11-09 09:50:29,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:29,310 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:29,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:29,500 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:29,500 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:29,501 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [497489289] [2021-11-09 09:50:29,501 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [497489289] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:29,501 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1022542393] [2021-11-09 09:50:29,501 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:50:29,501 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:29,501 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:29,503 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:29,504 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2021-11-09 09:50:29,652 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:50:29,653 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:29,654 INFO L263 TraceCheckSpWp]: Trace formula consists of 155 conjuncts, 16 conjunts are in the unsatisfiable core [2021-11-09 09:50:29,655 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:29,762 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:29,762 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1022542393] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:29,763 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:29,763 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 18 [2021-11-09 09:50:29,763 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1025555690] [2021-11-09 09:50:29,763 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:29,764 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:29,764 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 15 times [2021-11-09 09:50:29,764 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:29,764 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1975124746] [2021-11-09 09:50:29,764 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:29,764 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:29,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:29,769 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:29,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:29,771 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:29,801 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:29,801 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2021-11-09 09:50:29,801 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2021-11-09 09:50:29,802 INFO L87 Difference]: Start difference. First operand 35 states and 36 transitions. cyclomatic complexity: 3 Second operand has 18 states, 18 states have (on average 1.9444444444444444) internal successors, (35), 18 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:29,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:29,916 INFO L93 Difference]: Finished difference Result 83 states and 84 transitions. [2021-11-09 09:50:29,916 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2021-11-09 09:50:29,917 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 83 states and 84 transitions. [2021-11-09 09:50:29,918 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:29,918 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 83 states to 83 states and 84 transitions. [2021-11-09 09:50:29,919 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 52 [2021-11-09 09:50:29,919 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 52 [2021-11-09 09:50:29,919 INFO L73 IsDeterministic]: Start isDeterministic. Operand 83 states and 84 transitions. [2021-11-09 09:50:29,919 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:29,919 INFO L681 BuchiCegarLoop]: Abstraction has 83 states and 84 transitions. [2021-11-09 09:50:29,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 83 states and 84 transitions. [2021-11-09 09:50:29,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 83 to 37. [2021-11-09 09:50:29,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 37 states have (on average 1.027027027027027) internal successors, (38), 36 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:29,922 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 38 transitions. [2021-11-09 09:50:29,922 INFO L704 BuchiCegarLoop]: Abstraction has 37 states and 38 transitions. [2021-11-09 09:50:29,922 INFO L587 BuchiCegarLoop]: Abstraction has 37 states and 38 transitions. [2021-11-09 09:50:29,922 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-09 09:50:29,922 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37 states and 38 transitions. [2021-11-09 09:50:29,923 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:29,923 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:29,923 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:29,924 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [15, 15, 1, 1, 1, 1] [2021-11-09 09:50:29,924 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:29,924 INFO L791 eck$LassoCheckResult]: Stem: 2118#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 2119#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 2120#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2121#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2122#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2116#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2117#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2150#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2149#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2148#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2147#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2146#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2145#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2144#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2143#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2142#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2141#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2140#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2139#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2138#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2137#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2136#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2135#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2134#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2133#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2132#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2131#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2130#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2129#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2128#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2127#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2126#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2125#L25-3 assume !(main_~i~0 < 1023); 2123#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 2124#L30-4 [2021-11-09 09:50:29,924 INFO L793 eck$LassoCheckResult]: Loop: 2124#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 2114#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 2115#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 2124#L30-4 [2021-11-09 09:50:29,924 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:29,925 INFO L85 PathProgramCache]: Analyzing trace with hash -1155248215, now seen corresponding path program 15 times [2021-11-09 09:50:29,925 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:29,925 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [85957310] [2021-11-09 09:50:29,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:29,925 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:29,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:30,103 INFO L134 CoverageAnalysis]: Checked inductivity of 225 backedges. 0 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:30,103 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:30,104 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [85957310] [2021-11-09 09:50:30,104 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [85957310] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:30,104 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [603659103] [2021-11-09 09:50:30,104 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:50:30,104 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:30,104 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:30,106 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:30,119 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2021-11-09 09:50:30,372 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2021-11-09 09:50:30,372 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:30,374 INFO L263 TraceCheckSpWp]: Trace formula consists of 163 conjuncts, 17 conjunts are in the unsatisfiable core [2021-11-09 09:50:30,376 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:30,511 INFO L134 CoverageAnalysis]: Checked inductivity of 225 backedges. 0 proven. 225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:30,512 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [603659103] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:30,512 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:30,512 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 19 [2021-11-09 09:50:30,512 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [779000373] [2021-11-09 09:50:30,513 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:30,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:30,513 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 16 times [2021-11-09 09:50:30,513 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:30,513 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [467860677] [2021-11-09 09:50:30,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:30,514 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:30,517 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:30,518 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:30,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:30,520 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:30,548 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:30,549 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2021-11-09 09:50:30,549 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2021-11-09 09:50:30,549 INFO L87 Difference]: Start difference. First operand 37 states and 38 transitions. cyclomatic complexity: 3 Second operand has 19 states, 19 states have (on average 1.9473684210526316) internal successors, (37), 19 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:30,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:30,649 INFO L93 Difference]: Finished difference Result 88 states and 89 transitions. [2021-11-09 09:50:30,650 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2021-11-09 09:50:30,650 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88 states and 89 transitions. [2021-11-09 09:50:30,651 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:30,652 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88 states to 88 states and 89 transitions. [2021-11-09 09:50:30,652 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55 [2021-11-09 09:50:30,652 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55 [2021-11-09 09:50:30,652 INFO L73 IsDeterministic]: Start isDeterministic. Operand 88 states and 89 transitions. [2021-11-09 09:50:30,652 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:30,652 INFO L681 BuchiCegarLoop]: Abstraction has 88 states and 89 transitions. [2021-11-09 09:50:30,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states and 89 transitions. [2021-11-09 09:50:30,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 39. [2021-11-09 09:50:30,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 39 states have (on average 1.0256410256410255) internal successors, (40), 38 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:30,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 40 transitions. [2021-11-09 09:50:30,655 INFO L704 BuchiCegarLoop]: Abstraction has 39 states and 40 transitions. [2021-11-09 09:50:30,655 INFO L587 BuchiCegarLoop]: Abstraction has 39 states and 40 transitions. [2021-11-09 09:50:30,655 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-09 09:50:30,655 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39 states and 40 transitions. [2021-11-09 09:50:30,656 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:30,656 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:30,656 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:30,657 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [16, 16, 1, 1, 1, 1] [2021-11-09 09:50:30,657 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:30,657 INFO L791 eck$LassoCheckResult]: Stem: 2364#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 2365#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 2366#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2367#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2368#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2362#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2363#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2398#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2397#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2396#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2395#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2394#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2393#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2392#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2391#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2390#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2389#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2388#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2387#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2386#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2385#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2384#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2383#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2382#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2381#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2380#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2379#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2378#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2377#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2376#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2375#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2374#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2373#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2372#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2371#L25-3 assume !(main_~i~0 < 1023); 2369#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 2370#L30-4 [2021-11-09 09:50:30,657 INFO L793 eck$LassoCheckResult]: Loop: 2370#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 2360#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 2361#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 2370#L30-4 [2021-11-09 09:50:30,658 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:30,658 INFO L85 PathProgramCache]: Analyzing trace with hash -2091916245, now seen corresponding path program 16 times [2021-11-09 09:50:30,658 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:30,658 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1440351677] [2021-11-09 09:50:30,658 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:30,658 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:30,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:30,866 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:30,866 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:30,866 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1440351677] [2021-11-09 09:50:30,867 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1440351677] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:30,867 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [77515803] [2021-11-09 09:50:30,867 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:50:30,867 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:30,867 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:30,873 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:30,882 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2021-11-09 09:50:31,042 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:50:31,042 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:31,044 INFO L263 TraceCheckSpWp]: Trace formula consists of 171 conjuncts, 18 conjunts are in the unsatisfiable core [2021-11-09 09:50:31,045 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:31,189 INFO L134 CoverageAnalysis]: Checked inductivity of 256 backedges. 0 proven. 256 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:31,189 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [77515803] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:31,189 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:31,190 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 20 [2021-11-09 09:50:31,190 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1763440143] [2021-11-09 09:50:31,191 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:31,191 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:31,191 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 17 times [2021-11-09 09:50:31,191 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:31,192 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1301479225] [2021-11-09 09:50:31,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:31,192 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:31,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:31,200 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:31,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:31,214 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:31,245 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:31,246 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2021-11-09 09:50:31,246 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2021-11-09 09:50:31,246 INFO L87 Difference]: Start difference. First operand 39 states and 40 transitions. cyclomatic complexity: 3 Second operand has 20 states, 20 states have (on average 1.95) internal successors, (39), 20 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:31,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:31,356 INFO L93 Difference]: Finished difference Result 93 states and 94 transitions. [2021-11-09 09:50:31,356 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2021-11-09 09:50:31,356 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 93 states and 94 transitions. [2021-11-09 09:50:31,357 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:31,358 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 93 states to 93 states and 94 transitions. [2021-11-09 09:50:31,359 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 58 [2021-11-09 09:50:31,359 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 58 [2021-11-09 09:50:31,359 INFO L73 IsDeterministic]: Start isDeterministic. Operand 93 states and 94 transitions. [2021-11-09 09:50:31,359 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:31,360 INFO L681 BuchiCegarLoop]: Abstraction has 93 states and 94 transitions. [2021-11-09 09:50:31,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states and 94 transitions. [2021-11-09 09:50:31,365 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 41. [2021-11-09 09:50:31,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 41 states have (on average 1.024390243902439) internal successors, (42), 40 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:31,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 42 transitions. [2021-11-09 09:50:31,366 INFO L704 BuchiCegarLoop]: Abstraction has 41 states and 42 transitions. [2021-11-09 09:50:31,366 INFO L587 BuchiCegarLoop]: Abstraction has 41 states and 42 transitions. [2021-11-09 09:50:31,366 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-09 09:50:31,366 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41 states and 42 transitions. [2021-11-09 09:50:31,366 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:31,366 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:31,367 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:31,368 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [17, 17, 1, 1, 1, 1] [2021-11-09 09:50:31,368 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:31,368 INFO L791 eck$LassoCheckResult]: Stem: 2624#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 2625#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 2626#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2627#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2628#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2622#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2623#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2660#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2659#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2658#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2657#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2656#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2655#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2654#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2653#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2652#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2651#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2650#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2649#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2648#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2647#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2646#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2645#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2644#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2643#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2642#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2641#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2640#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2639#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2638#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2637#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2636#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2635#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2634#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2633#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2632#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2631#L25-3 assume !(main_~i~0 < 1023); 2629#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 2630#L30-4 [2021-11-09 09:50:31,369 INFO L793 eck$LassoCheckResult]: Loop: 2630#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 2620#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 2621#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 2630#L30-4 [2021-11-09 09:50:31,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:31,369 INFO L85 PathProgramCache]: Analyzing trace with hash -286760915, now seen corresponding path program 17 times [2021-11-09 09:50:31,369 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:31,369 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [20867609] [2021-11-09 09:50:31,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:31,370 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:31,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:31,589 INFO L134 CoverageAnalysis]: Checked inductivity of 289 backedges. 0 proven. 289 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:31,589 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:31,589 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [20867609] [2021-11-09 09:50:31,590 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [20867609] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:31,590 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1835520138] [2021-11-09 09:50:31,590 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:50:31,590 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:31,590 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:31,592 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:31,616 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2021-11-09 09:50:31,875 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2021-11-09 09:50:31,875 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:31,877 INFO L263 TraceCheckSpWp]: Trace formula consists of 179 conjuncts, 19 conjunts are in the unsatisfiable core [2021-11-09 09:50:31,878 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:32,022 INFO L134 CoverageAnalysis]: Checked inductivity of 289 backedges. 0 proven. 289 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:32,022 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1835520138] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:32,022 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:32,023 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 21 [2021-11-09 09:50:32,023 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [126904824] [2021-11-09 09:50:32,023 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:32,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:32,024 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 18 times [2021-11-09 09:50:32,024 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:32,024 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [255023538] [2021-11-09 09:50:32,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:32,024 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:32,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:32,028 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:32,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:32,030 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:32,065 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:32,066 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2021-11-09 09:50:32,066 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=210, Invalid=210, Unknown=0, NotChecked=0, Total=420 [2021-11-09 09:50:32,067 INFO L87 Difference]: Start difference. First operand 41 states and 42 transitions. cyclomatic complexity: 3 Second operand has 21 states, 21 states have (on average 1.9523809523809523) internal successors, (41), 21 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:32,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:32,205 INFO L93 Difference]: Finished difference Result 98 states and 99 transitions. [2021-11-09 09:50:32,205 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2021-11-09 09:50:32,205 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 98 states and 99 transitions. [2021-11-09 09:50:32,206 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:32,207 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 98 states to 98 states and 99 transitions. [2021-11-09 09:50:32,207 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 61 [2021-11-09 09:50:32,209 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 61 [2021-11-09 09:50:32,209 INFO L73 IsDeterministic]: Start isDeterministic. Operand 98 states and 99 transitions. [2021-11-09 09:50:32,210 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:32,210 INFO L681 BuchiCegarLoop]: Abstraction has 98 states and 99 transitions. [2021-11-09 09:50:32,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states and 99 transitions. [2021-11-09 09:50:32,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 43. [2021-11-09 09:50:32,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43 states, 43 states have (on average 1.0232558139534884) internal successors, (44), 42 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:32,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 44 transitions. [2021-11-09 09:50:32,212 INFO L704 BuchiCegarLoop]: Abstraction has 43 states and 44 transitions. [2021-11-09 09:50:32,212 INFO L587 BuchiCegarLoop]: Abstraction has 43 states and 44 transitions. [2021-11-09 09:50:32,212 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-09 09:50:32,212 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43 states and 44 transitions. [2021-11-09 09:50:32,213 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:32,213 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:32,213 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:32,218 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [18, 18, 1, 1, 1, 1] [2021-11-09 09:50:32,218 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:32,220 INFO L791 eck$LassoCheckResult]: Stem: 2898#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 2899#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 2900#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2901#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2902#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2896#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2897#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2936#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2935#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2934#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2933#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2932#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2931#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2930#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2929#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2928#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2927#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2926#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2925#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2924#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2923#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2922#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2921#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2920#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2919#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2918#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2917#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2916#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2915#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2914#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2913#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2912#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2911#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2910#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2909#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2908#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2907#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 2906#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 2905#L25-3 assume !(main_~i~0 < 1023); 2903#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 2904#L30-4 [2021-11-09 09:50:32,220 INFO L793 eck$LassoCheckResult]: Loop: 2904#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 2894#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 2895#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 2904#L30-4 [2021-11-09 09:50:32,221 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:32,221 INFO L85 PathProgramCache]: Analyzing trace with hash -699276369, now seen corresponding path program 18 times [2021-11-09 09:50:32,221 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:32,221 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1988379579] [2021-11-09 09:50:32,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:32,221 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:32,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:32,444 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 0 proven. 324 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:32,444 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:32,444 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1988379579] [2021-11-09 09:50:32,445 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1988379579] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:32,445 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1210030713] [2021-11-09 09:50:32,445 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:50:32,445 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:32,445 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:32,451 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:32,480 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2021-11-09 09:50:33,096 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2021-11-09 09:50:33,096 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:33,099 INFO L263 TraceCheckSpWp]: Trace formula consists of 187 conjuncts, 20 conjunts are in the unsatisfiable core [2021-11-09 09:50:33,100 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:33,233 INFO L134 CoverageAnalysis]: Checked inductivity of 324 backedges. 0 proven. 324 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:33,233 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1210030713] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:33,233 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:33,233 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21] total 22 [2021-11-09 09:50:33,234 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [891475527] [2021-11-09 09:50:33,234 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:33,234 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:33,234 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 19 times [2021-11-09 09:50:33,235 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:33,235 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2020732674] [2021-11-09 09:50:33,235 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:33,235 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:33,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:33,239 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:33,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:33,241 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:33,274 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:33,275 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2021-11-09 09:50:33,275 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2021-11-09 09:50:33,275 INFO L87 Difference]: Start difference. First operand 43 states and 44 transitions. cyclomatic complexity: 3 Second operand has 22 states, 22 states have (on average 1.9545454545454546) internal successors, (43), 22 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:33,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:33,410 INFO L93 Difference]: Finished difference Result 103 states and 104 transitions. [2021-11-09 09:50:33,410 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2021-11-09 09:50:33,410 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 103 states and 104 transitions. [2021-11-09 09:50:33,412 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:33,413 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 103 states to 103 states and 104 transitions. [2021-11-09 09:50:33,413 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 64 [2021-11-09 09:50:33,414 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 64 [2021-11-09 09:50:33,414 INFO L73 IsDeterministic]: Start isDeterministic. Operand 103 states and 104 transitions. [2021-11-09 09:50:33,414 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:33,414 INFO L681 BuchiCegarLoop]: Abstraction has 103 states and 104 transitions. [2021-11-09 09:50:33,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states and 104 transitions. [2021-11-09 09:50:33,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 45. [2021-11-09 09:50:33,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 45 states have (on average 1.0222222222222221) internal successors, (46), 44 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:33,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 46 transitions. [2021-11-09 09:50:33,425 INFO L704 BuchiCegarLoop]: Abstraction has 45 states and 46 transitions. [2021-11-09 09:50:33,425 INFO L587 BuchiCegarLoop]: Abstraction has 45 states and 46 transitions. [2021-11-09 09:50:33,426 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-09 09:50:33,426 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45 states and 46 transitions. [2021-11-09 09:50:33,426 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:33,426 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:33,426 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:33,428 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [19, 19, 1, 1, 1, 1] [2021-11-09 09:50:33,428 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:33,428 INFO L791 eck$LassoCheckResult]: Stem: 3186#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 3187#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 3188#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3189#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3190#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3184#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3185#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3226#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3225#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3224#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3223#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3222#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3221#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3220#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3219#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3218#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3217#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3216#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3215#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3214#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3213#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3212#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3211#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3210#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3209#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3208#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3207#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3206#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3205#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3204#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3203#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3202#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3201#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3200#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3199#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3198#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3197#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3196#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3195#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3194#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3193#L25-3 assume !(main_~i~0 < 1023); 3191#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 3192#L30-4 [2021-11-09 09:50:33,428 INFO L793 eck$LassoCheckResult]: Loop: 3192#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 3182#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 3183#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 3192#L30-4 [2021-11-09 09:50:33,429 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:33,429 INFO L85 PathProgramCache]: Analyzing trace with hash -1989636431, now seen corresponding path program 19 times [2021-11-09 09:50:33,429 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:33,429 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1812028764] [2021-11-09 09:50:33,429 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:33,430 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:33,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:33,704 INFO L134 CoverageAnalysis]: Checked inductivity of 361 backedges. 0 proven. 361 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:33,705 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:33,705 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1812028764] [2021-11-09 09:50:33,705 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1812028764] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:33,705 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [510696765] [2021-11-09 09:50:33,705 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:50:33,705 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:33,705 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:33,707 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:33,721 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2021-11-09 09:50:33,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:33,900 INFO L263 TraceCheckSpWp]: Trace formula consists of 195 conjuncts, 21 conjunts are in the unsatisfiable core [2021-11-09 09:50:33,901 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:34,060 INFO L134 CoverageAnalysis]: Checked inductivity of 361 backedges. 0 proven. 361 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:34,060 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [510696765] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:34,061 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:34,061 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 23 [2021-11-09 09:50:34,062 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [49492701] [2021-11-09 09:50:34,064 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:34,064 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:34,064 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 20 times [2021-11-09 09:50:34,064 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:34,064 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1716544957] [2021-11-09 09:50:34,064 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:34,065 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:34,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:34,069 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:34,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:34,072 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:34,104 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:34,105 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2021-11-09 09:50:34,105 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=253, Unknown=0, NotChecked=0, Total=506 [2021-11-09 09:50:34,106 INFO L87 Difference]: Start difference. First operand 45 states and 46 transitions. cyclomatic complexity: 3 Second operand has 23 states, 23 states have (on average 1.9565217391304348) internal successors, (45), 23 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:34,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:34,259 INFO L93 Difference]: Finished difference Result 108 states and 109 transitions. [2021-11-09 09:50:34,259 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2021-11-09 09:50:34,259 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 108 states and 109 transitions. [2021-11-09 09:50:34,264 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:34,266 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 108 states to 108 states and 109 transitions. [2021-11-09 09:50:34,268 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67 [2021-11-09 09:50:34,268 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67 [2021-11-09 09:50:34,269 INFO L73 IsDeterministic]: Start isDeterministic. Operand 108 states and 109 transitions. [2021-11-09 09:50:34,269 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:34,269 INFO L681 BuchiCegarLoop]: Abstraction has 108 states and 109 transitions. [2021-11-09 09:50:34,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states and 109 transitions. [2021-11-09 09:50:34,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 47. [2021-11-09 09:50:34,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 47 states have (on average 1.0212765957446808) internal successors, (48), 46 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:34,272 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 48 transitions. [2021-11-09 09:50:34,272 INFO L704 BuchiCegarLoop]: Abstraction has 47 states and 48 transitions. [2021-11-09 09:50:34,272 INFO L587 BuchiCegarLoop]: Abstraction has 47 states and 48 transitions. [2021-11-09 09:50:34,272 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-09 09:50:34,272 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 47 states and 48 transitions. [2021-11-09 09:50:34,272 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:34,273 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:34,273 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:34,273 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [20, 20, 1, 1, 1, 1] [2021-11-09 09:50:34,273 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:34,274 INFO L791 eck$LassoCheckResult]: Stem: 3488#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 3489#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 3490#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3491#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3492#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3486#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3487#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3530#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3529#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3528#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3527#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3526#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3525#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3524#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3523#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3522#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3521#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3520#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3519#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3518#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3517#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3516#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3515#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3514#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3513#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3512#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3511#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3510#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3509#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3508#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3507#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3506#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3505#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3504#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3503#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3502#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3501#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3500#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3499#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3498#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3497#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3496#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3495#L25-3 assume !(main_~i~0 < 1023); 3493#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 3494#L30-4 [2021-11-09 09:50:34,274 INFO L793 eck$LassoCheckResult]: Loop: 3494#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 3484#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 3485#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 3494#L30-4 [2021-11-09 09:50:34,274 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:34,274 INFO L85 PathProgramCache]: Analyzing trace with hash -780107469, now seen corresponding path program 20 times [2021-11-09 09:50:34,274 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:34,275 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1969748814] [2021-11-09 09:50:34,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:34,275 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:34,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:34,540 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 0 proven. 400 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:34,540 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:34,540 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1969748814] [2021-11-09 09:50:34,540 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1969748814] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:34,541 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [779135615] [2021-11-09 09:50:34,541 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:50:34,541 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:34,541 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:34,543 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:34,561 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2021-11-09 09:50:34,759 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:50:34,759 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:34,761 INFO L263 TraceCheckSpWp]: Trace formula consists of 203 conjuncts, 22 conjunts are in the unsatisfiable core [2021-11-09 09:50:34,783 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:34,936 INFO L134 CoverageAnalysis]: Checked inductivity of 400 backedges. 0 proven. 400 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:34,936 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [779135615] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:34,936 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:34,936 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23] total 24 [2021-11-09 09:50:34,936 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1717681413] [2021-11-09 09:50:34,937 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:34,937 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:34,937 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 21 times [2021-11-09 09:50:34,937 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:34,937 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [881230774] [2021-11-09 09:50:34,938 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:34,938 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:34,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:34,941 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:34,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:34,944 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:34,975 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:34,976 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2021-11-09 09:50:34,977 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2021-11-09 09:50:34,977 INFO L87 Difference]: Start difference. First operand 47 states and 48 transitions. cyclomatic complexity: 3 Second operand has 24 states, 24 states have (on average 1.9583333333333333) internal successors, (47), 24 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:35,118 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:35,118 INFO L93 Difference]: Finished difference Result 113 states and 114 transitions. [2021-11-09 09:50:35,118 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2021-11-09 09:50:35,118 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 113 states and 114 transitions. [2021-11-09 09:50:35,119 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:35,121 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 113 states to 113 states and 114 transitions. [2021-11-09 09:50:35,121 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 70 [2021-11-09 09:50:35,121 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 70 [2021-11-09 09:50:35,121 INFO L73 IsDeterministic]: Start isDeterministic. Operand 113 states and 114 transitions. [2021-11-09 09:50:35,121 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:35,122 INFO L681 BuchiCegarLoop]: Abstraction has 113 states and 114 transitions. [2021-11-09 09:50:35,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states and 114 transitions. [2021-11-09 09:50:35,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 49. [2021-11-09 09:50:35,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49 states, 49 states have (on average 1.0204081632653061) internal successors, (50), 48 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:35,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 50 transitions. [2021-11-09 09:50:35,123 INFO L704 BuchiCegarLoop]: Abstraction has 49 states and 50 transitions. [2021-11-09 09:50:35,124 INFO L587 BuchiCegarLoop]: Abstraction has 49 states and 50 transitions. [2021-11-09 09:50:35,124 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-11-09 09:50:35,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 49 states and 50 transitions. [2021-11-09 09:50:35,124 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:35,124 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:35,125 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:35,126 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [21, 21, 1, 1, 1, 1] [2021-11-09 09:50:35,126 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:35,126 INFO L791 eck$LassoCheckResult]: Stem: 3804#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 3805#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 3806#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3807#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3808#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3802#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3803#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3848#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3847#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3846#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3845#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3844#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3843#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3842#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3841#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3840#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3839#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3838#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3837#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3836#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3835#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3834#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3833#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3832#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3831#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3830#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3829#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3828#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3827#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3826#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3825#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3824#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3823#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3822#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3821#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3820#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3819#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3818#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3817#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3816#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3815#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3814#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3813#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 3812#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 3811#L25-3 assume !(main_~i~0 < 1023); 3809#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 3810#L30-4 [2021-11-09 09:50:35,126 INFO L793 eck$LassoCheckResult]: Loop: 3810#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 3800#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 3801#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 3810#L30-4 [2021-11-09 09:50:35,126 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:35,126 INFO L85 PathProgramCache]: Analyzing trace with hash 1936055093, now seen corresponding path program 21 times [2021-11-09 09:50:35,126 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:35,126 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1771857364] [2021-11-09 09:50:35,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:35,127 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:35,141 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:35,398 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 0 proven. 441 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:35,398 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:35,398 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1771857364] [2021-11-09 09:50:35,398 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1771857364] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:35,398 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [225974936] [2021-11-09 09:50:35,398 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:50:35,398 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:35,399 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:35,406 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:35,424 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2021-11-09 09:50:36,093 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2021-11-09 09:50:36,093 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:36,097 INFO L263 TraceCheckSpWp]: Trace formula consists of 211 conjuncts, 23 conjunts are in the unsatisfiable core [2021-11-09 09:50:36,098 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:36,288 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 0 proven. 441 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:36,289 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [225974936] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:36,289 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:36,289 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24] total 25 [2021-11-09 09:50:36,289 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1481714674] [2021-11-09 09:50:36,289 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:36,290 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:36,290 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 22 times [2021-11-09 09:50:36,290 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:36,290 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1681547305] [2021-11-09 09:50:36,290 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:36,291 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:36,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:36,296 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:36,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:36,299 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:36,333 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:36,333 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2021-11-09 09:50:36,334 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2021-11-09 09:50:36,334 INFO L87 Difference]: Start difference. First operand 49 states and 50 transitions. cyclomatic complexity: 3 Second operand has 25 states, 25 states have (on average 1.96) internal successors, (49), 25 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:36,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:36,455 INFO L93 Difference]: Finished difference Result 118 states and 119 transitions. [2021-11-09 09:50:36,455 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2021-11-09 09:50:36,455 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 118 states and 119 transitions. [2021-11-09 09:50:36,456 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:36,457 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 118 states to 118 states and 119 transitions. [2021-11-09 09:50:36,458 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 73 [2021-11-09 09:50:36,458 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 73 [2021-11-09 09:50:36,458 INFO L73 IsDeterministic]: Start isDeterministic. Operand 118 states and 119 transitions. [2021-11-09 09:50:36,458 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:36,459 INFO L681 BuchiCegarLoop]: Abstraction has 118 states and 119 transitions. [2021-11-09 09:50:36,459 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states and 119 transitions. [2021-11-09 09:50:36,460 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 51. [2021-11-09 09:50:36,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 51 states have (on average 1.0196078431372548) internal successors, (52), 50 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:36,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 52 transitions. [2021-11-09 09:50:36,461 INFO L704 BuchiCegarLoop]: Abstraction has 51 states and 52 transitions. [2021-11-09 09:50:36,461 INFO L587 BuchiCegarLoop]: Abstraction has 51 states and 52 transitions. [2021-11-09 09:50:36,461 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-11-09 09:50:36,461 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51 states and 52 transitions. [2021-11-09 09:50:36,462 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:36,462 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:36,462 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:36,463 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [22, 22, 1, 1, 1, 1] [2021-11-09 09:50:36,463 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:36,463 INFO L791 eck$LassoCheckResult]: Stem: 4134#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 4135#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 4136#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4137#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4138#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4132#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4133#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4180#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4179#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4178#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4177#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4176#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4175#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4174#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4173#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4172#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4171#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4170#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4169#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4168#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4167#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4166#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4165#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4164#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4163#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4162#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4161#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4160#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4159#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4158#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4157#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4156#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4155#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4154#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4153#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4152#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4151#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4150#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4149#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4148#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4147#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4146#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4145#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4144#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4143#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4142#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4141#L25-3 assume !(main_~i~0 < 1023); 4139#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 4140#L30-4 [2021-11-09 09:50:36,464 INFO L793 eck$LassoCheckResult]: Loop: 4140#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 4130#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 4131#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 4140#L30-4 [2021-11-09 09:50:36,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:36,464 INFO L85 PathProgramCache]: Analyzing trace with hash 828161207, now seen corresponding path program 22 times [2021-11-09 09:50:36,464 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:36,465 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1114378458] [2021-11-09 09:50:36,465 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:36,465 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:36,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:36,728 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:36,728 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:36,729 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1114378458] [2021-11-09 09:50:36,729 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1114378458] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:36,729 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1543193700] [2021-11-09 09:50:36,729 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:50:36,729 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:36,729 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:36,737 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:36,745 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2021-11-09 09:50:36,963 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:50:36,963 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:36,964 INFO L263 TraceCheckSpWp]: Trace formula consists of 219 conjuncts, 24 conjunts are in the unsatisfiable core [2021-11-09 09:50:36,965 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:37,126 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:37,127 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1543193700] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:37,127 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:37,127 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25] total 26 [2021-11-09 09:50:37,127 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1849129572] [2021-11-09 09:50:37,128 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:37,128 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:37,128 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 23 times [2021-11-09 09:50:37,128 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:37,128 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1756985145] [2021-11-09 09:50:37,128 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:37,129 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:37,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:37,134 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:37,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:37,137 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:37,167 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:37,168 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2021-11-09 09:50:37,169 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2021-11-09 09:50:37,170 INFO L87 Difference]: Start difference. First operand 51 states and 52 transitions. cyclomatic complexity: 3 Second operand has 26 states, 26 states have (on average 1.9615384615384615) internal successors, (51), 26 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:37,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:37,350 INFO L93 Difference]: Finished difference Result 123 states and 124 transitions. [2021-11-09 09:50:37,365 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2021-11-09 09:50:37,366 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 123 states and 124 transitions. [2021-11-09 09:50:37,369 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:37,371 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 123 states to 123 states and 124 transitions. [2021-11-09 09:50:37,371 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 76 [2021-11-09 09:50:37,371 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 76 [2021-11-09 09:50:37,371 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123 states and 124 transitions. [2021-11-09 09:50:37,371 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:37,372 INFO L681 BuchiCegarLoop]: Abstraction has 123 states and 124 transitions. [2021-11-09 09:50:37,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123 states and 124 transitions. [2021-11-09 09:50:37,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123 to 53. [2021-11-09 09:50:37,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53 states, 53 states have (on average 1.0188679245283019) internal successors, (54), 52 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:37,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 54 transitions. [2021-11-09 09:50:37,375 INFO L704 BuchiCegarLoop]: Abstraction has 53 states and 54 transitions. [2021-11-09 09:50:37,375 INFO L587 BuchiCegarLoop]: Abstraction has 53 states and 54 transitions. [2021-11-09 09:50:37,375 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-11-09 09:50:37,375 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53 states and 54 transitions. [2021-11-09 09:50:37,378 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:37,378 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:37,378 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:37,379 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [23, 23, 1, 1, 1, 1] [2021-11-09 09:50:37,379 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:37,379 INFO L791 eck$LassoCheckResult]: Stem: 4478#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 4479#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 4480#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4481#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4482#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4476#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4477#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4526#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4525#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4524#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4523#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4522#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4521#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4520#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4519#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4518#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4517#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4516#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4515#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4514#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4513#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4512#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4511#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4510#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4509#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4508#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4507#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4506#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4505#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4504#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4503#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4502#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4501#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4500#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4499#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4498#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4497#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4496#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4495#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4494#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4493#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4492#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4491#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4490#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4489#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4488#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4487#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4486#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4485#L25-3 assume !(main_~i~0 < 1023); 4483#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 4484#L30-4 [2021-11-09 09:50:37,379 INFO L793 eck$LassoCheckResult]: Loop: 4484#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 4474#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 4475#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 4484#L30-4 [2021-11-09 09:50:37,380 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:37,380 INFO L85 PathProgramCache]: Analyzing trace with hash 1294026169, now seen corresponding path program 23 times [2021-11-09 09:50:37,380 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:37,380 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [654898484] [2021-11-09 09:50:37,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:37,381 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:37,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:37,689 INFO L134 CoverageAnalysis]: Checked inductivity of 529 backedges. 0 proven. 529 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:37,689 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:37,690 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [654898484] [2021-11-09 09:50:37,690 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [654898484] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:37,690 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [700926171] [2021-11-09 09:50:37,690 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:50:37,690 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:37,690 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:37,691 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:37,692 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2021-11-09 09:50:38,317 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2021-11-09 09:50:38,317 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:38,320 INFO L263 TraceCheckSpWp]: Trace formula consists of 227 conjuncts, 25 conjunts are in the unsatisfiable core [2021-11-09 09:50:38,321 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:38,476 INFO L134 CoverageAnalysis]: Checked inductivity of 529 backedges. 0 proven. 529 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:38,476 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [700926171] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:38,476 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:38,477 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26] total 27 [2021-11-09 09:50:38,477 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [289336699] [2021-11-09 09:50:38,477 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:38,477 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:38,477 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 24 times [2021-11-09 09:50:38,477 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:38,477 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [144829593] [2021-11-09 09:50:38,477 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:38,478 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:38,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:38,500 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:38,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:38,504 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:38,533 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:38,534 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2021-11-09 09:50:38,534 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=351, Invalid=351, Unknown=0, NotChecked=0, Total=702 [2021-11-09 09:50:38,534 INFO L87 Difference]: Start difference. First operand 53 states and 54 transitions. cyclomatic complexity: 3 Second operand has 27 states, 27 states have (on average 1.962962962962963) internal successors, (53), 27 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:38,714 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:38,714 INFO L93 Difference]: Finished difference Result 128 states and 129 transitions. [2021-11-09 09:50:38,714 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2021-11-09 09:50:38,714 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128 states and 129 transitions. [2021-11-09 09:50:38,715 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:38,716 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128 states to 128 states and 129 transitions. [2021-11-09 09:50:38,716 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 79 [2021-11-09 09:50:38,716 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 79 [2021-11-09 09:50:38,717 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128 states and 129 transitions. [2021-11-09 09:50:38,717 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:38,717 INFO L681 BuchiCegarLoop]: Abstraction has 128 states and 129 transitions. [2021-11-09 09:50:38,717 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states and 129 transitions. [2021-11-09 09:50:38,718 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 55. [2021-11-09 09:50:38,719 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 55 states have (on average 1.018181818181818) internal successors, (56), 54 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:38,719 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 56 transitions. [2021-11-09 09:50:38,719 INFO L704 BuchiCegarLoop]: Abstraction has 55 states and 56 transitions. [2021-11-09 09:50:38,719 INFO L587 BuchiCegarLoop]: Abstraction has 55 states and 56 transitions. [2021-11-09 09:50:38,719 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-11-09 09:50:38,719 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 55 states and 56 transitions. [2021-11-09 09:50:38,720 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:38,720 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:38,720 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:38,721 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [24, 24, 1, 1, 1, 1] [2021-11-09 09:50:38,721 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:38,721 INFO L791 eck$LassoCheckResult]: Stem: 4836#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 4837#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 4838#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4839#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4840#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4834#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4835#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4886#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4885#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4884#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4883#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4882#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4881#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4880#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4879#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4878#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4877#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4876#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4875#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4874#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4873#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4872#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4871#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4870#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4869#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4868#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4867#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4866#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4865#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4864#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4863#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4862#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4861#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4860#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4859#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4858#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4857#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4856#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4855#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4854#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4853#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4852#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4851#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4850#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4849#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4848#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4847#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4846#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4845#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 4844#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 4843#L25-3 assume !(main_~i~0 < 1023); 4841#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 4842#L30-4 [2021-11-09 09:50:38,721 INFO L793 eck$LassoCheckResult]: Loop: 4842#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 4832#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 4833#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 4842#L30-4 [2021-11-09 09:50:38,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:38,722 INFO L85 PathProgramCache]: Analyzing trace with hash -1981311429, now seen corresponding path program 24 times [2021-11-09 09:50:38,722 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:38,722 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500105127] [2021-11-09 09:50:38,722 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:38,722 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:38,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:39,019 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 576 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:39,019 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:39,020 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [500105127] [2021-11-09 09:50:39,020 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [500105127] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:39,020 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [242471001] [2021-11-09 09:50:39,020 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:50:39,020 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:39,020 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:39,027 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:39,029 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2021-11-09 09:50:42,079 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) [2021-11-09 09:50:42,079 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:42,087 INFO L263 TraceCheckSpWp]: Trace formula consists of 235 conjuncts, 26 conjunts are in the unsatisfiable core [2021-11-09 09:50:42,088 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:42,251 INFO L134 CoverageAnalysis]: Checked inductivity of 576 backedges. 0 proven. 576 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:42,251 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [242471001] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:42,251 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:42,252 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27] total 28 [2021-11-09 09:50:42,252 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1233477782] [2021-11-09 09:50:42,253 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:42,253 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:42,253 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 25 times [2021-11-09 09:50:42,253 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:42,254 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1019812761] [2021-11-09 09:50:42,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:42,255 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:42,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:42,259 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:42,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:42,265 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:42,297 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:42,297 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2021-11-09 09:50:42,298 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2021-11-09 09:50:42,298 INFO L87 Difference]: Start difference. First operand 55 states and 56 transitions. cyclomatic complexity: 3 Second operand has 28 states, 28 states have (on average 1.9642857142857142) internal successors, (55), 28 states have internal predecessors, (55), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:42,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:42,492 INFO L93 Difference]: Finished difference Result 133 states and 134 transitions. [2021-11-09 09:50:42,492 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2021-11-09 09:50:42,493 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 133 states and 134 transitions. [2021-11-09 09:50:42,494 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:42,495 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 133 states to 133 states and 134 transitions. [2021-11-09 09:50:42,495 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 82 [2021-11-09 09:50:42,495 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 82 [2021-11-09 09:50:42,496 INFO L73 IsDeterministic]: Start isDeterministic. Operand 133 states and 134 transitions. [2021-11-09 09:50:42,496 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:42,496 INFO L681 BuchiCegarLoop]: Abstraction has 133 states and 134 transitions. [2021-11-09 09:50:42,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states and 134 transitions. [2021-11-09 09:50:42,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 57. [2021-11-09 09:50:42,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 57 states have (on average 1.0175438596491229) internal successors, (58), 56 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:42,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 58 transitions. [2021-11-09 09:50:42,498 INFO L704 BuchiCegarLoop]: Abstraction has 57 states and 58 transitions. [2021-11-09 09:50:42,498 INFO L587 BuchiCegarLoop]: Abstraction has 57 states and 58 transitions. [2021-11-09 09:50:42,498 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-11-09 09:50:42,498 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 57 states and 58 transitions. [2021-11-09 09:50:42,499 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:42,499 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:42,499 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:42,500 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [25, 25, 1, 1, 1, 1] [2021-11-09 09:50:42,500 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:42,500 INFO L791 eck$LassoCheckResult]: Stem: 5208#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 5209#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 5210#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5211#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5212#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5206#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5207#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5260#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5259#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5258#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5257#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5256#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5255#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5254#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5253#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5252#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5251#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5250#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5249#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5248#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5247#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5246#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5245#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5244#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5243#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5242#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5241#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5240#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5239#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5238#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5237#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5236#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5235#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5234#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5233#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5232#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5231#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5230#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5229#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5228#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5227#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5226#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5225#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5224#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5223#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5222#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5221#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5220#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5219#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5218#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5217#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5216#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5215#L25-3 assume !(main_~i~0 < 1023); 5213#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 5214#L30-4 [2021-11-09 09:50:42,500 INFO L793 eck$LassoCheckResult]: Loop: 5214#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 5204#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 5205#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 5214#L30-4 [2021-11-09 09:50:42,501 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:42,501 INFO L85 PathProgramCache]: Analyzing trace with hash -1369715139, now seen corresponding path program 25 times [2021-11-09 09:50:42,501 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:42,501 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [111665773] [2021-11-09 09:50:42,501 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:42,501 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:42,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:42,824 INFO L134 CoverageAnalysis]: Checked inductivity of 625 backedges. 0 proven. 625 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:42,825 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:42,825 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [111665773] [2021-11-09 09:50:42,825 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [111665773] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:42,825 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1054304107] [2021-11-09 09:50:42,825 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:50:42,825 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:42,825 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:42,826 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:42,827 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2021-11-09 09:50:43,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:43,093 INFO L263 TraceCheckSpWp]: Trace formula consists of 243 conjuncts, 27 conjunts are in the unsatisfiable core [2021-11-09 09:50:43,094 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:43,291 INFO L134 CoverageAnalysis]: Checked inductivity of 625 backedges. 0 proven. 625 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:43,291 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1054304107] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:43,291 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:43,291 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28] total 29 [2021-11-09 09:50:43,292 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1668392430] [2021-11-09 09:50:43,292 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:43,292 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:43,292 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 26 times [2021-11-09 09:50:43,293 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:43,293 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2087528003] [2021-11-09 09:50:43,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:43,293 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:43,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:43,300 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:43,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:43,302 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:43,331 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:43,331 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2021-11-09 09:50:43,332 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=406, Invalid=406, Unknown=0, NotChecked=0, Total=812 [2021-11-09 09:50:43,332 INFO L87 Difference]: Start difference. First operand 57 states and 58 transitions. cyclomatic complexity: 3 Second operand has 29 states, 29 states have (on average 1.9655172413793103) internal successors, (57), 29 states have internal predecessors, (57), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:43,530 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:43,530 INFO L93 Difference]: Finished difference Result 138 states and 139 transitions. [2021-11-09 09:50:43,531 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2021-11-09 09:50:43,531 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 138 states and 139 transitions. [2021-11-09 09:50:43,532 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:43,533 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 138 states to 138 states and 139 transitions. [2021-11-09 09:50:43,534 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 85 [2021-11-09 09:50:43,534 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 85 [2021-11-09 09:50:43,534 INFO L73 IsDeterministic]: Start isDeterministic. Operand 138 states and 139 transitions. [2021-11-09 09:50:43,534 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:43,534 INFO L681 BuchiCegarLoop]: Abstraction has 138 states and 139 transitions. [2021-11-09 09:50:43,535 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states and 139 transitions. [2021-11-09 09:50:43,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 59. [2021-11-09 09:50:43,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 59 states have (on average 1.0169491525423728) internal successors, (60), 58 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:43,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 60 transitions. [2021-11-09 09:50:43,537 INFO L704 BuchiCegarLoop]: Abstraction has 59 states and 60 transitions. [2021-11-09 09:50:43,537 INFO L587 BuchiCegarLoop]: Abstraction has 59 states and 60 transitions. [2021-11-09 09:50:43,537 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-11-09 09:50:43,537 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59 states and 60 transitions. [2021-11-09 09:50:43,538 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:43,538 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:43,538 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:43,539 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [26, 26, 1, 1, 1, 1] [2021-11-09 09:50:43,539 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:43,539 INFO L791 eck$LassoCheckResult]: Stem: 5594#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 5595#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 5596#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5597#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5598#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5592#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5593#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5648#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5647#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5646#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5645#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5644#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5643#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5642#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5641#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5640#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5639#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5638#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5637#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5636#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5635#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5634#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5633#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5632#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5631#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5630#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5629#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5628#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5627#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5626#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5625#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5624#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5623#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5622#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5621#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5620#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5619#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5618#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5617#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5616#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5615#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5614#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5613#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5612#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5611#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5610#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5609#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5608#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5607#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5606#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5605#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5604#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5603#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5602#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5601#L25-3 assume !(main_~i~0 < 1023); 5599#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 5600#L30-4 [2021-11-09 09:50:43,539 INFO L793 eck$LassoCheckResult]: Loop: 5600#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 5590#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 5591#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 5600#L30-4 [2021-11-09 09:50:43,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:43,540 INFO L85 PathProgramCache]: Analyzing trace with hash -2036200001, now seen corresponding path program 26 times [2021-11-09 09:50:43,540 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:43,540 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [633486667] [2021-11-09 09:50:43,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:43,541 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:43,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:43,979 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 0 proven. 676 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:43,980 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:43,980 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [633486667] [2021-11-09 09:50:43,980 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [633486667] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:43,980 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1009715423] [2021-11-09 09:50:43,980 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:50:43,980 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:43,980 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:43,989 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:44,005 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2021-11-09 09:50:44,380 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:50:44,380 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:44,382 INFO L263 TraceCheckSpWp]: Trace formula consists of 251 conjuncts, 28 conjunts are in the unsatisfiable core [2021-11-09 09:50:44,383 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:44,592 INFO L134 CoverageAnalysis]: Checked inductivity of 676 backedges. 0 proven. 676 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:44,592 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1009715423] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:44,592 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:44,592 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29] total 30 [2021-11-09 09:50:44,592 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1463037131] [2021-11-09 09:50:44,593 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:44,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:44,593 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 27 times [2021-11-09 09:50:44,593 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:44,593 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1938184938] [2021-11-09 09:50:44,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:44,594 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:44,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:44,598 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:44,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:44,600 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:44,627 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:44,627 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2021-11-09 09:50:44,628 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2021-11-09 09:50:44,628 INFO L87 Difference]: Start difference. First operand 59 states and 60 transitions. cyclomatic complexity: 3 Second operand has 30 states, 30 states have (on average 1.9666666666666666) internal successors, (59), 30 states have internal predecessors, (59), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:44,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:44,787 INFO L93 Difference]: Finished difference Result 143 states and 144 transitions. [2021-11-09 09:50:44,788 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2021-11-09 09:50:44,788 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 143 states and 144 transitions. [2021-11-09 09:50:44,789 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:44,790 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 143 states to 143 states and 144 transitions. [2021-11-09 09:50:44,790 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 88 [2021-11-09 09:50:44,790 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 88 [2021-11-09 09:50:44,790 INFO L73 IsDeterministic]: Start isDeterministic. Operand 143 states and 144 transitions. [2021-11-09 09:50:44,791 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:44,791 INFO L681 BuchiCegarLoop]: Abstraction has 143 states and 144 transitions. [2021-11-09 09:50:44,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143 states and 144 transitions. [2021-11-09 09:50:44,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143 to 61. [2021-11-09 09:50:44,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61 states, 61 states have (on average 1.0163934426229508) internal successors, (62), 60 states have internal predecessors, (62), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:44,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 62 transitions. [2021-11-09 09:50:44,793 INFO L704 BuchiCegarLoop]: Abstraction has 61 states and 62 transitions. [2021-11-09 09:50:44,793 INFO L587 BuchiCegarLoop]: Abstraction has 61 states and 62 transitions. [2021-11-09 09:50:44,793 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-11-09 09:50:44,793 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 61 states and 62 transitions. [2021-11-09 09:50:44,794 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:44,794 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:44,794 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:44,794 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [27, 27, 1, 1, 1, 1] [2021-11-09 09:50:44,795 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:44,795 INFO L791 eck$LassoCheckResult]: Stem: 5994#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 5995#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 5996#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5997#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5998#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 5992#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 5993#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6050#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6049#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6048#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6047#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6046#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6045#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6044#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6043#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6042#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6041#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6040#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6039#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6038#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6037#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6036#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6035#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6034#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6033#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6032#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6031#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6030#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6029#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6028#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6027#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6026#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6025#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6024#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6023#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6022#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6021#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6020#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6019#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6018#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6017#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6016#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6015#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6014#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6013#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6012#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6011#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6010#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6009#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6008#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6007#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6006#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6005#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6004#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6003#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6002#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6001#L25-3 assume !(main_~i~0 < 1023); 5999#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 6000#L30-4 [2021-11-09 09:50:44,795 INFO L793 eck$LassoCheckResult]: Loop: 6000#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 5990#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 5991#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 6000#L30-4 [2021-11-09 09:50:44,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:44,795 INFO L85 PathProgramCache]: Analyzing trace with hash 1716942017, now seen corresponding path program 27 times [2021-11-09 09:50:44,796 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:44,796 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [373097559] [2021-11-09 09:50:44,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:44,796 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:44,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:45,205 INFO L134 CoverageAnalysis]: Checked inductivity of 729 backedges. 0 proven. 729 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:45,205 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:45,205 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [373097559] [2021-11-09 09:50:45,205 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [373097559] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:45,205 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1905566177] [2021-11-09 09:50:45,205 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:50:45,206 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:45,206 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:45,211 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:45,228 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2021-11-09 09:50:53,575 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2021-11-09 09:50:53,575 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:53,593 INFO L263 TraceCheckSpWp]: Trace formula consists of 259 conjuncts, 29 conjunts are in the unsatisfiable core [2021-11-09 09:50:53,594 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:53,803 INFO L134 CoverageAnalysis]: Checked inductivity of 729 backedges. 0 proven. 729 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:53,803 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1905566177] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:53,803 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:53,803 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 31 [2021-11-09 09:50:53,804 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2085137174] [2021-11-09 09:50:53,804 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:53,804 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:53,804 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 28 times [2021-11-09 09:50:53,805 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:53,805 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1820419206] [2021-11-09 09:50:53,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:53,805 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:53,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:53,810 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:53,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:53,813 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:53,852 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:53,852 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2021-11-09 09:50:53,853 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=465, Invalid=465, Unknown=0, NotChecked=0, Total=930 [2021-11-09 09:50:53,853 INFO L87 Difference]: Start difference. First operand 61 states and 62 transitions. cyclomatic complexity: 3 Second operand has 31 states, 31 states have (on average 1.967741935483871) internal successors, (61), 31 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:54,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:54,056 INFO L93 Difference]: Finished difference Result 148 states and 149 transitions. [2021-11-09 09:50:54,056 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2021-11-09 09:50:54,057 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 148 states and 149 transitions. [2021-11-09 09:50:54,058 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:54,059 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 148 states to 148 states and 149 transitions. [2021-11-09 09:50:54,059 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 91 [2021-11-09 09:50:54,060 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 91 [2021-11-09 09:50:54,060 INFO L73 IsDeterministic]: Start isDeterministic. Operand 148 states and 149 transitions. [2021-11-09 09:50:54,060 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:54,060 INFO L681 BuchiCegarLoop]: Abstraction has 148 states and 149 transitions. [2021-11-09 09:50:54,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states and 149 transitions. [2021-11-09 09:50:54,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 63. [2021-11-09 09:50:54,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63 states, 63 states have (on average 1.0158730158730158) internal successors, (64), 62 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:54,063 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 64 transitions. [2021-11-09 09:50:54,063 INFO L704 BuchiCegarLoop]: Abstraction has 63 states and 64 transitions. [2021-11-09 09:50:54,063 INFO L587 BuchiCegarLoop]: Abstraction has 63 states and 64 transitions. [2021-11-09 09:50:54,063 INFO L425 BuchiCegarLoop]: ======== Iteration 30============ [2021-11-09 09:50:54,063 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 63 states and 64 transitions. [2021-11-09 09:50:54,064 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:54,064 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:54,064 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:54,064 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [28, 28, 1, 1, 1, 1] [2021-11-09 09:50:54,065 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:54,065 INFO L791 eck$LassoCheckResult]: Stem: 6408#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 6409#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 6410#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6411#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6412#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6406#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6407#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6466#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6465#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6464#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6463#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6462#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6461#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6460#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6459#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6458#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6457#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6456#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6455#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6454#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6453#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6452#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6451#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6450#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6449#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6448#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6447#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6446#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6445#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6444#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6443#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6442#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6441#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6440#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6439#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6438#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6437#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6436#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6435#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6434#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6433#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6432#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6431#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6430#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6429#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6428#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6427#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6426#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6425#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6424#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6423#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6422#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6421#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6420#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6419#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6418#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6417#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6416#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6415#L25-3 assume !(main_~i~0 < 1023); 6413#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 6414#L30-4 [2021-11-09 09:50:54,065 INFO L793 eck$LassoCheckResult]: Loop: 6414#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 6404#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 6405#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 6414#L30-4 [2021-11-09 09:50:54,065 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:54,066 INFO L85 PathProgramCache]: Analyzing trace with hash 713892675, now seen corresponding path program 28 times [2021-11-09 09:50:54,066 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:54,066 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [869599291] [2021-11-09 09:50:54,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:54,066 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:54,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:54,554 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 0 proven. 784 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:54,554 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:54,554 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [869599291] [2021-11-09 09:50:54,554 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [869599291] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:54,554 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [629953012] [2021-11-09 09:50:54,554 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:50:54,554 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:54,554 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:54,559 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:54,576 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2021-11-09 09:50:55,000 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:50:55,000 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:55,003 INFO L263 TraceCheckSpWp]: Trace formula consists of 267 conjuncts, 30 conjunts are in the unsatisfiable core [2021-11-09 09:50:55,004 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:55,223 INFO L134 CoverageAnalysis]: Checked inductivity of 784 backedges. 0 proven. 784 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:55,223 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [629953012] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:55,224 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:55,224 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31] total 32 [2021-11-09 09:50:55,224 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1534633791] [2021-11-09 09:50:55,224 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:55,225 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:55,225 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 29 times [2021-11-09 09:50:55,225 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:55,225 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1776656928] [2021-11-09 09:50:55,225 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:55,225 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:55,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:55,230 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:55,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:55,232 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:55,265 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:55,266 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2021-11-09 09:50:55,267 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2021-11-09 09:50:55,267 INFO L87 Difference]: Start difference. First operand 63 states and 64 transitions. cyclomatic complexity: 3 Second operand has 32 states, 32 states have (on average 1.96875) internal successors, (63), 32 states have internal predecessors, (63), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:55,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:55,481 INFO L93 Difference]: Finished difference Result 153 states and 154 transitions. [2021-11-09 09:50:55,481 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2021-11-09 09:50:55,481 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 153 states and 154 transitions. [2021-11-09 09:50:55,486 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:55,487 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 153 states to 153 states and 154 transitions. [2021-11-09 09:50:55,487 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 94 [2021-11-09 09:50:55,488 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 94 [2021-11-09 09:50:55,488 INFO L73 IsDeterministic]: Start isDeterministic. Operand 153 states and 154 transitions. [2021-11-09 09:50:55,488 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:55,488 INFO L681 BuchiCegarLoop]: Abstraction has 153 states and 154 transitions. [2021-11-09 09:50:55,488 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153 states and 154 transitions. [2021-11-09 09:50:55,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153 to 65. [2021-11-09 09:50:55,490 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 65 states have (on average 1.0153846153846153) internal successors, (66), 64 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:55,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 66 transitions. [2021-11-09 09:50:55,491 INFO L704 BuchiCegarLoop]: Abstraction has 65 states and 66 transitions. [2021-11-09 09:50:55,491 INFO L587 BuchiCegarLoop]: Abstraction has 65 states and 66 transitions. [2021-11-09 09:50:55,491 INFO L425 BuchiCegarLoop]: ======== Iteration 31============ [2021-11-09 09:50:55,491 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65 states and 66 transitions. [2021-11-09 09:50:55,491 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:55,492 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:55,492 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:55,492 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [29, 29, 1, 1, 1, 1] [2021-11-09 09:50:55,492 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:55,493 INFO L791 eck$LassoCheckResult]: Stem: 6836#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 6837#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 6838#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6839#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6840#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6834#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6835#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6896#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6895#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6894#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6893#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6892#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6891#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6890#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6889#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6888#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6887#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6886#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6885#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6884#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6883#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6882#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6881#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6880#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6879#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6878#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6877#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6876#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6875#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6874#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6873#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6872#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6871#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6870#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6869#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6868#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6867#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6866#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6865#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6864#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6863#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6862#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6861#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6860#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6859#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6858#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6857#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6856#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6855#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6854#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6853#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6852#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6851#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6850#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6849#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6848#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6847#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6846#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6845#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 6844#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 6843#L25-3 assume !(main_~i~0 < 1023); 6841#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 6842#L30-4 [2021-11-09 09:50:55,509 INFO L793 eck$LassoCheckResult]: Loop: 6842#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 6832#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 6833#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 6842#L30-4 [2021-11-09 09:50:55,510 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:55,510 INFO L85 PathProgramCache]: Analyzing trace with hash -1143850683, now seen corresponding path program 29 times [2021-11-09 09:50:55,510 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:55,510 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [944589591] [2021-11-09 09:50:55,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:55,511 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:55,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:56,122 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 841 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:56,122 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:56,122 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [944589591] [2021-11-09 09:50:56,122 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [944589591] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:56,122 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [710838540] [2021-11-09 09:50:56,122 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:50:56,123 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:56,123 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:56,157 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:56,202 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2021-11-09 09:50:57,497 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 30 check-sat command(s) [2021-11-09 09:50:57,497 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:50:57,503 INFO L263 TraceCheckSpWp]: Trace formula consists of 275 conjuncts, 31 conjunts are in the unsatisfiable core [2021-11-09 09:50:57,504 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:50:57,712 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 841 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:57,713 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [710838540] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:57,713 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:50:57,713 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32] total 33 [2021-11-09 09:50:57,713 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [232358015] [2021-11-09 09:50:57,713 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:50:57,713 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:57,713 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 30 times [2021-11-09 09:50:57,714 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:57,714 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1957144234] [2021-11-09 09:50:57,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:57,714 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:57,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:57,728 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:50:57,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:50:57,731 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:50:57,757 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:50:57,757 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2021-11-09 09:50:57,758 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=528, Invalid=528, Unknown=0, NotChecked=0, Total=1056 [2021-11-09 09:50:57,758 INFO L87 Difference]: Start difference. First operand 65 states and 66 transitions. cyclomatic complexity: 3 Second operand has 33 states, 33 states have (on average 1.9696969696969697) internal successors, (65), 33 states have internal predecessors, (65), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:57,983 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:50:57,983 INFO L93 Difference]: Finished difference Result 158 states and 159 transitions. [2021-11-09 09:50:57,983 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2021-11-09 09:50:57,983 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 158 states and 159 transitions. [2021-11-09 09:50:57,984 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:57,989 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 158 states to 158 states and 159 transitions. [2021-11-09 09:50:57,990 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97 [2021-11-09 09:50:57,991 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97 [2021-11-09 09:50:57,991 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158 states and 159 transitions. [2021-11-09 09:50:57,991 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:50:57,992 INFO L681 BuchiCegarLoop]: Abstraction has 158 states and 159 transitions. [2021-11-09 09:50:57,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states and 159 transitions. [2021-11-09 09:50:57,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 67. [2021-11-09 09:50:57,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67 states, 67 states have (on average 1.0149253731343284) internal successors, (68), 66 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:50:57,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 68 transitions. [2021-11-09 09:50:57,995 INFO L704 BuchiCegarLoop]: Abstraction has 67 states and 68 transitions. [2021-11-09 09:50:57,995 INFO L587 BuchiCegarLoop]: Abstraction has 67 states and 68 transitions. [2021-11-09 09:50:57,995 INFO L425 BuchiCegarLoop]: ======== Iteration 32============ [2021-11-09 09:50:57,995 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67 states and 68 transitions. [2021-11-09 09:50:57,995 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:50:57,996 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:50:57,996 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:50:57,996 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [30, 30, 1, 1, 1, 1] [2021-11-09 09:50:57,996 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:50:57,997 INFO L791 eck$LassoCheckResult]: Stem: 7278#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 7279#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 7280#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7281#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7282#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7276#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7277#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7340#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7339#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7338#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7337#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7336#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7335#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7334#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7333#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7332#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7331#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7330#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7329#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7328#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7327#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7326#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7325#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7324#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7323#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7322#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7321#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7320#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7319#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7318#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7317#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7316#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7315#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7314#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7313#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7312#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7311#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7310#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7309#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7308#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7307#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7306#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7305#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7304#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7303#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7302#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7301#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7300#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7299#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7298#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7297#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7296#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7295#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7294#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7293#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7292#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7291#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7290#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7289#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7288#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7287#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7286#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7285#L25-3 assume !(main_~i~0 < 1023); 7283#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 7284#L30-4 [2021-11-09 09:50:57,997 INFO L793 eck$LassoCheckResult]: Loop: 7284#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 7274#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 7275#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 7284#L30-4 [2021-11-09 09:50:57,997 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:50:57,998 INFO L85 PathProgramCache]: Analyzing trace with hash 271177415, now seen corresponding path program 30 times [2021-11-09 09:50:57,998 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:50:57,998 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2086831573] [2021-11-09 09:50:57,998 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:50:57,998 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:50:58,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:50:58,613 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 0 proven. 900 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:50:58,613 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:50:58,613 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2086831573] [2021-11-09 09:50:58,613 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2086831573] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:50:58,613 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [109399616] [2021-11-09 09:50:58,613 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:50:58,613 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:50:58,614 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:50:58,616 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:50:58,632 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2021-11-09 09:51:09,120 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 31 check-sat command(s) [2021-11-09 09:51:09,120 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:51:09,139 INFO L263 TraceCheckSpWp]: Trace formula consists of 283 conjuncts, 32 conjunts are in the unsatisfiable core [2021-11-09 09:51:09,141 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:51:09,351 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 0 proven. 900 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:51:09,351 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [109399616] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:51:09,352 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:51:09,352 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33] total 34 [2021-11-09 09:51:09,353 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1096789600] [2021-11-09 09:51:09,355 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:51:09,355 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:51:09,356 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 31 times [2021-11-09 09:51:09,356 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:51:09,357 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [557301054] [2021-11-09 09:51:09,357 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:51:09,357 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:51:09,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:51:09,363 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:51:09,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:51:09,366 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:51:09,394 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:51:09,395 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2021-11-09 09:51:09,396 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2021-11-09 09:51:09,396 INFO L87 Difference]: Start difference. First operand 67 states and 68 transitions. cyclomatic complexity: 3 Second operand has 34 states, 34 states have (on average 1.9705882352941178) internal successors, (67), 34 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:51:09,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:51:09,674 INFO L93 Difference]: Finished difference Result 163 states and 164 transitions. [2021-11-09 09:51:09,680 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2021-11-09 09:51:09,681 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 163 states and 164 transitions. [2021-11-09 09:51:09,686 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:51:09,688 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 163 states to 163 states and 164 transitions. [2021-11-09 09:51:09,688 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 100 [2021-11-09 09:51:09,688 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 100 [2021-11-09 09:51:09,689 INFO L73 IsDeterministic]: Start isDeterministic. Operand 163 states and 164 transitions. [2021-11-09 09:51:09,689 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:51:09,689 INFO L681 BuchiCegarLoop]: Abstraction has 163 states and 164 transitions. [2021-11-09 09:51:09,689 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states and 164 transitions. [2021-11-09 09:51:09,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 69. [2021-11-09 09:51:09,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69 states, 69 states have (on average 1.0144927536231885) internal successors, (70), 68 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:51:09,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 70 transitions. [2021-11-09 09:51:09,692 INFO L704 BuchiCegarLoop]: Abstraction has 69 states and 70 transitions. [2021-11-09 09:51:09,693 INFO L587 BuchiCegarLoop]: Abstraction has 69 states and 70 transitions. [2021-11-09 09:51:09,693 INFO L425 BuchiCegarLoop]: ======== Iteration 33============ [2021-11-09 09:51:09,693 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 69 states and 70 transitions. [2021-11-09 09:51:09,694 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:51:09,694 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:51:09,694 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:51:09,695 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [31, 31, 1, 1, 1, 1] [2021-11-09 09:51:09,695 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:51:09,695 INFO L791 eck$LassoCheckResult]: Stem: 7734#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 7735#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 7736#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7737#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7738#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7732#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7733#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7798#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7797#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7796#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7795#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7794#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7793#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7792#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7791#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7790#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7789#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7788#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7787#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7786#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7785#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7784#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7783#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7782#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7781#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7780#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7779#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7778#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7777#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7776#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7775#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7774#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7773#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7772#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7771#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7770#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7769#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7768#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7767#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7766#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7765#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7764#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7763#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7762#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7761#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7760#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7759#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7758#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7757#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7756#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7755#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7754#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7753#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7752#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7751#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7750#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7749#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7748#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7747#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7746#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7745#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7744#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7743#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 7742#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 7741#L25-3 assume !(main_~i~0 < 1023); 7739#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 7740#L30-4 [2021-11-09 09:51:09,696 INFO L793 eck$LassoCheckResult]: Loop: 7740#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 7730#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 7731#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 7740#L30-4 [2021-11-09 09:51:09,700 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:51:09,700 INFO L85 PathProgramCache]: Analyzing trace with hash -1391453239, now seen corresponding path program 31 times [2021-11-09 09:51:09,701 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:51:09,701 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [694506461] [2021-11-09 09:51:09,701 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:51:09,701 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:51:09,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:51:10,377 INFO L134 CoverageAnalysis]: Checked inductivity of 961 backedges. 0 proven. 961 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:51:10,377 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:51:10,377 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [694506461] [2021-11-09 09:51:10,377 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [694506461] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:51:10,378 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [507756160] [2021-11-09 09:51:10,378 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:51:10,378 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:51:10,378 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:51:10,382 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:51:10,397 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2021-11-09 09:51:10,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:51:10,871 INFO L263 TraceCheckSpWp]: Trace formula consists of 291 conjuncts, 33 conjunts are in the unsatisfiable core [2021-11-09 09:51:10,873 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:51:11,100 INFO L134 CoverageAnalysis]: Checked inductivity of 961 backedges. 0 proven. 961 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:51:11,100 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [507756160] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:51:11,100 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:51:11,101 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34] total 35 [2021-11-09 09:51:11,101 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [369132879] [2021-11-09 09:51:11,101 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:51:11,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:51:11,102 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 32 times [2021-11-09 09:51:11,102 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:51:11,102 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221001274] [2021-11-09 09:51:11,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:51:11,103 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:51:11,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:51:11,122 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:51:11,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:51:11,125 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:51:11,162 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:51:11,162 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2021-11-09 09:51:11,163 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=595, Invalid=595, Unknown=0, NotChecked=0, Total=1190 [2021-11-09 09:51:11,163 INFO L87 Difference]: Start difference. First operand 69 states and 70 transitions. cyclomatic complexity: 3 Second operand has 35 states, 35 states have (on average 1.9714285714285715) internal successors, (69), 35 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:51:11,417 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:51:11,417 INFO L93 Difference]: Finished difference Result 168 states and 169 transitions. [2021-11-09 09:51:11,417 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2021-11-09 09:51:11,418 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 168 states and 169 transitions. [2021-11-09 09:51:11,419 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:51:11,420 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 168 states to 168 states and 169 transitions. [2021-11-09 09:51:11,420 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 103 [2021-11-09 09:51:11,421 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 103 [2021-11-09 09:51:11,421 INFO L73 IsDeterministic]: Start isDeterministic. Operand 168 states and 169 transitions. [2021-11-09 09:51:11,421 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:51:11,421 INFO L681 BuchiCegarLoop]: Abstraction has 168 states and 169 transitions. [2021-11-09 09:51:11,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 168 states and 169 transitions. [2021-11-09 09:51:11,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 168 to 71. [2021-11-09 09:51:11,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 71 states, 71 states have (on average 1.0140845070422535) internal successors, (72), 70 states have internal predecessors, (72), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:51:11,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71 states to 71 states and 72 transitions. [2021-11-09 09:51:11,423 INFO L704 BuchiCegarLoop]: Abstraction has 71 states and 72 transitions. [2021-11-09 09:51:11,423 INFO L587 BuchiCegarLoop]: Abstraction has 71 states and 72 transitions. [2021-11-09 09:51:11,424 INFO L425 BuchiCegarLoop]: ======== Iteration 34============ [2021-11-09 09:51:11,424 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71 states and 72 transitions. [2021-11-09 09:51:11,424 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:51:11,425 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:51:11,425 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:51:11,426 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [32, 32, 1, 1, 1, 1] [2021-11-09 09:51:11,426 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:51:11,426 INFO L791 eck$LassoCheckResult]: Stem: 8204#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 8205#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 8206#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8207#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8208#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8202#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8203#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8270#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8269#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8268#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8267#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8266#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8265#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8264#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8263#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8262#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8261#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8260#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8259#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8258#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8257#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8256#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8255#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8254#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8253#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8252#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8251#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8250#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8249#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8248#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8247#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8246#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8245#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8244#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8243#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8242#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8241#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8240#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8239#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8238#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8237#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8236#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8235#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8234#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8233#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8232#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8231#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8230#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8229#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8228#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8227#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8226#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8225#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8224#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8223#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8222#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8221#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8220#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8219#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8218#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8217#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8216#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8215#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8214#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8213#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8212#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8211#L25-3 assume !(main_~i~0 < 1023); 8209#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 8210#L30-4 [2021-11-09 09:51:11,426 INFO L793 eck$LassoCheckResult]: Loop: 8210#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 8200#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 8201#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 8210#L30-4 [2021-11-09 09:51:11,427 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:51:11,427 INFO L85 PathProgramCache]: Analyzing trace with hash -1451677621, now seen corresponding path program 32 times [2021-11-09 09:51:11,427 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:51:11,427 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2109951998] [2021-11-09 09:51:11,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:51:11,427 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:51:11,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:51:11,986 INFO L134 CoverageAnalysis]: Checked inductivity of 1024 backedges. 0 proven. 1024 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:51:11,986 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:51:11,987 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2109951998] [2021-11-09 09:51:11,987 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2109951998] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:51:11,987 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1996462978] [2021-11-09 09:51:11,987 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:51:11,987 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:51:11,987 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:51:11,988 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:51:11,989 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2021-11-09 09:51:12,412 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:51:12,412 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:51:12,414 INFO L263 TraceCheckSpWp]: Trace formula consists of 299 conjuncts, 34 conjunts are in the unsatisfiable core [2021-11-09 09:51:12,415 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:51:12,636 INFO L134 CoverageAnalysis]: Checked inductivity of 1024 backedges. 0 proven. 1024 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:51:12,636 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1996462978] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:51:12,636 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:51:12,636 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35] total 36 [2021-11-09 09:51:12,636 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1171570886] [2021-11-09 09:51:12,636 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:51:12,637 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:51:12,637 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 33 times [2021-11-09 09:51:12,637 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:51:12,637 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2091047920] [2021-11-09 09:51:12,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:51:12,638 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:51:12,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:51:12,653 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:51:12,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:51:12,656 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:51:12,697 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:51:12,698 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2021-11-09 09:51:12,699 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2021-11-09 09:51:12,699 INFO L87 Difference]: Start difference. First operand 71 states and 72 transitions. cyclomatic complexity: 3 Second operand has 36 states, 36 states have (on average 1.9722222222222223) internal successors, (71), 36 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:51:12,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:51:12,910 INFO L93 Difference]: Finished difference Result 173 states and 174 transitions. [2021-11-09 09:51:12,911 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2021-11-09 09:51:12,912 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 173 states and 174 transitions. [2021-11-09 09:51:12,913 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:51:12,915 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 173 states to 173 states and 174 transitions. [2021-11-09 09:51:12,915 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 106 [2021-11-09 09:51:12,915 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 106 [2021-11-09 09:51:12,915 INFO L73 IsDeterministic]: Start isDeterministic. Operand 173 states and 174 transitions. [2021-11-09 09:51:12,934 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:51:12,934 INFO L681 BuchiCegarLoop]: Abstraction has 173 states and 174 transitions. [2021-11-09 09:51:12,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 173 states and 174 transitions. [2021-11-09 09:51:12,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 173 to 73. [2021-11-09 09:51:12,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73 states, 73 states have (on average 1.0136986301369864) internal successors, (74), 72 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:51:12,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 74 transitions. [2021-11-09 09:51:12,938 INFO L704 BuchiCegarLoop]: Abstraction has 73 states and 74 transitions. [2021-11-09 09:51:12,939 INFO L587 BuchiCegarLoop]: Abstraction has 73 states and 74 transitions. [2021-11-09 09:51:12,939 INFO L425 BuchiCegarLoop]: ======== Iteration 35============ [2021-11-09 09:51:12,939 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73 states and 74 transitions. [2021-11-09 09:51:12,939 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:51:12,940 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:51:12,940 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:51:12,941 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [33, 33, 1, 1, 1, 1] [2021-11-09 09:51:12,941 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:51:12,941 INFO L791 eck$LassoCheckResult]: Stem: 8688#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 8689#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 8690#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8691#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8692#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8686#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8687#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8756#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8755#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8754#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8753#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8752#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8751#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8750#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8749#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8748#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8747#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8746#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8745#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8744#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8743#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8742#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8741#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8740#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8739#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8738#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8737#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8736#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8735#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8734#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8733#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8732#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8731#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8730#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8729#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8728#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8727#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8726#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8725#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8724#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8723#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8722#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8721#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8720#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8719#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8718#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8717#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8716#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8715#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8714#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8713#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8712#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8711#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8710#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8709#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8708#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8707#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8706#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8705#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8704#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8703#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8702#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8701#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8700#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8699#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8698#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8697#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 8696#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 8695#L25-3 assume !(main_~i~0 < 1023); 8693#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 8694#L30-4 [2021-11-09 09:51:12,941 INFO L793 eck$LassoCheckResult]: Loop: 8694#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 8684#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 8685#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 8694#L30-4 [2021-11-09 09:51:12,942 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:51:12,942 INFO L85 PathProgramCache]: Analyzing trace with hash 802233421, now seen corresponding path program 33 times [2021-11-09 09:51:12,942 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:51:12,942 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1013914030] [2021-11-09 09:51:12,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:51:12,942 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:51:12,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:51:13,576 INFO L134 CoverageAnalysis]: Checked inductivity of 1089 backedges. 0 proven. 1089 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:51:13,576 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:51:13,576 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1013914030] [2021-11-09 09:51:13,576 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1013914030] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:51:13,577 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2027268137] [2021-11-09 09:51:13,577 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:51:13,577 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:51:13,577 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:51:13,579 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:51:13,593 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2021-11-09 09:51:34,062 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 34 check-sat command(s) [2021-11-09 09:51:34,062 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:51:34,094 INFO L263 TraceCheckSpWp]: Trace formula consists of 307 conjuncts, 35 conjunts are in the unsatisfiable core [2021-11-09 09:51:34,095 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:51:34,320 INFO L134 CoverageAnalysis]: Checked inductivity of 1089 backedges. 0 proven. 1089 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:51:34,320 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2027268137] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:51:34,320 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:51:34,320 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36] total 37 [2021-11-09 09:51:34,320 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1912259970] [2021-11-09 09:51:34,321 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:51:34,321 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:51:34,321 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 34 times [2021-11-09 09:51:34,322 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:51:34,322 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [957766027] [2021-11-09 09:51:34,322 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:51:34,322 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:51:34,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:51:34,331 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:51:34,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:51:34,339 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:51:34,378 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:51:34,378 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2021-11-09 09:51:34,379 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=666, Invalid=666, Unknown=0, NotChecked=0, Total=1332 [2021-11-09 09:51:34,379 INFO L87 Difference]: Start difference. First operand 73 states and 74 transitions. cyclomatic complexity: 3 Second operand has 37 states, 37 states have (on average 1.972972972972973) internal successors, (73), 37 states have internal predecessors, (73), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:51:34,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:51:34,850 INFO L93 Difference]: Finished difference Result 178 states and 179 transitions. [2021-11-09 09:51:34,851 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2021-11-09 09:51:34,851 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 178 states and 179 transitions. [2021-11-09 09:51:34,852 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:51:34,854 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 178 states to 178 states and 179 transitions. [2021-11-09 09:51:34,854 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 109 [2021-11-09 09:51:34,854 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 109 [2021-11-09 09:51:34,854 INFO L73 IsDeterministic]: Start isDeterministic. Operand 178 states and 179 transitions. [2021-11-09 09:51:34,854 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:51:34,855 INFO L681 BuchiCegarLoop]: Abstraction has 178 states and 179 transitions. [2021-11-09 09:51:34,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states and 179 transitions. [2021-11-09 09:51:34,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 75. [2021-11-09 09:51:34,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75 states, 75 states have (on average 1.0133333333333334) internal successors, (76), 74 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:51:34,857 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 76 transitions. [2021-11-09 09:51:34,857 INFO L704 BuchiCegarLoop]: Abstraction has 75 states and 76 transitions. [2021-11-09 09:51:34,857 INFO L587 BuchiCegarLoop]: Abstraction has 75 states and 76 transitions. [2021-11-09 09:51:34,857 INFO L425 BuchiCegarLoop]: ======== Iteration 36============ [2021-11-09 09:51:34,858 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75 states and 76 transitions. [2021-11-09 09:51:34,859 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:51:34,859 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:51:34,859 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:51:34,860 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [34, 34, 1, 1, 1, 1] [2021-11-09 09:51:34,860 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:51:34,860 INFO L791 eck$LassoCheckResult]: Stem: 9186#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 9187#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 9188#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9189#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9190#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9184#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9185#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9256#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9255#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9254#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9253#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9252#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9251#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9250#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9249#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9248#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9247#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9246#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9245#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9244#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9243#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9242#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9241#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9240#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9239#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9238#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9237#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9236#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9235#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9234#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9233#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9232#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9231#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9230#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9229#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9228#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9227#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9226#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9225#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9224#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9223#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9222#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9221#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9220#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9219#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9218#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9217#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9216#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9215#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9214#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9213#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9212#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9211#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9210#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9209#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9208#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9207#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9206#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9205#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9204#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9203#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9202#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9201#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9200#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9199#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9198#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9197#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9196#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9195#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9194#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9193#L25-3 assume !(main_~i~0 < 1023); 9191#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 9192#L30-4 [2021-11-09 09:51:34,860 INFO L793 eck$LassoCheckResult]: Loop: 9192#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 9182#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 9183#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 9192#L30-4 [2021-11-09 09:51:34,861 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:51:34,861 INFO L85 PathProgramCache]: Analyzing trace with hash 2147227599, now seen corresponding path program 34 times [2021-11-09 09:51:34,861 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:51:34,861 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2020540018] [2021-11-09 09:51:34,861 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:51:34,861 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:51:34,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:51:35,556 INFO L134 CoverageAnalysis]: Checked inductivity of 1156 backedges. 0 proven. 1156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:51:35,556 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:51:35,556 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2020540018] [2021-11-09 09:51:35,556 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2020540018] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:51:35,556 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [644840653] [2021-11-09 09:51:35,556 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:51:35,556 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:51:35,557 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:51:35,563 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:51:35,567 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2021-11-09 09:51:36,180 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:51:36,180 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:51:36,183 INFO L263 TraceCheckSpWp]: Trace formula consists of 315 conjuncts, 36 conjunts are in the unsatisfiable core [2021-11-09 09:51:36,185 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:51:36,449 INFO L134 CoverageAnalysis]: Checked inductivity of 1156 backedges. 0 proven. 1156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:51:36,450 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [644840653] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:51:36,450 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:51:36,450 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37] total 38 [2021-11-09 09:51:36,450 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1473454391] [2021-11-09 09:51:36,450 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:51:36,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:51:36,451 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 35 times [2021-11-09 09:51:36,451 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:51:36,451 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [9424906] [2021-11-09 09:51:36,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:51:36,452 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:51:36,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:51:36,509 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:51:36,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:51:36,511 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:51:36,549 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:51:36,550 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2021-11-09 09:51:36,551 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2021-11-09 09:51:36,551 INFO L87 Difference]: Start difference. First operand 75 states and 76 transitions. cyclomatic complexity: 3 Second operand has 38 states, 38 states have (on average 1.9736842105263157) internal successors, (75), 38 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:51:36,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:51:36,876 INFO L93 Difference]: Finished difference Result 183 states and 184 transitions. [2021-11-09 09:51:36,876 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2021-11-09 09:51:36,876 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 183 states and 184 transitions. [2021-11-09 09:51:36,886 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:51:36,887 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 183 states to 183 states and 184 transitions. [2021-11-09 09:51:36,887 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 112 [2021-11-09 09:51:36,887 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 112 [2021-11-09 09:51:36,888 INFO L73 IsDeterministic]: Start isDeterministic. Operand 183 states and 184 transitions. [2021-11-09 09:51:36,888 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:51:36,888 INFO L681 BuchiCegarLoop]: Abstraction has 183 states and 184 transitions. [2021-11-09 09:51:36,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 183 states and 184 transitions. [2021-11-09 09:51:36,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 183 to 77. [2021-11-09 09:51:36,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77 states, 77 states have (on average 1.0129870129870129) internal successors, (78), 76 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:51:36,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 78 transitions. [2021-11-09 09:51:36,891 INFO L704 BuchiCegarLoop]: Abstraction has 77 states and 78 transitions. [2021-11-09 09:51:36,891 INFO L587 BuchiCegarLoop]: Abstraction has 77 states and 78 transitions. [2021-11-09 09:51:36,891 INFO L425 BuchiCegarLoop]: ======== Iteration 37============ [2021-11-09 09:51:36,891 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77 states and 78 transitions. [2021-11-09 09:51:36,892 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:51:36,892 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:51:36,892 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:51:36,893 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [35, 35, 1, 1, 1, 1] [2021-11-09 09:51:36,893 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:51:36,893 INFO L791 eck$LassoCheckResult]: Stem: 9698#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 9699#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 9700#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9701#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9702#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9696#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9697#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9770#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9769#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9768#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9767#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9766#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9765#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9764#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9763#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9762#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9761#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9760#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9759#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9758#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9757#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9756#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9755#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9754#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9753#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9752#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9751#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9750#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9749#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9748#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9747#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9746#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9745#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9744#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9743#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9742#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9741#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9740#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9739#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9738#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9737#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9736#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9735#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9734#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9733#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9732#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9731#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9730#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9729#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9728#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9727#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9726#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9725#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9724#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9723#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9722#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9721#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9720#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9719#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9718#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9717#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9716#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9715#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9714#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9713#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9712#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9711#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9710#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9709#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9708#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9707#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 9706#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 9705#L25-3 assume !(main_~i~0 < 1023); 9703#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 9704#L30-4 [2021-11-09 09:51:36,893 INFO L793 eck$LassoCheckResult]: Loop: 9704#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 9694#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 9695#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 9704#L30-4 [2021-11-09 09:51:36,894 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:51:36,894 INFO L85 PathProgramCache]: Analyzing trace with hash 1901476561, now seen corresponding path program 35 times [2021-11-09 09:51:36,894 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:51:36,894 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [375250921] [2021-11-09 09:51:36,895 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:51:36,895 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:51:36,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:51:37,752 INFO L134 CoverageAnalysis]: Checked inductivity of 1225 backedges. 0 proven. 1225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:51:37,752 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:51:37,753 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [375250921] [2021-11-09 09:51:37,753 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [375250921] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:51:37,753 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [626120919] [2021-11-09 09:51:37,753 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:51:37,753 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:51:37,753 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:51:37,759 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:51:37,773 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (47)] Waiting until timeout for monitored process [2021-11-09 09:51:39,564 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 36 check-sat command(s) [2021-11-09 09:51:39,564 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:51:39,570 INFO L263 TraceCheckSpWp]: Trace formula consists of 323 conjuncts, 37 conjunts are in the unsatisfiable core [2021-11-09 09:51:39,572 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:51:39,814 INFO L134 CoverageAnalysis]: Checked inductivity of 1225 backedges. 0 proven. 1225 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:51:39,815 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [626120919] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:51:39,815 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:51:39,815 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38] total 39 [2021-11-09 09:51:39,815 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2077770933] [2021-11-09 09:51:39,816 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:51:39,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:51:39,816 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 36 times [2021-11-09 09:51:39,816 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:51:39,816 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [990106042] [2021-11-09 09:51:39,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:51:39,817 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:51:39,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:51:39,823 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:51:39,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:51:39,825 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:51:39,854 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:51:39,854 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2021-11-09 09:51:39,855 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=741, Invalid=741, Unknown=0, NotChecked=0, Total=1482 [2021-11-09 09:51:39,855 INFO L87 Difference]: Start difference. First operand 77 states and 78 transitions. cyclomatic complexity: 3 Second operand has 39 states, 39 states have (on average 1.9743589743589745) internal successors, (77), 39 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:51:40,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:51:40,137 INFO L93 Difference]: Finished difference Result 188 states and 189 transitions. [2021-11-09 09:51:40,137 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2021-11-09 09:51:40,138 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 188 states and 189 transitions. [2021-11-09 09:51:40,139 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:51:40,141 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 188 states to 188 states and 189 transitions. [2021-11-09 09:51:40,142 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 115 [2021-11-09 09:51:40,142 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 115 [2021-11-09 09:51:40,142 INFO L73 IsDeterministic]: Start isDeterministic. Operand 188 states and 189 transitions. [2021-11-09 09:51:40,143 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:51:40,143 INFO L681 BuchiCegarLoop]: Abstraction has 188 states and 189 transitions. [2021-11-09 09:51:40,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states and 189 transitions. [2021-11-09 09:51:40,147 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 79. [2021-11-09 09:51:40,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 79 states, 79 states have (on average 1.0126582278481013) internal successors, (80), 78 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:51:40,148 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 80 transitions. [2021-11-09 09:51:40,148 INFO L704 BuchiCegarLoop]: Abstraction has 79 states and 80 transitions. [2021-11-09 09:51:40,149 INFO L587 BuchiCegarLoop]: Abstraction has 79 states and 80 transitions. [2021-11-09 09:51:40,149 INFO L425 BuchiCegarLoop]: ======== Iteration 38============ [2021-11-09 09:51:40,149 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 79 states and 80 transitions. [2021-11-09 09:51:40,149 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:51:40,150 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:51:40,150 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:51:40,151 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [36, 36, 1, 1, 1, 1] [2021-11-09 09:51:40,151 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:51:40,151 INFO L791 eck$LassoCheckResult]: Stem: 10224#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 10225#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 10226#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10227#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10228#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10222#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10223#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10298#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10297#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10296#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10295#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10294#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10293#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10292#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10291#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10290#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10289#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10288#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10287#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10286#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10285#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10284#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10283#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10282#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10281#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10280#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10279#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10278#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10277#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10276#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10275#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10274#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10273#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10272#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10271#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10270#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10269#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10268#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10267#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10266#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10265#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10264#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10263#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10262#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10261#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10260#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10259#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10258#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10257#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10256#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10255#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10254#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10253#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10252#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10251#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10250#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10249#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10248#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10247#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10246#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10245#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10244#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10243#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10242#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10241#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10240#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10239#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10238#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10237#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10236#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10235#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10234#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10233#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10232#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10231#L25-3 assume !(main_~i~0 < 1023); 10229#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 10230#L30-4 [2021-11-09 09:51:40,151 INFO L793 eck$LassoCheckResult]: Loop: 10230#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 10220#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 10221#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 10230#L30-4 [2021-11-09 09:51:40,152 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:51:40,152 INFO L85 PathProgramCache]: Analyzing trace with hash 1957930323, now seen corresponding path program 36 times [2021-11-09 09:51:40,152 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:51:40,152 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1927785707] [2021-11-09 09:51:40,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:51:40,152 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:51:40,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:51:41,025 INFO L134 CoverageAnalysis]: Checked inductivity of 1296 backedges. 0 proven. 1296 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:51:41,026 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:51:41,026 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1927785707] [2021-11-09 09:51:41,026 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1927785707] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:51:41,026 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [241614175] [2021-11-09 09:51:41,026 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:51:41,026 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:51:41,027 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:51:41,057 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:51:41,114 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (48)] Waiting until timeout for monitored process [2021-11-09 09:52:30,247 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 37 check-sat command(s) [2021-11-09 09:52:30,248 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:52:30,300 INFO L263 TraceCheckSpWp]: Trace formula consists of 331 conjuncts, 38 conjunts are in the unsatisfiable core [2021-11-09 09:52:30,301 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:52:30,543 INFO L134 CoverageAnalysis]: Checked inductivity of 1296 backedges. 0 proven. 1296 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:52:30,543 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [241614175] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:52:30,543 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:52:30,543 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39] total 40 [2021-11-09 09:52:30,543 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [100540051] [2021-11-09 09:52:30,543 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:52:30,544 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:52:30,544 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 37 times [2021-11-09 09:52:30,544 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:52:30,544 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1659810500] [2021-11-09 09:52:30,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:52:30,545 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:52:30,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:52:30,553 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:52:30,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:52:30,556 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:52:30,593 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:52:30,594 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2021-11-09 09:52:30,594 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2021-11-09 09:52:30,595 INFO L87 Difference]: Start difference. First operand 79 states and 80 transitions. cyclomatic complexity: 3 Second operand has 40 states, 40 states have (on average 1.975) internal successors, (79), 40 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:52:30,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:52:30,881 INFO L93 Difference]: Finished difference Result 193 states and 194 transitions. [2021-11-09 09:52:30,881 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2021-11-09 09:52:30,881 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 193 states and 194 transitions. [2021-11-09 09:52:30,882 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:52:30,883 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 193 states to 193 states and 194 transitions. [2021-11-09 09:52:30,883 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 118 [2021-11-09 09:52:30,883 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 118 [2021-11-09 09:52:30,883 INFO L73 IsDeterministic]: Start isDeterministic. Operand 193 states and 194 transitions. [2021-11-09 09:52:30,883 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:52:30,884 INFO L681 BuchiCegarLoop]: Abstraction has 193 states and 194 transitions. [2021-11-09 09:52:30,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193 states and 194 transitions. [2021-11-09 09:52:30,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193 to 81. [2021-11-09 09:52:30,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81 states, 81 states have (on average 1.0123456790123457) internal successors, (82), 80 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:52:30,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 82 transitions. [2021-11-09 09:52:30,886 INFO L704 BuchiCegarLoop]: Abstraction has 81 states and 82 transitions. [2021-11-09 09:52:30,886 INFO L587 BuchiCegarLoop]: Abstraction has 81 states and 82 transitions. [2021-11-09 09:52:30,886 INFO L425 BuchiCegarLoop]: ======== Iteration 39============ [2021-11-09 09:52:30,886 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81 states and 82 transitions. [2021-11-09 09:52:30,886 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:52:30,886 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:52:30,886 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:52:30,887 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [37, 37, 1, 1, 1, 1] [2021-11-09 09:52:30,887 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:52:30,887 INFO L791 eck$LassoCheckResult]: Stem: 10764#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 10765#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 10766#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10767#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10768#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10762#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10763#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10840#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10839#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10838#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10837#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10836#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10835#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10834#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10833#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10832#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10831#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10830#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10829#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10828#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10827#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10826#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10825#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10824#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10823#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10822#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10821#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10820#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10819#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10818#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10817#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10816#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10815#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10814#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10813#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10812#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10811#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10810#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10809#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10808#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10807#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10806#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10805#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10804#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10803#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10802#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10801#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10800#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10799#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10798#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10797#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10796#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10795#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10794#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10793#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10792#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10791#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10790#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10789#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10788#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10787#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10786#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10785#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10784#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10783#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10782#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10781#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10780#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10779#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10778#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10777#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10776#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10775#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10774#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10773#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 10772#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 10771#L25-3 assume !(main_~i~0 < 1023); 10769#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 10770#L30-4 [2021-11-09 09:52:30,887 INFO L793 eck$LassoCheckResult]: Loop: 10770#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 10760#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 10761#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 10770#L30-4 [2021-11-09 09:52:30,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:52:30,887 INFO L85 PathProgramCache]: Analyzing trace with hash 375420757, now seen corresponding path program 37 times [2021-11-09 09:52:30,887 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:52:30,887 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [450011144] [2021-11-09 09:52:30,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:52:30,888 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:52:30,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:52:31,584 INFO L134 CoverageAnalysis]: Checked inductivity of 1369 backedges. 0 proven. 1369 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:52:31,585 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:52:31,585 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [450011144] [2021-11-09 09:52:31,585 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [450011144] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:52:31,585 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2087459729] [2021-11-09 09:52:31,585 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:52:31,585 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:52:31,585 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:52:31,591 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:52:31,606 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (49)] Waiting until timeout for monitored process [2021-11-09 09:52:32,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:52:32,229 INFO L263 TraceCheckSpWp]: Trace formula consists of 339 conjuncts, 39 conjunts are in the unsatisfiable core [2021-11-09 09:52:32,231 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:52:32,535 INFO L134 CoverageAnalysis]: Checked inductivity of 1369 backedges. 0 proven. 1369 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:52:32,535 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2087459729] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:52:32,536 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:52:32,536 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40] total 41 [2021-11-09 09:52:32,536 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1647345190] [2021-11-09 09:52:32,536 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:52:32,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:52:32,536 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 38 times [2021-11-09 09:52:32,536 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:52:32,536 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [213745402] [2021-11-09 09:52:32,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:52:32,537 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:52:32,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:52:32,542 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:52:32,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:52:32,544 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:52:32,574 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:52:32,575 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2021-11-09 09:52:32,575 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=820, Invalid=820, Unknown=0, NotChecked=0, Total=1640 [2021-11-09 09:52:32,575 INFO L87 Difference]: Start difference. First operand 81 states and 82 transitions. cyclomatic complexity: 3 Second operand has 41 states, 41 states have (on average 1.975609756097561) internal successors, (81), 41 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:52:32,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:52:32,834 INFO L93 Difference]: Finished difference Result 198 states and 199 transitions. [2021-11-09 09:52:32,834 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2021-11-09 09:52:32,834 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 198 states and 199 transitions. [2021-11-09 09:52:32,835 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:52:32,836 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 198 states to 198 states and 199 transitions. [2021-11-09 09:52:32,836 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 121 [2021-11-09 09:52:32,836 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 121 [2021-11-09 09:52:32,836 INFO L73 IsDeterministic]: Start isDeterministic. Operand 198 states and 199 transitions. [2021-11-09 09:52:32,836 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:52:32,836 INFO L681 BuchiCegarLoop]: Abstraction has 198 states and 199 transitions. [2021-11-09 09:52:32,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states and 199 transitions. [2021-11-09 09:52:32,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 83. [2021-11-09 09:52:32,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83 states, 83 states have (on average 1.0120481927710843) internal successors, (84), 82 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:52:32,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 84 transitions. [2021-11-09 09:52:32,838 INFO L704 BuchiCegarLoop]: Abstraction has 83 states and 84 transitions. [2021-11-09 09:52:32,838 INFO L587 BuchiCegarLoop]: Abstraction has 83 states and 84 transitions. [2021-11-09 09:52:32,838 INFO L425 BuchiCegarLoop]: ======== Iteration 40============ [2021-11-09 09:52:32,839 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83 states and 84 transitions. [2021-11-09 09:52:32,839 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:52:32,839 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:52:32,839 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:52:32,840 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [38, 38, 1, 1, 1, 1] [2021-11-09 09:52:32,840 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:52:32,840 INFO L791 eck$LassoCheckResult]: Stem: 11318#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 11319#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 11320#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11321#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11322#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11316#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11317#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11396#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11395#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11394#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11393#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11392#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11391#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11390#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11389#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11388#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11387#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11386#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11385#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11384#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11383#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11382#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11381#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11380#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11379#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11378#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11377#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11376#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11375#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11374#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11373#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11372#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11371#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11370#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11369#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11368#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11367#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11366#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11365#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11364#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11363#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11362#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11361#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11360#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11359#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11358#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11357#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11356#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11355#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11354#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11353#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11352#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11351#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11350#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11349#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11348#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11347#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11346#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11345#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11344#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11343#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11342#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11341#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11340#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11339#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11338#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11337#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11336#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11335#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11334#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11333#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11332#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11331#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11330#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11329#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11328#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11327#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11326#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11325#L25-3 assume !(main_~i~0 < 1023); 11323#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 11324#L30-4 [2021-11-09 09:52:32,840 INFO L793 eck$LassoCheckResult]: Loop: 11324#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 11314#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 11315#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 11324#L30-4 [2021-11-09 09:52:32,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:52:32,841 INFO L85 PathProgramCache]: Analyzing trace with hash 2150615, now seen corresponding path program 38 times [2021-11-09 09:52:32,841 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:52:32,841 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [221891396] [2021-11-09 09:52:32,862 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:52:32,862 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:52:32,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:52:33,473 INFO L134 CoverageAnalysis]: Checked inductivity of 1444 backedges. 0 proven. 1444 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:52:33,474 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:52:33,474 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [221891396] [2021-11-09 09:52:33,474 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [221891396] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:52:33,474 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1957593054] [2021-11-09 09:52:33,474 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:52:33,474 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:52:33,475 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:52:33,476 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:52:33,477 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (50)] Waiting until timeout for monitored process [2021-11-09 09:52:34,032 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:52:34,032 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:52:34,034 INFO L263 TraceCheckSpWp]: Trace formula consists of 347 conjuncts, 40 conjunts are in the unsatisfiable core [2021-11-09 09:52:34,035 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:52:34,259 INFO L134 CoverageAnalysis]: Checked inductivity of 1444 backedges. 0 proven. 1444 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:52:34,260 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1957593054] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:52:34,260 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:52:34,260 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41] total 42 [2021-11-09 09:52:34,260 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1431599274] [2021-11-09 09:52:34,260 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:52:34,261 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:52:34,261 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 39 times [2021-11-09 09:52:34,261 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:52:34,261 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [120447937] [2021-11-09 09:52:34,261 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:52:34,261 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:52:34,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:52:34,268 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:52:34,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:52:34,271 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:52:34,302 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:52:34,303 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2021-11-09 09:52:34,304 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2021-11-09 09:52:34,304 INFO L87 Difference]: Start difference. First operand 83 states and 84 transitions. cyclomatic complexity: 3 Second operand has 42 states, 42 states have (on average 1.9761904761904763) internal successors, (83), 42 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:52:34,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:52:34,618 INFO L93 Difference]: Finished difference Result 203 states and 204 transitions. [2021-11-09 09:52:34,618 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2021-11-09 09:52:34,618 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 203 states and 204 transitions. [2021-11-09 09:52:34,619 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:52:34,620 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 203 states to 203 states and 204 transitions. [2021-11-09 09:52:34,620 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 124 [2021-11-09 09:52:34,620 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 124 [2021-11-09 09:52:34,620 INFO L73 IsDeterministic]: Start isDeterministic. Operand 203 states and 204 transitions. [2021-11-09 09:52:34,621 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:52:34,621 INFO L681 BuchiCegarLoop]: Abstraction has 203 states and 204 transitions. [2021-11-09 09:52:34,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 203 states and 204 transitions. [2021-11-09 09:52:34,622 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 203 to 85. [2021-11-09 09:52:34,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 85 states, 85 states have (on average 1.011764705882353) internal successors, (86), 84 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:52:34,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 86 transitions. [2021-11-09 09:52:34,623 INFO L704 BuchiCegarLoop]: Abstraction has 85 states and 86 transitions. [2021-11-09 09:52:34,623 INFO L587 BuchiCegarLoop]: Abstraction has 85 states and 86 transitions. [2021-11-09 09:52:34,623 INFO L425 BuchiCegarLoop]: ======== Iteration 41============ [2021-11-09 09:52:34,623 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 85 states and 86 transitions. [2021-11-09 09:52:34,624 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:52:34,624 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:52:34,624 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:52:34,625 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [39, 39, 1, 1, 1, 1] [2021-11-09 09:52:34,625 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:52:34,625 INFO L791 eck$LassoCheckResult]: Stem: 11886#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 11887#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 11888#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11889#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11890#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11884#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11885#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11966#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11965#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11964#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11963#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11962#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11961#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11960#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11959#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11958#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11957#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11956#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11955#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11954#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11953#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11952#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11951#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11950#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11949#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11948#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11947#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11946#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11945#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11944#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11943#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11942#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11941#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11940#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11939#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11938#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11937#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11936#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11935#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11934#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11933#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11932#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11931#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11930#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11929#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11928#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11927#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11926#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11925#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11924#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11923#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11922#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11921#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11920#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11919#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11918#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11917#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11916#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11915#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11914#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11913#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11912#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11911#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11910#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11909#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11908#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11907#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11906#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11905#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11904#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11903#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11902#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11901#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11900#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11899#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11898#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11897#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11896#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11895#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 11894#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 11893#L25-3 assume !(main_~i~0 < 1023); 11891#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 11892#L30-4 [2021-11-09 09:52:34,625 INFO L793 eck$LassoCheckResult]: Loop: 11892#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 11882#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 11883#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 11892#L30-4 [2021-11-09 09:52:34,625 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:52:34,625 INFO L85 PathProgramCache]: Analyzing trace with hash 2066797017, now seen corresponding path program 39 times [2021-11-09 09:52:34,626 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:52:34,626 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [416873034] [2021-11-09 09:52:34,626 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:52:34,626 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:52:34,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:52:35,349 INFO L134 CoverageAnalysis]: Checked inductivity of 1521 backedges. 0 proven. 1521 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:52:35,349 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:52:35,349 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [416873034] [2021-11-09 09:52:35,349 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [416873034] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:52:35,350 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [498811288] [2021-11-09 09:52:35,350 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:52:35,350 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:52:35,350 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:52:35,357 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:52:35,376 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (51)] Waiting until timeout for monitored process [2021-11-09 09:54:10,518 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 40 check-sat command(s) [2021-11-09 09:54:10,518 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:54:10,621 INFO L263 TraceCheckSpWp]: Trace formula consists of 355 conjuncts, 41 conjunts are in the unsatisfiable core [2021-11-09 09:54:10,623 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:54:10,852 INFO L134 CoverageAnalysis]: Checked inductivity of 1521 backedges. 0 proven. 1521 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:54:10,852 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [498811288] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:54:10,852 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:54:10,852 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42] total 43 [2021-11-09 09:54:10,853 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [498491947] [2021-11-09 09:54:10,853 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:54:10,853 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:54:10,853 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 40 times [2021-11-09 09:54:10,853 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:54:10,853 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1743248870] [2021-11-09 09:54:10,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:54:10,853 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:54:10,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:54:10,878 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:54:10,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:54:10,879 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:54:10,906 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:54:10,906 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2021-11-09 09:54:10,907 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=903, Invalid=903, Unknown=0, NotChecked=0, Total=1806 [2021-11-09 09:54:10,907 INFO L87 Difference]: Start difference. First operand 85 states and 86 transitions. cyclomatic complexity: 3 Second operand has 43 states, 43 states have (on average 1.9767441860465116) internal successors, (85), 43 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:54:11,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:54:11,210 INFO L93 Difference]: Finished difference Result 208 states and 209 transitions. [2021-11-09 09:54:11,211 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2021-11-09 09:54:11,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 208 states and 209 transitions. [2021-11-09 09:54:11,212 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:54:11,213 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 208 states to 208 states and 209 transitions. [2021-11-09 09:54:11,214 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 127 [2021-11-09 09:54:11,214 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 127 [2021-11-09 09:54:11,214 INFO L73 IsDeterministic]: Start isDeterministic. Operand 208 states and 209 transitions. [2021-11-09 09:54:11,214 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:54:11,214 INFO L681 BuchiCegarLoop]: Abstraction has 208 states and 209 transitions. [2021-11-09 09:54:11,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 208 states and 209 transitions. [2021-11-09 09:54:11,216 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 208 to 87. [2021-11-09 09:54:11,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87 states, 87 states have (on average 1.0114942528735633) internal successors, (88), 86 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:54:11,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 88 transitions. [2021-11-09 09:54:11,217 INFO L704 BuchiCegarLoop]: Abstraction has 87 states and 88 transitions. [2021-11-09 09:54:11,217 INFO L587 BuchiCegarLoop]: Abstraction has 87 states and 88 transitions. [2021-11-09 09:54:11,217 INFO L425 BuchiCegarLoop]: ======== Iteration 42============ [2021-11-09 09:54:11,217 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 87 states and 88 transitions. [2021-11-09 09:54:11,218 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:54:11,218 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:54:11,218 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:54:11,219 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [40, 40, 1, 1, 1, 1] [2021-11-09 09:54:11,219 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:54:11,219 INFO L791 eck$LassoCheckResult]: Stem: 12468#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 12469#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 12470#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12471#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12472#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12466#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12467#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12550#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12549#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12548#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12547#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12546#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12545#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12544#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12543#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12542#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12541#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12540#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12539#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12538#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12537#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12536#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12535#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12534#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12533#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12532#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12531#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12530#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12529#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12528#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12527#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12526#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12525#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12524#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12523#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12522#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12521#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12520#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12519#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12518#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12517#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12516#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12515#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12514#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12513#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12512#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12511#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12510#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12509#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12508#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12507#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12506#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12505#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12504#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12503#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12502#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12501#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12500#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12499#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12498#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12497#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12496#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12495#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12494#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12493#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12492#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12491#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12490#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12489#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12488#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12487#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12486#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12485#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12484#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12483#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12482#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12481#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12480#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12479#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12478#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12477#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 12476#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 12475#L25-3 assume !(main_~i~0 < 1023); 12473#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 12474#L30-4 [2021-11-09 09:54:11,219 INFO L793 eck$LassoCheckResult]: Loop: 12474#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 12464#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 12465#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 12474#L30-4 [2021-11-09 09:54:11,219 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:54:11,219 INFO L85 PathProgramCache]: Analyzing trace with hash 1917098587, now seen corresponding path program 40 times [2021-11-09 09:54:11,220 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:54:11,220 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [959241327] [2021-11-09 09:54:11,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:54:11,220 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:54:11,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:54:11,917 INFO L134 CoverageAnalysis]: Checked inductivity of 1600 backedges. 0 proven. 1600 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:54:11,917 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:54:11,917 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [959241327] [2021-11-09 09:54:11,917 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [959241327] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:54:11,917 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1381024479] [2021-11-09 09:54:11,917 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:54:11,917 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:54:11,917 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:54:11,919 INFO L229 MonitoredProcess]: Starting monitored process 52 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:54:11,919 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (52)] Waiting until timeout for monitored process [2021-11-09 09:54:12,536 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:54:12,536 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:54:12,539 INFO L263 TraceCheckSpWp]: Trace formula consists of 363 conjuncts, 42 conjunts are in the unsatisfiable core [2021-11-09 09:54:12,541 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:54:12,806 INFO L134 CoverageAnalysis]: Checked inductivity of 1600 backedges. 0 proven. 1600 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:54:12,806 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1381024479] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:54:12,806 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:54:12,807 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43] total 44 [2021-11-09 09:54:12,807 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [412972530] [2021-11-09 09:54:12,807 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:54:12,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:54:12,808 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 41 times [2021-11-09 09:54:12,808 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:54:12,808 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1835334750] [2021-11-09 09:54:12,808 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:54:12,808 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:54:12,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:54:12,841 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:54:12,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:54:12,844 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:54:12,887 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:54:12,888 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2021-11-09 09:54:12,889 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2021-11-09 09:54:12,889 INFO L87 Difference]: Start difference. First operand 87 states and 88 transitions. cyclomatic complexity: 3 Second operand has 44 states, 44 states have (on average 1.9772727272727273) internal successors, (87), 44 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:54:13,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:54:13,221 INFO L93 Difference]: Finished difference Result 213 states and 214 transitions. [2021-11-09 09:54:13,221 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2021-11-09 09:54:13,221 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 213 states and 214 transitions. [2021-11-09 09:54:13,222 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:54:13,223 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 213 states to 213 states and 214 transitions. [2021-11-09 09:54:13,223 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 130 [2021-11-09 09:54:13,223 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 130 [2021-11-09 09:54:13,224 INFO L73 IsDeterministic]: Start isDeterministic. Operand 213 states and 214 transitions. [2021-11-09 09:54:13,224 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:54:13,224 INFO L681 BuchiCegarLoop]: Abstraction has 213 states and 214 transitions. [2021-11-09 09:54:13,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 213 states and 214 transitions. [2021-11-09 09:54:13,225 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 213 to 89. [2021-11-09 09:54:13,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 89 states, 89 states have (on average 1.0112359550561798) internal successors, (90), 88 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:54:13,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 90 transitions. [2021-11-09 09:54:13,226 INFO L704 BuchiCegarLoop]: Abstraction has 89 states and 90 transitions. [2021-11-09 09:54:13,226 INFO L587 BuchiCegarLoop]: Abstraction has 89 states and 90 transitions. [2021-11-09 09:54:13,226 INFO L425 BuchiCegarLoop]: ======== Iteration 43============ [2021-11-09 09:54:13,226 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 89 states and 90 transitions. [2021-11-09 09:54:13,227 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:54:13,227 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:54:13,227 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:54:13,228 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [41, 41, 1, 1, 1, 1] [2021-11-09 09:54:13,228 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:54:13,228 INFO L791 eck$LassoCheckResult]: Stem: 13064#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 13065#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 13066#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13067#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13068#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13062#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13063#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13148#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13147#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13146#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13145#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13144#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13143#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13142#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13141#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13140#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13139#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13138#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13137#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13136#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13135#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13134#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13133#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13132#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13131#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13130#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13129#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13128#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13127#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13126#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13125#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13124#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13123#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13122#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13121#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13120#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13119#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13118#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13117#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13116#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13115#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13114#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13113#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13112#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13111#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13110#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13109#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13108#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13107#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13106#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13105#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13104#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13103#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13102#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13101#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13100#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13099#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13098#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13097#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13096#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13095#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13094#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13093#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13092#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13091#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13090#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13089#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13088#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13087#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13086#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13085#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13084#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13083#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13082#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13081#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13080#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13079#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13078#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13077#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13076#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13075#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13074#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13073#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13072#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13071#L25-3 assume !(main_~i~0 < 1023); 13069#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 13070#L30-4 [2021-11-09 09:54:13,229 INFO L793 eck$LassoCheckResult]: Loop: 13070#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 13060#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 13061#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 13070#L30-4 [2021-11-09 09:54:13,229 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:54:13,229 INFO L85 PathProgramCache]: Analyzing trace with hash -209171875, now seen corresponding path program 41 times [2021-11-09 09:54:13,229 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:54:13,229 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [224131008] [2021-11-09 09:54:13,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:54:13,230 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:54:13,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:54:14,083 INFO L134 CoverageAnalysis]: Checked inductivity of 1681 backedges. 0 proven. 1681 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:54:14,083 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:54:14,083 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [224131008] [2021-11-09 09:54:14,084 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [224131008] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:54:14,084 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [520045505] [2021-11-09 09:54:14,084 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:54:14,084 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:54:14,084 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:54:14,086 INFO L229 MonitoredProcess]: Starting monitored process 53 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:54:14,121 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (53)] Waiting until timeout for monitored process [2021-11-09 09:54:19,419 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 42 check-sat command(s) [2021-11-09 09:54:19,420 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:54:19,433 INFO L263 TraceCheckSpWp]: Trace formula consists of 371 conjuncts, 43 conjunts are in the unsatisfiable core [2021-11-09 09:54:19,434 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:54:19,692 INFO L134 CoverageAnalysis]: Checked inductivity of 1681 backedges. 0 proven. 1681 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:54:19,692 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [520045505] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:54:19,693 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:54:19,693 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44] total 45 [2021-11-09 09:54:19,693 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [91498228] [2021-11-09 09:54:19,693 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:54:19,693 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:54:19,693 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 42 times [2021-11-09 09:54:19,694 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:54:19,694 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [336599312] [2021-11-09 09:54:19,694 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:54:19,695 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:54:19,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:54:19,701 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:54:19,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:54:19,703 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:54:19,734 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:54:19,735 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2021-11-09 09:54:19,735 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=990, Invalid=990, Unknown=0, NotChecked=0, Total=1980 [2021-11-09 09:54:19,735 INFO L87 Difference]: Start difference. First operand 89 states and 90 transitions. cyclomatic complexity: 3 Second operand has 45 states, 45 states have (on average 1.9777777777777779) internal successors, (89), 45 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:54:20,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:54:20,082 INFO L93 Difference]: Finished difference Result 218 states and 219 transitions. [2021-11-09 09:54:20,082 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2021-11-09 09:54:20,082 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 218 states and 219 transitions. [2021-11-09 09:54:20,084 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:54:20,085 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 218 states to 218 states and 219 transitions. [2021-11-09 09:54:20,085 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 133 [2021-11-09 09:54:20,086 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 133 [2021-11-09 09:54:20,086 INFO L73 IsDeterministic]: Start isDeterministic. Operand 218 states and 219 transitions. [2021-11-09 09:54:20,086 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:54:20,086 INFO L681 BuchiCegarLoop]: Abstraction has 218 states and 219 transitions. [2021-11-09 09:54:20,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 218 states and 219 transitions. [2021-11-09 09:54:20,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 218 to 91. [2021-11-09 09:54:20,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 91 states, 91 states have (on average 1.010989010989011) internal successors, (92), 90 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:54:20,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 92 transitions. [2021-11-09 09:54:20,109 INFO L704 BuchiCegarLoop]: Abstraction has 91 states and 92 transitions. [2021-11-09 09:54:20,109 INFO L587 BuchiCegarLoop]: Abstraction has 91 states and 92 transitions. [2021-11-09 09:54:20,109 INFO L425 BuchiCegarLoop]: ======== Iteration 44============ [2021-11-09 09:54:20,110 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 91 states and 92 transitions. [2021-11-09 09:54:20,110 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:54:20,110 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:54:20,110 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:54:20,122 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [42, 42, 1, 1, 1, 1] [2021-11-09 09:54:20,122 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:54:20,122 INFO L791 eck$LassoCheckResult]: Stem: 13674#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 13675#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 13676#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13677#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13678#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13672#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13673#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13760#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13759#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13758#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13757#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13756#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13755#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13754#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13753#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13752#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13751#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13750#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13749#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13748#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13747#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13746#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13745#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13744#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13743#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13742#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13741#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13740#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13739#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13738#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13737#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13736#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13735#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13734#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13733#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13732#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13731#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13730#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13729#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13728#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13727#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13726#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13725#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13724#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13723#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13722#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13721#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13720#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13719#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13718#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13717#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13716#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13715#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13714#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13713#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13712#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13711#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13710#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13709#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13708#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13707#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13706#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13705#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13704#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13703#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13702#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13701#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13700#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13699#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13698#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13697#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13696#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13695#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13694#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13693#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13692#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13691#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13690#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13689#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13688#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13687#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13686#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13685#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13684#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13683#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 13682#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 13681#L25-3 assume !(main_~i~0 < 1023); 13679#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 13680#L30-4 [2021-11-09 09:54:20,123 INFO L793 eck$LassoCheckResult]: Loop: 13680#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 13670#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 13671#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 13680#L30-4 [2021-11-09 09:54:20,123 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:54:20,123 INFO L85 PathProgramCache]: Analyzing trace with hash 849347039, now seen corresponding path program 42 times [2021-11-09 09:54:20,123 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:54:20,123 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [949498253] [2021-11-09 09:54:20,124 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:54:20,124 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:54:20,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:54:21,081 INFO L134 CoverageAnalysis]: Checked inductivity of 1764 backedges. 0 proven. 1764 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:54:21,081 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:54:21,082 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [949498253] [2021-11-09 09:54:21,082 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [949498253] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:54:21,082 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [588573771] [2021-11-09 09:54:21,082 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:54:21,082 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:54:21,082 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:54:21,084 INFO L229 MonitoredProcess]: Starting monitored process 54 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:54:21,084 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (54)] Waiting until timeout for monitored process [2021-11-09 09:56:34,220 INFO L228 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 43 check-sat command(s) [2021-11-09 09:56:34,220 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:56:34,345 INFO L263 TraceCheckSpWp]: Trace formula consists of 379 conjuncts, 44 conjunts are in the unsatisfiable core [2021-11-09 09:56:34,346 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:56:34,606 INFO L134 CoverageAnalysis]: Checked inductivity of 1764 backedges. 0 proven. 1764 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:56:34,606 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [588573771] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:56:34,606 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:56:34,606 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45] total 46 [2021-11-09 09:56:34,606 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [896732617] [2021-11-09 09:56:34,607 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:56:34,607 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:56:34,607 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 43 times [2021-11-09 09:56:34,607 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:56:34,607 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [199274440] [2021-11-09 09:56:34,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:56:34,608 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:56:34,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:56:34,632 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:56:34,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:56:34,634 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:56:34,683 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:56:34,683 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2021-11-09 09:56:34,684 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2021-11-09 09:56:34,684 INFO L87 Difference]: Start difference. First operand 91 states and 92 transitions. cyclomatic complexity: 3 Second operand has 46 states, 46 states have (on average 1.9782608695652173) internal successors, (91), 46 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:56:35,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:56:35,080 INFO L93 Difference]: Finished difference Result 223 states and 224 transitions. [2021-11-09 09:56:35,081 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2021-11-09 09:56:35,081 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 223 states and 224 transitions. [2021-11-09 09:56:35,084 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:56:35,085 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 223 states to 223 states and 224 transitions. [2021-11-09 09:56:35,086 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 136 [2021-11-09 09:56:35,086 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 136 [2021-11-09 09:56:35,086 INFO L73 IsDeterministic]: Start isDeterministic. Operand 223 states and 224 transitions. [2021-11-09 09:56:35,086 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:56:35,086 INFO L681 BuchiCegarLoop]: Abstraction has 223 states and 224 transitions. [2021-11-09 09:56:35,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states and 224 transitions. [2021-11-09 09:56:35,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 93. [2021-11-09 09:56:35,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 93 states, 93 states have (on average 1.010752688172043) internal successors, (94), 92 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:56:35,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 94 transitions. [2021-11-09 09:56:35,090 INFO L704 BuchiCegarLoop]: Abstraction has 93 states and 94 transitions. [2021-11-09 09:56:35,091 INFO L587 BuchiCegarLoop]: Abstraction has 93 states and 94 transitions. [2021-11-09 09:56:35,091 INFO L425 BuchiCegarLoop]: ======== Iteration 45============ [2021-11-09 09:56:35,091 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 93 states and 94 transitions. [2021-11-09 09:56:35,091 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:56:35,092 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:56:35,092 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:56:35,093 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [43, 43, 1, 1, 1, 1] [2021-11-09 09:56:35,094 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:56:35,094 INFO L791 eck$LassoCheckResult]: Stem: 14298#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 14299#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 14300#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14301#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14302#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14296#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14297#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14386#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14385#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14384#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14383#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14382#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14381#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14380#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14379#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14378#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14377#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14376#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14375#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14374#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14373#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14372#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14371#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14370#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14369#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14368#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14367#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14366#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14365#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14364#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14363#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14362#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14361#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14360#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14359#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14358#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14357#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14356#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14355#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14354#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14353#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14352#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14351#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14350#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14349#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14348#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14347#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14346#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14345#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14344#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14343#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14342#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14341#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14340#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14339#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14338#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14337#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14336#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14335#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14334#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14333#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14332#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14331#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14330#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14329#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14328#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14327#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14326#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14325#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14324#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14323#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14322#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14321#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14320#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14319#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14318#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14317#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14316#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14315#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14314#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14313#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14312#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14311#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14310#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14309#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14308#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14307#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14306#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14305#L25-3 assume !(main_~i~0 < 1023); 14303#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 14304#L30-4 [2021-11-09 09:56:35,094 INFO L793 eck$LassoCheckResult]: Loop: 14304#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 14294#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 14295#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 14304#L30-4 [2021-11-09 09:56:35,095 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:56:35,095 INFO L85 PathProgramCache]: Analyzing trace with hash 178774241, now seen corresponding path program 43 times [2021-11-09 09:56:35,095 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:56:35,095 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [298356554] [2021-11-09 09:56:35,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:56:35,096 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:56:35,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:56:36,181 INFO L134 CoverageAnalysis]: Checked inductivity of 1849 backedges. 0 proven. 1849 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:56:36,181 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:56:36,181 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [298356554] [2021-11-09 09:56:36,181 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [298356554] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:56:36,182 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1259626132] [2021-11-09 09:56:36,182 INFO L93 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2021-11-09 09:56:36,182 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:56:36,182 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:56:36,185 INFO L229 MonitoredProcess]: Starting monitored process 55 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:56:36,200 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (55)] Waiting until timeout for monitored process [2021-11-09 09:56:36,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:56:36,891 INFO L263 TraceCheckSpWp]: Trace formula consists of 387 conjuncts, 45 conjunts are in the unsatisfiable core [2021-11-09 09:56:36,893 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:56:37,217 INFO L134 CoverageAnalysis]: Checked inductivity of 1849 backedges. 0 proven. 1849 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:56:37,217 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1259626132] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:56:37,218 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:56:37,218 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46] total 47 [2021-11-09 09:56:37,218 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [242325399] [2021-11-09 09:56:37,218 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:56:37,219 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:56:37,219 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 44 times [2021-11-09 09:56:37,219 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:56:37,219 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [441454321] [2021-11-09 09:56:37,219 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:56:37,219 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:56:37,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:56:37,227 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:56:37,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:56:37,245 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:56:37,290 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:56:37,291 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2021-11-09 09:56:37,292 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1081, Invalid=1081, Unknown=0, NotChecked=0, Total=2162 [2021-11-09 09:56:37,292 INFO L87 Difference]: Start difference. First operand 93 states and 94 transitions. cyclomatic complexity: 3 Second operand has 47 states, 47 states have (on average 1.9787234042553192) internal successors, (93), 47 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:56:37,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:56:37,804 INFO L93 Difference]: Finished difference Result 228 states and 229 transitions. [2021-11-09 09:56:37,805 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2021-11-09 09:56:37,805 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 228 states and 229 transitions. [2021-11-09 09:56:37,806 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:56:37,807 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 228 states to 228 states and 229 transitions. [2021-11-09 09:56:37,808 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 139 [2021-11-09 09:56:37,808 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 139 [2021-11-09 09:56:37,808 INFO L73 IsDeterministic]: Start isDeterministic. Operand 228 states and 229 transitions. [2021-11-09 09:56:37,808 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:56:37,808 INFO L681 BuchiCegarLoop]: Abstraction has 228 states and 229 transitions. [2021-11-09 09:56:37,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228 states and 229 transitions. [2021-11-09 09:56:37,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228 to 95. [2021-11-09 09:56:37,811 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 95 states, 95 states have (on average 1.0105263157894737) internal successors, (96), 94 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:56:37,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 96 transitions. [2021-11-09 09:56:37,811 INFO L704 BuchiCegarLoop]: Abstraction has 95 states and 96 transitions. [2021-11-09 09:56:37,811 INFO L587 BuchiCegarLoop]: Abstraction has 95 states and 96 transitions. [2021-11-09 09:56:37,811 INFO L425 BuchiCegarLoop]: ======== Iteration 46============ [2021-11-09 09:56:37,811 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 95 states and 96 transitions. [2021-11-09 09:56:37,812 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:56:37,812 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:56:37,812 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:56:37,813 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [44, 44, 1, 1, 1, 1] [2021-11-09 09:56:37,813 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:56:37,813 INFO L791 eck$LassoCheckResult]: Stem: 14936#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 14937#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 14938#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14939#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14940#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14934#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14935#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15026#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15025#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15024#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15023#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15022#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15021#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15020#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15019#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15018#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15017#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15016#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15015#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15014#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15013#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15012#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15011#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15010#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15009#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15008#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15007#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15006#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15005#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15004#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15003#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15002#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15001#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15000#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14999#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14998#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14997#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14996#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14995#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14994#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14993#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14992#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14991#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14990#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14989#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14988#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14987#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14986#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14985#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14984#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14983#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14982#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14981#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14980#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14979#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14978#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14977#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14976#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14975#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14974#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14973#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14972#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14971#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14970#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14969#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14968#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14967#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14966#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14965#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14964#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14963#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14962#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14961#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14960#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14959#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14958#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14957#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14956#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14955#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14954#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14953#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14952#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14951#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14950#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14949#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14948#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14947#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14946#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14945#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 14944#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 14943#L25-3 assume !(main_~i~0 < 1023); 14941#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 14942#L30-4 [2021-11-09 09:56:37,813 INFO L793 eck$LassoCheckResult]: Loop: 14942#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 14932#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 14933#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 14942#L30-4 [2021-11-09 09:56:37,814 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:56:37,814 INFO L85 PathProgramCache]: Analyzing trace with hash 3409763, now seen corresponding path program 44 times [2021-11-09 09:56:37,814 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:56:37,814 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1296049555] [2021-11-09 09:56:37,815 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:56:37,815 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:56:37,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:56:38,883 INFO L134 CoverageAnalysis]: Checked inductivity of 1936 backedges. 0 proven. 1936 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:56:38,883 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:56:38,884 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1296049555] [2021-11-09 09:56:38,884 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1296049555] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:56:38,884 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [386869097] [2021-11-09 09:56:38,884 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2021-11-09 09:56:38,884 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:56:38,884 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:56:38,886 INFO L229 MonitoredProcess]: Starting monitored process 56 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:56:38,887 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (56)] Waiting until timeout for monitored process [2021-11-09 09:56:39,602 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2021-11-09 09:56:39,602 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:56:39,604 INFO L263 TraceCheckSpWp]: Trace formula consists of 395 conjuncts, 46 conjunts are in the unsatisfiable core [2021-11-09 09:56:39,605 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:56:39,851 INFO L134 CoverageAnalysis]: Checked inductivity of 1936 backedges. 0 proven. 1936 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:56:39,851 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [386869097] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:56:39,851 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:56:39,852 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47] total 48 [2021-11-09 09:56:39,852 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1777755125] [2021-11-09 09:56:39,852 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:56:39,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:56:39,852 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 45 times [2021-11-09 09:56:39,853 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:56:39,853 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [21451061] [2021-11-09 09:56:39,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:56:39,853 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:56:39,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:56:39,859 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:56:39,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:56:39,860 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:56:39,893 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:56:39,894 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2021-11-09 09:56:39,894 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2021-11-09 09:56:39,895 INFO L87 Difference]: Start difference. First operand 95 states and 96 transitions. cyclomatic complexity: 3 Second operand has 48 states, 48 states have (on average 1.9791666666666667) internal successors, (95), 48 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:56:40,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:56:40,351 INFO L93 Difference]: Finished difference Result 233 states and 234 transitions. [2021-11-09 09:56:40,352 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2021-11-09 09:56:40,352 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 233 states and 234 transitions. [2021-11-09 09:56:40,354 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:56:40,356 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 233 states to 233 states and 234 transitions. [2021-11-09 09:56:40,356 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 142 [2021-11-09 09:56:40,356 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 142 [2021-11-09 09:56:40,356 INFO L73 IsDeterministic]: Start isDeterministic. Operand 233 states and 234 transitions. [2021-11-09 09:56:40,357 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:56:40,357 INFO L681 BuchiCegarLoop]: Abstraction has 233 states and 234 transitions. [2021-11-09 09:56:40,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 233 states and 234 transitions. [2021-11-09 09:56:40,360 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 233 to 97. [2021-11-09 09:56:40,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97 states, 97 states have (on average 1.0103092783505154) internal successors, (98), 96 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:56:40,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 98 transitions. [2021-11-09 09:56:40,361 INFO L704 BuchiCegarLoop]: Abstraction has 97 states and 98 transitions. [2021-11-09 09:56:40,361 INFO L587 BuchiCegarLoop]: Abstraction has 97 states and 98 transitions. [2021-11-09 09:56:40,361 INFO L425 BuchiCegarLoop]: ======== Iteration 47============ [2021-11-09 09:56:40,361 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97 states and 98 transitions. [2021-11-09 09:56:40,362 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:56:40,362 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:56:40,362 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:56:40,363 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [45, 45, 1, 1, 1, 1] [2021-11-09 09:56:40,363 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:56:40,363 INFO L791 eck$LassoCheckResult]: Stem: 15588#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 15589#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 15590#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15591#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15592#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15586#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15587#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15680#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15679#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15678#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15677#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15676#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15675#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15674#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15673#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15672#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15671#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15670#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15669#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15668#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15667#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15666#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15665#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15664#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15663#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15662#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15661#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15660#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15659#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15658#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15657#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15656#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15655#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15654#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15653#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15652#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15651#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15650#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15649#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15648#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15647#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15646#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15645#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15644#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15643#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15642#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15641#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15640#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15639#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15638#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15637#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15636#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15635#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15634#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15633#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15632#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15631#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15630#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15629#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15628#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15627#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15626#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15625#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15624#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15623#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15622#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15621#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15620#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15619#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15618#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15617#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15616#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15615#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15614#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15613#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15612#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15611#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15610#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15609#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15608#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15607#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15606#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15605#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15604#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15603#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15602#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15601#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15600#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15599#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15598#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15597#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 15596#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 15595#L25-3 assume !(main_~i~0 < 1023); 15593#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 15594#L30-4 [2021-11-09 09:56:40,363 INFO L793 eck$LassoCheckResult]: Loop: 15594#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 15584#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 15585#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 15594#L30-4 [2021-11-09 09:56:40,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:56:40,364 INFO L85 PathProgramCache]: Analyzing trace with hash -1018129051, now seen corresponding path program 45 times [2021-11-09 09:56:40,364 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:56:40,364 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1364704295] [2021-11-09 09:56:40,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:56:40,364 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:56:40,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:56:41,682 INFO L134 CoverageAnalysis]: Checked inductivity of 2025 backedges. 0 proven. 2025 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:56:41,682 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:56:41,682 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1364704295] [2021-11-09 09:56:41,682 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1364704295] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:56:41,682 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1972478193] [2021-11-09 09:56:41,682 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2021-11-09 09:56:41,683 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:56:41,683 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:56:41,707 INFO L229 MonitoredProcess]: Starting monitored process 57 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:56:41,721 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (57)] Waiting until timeout for monitored process [2021-11-09 09:59:00,202 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 46 check-sat command(s) [2021-11-09 09:59:00,202 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:59:00,351 INFO L263 TraceCheckSpWp]: Trace formula consists of 403 conjuncts, 47 conjunts are in the unsatisfiable core [2021-11-09 09:59:00,355 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:59:00,666 INFO L134 CoverageAnalysis]: Checked inductivity of 2025 backedges. 0 proven. 2025 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:59:00,667 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1972478193] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:59:00,667 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:59:00,667 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48] total 49 [2021-11-09 09:59:00,668 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1784813829] [2021-11-09 09:59:00,668 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:59:00,669 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:59:00,669 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 46 times [2021-11-09 09:59:00,669 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:59:00,669 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2092799844] [2021-11-09 09:59:00,670 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:59:00,670 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:59:00,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:59:00,702 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:59:00,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:59:00,705 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:59:00,738 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:59:00,739 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2021-11-09 09:59:00,740 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1176, Invalid=1176, Unknown=0, NotChecked=0, Total=2352 [2021-11-09 09:59:00,741 INFO L87 Difference]: Start difference. First operand 97 states and 98 transitions. cyclomatic complexity: 3 Second operand has 49 states, 49 states have (on average 1.9795918367346939) internal successors, (97), 49 states have internal predecessors, (97), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:59:01,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:59:01,227 INFO L93 Difference]: Finished difference Result 238 states and 239 transitions. [2021-11-09 09:59:01,228 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2021-11-09 09:59:01,228 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 238 states and 239 transitions. [2021-11-09 09:59:01,233 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:59:01,235 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 238 states to 238 states and 239 transitions. [2021-11-09 09:59:01,235 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 145 [2021-11-09 09:59:01,236 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 145 [2021-11-09 09:59:01,236 INFO L73 IsDeterministic]: Start isDeterministic. Operand 238 states and 239 transitions. [2021-11-09 09:59:01,236 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:59:01,237 INFO L681 BuchiCegarLoop]: Abstraction has 238 states and 239 transitions. [2021-11-09 09:59:01,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 238 states and 239 transitions. [2021-11-09 09:59:01,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 238 to 99. [2021-11-09 09:59:01,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99 states, 99 states have (on average 1.0101010101010102) internal successors, (100), 98 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:59:01,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 100 transitions. [2021-11-09 09:59:01,244 INFO L704 BuchiCegarLoop]: Abstraction has 99 states and 100 transitions. [2021-11-09 09:59:01,244 INFO L587 BuchiCegarLoop]: Abstraction has 99 states and 100 transitions. [2021-11-09 09:59:01,244 INFO L425 BuchiCegarLoop]: ======== Iteration 48============ [2021-11-09 09:59:01,244 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99 states and 100 transitions. [2021-11-09 09:59:01,245 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:59:01,245 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:59:01,245 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:59:01,246 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [46, 46, 1, 1, 1, 1] [2021-11-09 09:59:01,247 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:59:01,247 INFO L791 eck$LassoCheckResult]: Stem: 16254#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 16255#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 16256#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16257#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16258#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16252#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16253#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16348#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16347#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16346#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16345#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16344#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16343#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16342#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16341#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16340#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16339#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16338#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16337#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16336#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16335#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16334#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16333#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16332#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16331#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16330#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16329#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16328#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16327#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16326#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16325#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16324#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16323#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16322#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16321#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16320#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16319#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16318#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16317#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16316#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16315#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16314#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16313#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16312#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16311#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16310#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16309#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16308#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16307#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16306#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16305#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16304#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16303#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16302#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16301#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16300#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16299#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16298#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16297#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16296#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16295#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16294#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16293#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16292#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16291#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16290#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16289#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16288#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16287#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16286#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16285#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16284#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16283#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16282#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16281#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16280#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16279#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16278#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16277#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16276#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16275#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16274#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16273#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16272#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16271#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16270#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16269#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16268#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16267#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16266#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16265#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16264#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16263#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16262#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16261#L25-3 assume !(main_~i~0 < 1023); 16259#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 16260#L30-4 [2021-11-09 09:59:01,247 INFO L793 eck$LassoCheckResult]: Loop: 16260#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 16250#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 16251#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 16260#L30-4 [2021-11-09 09:59:01,247 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:59:01,247 INFO L85 PathProgramCache]: Analyzing trace with hash 830581479, now seen corresponding path program 46 times [2021-11-09 09:59:01,247 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:59:01,247 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1026705388] [2021-11-09 09:59:01,247 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:59:01,248 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:59:01,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:59:02,490 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:59:02,490 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:59:02,490 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1026705388] [2021-11-09 09:59:02,490 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1026705388] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:59:02,491 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1579671611] [2021-11-09 09:59:02,491 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2021-11-09 09:59:02,491 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:59:02,491 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:59:02,493 INFO L229 MonitoredProcess]: Starting monitored process 58 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:59:02,516 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (58)] Waiting until timeout for monitored process [2021-11-09 09:59:03,357 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2021-11-09 09:59:03,357 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:59:03,359 INFO L263 TraceCheckSpWp]: Trace formula consists of 411 conjuncts, 48 conjunts are in the unsatisfiable core [2021-11-09 09:59:03,361 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:59:03,614 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:59:03,614 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1579671611] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:59:03,614 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:59:03,614 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49] total 50 [2021-11-09 09:59:03,615 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [559995039] [2021-11-09 09:59:03,616 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:59:03,616 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:59:03,616 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 47 times [2021-11-09 09:59:03,616 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:59:03,616 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1468858636] [2021-11-09 09:59:03,616 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:59:03,616 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:59:03,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:59:03,622 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:59:03,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:59:03,624 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:59:03,670 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:59:03,671 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2021-11-09 09:59:03,672 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2021-11-09 09:59:03,672 INFO L87 Difference]: Start difference. First operand 99 states and 100 transitions. cyclomatic complexity: 3 Second operand has 50 states, 50 states have (on average 1.98) internal successors, (99), 50 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:59:04,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:59:04,056 INFO L93 Difference]: Finished difference Result 243 states and 244 transitions. [2021-11-09 09:59:04,057 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2021-11-09 09:59:04,057 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 243 states and 244 transitions. [2021-11-09 09:59:04,058 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:59:04,060 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 243 states to 243 states and 244 transitions. [2021-11-09 09:59:04,060 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 148 [2021-11-09 09:59:04,060 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 148 [2021-11-09 09:59:04,061 INFO L73 IsDeterministic]: Start isDeterministic. Operand 243 states and 244 transitions. [2021-11-09 09:59:04,061 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:59:04,061 INFO L681 BuchiCegarLoop]: Abstraction has 243 states and 244 transitions. [2021-11-09 09:59:04,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 243 states and 244 transitions. [2021-11-09 09:59:04,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 243 to 101. [2021-11-09 09:59:04,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101 states, 101 states have (on average 1.00990099009901) internal successors, (102), 100 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:59:04,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 102 transitions. [2021-11-09 09:59:04,065 INFO L704 BuchiCegarLoop]: Abstraction has 101 states and 102 transitions. [2021-11-09 09:59:04,065 INFO L587 BuchiCegarLoop]: Abstraction has 101 states and 102 transitions. [2021-11-09 09:59:04,065 INFO L425 BuchiCegarLoop]: ======== Iteration 49============ [2021-11-09 09:59:04,065 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101 states and 102 transitions. [2021-11-09 09:59:04,066 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:59:04,066 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:59:04,066 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:59:04,067 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [47, 47, 1, 1, 1, 1] [2021-11-09 09:59:04,067 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:59:04,068 INFO L791 eck$LassoCheckResult]: Stem: 16934#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 16935#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 16936#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16937#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16938#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16932#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16933#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17030#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17029#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17028#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17027#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17026#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17025#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17024#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17023#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17022#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17021#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17020#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17019#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17018#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17017#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17016#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17015#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17014#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17013#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17012#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17011#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17010#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17009#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17008#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17007#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17006#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17005#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17004#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17003#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17002#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17001#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17000#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16999#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16998#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16997#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16996#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16995#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16994#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16993#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16992#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16991#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16990#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16989#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16988#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16987#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16986#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16985#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16984#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16983#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16982#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16981#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16980#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16979#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16978#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16977#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16976#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16975#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16974#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16973#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16972#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16971#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16970#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16969#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16968#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16967#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16966#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16965#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16964#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16963#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16962#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16961#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16960#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16959#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16958#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16957#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16956#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16955#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16954#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16953#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16952#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16951#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16950#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16949#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16948#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16947#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16946#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16945#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16944#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16943#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 16942#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 16941#L25-3 assume !(main_~i~0 < 1023); 16939#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 16940#L30-4 [2021-11-09 09:59:04,068 INFO L793 eck$LassoCheckResult]: Loop: 16940#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 16930#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 16931#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 16940#L30-4 [2021-11-09 09:59:04,068 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:59:04,069 INFO L85 PathProgramCache]: Analyzing trace with hash -675059735, now seen corresponding path program 47 times [2021-11-09 09:59:04,069 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:59:04,069 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [299065181] [2021-11-09 09:59:04,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:59:04,069 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:59:04,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:59:05,482 INFO L134 CoverageAnalysis]: Checked inductivity of 2209 backedges. 0 proven. 2209 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:59:05,482 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:59:05,482 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [299065181] [2021-11-09 09:59:05,483 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [299065181] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:59:05,483 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2083167185] [2021-11-09 09:59:05,483 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2021-11-09 09:59:05,483 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:59:05,483 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:59:05,517 INFO L229 MonitoredProcess]: Starting monitored process 59 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:59:05,584 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (59)] Waiting until timeout for monitored process [2021-11-09 09:59:24,908 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 48 check-sat command(s) [2021-11-09 09:59:24,909 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2021-11-09 09:59:24,938 INFO L263 TraceCheckSpWp]: Trace formula consists of 419 conjuncts, 49 conjunts are in the unsatisfiable core [2021-11-09 09:59:24,939 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2021-11-09 09:59:25,286 INFO L134 CoverageAnalysis]: Checked inductivity of 2209 backedges. 0 proven. 2209 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:59:25,286 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2083167185] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:59:25,286 INFO L186 FreeRefinementEngine]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2021-11-09 09:59:25,289 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50] total 51 [2021-11-09 09:59:25,290 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1384680815] [2021-11-09 09:59:25,290 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:59:25,291 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:59:25,291 INFO L85 PathProgramCache]: Analyzing trace with hash 49813, now seen corresponding path program 48 times [2021-11-09 09:59:25,291 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:59:25,291 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1569146889] [2021-11-09 09:59:25,291 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:59:25,291 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:59:25,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:59:25,303 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:59:25,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:59:25,305 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:59:25,337 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:59:25,338 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2021-11-09 09:59:25,339 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1275, Invalid=1275, Unknown=0, NotChecked=0, Total=2550 [2021-11-09 09:59:25,340 INFO L87 Difference]: Start difference. First operand 101 states and 102 transitions. cyclomatic complexity: 3 Second operand has 51 states, 51 states have (on average 1.9803921568627452) internal successors, (101), 51 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:59:25,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:59:25,758 INFO L93 Difference]: Finished difference Result 248 states and 249 transitions. [2021-11-09 09:59:25,759 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2021-11-09 09:59:25,759 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 248 states and 249 transitions. [2021-11-09 09:59:25,760 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:59:25,761 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 248 states to 248 states and 249 transitions. [2021-11-09 09:59:25,762 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 151 [2021-11-09 09:59:25,762 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 151 [2021-11-09 09:59:25,762 INFO L73 IsDeterministic]: Start isDeterministic. Operand 248 states and 249 transitions. [2021-11-09 09:59:25,762 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:59:25,762 INFO L681 BuchiCegarLoop]: Abstraction has 248 states and 249 transitions. [2021-11-09 09:59:25,762 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 248 states and 249 transitions. [2021-11-09 09:59:25,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 248 to 103. [2021-11-09 09:59:25,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 103 states, 103 states have (on average 1.0097087378640777) internal successors, (104), 102 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:59:25,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103 states to 103 states and 104 transitions. [2021-11-09 09:59:25,765 INFO L704 BuchiCegarLoop]: Abstraction has 103 states and 104 transitions. [2021-11-09 09:59:25,765 INFO L587 BuchiCegarLoop]: Abstraction has 103 states and 104 transitions. [2021-11-09 09:59:25,765 INFO L425 BuchiCegarLoop]: ======== Iteration 50============ [2021-11-09 09:59:25,765 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 103 states and 104 transitions. [2021-11-09 09:59:25,766 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3 [2021-11-09 09:59:25,766 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:59:25,766 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:59:25,767 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [48, 48, 1, 1, 1, 1] [2021-11-09 09:59:25,767 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1] [2021-11-09 09:59:25,767 INFO L791 eck$LassoCheckResult]: Stem: 17628#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string0.base, #t~string0.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string0.base, #t~string0.offset, 1);call write~init~int(0, #t~string0.base, 1 + #t~string0.offset, 1);call #t~string1.base, #t~string1.offset := #Ultimate.allocOnStack(10); 17629#L-1 havoc main_#res;havoc main_#t~nondet4, main_#t~post3, main_#t~post5, main_#t~mem6, main_~#A~0.base, main_~#A~0.offset, main_~i~0;call main_~#A~0.base, main_~#A~0.offset := #Ultimate.allocOnStack(4096);havoc main_~i~0;main_~i~0 := 0; 17630#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17631#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17632#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17626#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17627#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17726#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17725#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17724#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17723#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17722#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17721#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17720#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17719#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17718#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17717#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17716#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17715#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17714#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17713#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17712#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17711#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17710#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17709#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17708#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17707#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17706#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17705#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17704#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17703#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17702#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17701#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17700#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17699#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17698#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17697#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17696#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17695#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17694#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17693#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17692#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17691#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17690#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17689#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17688#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17687#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17686#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17685#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17684#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17683#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17682#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17681#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17680#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17679#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17678#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17677#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17676#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17675#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17674#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17673#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17672#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17671#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17670#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17669#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17668#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17667#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17666#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17665#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17664#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17663#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17662#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17661#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17660#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17659#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17658#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17657#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17656#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17655#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17654#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17653#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17652#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17651#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17650#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17649#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17648#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17647#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17646#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17645#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17644#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17643#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17642#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17641#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17640#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17639#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17638#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17637#L25-3 assume !!(main_~i~0 < 1023);call write~int(main_#t~nondet4, main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4);havoc main_#t~nondet4; 17636#L25-2 main_#t~post3 := main_~i~0;main_~i~0 := 1 + main_#t~post3;havoc main_#t~post3; 17635#L25-3 assume !(main_~i~0 < 1023); 17633#L25-4 call write~int(0, main_~#A~0.base, 4092 + main_~#A~0.offset, 4);main_~i~0 := 0; 17634#L30-4 [2021-11-09 09:59:25,767 INFO L793 eck$LassoCheckResult]: Loop: 17634#L30-4 call main_#t~mem6 := read~int(main_~#A~0.base, main_~#A~0.offset + 4 * main_~i~0, 4); 17624#L30-1 assume !!(0 != main_#t~mem6);havoc main_#t~mem6; 17625#L30-3 main_#t~post5 := main_~i~0;main_~i~0 := 1 + main_#t~post5;havoc main_#t~post5; 17634#L30-4 [2021-11-09 09:59:25,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:59:25,768 INFO L85 PathProgramCache]: Analyzing trace with hash -192287637, now seen corresponding path program 48 times [2021-11-09 09:59:25,768 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:59:25,768 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1293741457] [2021-11-09 09:59:25,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:59:25,768 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:59:25,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:59:27,291 INFO L134 CoverageAnalysis]: Checked inductivity of 2304 backedges. 0 proven. 2304 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:59:27,292 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:59:27,292 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1293741457] [2021-11-09 09:59:27,292 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1293741457] provided 0 perfect and 1 imperfect interpolant sequences [2021-11-09 09:59:27,292 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1482053986] [2021-11-09 09:59:27,292 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2021-11-09 09:59:27,292 INFO L168 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2021-11-09 09:59:27,292 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:59:27,295 INFO L229 MonitoredProcess]: Starting monitored process 60 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2021-11-09 09:59:27,309 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_d0476cb9-3642-4f9b-b61e-d0064e1cf5cf/bin/uautomizer-IVEQpCNsaX/z3 -smt2 -in SMTLIB2_COMPLIANT=true (60)] Waiting until timeout for monitored process