./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f8e1c903 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_505d4f12-3627-4247-8bc7-397770d253d9/bin/uautomizer-IVEQpCNsaX/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_505d4f12-3627-4247-8bc7-397770d253d9/bin/uautomizer-IVEQpCNsaX/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_505d4f12-3627-4247-8bc7-397770d253d9/bin/uautomizer-IVEQpCNsaX/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_505d4f12-3627-4247-8bc7-397770d253d9/bin/uautomizer-IVEQpCNsaX/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_505d4f12-3627-4247-8bc7-397770d253d9/bin/uautomizer-IVEQpCNsaX/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_505d4f12-3627-4247-8bc7-397770d253d9/bin/uautomizer-IVEQpCNsaX --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 16e147b68a860b93a665f8bd36a316225675cf186d50a72fc3242bc6ec552f78 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-f8e1c90 [2021-11-09 09:41:54,930 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-09 09:41:54,934 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-09 09:41:54,987 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-09 09:41:54,988 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-09 09:41:54,990 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-09 09:41:54,992 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-09 09:41:55,000 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-09 09:41:55,004 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-09 09:41:55,007 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-09 09:41:55,009 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-09 09:41:55,013 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-09 09:41:55,014 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-09 09:41:55,024 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-09 09:41:55,028 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-09 09:41:55,031 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-09 09:41:55,035 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-09 09:41:55,039 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-09 09:41:55,042 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-09 09:41:55,049 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-09 09:41:55,052 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-09 09:41:55,058 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-09 09:41:55,062 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-09 09:41:55,064 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-09 09:41:55,073 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-09 09:41:55,077 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-09 09:41:55,077 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-09 09:41:55,080 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-09 09:41:55,082 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-09 09:41:55,084 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-09 09:41:55,085 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-09 09:41:55,087 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-09 09:41:55,089 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-09 09:41:55,091 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-09 09:41:55,093 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-09 09:41:55,093 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-09 09:41:55,094 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-09 09:41:55,095 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-09 09:41:55,095 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-09 09:41:55,096 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-09 09:41:55,097 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-09 09:41:55,099 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_505d4f12-3627-4247-8bc7-397770d253d9/bin/uautomizer-IVEQpCNsaX/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-09 09:41:55,161 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-09 09:41:55,161 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-09 09:41:55,161 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-09 09:41:55,161 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-09 09:41:55,163 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-09 09:41:55,163 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-09 09:41:55,163 INFO L138 SettingsManager]: * Use SBE=true [2021-11-09 09:41:55,163 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-09 09:41:55,163 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-09 09:41:55,164 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-09 09:41:55,164 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-09 09:41:55,164 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-09 09:41:55,164 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-09 09:41:55,164 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-09 09:41:55,165 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-09 09:41:55,165 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-09 09:41:55,165 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-09 09:41:55,165 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-09 09:41:55,166 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-09 09:41:55,166 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-09 09:41:55,166 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-09 09:41:55,166 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-09 09:41:55,167 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-09 09:41:55,167 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-09 09:41:55,167 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-09 09:41:55,168 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-09 09:41:55,168 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-09 09:41:55,168 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-09 09:41:55,169 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-09 09:41:55,169 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-09 09:41:55,170 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-09 09:41:55,170 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-09 09:41:55,171 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-09 09:41:55,172 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_505d4f12-3627-4247-8bc7-397770d253d9/bin/uautomizer-IVEQpCNsaX/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_505d4f12-3627-4247-8bc7-397770d253d9/bin/uautomizer-IVEQpCNsaX Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 16e147b68a860b93a665f8bd36a316225675cf186d50a72fc3242bc6ec552f78 [2021-11-09 09:41:55,495 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-09 09:41:55,526 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-09 09:41:55,529 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-09 09:41:55,531 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-09 09:41:55,532 INFO L275 PluginConnector]: CDTParser initialized [2021-11-09 09:41:55,533 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_505d4f12-3627-4247-8bc7-397770d253d9/bin/uautomizer-IVEQpCNsaX/../../sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2021-11-09 09:41:55,675 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_505d4f12-3627-4247-8bc7-397770d253d9/bin/uautomizer-IVEQpCNsaX/data/cb7013629/3495442ac8d149938bfc33264f01a821/FLAG14ed26e39 [2021-11-09 09:41:56,214 INFO L306 CDTParser]: Found 1 translation units. [2021-11-09 09:41:56,215 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_505d4f12-3627-4247-8bc7-397770d253d9/sv-benchmarks/c/systemc/token_ring.05.cil-2.c [2021-11-09 09:41:56,229 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_505d4f12-3627-4247-8bc7-397770d253d9/bin/uautomizer-IVEQpCNsaX/data/cb7013629/3495442ac8d149938bfc33264f01a821/FLAG14ed26e39 [2021-11-09 09:41:56,536 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_505d4f12-3627-4247-8bc7-397770d253d9/bin/uautomizer-IVEQpCNsaX/data/cb7013629/3495442ac8d149938bfc33264f01a821 [2021-11-09 09:41:56,539 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-09 09:41:56,542 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-09 09:41:56,556 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-09 09:41:56,556 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-09 09:41:56,562 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-09 09:41:56,563 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 09:41:56" (1/1) ... [2021-11-09 09:41:56,565 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@54da408e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:41:56, skipping insertion in model container [2021-11-09 09:41:56,569 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 09:41:56" (1/1) ... [2021-11-09 09:41:56,579 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-09 09:41:56,636 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-09 09:41:56,864 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_505d4f12-3627-4247-8bc7-397770d253d9/sv-benchmarks/c/systemc/token_ring.05.cil-2.c[671,684] [2021-11-09 09:41:56,973 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-09 09:41:57,011 INFO L203 MainTranslator]: Completed pre-run [2021-11-09 09:41:57,037 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_505d4f12-3627-4247-8bc7-397770d253d9/sv-benchmarks/c/systemc/token_ring.05.cil-2.c[671,684] [2021-11-09 09:41:57,140 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-09 09:41:57,177 INFO L208 MainTranslator]: Completed translation [2021-11-09 09:41:57,178 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:41:57 WrapperNode [2021-11-09 09:41:57,178 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-09 09:41:57,180 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-09 09:41:57,180 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-09 09:41:57,181 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-09 09:41:57,190 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:41:57" (1/1) ... [2021-11-09 09:41:57,220 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:41:57" (1/1) ... [2021-11-09 09:41:57,335 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-09 09:41:57,336 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-09 09:41:57,336 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-09 09:41:57,336 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-09 09:41:57,351 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:41:57" (1/1) ... [2021-11-09 09:41:57,351 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:41:57" (1/1) ... [2021-11-09 09:41:57,367 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:41:57" (1/1) ... [2021-11-09 09:41:57,367 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:41:57" (1/1) ... [2021-11-09 09:41:57,422 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:41:57" (1/1) ... [2021-11-09 09:41:57,448 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:41:57" (1/1) ... [2021-11-09 09:41:57,453 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:41:57" (1/1) ... [2021-11-09 09:41:57,462 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-09 09:41:57,464 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-09 09:41:57,464 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-09 09:41:57,464 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-09 09:41:57,466 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:41:57" (1/1) ... [2021-11-09 09:41:57,492 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:41:57,523 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_505d4f12-3627-4247-8bc7-397770d253d9/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:41:57,546 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_505d4f12-3627-4247-8bc7-397770d253d9/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:41:57,554 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_505d4f12-3627-4247-8bc7-397770d253d9/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-09 09:41:57,593 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-09 09:41:57,593 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-09 09:41:57,593 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-09 09:41:57,594 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-09 09:41:59,108 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-09 09:41:59,109 INFO L299 CfgBuilder]: Removed 198 assume(true) statements. [2021-11-09 09:41:59,113 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 09:41:59 BoogieIcfgContainer [2021-11-09 09:41:59,113 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-09 09:41:59,114 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-09 09:41:59,114 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-09 09:41:59,118 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-09 09:41:59,119 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-09 09:41:59,120 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 09.11 09:41:56" (1/3) ... [2021-11-09 09:41:59,121 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2db99681 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 09:41:59, skipping insertion in model container [2021-11-09 09:41:59,122 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-09 09:41:59,122 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:41:57" (2/3) ... [2021-11-09 09:41:59,122 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2db99681 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 09:41:59, skipping insertion in model container [2021-11-09 09:41:59,122 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-09 09:41:59,123 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 09:41:59" (3/3) ... [2021-11-09 09:41:59,124 INFO L389 chiAutomizerObserver]: Analyzing ICFG token_ring.05.cil-2.c [2021-11-09 09:41:59,178 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-09 09:41:59,179 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-09 09:41:59,179 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-09 09:41:59,179 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-09 09:41:59,179 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-09 09:41:59,179 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-09 09:41:59,179 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-09 09:41:59,180 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-09 09:41:59,218 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 538 states, 537 states have (on average 1.5512104283054005) internal successors, (833), 537 states have internal predecessors, (833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:41:59,285 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 459 [2021-11-09 09:41:59,293 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:41:59,293 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:41:59,308 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:41:59,309 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:41:59,309 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-09 09:41:59,312 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 538 states, 537 states have (on average 1.5512104283054005) internal successors, (833), 537 states have internal predecessors, (833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:41:59,334 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 459 [2021-11-09 09:41:59,335 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:41:59,335 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:41:59,341 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:41:59,342 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:41:59,352 INFO L791 eck$LassoCheckResult]: Stem: 521#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 449#L-1true havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 247#L903true havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7#L419true assume !(1 == ~m_i~0);~m_st~0 := 2; 352#L426-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 149#L431-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 303#L436-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 135#L441-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 484#L446-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 341#L451-1true assume !(0 == ~M_E~0); 504#L611-1true assume !(0 == ~T1_E~0); 360#L616-1true assume !(0 == ~T2_E~0); 370#L621-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 69#L626-1true assume !(0 == ~T4_E~0); 331#L631-1true assume !(0 == ~T5_E~0); 174#L636-1true assume !(0 == ~E_M~0); 90#L641-1true assume !(0 == ~E_1~0); 184#L646-1true assume !(0 == ~E_2~0); 474#L651-1true assume !(0 == ~E_3~0); 426#L656-1true assume !(0 == ~E_4~0); 339#L661-1true assume 0 == ~E_5~0;~E_5~0 := 1; 387#L666-1true havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 505#L304true assume 1 == ~m_pc~0; 219#L305true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 58#L315true is_master_triggered_#res := is_master_triggered_~__retres1~0; 519#L316true activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 29#L755true assume !(0 != activate_threads_~tmp~1); 526#L755-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8#L323true assume !(1 == ~t1_pc~0); 218#L323-2true is_transmit1_triggered_~__retres1~1 := 0; 39#L334true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 301#L335true activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 475#L763true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 486#L763-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 41#L342true assume 1 == ~t2_pc~0; 501#L343true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 104#L353true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 466#L354true activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 507#L771true assume !(0 != activate_threads_~tmp___1~0); 332#L771-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 230#L361true assume !(1 == ~t3_pc~0); 249#L361-2true is_transmit3_triggered_~__retres1~3 := 0; 443#L372true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 128#L373true activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 418#L779true assume !(0 != activate_threads_~tmp___2~0); 47#L779-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 228#L380true assume 1 == ~t4_pc~0; 80#L381true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 354#L391true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 454#L392true activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 262#L787true assume !(0 != activate_threads_~tmp___3~0); 499#L787-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 81#L399true assume !(1 == ~t5_pc~0); 155#L399-2true is_transmit5_triggered_~__retres1~5 := 0; 367#L410true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 465#L411true activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 150#L795true assume !(0 != activate_threads_~tmp___4~0); 437#L795-2true assume !(1 == ~M_E~0); 353#L679-1true assume !(1 == ~T1_E~0); 111#L684-1true assume !(1 == ~T2_E~0); 238#L689-1true assume !(1 == ~T3_E~0); 516#L694-1true assume !(1 == ~T4_E~0); 237#L699-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 340#L704-1true assume !(1 == ~E_M~0); 217#L709-1true assume !(1 == ~E_1~0); 177#L714-1true assume !(1 == ~E_2~0); 323#L719-1true assume !(1 == ~E_3~0); 461#L724-1true assume !(1 == ~E_4~0); 64#L729-1true assume !(1 == ~E_5~0); 55#L940-1true [2021-11-09 09:41:59,355 INFO L793 eck$LassoCheckResult]: Loop: 55#L940-1true assume !false; 381#L941true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 109#L586true assume !true; 468#L601true start_simulation_~kernel_st~0 := 2; 400#L419-1true start_simulation_~kernel_st~0 := 3; 365#L611-2true assume 0 == ~M_E~0;~M_E~0 := 1; 234#L611-4true assume !(0 == ~T1_E~0); 297#L616-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 62#L621-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 32#L626-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 535#L631-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 33#L636-3true assume 0 == ~E_M~0;~E_M~0 := 1; 70#L641-3true assume 0 == ~E_1~0;~E_1~0 := 1; 233#L646-3true assume 0 == ~E_2~0;~E_2~0 := 1; 76#L651-3true assume !(0 == ~E_3~0); 209#L656-3true assume 0 == ~E_4~0;~E_4~0 := 1; 476#L661-3true assume 0 == ~E_5~0;~E_5~0 := 1; 488#L666-3true havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 152#L304-21true assume 1 == ~m_pc~0; 497#L305-7true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 259#L315-7true is_master_triggered_#res := is_master_triggered_~__retres1~0; 489#L316-7true activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 194#L755-21true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 211#L755-23true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 473#L323-21true assume 1 == ~t1_pc~0; 16#L324-7true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 388#L334-7true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 302#L335-7true activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 382#L763-21true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 405#L763-23true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 532#L342-21true assume 1 == ~t2_pc~0; 27#L343-7true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 254#L353-7true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 376#L354-7true activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 334#L771-21true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 82#L771-23true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 455#L361-21true assume 1 == ~t3_pc~0; 487#L362-7true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 460#L372-7true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 356#L373-7true activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 175#L779-21true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 31#L779-23true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 496#L380-21true assume !(1 == ~t4_pc~0); 67#L380-23true is_transmit4_triggered_~__retres1~4 := 0; 96#L391-7true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 310#L392-7true activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 322#L787-21true assume !(0 != activate_threads_~tmp___3~0); 263#L787-23true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 140#L399-21true assume !(1 == ~t5_pc~0); 72#L399-23true is_transmit5_triggered_~__retres1~5 := 0; 274#L410-7true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 403#L411-7true activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 481#L795-21true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 431#L795-23true assume 1 == ~M_E~0;~M_E~0 := 2; 28#L679-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 220#L684-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 3#L689-3true assume !(1 == ~T3_E~0); 165#L694-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 22#L699-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 287#L704-3true assume 1 == ~E_M~0;~E_M~0 := 2; 380#L709-3true assume 1 == ~E_1~0;~E_1~0 := 2; 279#L714-3true assume 1 == ~E_2~0;~E_2~0 := 2; 159#L719-3true assume 1 == ~E_3~0;~E_3~0 := 2; 21#L724-3true assume 1 == ~E_4~0;~E_4~0 := 2; 267#L729-3true assume !(1 == ~E_5~0); 306#L734-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 38#L464-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 210#L496-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 45#L497-1true start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 246#L959true assume !(0 == start_simulation_~tmp~3); 456#L959-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 179#L464-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 364#L496-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 440#L497-2true stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 349#L914true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 122#L921true stop_simulation_#res := stop_simulation_~__retres2~0; 523#L922true start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 288#L972true assume !(0 != start_simulation_~tmp___0~1); 55#L940-1true [2021-11-09 09:41:59,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:41:59,363 INFO L85 PathProgramCache]: Analyzing trace with hash -81461004, now seen corresponding path program 1 times [2021-11-09 09:41:59,375 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:41:59,375 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1021253972] [2021-11-09 09:41:59,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:41:59,377 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:41:59,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:41:59,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:41:59,647 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:41:59,647 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1021253972] [2021-11-09 09:41:59,649 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1021253972] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:41:59,649 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:41:59,649 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:41:59,651 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1551241840] [2021-11-09 09:41:59,658 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:41:59,659 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:41:59,659 INFO L85 PathProgramCache]: Analyzing trace with hash 428772577, now seen corresponding path program 1 times [2021-11-09 09:41:59,660 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:41:59,660 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364920128] [2021-11-09 09:41:59,660 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:41:59,661 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:41:59,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:41:59,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:41:59,700 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:41:59,700 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [364920128] [2021-11-09 09:41:59,701 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [364920128] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:41:59,701 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:41:59,701 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-09 09:41:59,702 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [18153736] [2021-11-09 09:41:59,703 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:41:59,705 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:41:59,723 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:41:59,724 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:41:59,728 INFO L87 Difference]: Start difference. First operand has 538 states, 537 states have (on average 1.5512104283054005) internal successors, (833), 537 states have internal predecessors, (833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:41:59,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:41:59,829 INFO L93 Difference]: Finished difference Result 538 states and 814 transitions. [2021-11-09 09:41:59,830 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:41:59,832 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 538 states and 814 transitions. [2021-11-09 09:41:59,841 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-11-09 09:41:59,856 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 538 states to 532 states and 808 transitions. [2021-11-09 09:41:59,858 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2021-11-09 09:41:59,860 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2021-11-09 09:41:59,861 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 808 transitions. [2021-11-09 09:41:59,866 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:41:59,866 INFO L681 BuchiCegarLoop]: Abstraction has 532 states and 808 transitions. [2021-11-09 09:41:59,889 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 808 transitions. [2021-11-09 09:41:59,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2021-11-09 09:41:59,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 532 states, 532 states have (on average 1.518796992481203) internal successors, (808), 531 states have internal predecessors, (808), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:41:59,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 808 transitions. [2021-11-09 09:41:59,964 INFO L704 BuchiCegarLoop]: Abstraction has 532 states and 808 transitions. [2021-11-09 09:41:59,964 INFO L587 BuchiCegarLoop]: Abstraction has 532 states and 808 transitions. [2021-11-09 09:41:59,964 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-09 09:41:59,965 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 808 transitions. [2021-11-09 09:41:59,971 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-11-09 09:41:59,971 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:41:59,971 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:41:59,976 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:41:59,977 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:41:59,977 INFO L791 eck$LassoCheckResult]: Stem: 1616#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 1608#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1494#L903 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1095#L419 assume 1 == ~m_i~0;~m_st~0 := 0; 1096#L426-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1361#L431-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1362#L436-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1339#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1340#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1555#L451-1 assume !(0 == ~M_E~0); 1556#L611-1 assume !(0 == ~T1_E~0); 1568#L616-1 assume !(0 == ~T2_E~0); 1569#L621-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1216#L626-1 assume !(0 == ~T4_E~0); 1217#L631-1 assume !(0 == ~T5_E~0); 1401#L636-1 assume !(0 == ~E_M~0); 1262#L641-1 assume !(0 == ~E_1~0); 1263#L646-1 assume !(0 == ~E_2~0); 1417#L651-1 assume !(0 == ~E_3~0); 1600#L656-1 assume !(0 == ~E_4~0); 1553#L661-1 assume 0 == ~E_5~0;~E_5~0 := 1; 1554#L666-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1581#L304 assume 1 == ~m_pc~0; 1460#L305 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1197#L315 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1198#L316 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1139#L755 assume !(0 != activate_threads_~tmp~1); 1140#L755-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1097#L323 assume !(1 == ~t1_pc~0); 1098#L323-2 is_transmit1_triggered_~__retres1~1 := 0; 1162#L334 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1163#L335 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1529#L763 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1612#L763-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1165#L342 assume 1 == ~t2_pc~0; 1166#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1285#L353 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1286#L354 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1610#L771 assume !(0 != activate_threads_~tmp___1~0); 1549#L771-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1473#L361 assume !(1 == ~t3_pc~0); 1474#L361-2 is_transmit3_triggered_~__retres1~3 := 0; 1495#L372 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1327#L373 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1328#L779 assume !(0 != activate_threads_~tmp___2~0); 1178#L779-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1179#L380 assume 1 == ~t4_pc~0; 1239#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1240#L391 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1562#L392 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1503#L787 assume !(0 != activate_threads_~tmp___3~0); 1504#L787-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1242#L399 assume !(1 == ~t5_pc~0); 1243#L399-2 is_transmit5_triggered_~__retres1~5 := 0; 1373#L410 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1572#L411 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1363#L795 assume !(0 != activate_threads_~tmp___4~0); 1364#L795-2 assume !(1 == ~M_E~0); 1560#L679-1 assume !(1 == ~T1_E~0); 1298#L684-1 assume !(1 == ~T2_E~0); 1299#L689-1 assume !(1 == ~T3_E~0); 1484#L694-1 assume !(1 == ~T4_E~0); 1482#L699-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1483#L704-1 assume !(1 == ~E_M~0); 1459#L709-1 assume !(1 == ~E_1~0); 1405#L714-1 assume !(1 == ~E_2~0); 1406#L719-1 assume !(1 == ~E_3~0); 1545#L724-1 assume !(1 == ~E_4~0); 1207#L729-1 assume !(1 == ~E_5~0); 1191#L940-1 [2021-11-09 09:41:59,978 INFO L793 eck$LassoCheckResult]: Loop: 1191#L940-1 assume !false; 1192#L941 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1294#L586 assume !false; 1295#L507 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1604#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1479#L496 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1480#L497 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 1468#L511 assume !(0 != eval_~tmp~0); 1469#L601 start_simulation_~kernel_st~0 := 2; 1590#L419-1 start_simulation_~kernel_st~0 := 3; 1571#L611-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1477#L611-4 assume !(0 == ~T1_E~0); 1478#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1205#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1146#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1147#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1148#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1149#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1218#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1230#L651-3 assume !(0 == ~E_3~0); 1231#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1453#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1613#L666-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1368#L304-21 assume !(1 == ~m_pc~0); 1234#L304-23 is_master_triggered_~__retres1~0 := 0; 1235#L315-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1500#L316-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1429#L755-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1430#L755-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1454#L323-21 assume 1 == ~t1_pc~0; 1110#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1111#L334-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1530#L335-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1531#L763-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1580#L763-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1594#L342-21 assume !(1 == ~t2_pc~0); 1136#L342-23 is_transmit2_triggered_~__retres1~2 := 0; 1135#L353-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1498#L354-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1550#L771-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1245#L771-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1246#L361-21 assume !(1 == ~t3_pc~0); 1605#L361-23 is_transmit3_triggered_~__retres1~3 := 0; 1606#L372-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1563#L373-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1404#L779-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1144#L779-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1145#L380-21 assume !(1 == ~t4_pc~0); 1212#L380-23 is_transmit4_triggered_~__retres1~4 := 0; 1213#L391-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1272#L392-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1535#L787-21 assume !(0 != activate_threads_~tmp___3~0); 1505#L787-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1349#L399-21 assume !(1 == ~t5_pc~0); 1222#L399-23 is_transmit5_triggered_~__retres1~5 := 0; 1223#L410-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1514#L411-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1593#L795-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1603#L795-23 assume 1 == ~M_E~0;~M_E~0 := 2; 1137#L679-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1138#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1087#L689-3 assume !(1 == ~T3_E~0); 1088#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1126#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1127#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1522#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1516#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1377#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1122#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1123#L729-3 assume !(1 == ~E_5~0); 1509#L734-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1159#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1160#L496-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1174#L497-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 1175#L959 assume !(0 == start_simulation_~tmp~3); 1493#L959-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1408#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1409#L496-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1570#L497-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 1559#L914 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1318#L921 stop_simulation_#res := stop_simulation_~__retres2~0; 1319#L922 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 1520#L972 assume !(0 != start_simulation_~tmp___0~1); 1191#L940-1 [2021-11-09 09:41:59,979 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:41:59,979 INFO L85 PathProgramCache]: Analyzing trace with hash 650506422, now seen corresponding path program 1 times [2021-11-09 09:41:59,979 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:41:59,980 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1920288950] [2021-11-09 09:41:59,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:41:59,980 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:00,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:00,060 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:00,062 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:00,062 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1920288950] [2021-11-09 09:42:00,063 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1920288950] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:00,063 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:00,063 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:42:00,066 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2037226995] [2021-11-09 09:42:00,067 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:42:00,068 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:00,081 INFO L85 PathProgramCache]: Analyzing trace with hash 308429749, now seen corresponding path program 1 times [2021-11-09 09:42:00,081 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:00,082 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1265216530] [2021-11-09 09:42:00,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:00,084 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:00,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:00,242 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:00,243 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:00,243 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1265216530] [2021-11-09 09:42:00,244 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1265216530] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:00,244 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:00,244 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:42:00,245 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [878002978] [2021-11-09 09:42:00,245 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:42:00,246 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:42:00,247 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:42:00,247 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:42:00,248 INFO L87 Difference]: Start difference. First operand 532 states and 808 transitions. cyclomatic complexity: 277 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:00,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:42:00,268 INFO L93 Difference]: Finished difference Result 532 states and 807 transitions. [2021-11-09 09:42:00,268 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:42:00,269 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 807 transitions. [2021-11-09 09:42:00,278 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-11-09 09:42:00,285 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 807 transitions. [2021-11-09 09:42:00,286 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2021-11-09 09:42:00,287 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2021-11-09 09:42:00,287 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 807 transitions. [2021-11-09 09:42:00,289 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:42:00,290 INFO L681 BuchiCegarLoop]: Abstraction has 532 states and 807 transitions. [2021-11-09 09:42:00,291 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 807 transitions. [2021-11-09 09:42:00,305 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2021-11-09 09:42:00,307 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 532 states, 532 states have (on average 1.5169172932330828) internal successors, (807), 531 states have internal predecessors, (807), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:00,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 807 transitions. [2021-11-09 09:42:00,310 INFO L704 BuchiCegarLoop]: Abstraction has 532 states and 807 transitions. [2021-11-09 09:42:00,311 INFO L587 BuchiCegarLoop]: Abstraction has 532 states and 807 transitions. [2021-11-09 09:42:00,311 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-09 09:42:00,311 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 807 transitions. [2021-11-09 09:42:00,317 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-11-09 09:42:00,317 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:42:00,317 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:42:00,323 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:00,323 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:00,324 INFO L791 eck$LassoCheckResult]: Stem: 2687#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 2679#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2565#L903 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2166#L419 assume 1 == ~m_i~0;~m_st~0 := 0; 2167#L426-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2432#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2433#L436-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2410#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2411#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2626#L451-1 assume !(0 == ~M_E~0); 2627#L611-1 assume !(0 == ~T1_E~0); 2639#L616-1 assume !(0 == ~T2_E~0); 2640#L621-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2289#L626-1 assume !(0 == ~T4_E~0); 2290#L631-1 assume !(0 == ~T5_E~0); 2472#L636-1 assume !(0 == ~E_M~0); 2333#L641-1 assume !(0 == ~E_1~0); 2334#L646-1 assume !(0 == ~E_2~0); 2488#L651-1 assume !(0 == ~E_3~0); 2671#L656-1 assume !(0 == ~E_4~0); 2624#L661-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2625#L666-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2652#L304 assume 1 == ~m_pc~0; 2531#L305 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2268#L315 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2269#L316 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2210#L755 assume !(0 != activate_threads_~tmp~1); 2211#L755-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2168#L323 assume !(1 == ~t1_pc~0); 2169#L323-2 is_transmit1_triggered_~__retres1~1 := 0; 2233#L334 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2234#L335 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2600#L763 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2683#L763-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2236#L342 assume 1 == ~t2_pc~0; 2237#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2356#L353 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2357#L354 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2681#L771 assume !(0 != activate_threads_~tmp___1~0); 2620#L771-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2544#L361 assume !(1 == ~t3_pc~0); 2545#L361-2 is_transmit3_triggered_~__retres1~3 := 0; 2566#L372 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2398#L373 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2399#L779 assume !(0 != activate_threads_~tmp___2~0); 2251#L779-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2252#L380 assume 1 == ~t4_pc~0; 2310#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2311#L391 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2633#L392 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2574#L787 assume !(0 != activate_threads_~tmp___3~0); 2575#L787-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2313#L399 assume !(1 == ~t5_pc~0); 2314#L399-2 is_transmit5_triggered_~__retres1~5 := 0; 2444#L410 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2643#L411 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 2434#L795 assume !(0 != activate_threads_~tmp___4~0); 2435#L795-2 assume !(1 == ~M_E~0); 2631#L679-1 assume !(1 == ~T1_E~0); 2369#L684-1 assume !(1 == ~T2_E~0); 2370#L689-1 assume !(1 == ~T3_E~0); 2555#L694-1 assume !(1 == ~T4_E~0); 2553#L699-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2554#L704-1 assume !(1 == ~E_M~0); 2530#L709-1 assume !(1 == ~E_1~0); 2479#L714-1 assume !(1 == ~E_2~0); 2480#L719-1 assume !(1 == ~E_3~0); 2616#L724-1 assume !(1 == ~E_4~0); 2278#L729-1 assume !(1 == ~E_5~0); 2262#L940-1 [2021-11-09 09:42:00,324 INFO L793 eck$LassoCheckResult]: Loop: 2262#L940-1 assume !false; 2263#L941 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 2365#L586 assume !false; 2366#L507 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2675#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2550#L496 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2551#L497 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 2539#L511 assume !(0 != eval_~tmp~0); 2540#L601 start_simulation_~kernel_st~0 := 2; 2661#L419-1 start_simulation_~kernel_st~0 := 3; 2642#L611-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2548#L611-4 assume !(0 == ~T1_E~0); 2549#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2276#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2217#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2218#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2219#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2220#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2291#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2301#L651-3 assume !(0 == ~E_3~0); 2302#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2524#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2684#L666-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2439#L304-21 assume !(1 == ~m_pc~0); 2305#L304-23 is_master_triggered_~__retres1~0 := 0; 2306#L315-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2571#L316-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2500#L755-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2501#L755-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2525#L323-21 assume 1 == ~t1_pc~0; 2181#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2182#L334-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2601#L335-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2602#L763-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2651#L763-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2665#L342-21 assume 1 == ~t2_pc~0; 2205#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2206#L353-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2569#L354-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2621#L771-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2316#L771-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2317#L361-21 assume !(1 == ~t3_pc~0); 2676#L361-23 is_transmit3_triggered_~__retres1~3 := 0; 2677#L372-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2634#L373-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2475#L779-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2215#L779-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2216#L380-21 assume !(1 == ~t4_pc~0); 2283#L380-23 is_transmit4_triggered_~__retres1~4 := 0; 2284#L391-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2343#L392-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2606#L787-21 assume !(0 != activate_threads_~tmp___3~0); 2576#L787-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2420#L399-21 assume 1 == ~t5_pc~0; 2391#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2288#L410-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2585#L411-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 2663#L795-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2674#L795-23 assume 1 == ~M_E~0;~M_E~0 := 2; 2208#L679-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2209#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2156#L689-3 assume !(1 == ~T3_E~0); 2157#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2195#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2196#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2591#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2587#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2445#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2193#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2194#L729-3 assume !(1 == ~E_5~0); 2580#L734-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2228#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2229#L496-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2243#L497-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 2244#L959 assume !(0 == start_simulation_~tmp~3); 2564#L959-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2476#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2477#L496-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2641#L497-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 2630#L914 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2389#L921 stop_simulation_#res := stop_simulation_~__retres2~0; 2390#L922 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 2592#L972 assume !(0 != start_simulation_~tmp___0~1); 2262#L940-1 [2021-11-09 09:42:00,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:00,325 INFO L85 PathProgramCache]: Analyzing trace with hash 704899320, now seen corresponding path program 1 times [2021-11-09 09:42:00,326 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:00,326 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333682225] [2021-11-09 09:42:00,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:00,327 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:00,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:00,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:00,400 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:00,400 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [333682225] [2021-11-09 09:42:00,401 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [333682225] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:00,401 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:00,401 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:42:00,401 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [284725660] [2021-11-09 09:42:00,402 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:42:00,403 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:00,403 INFO L85 PathProgramCache]: Analyzing trace with hash -1067260745, now seen corresponding path program 1 times [2021-11-09 09:42:00,403 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:00,404 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1298632818] [2021-11-09 09:42:00,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:00,405 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:00,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:00,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:00,530 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:00,530 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1298632818] [2021-11-09 09:42:00,530 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1298632818] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:00,530 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:00,531 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:42:00,531 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1894608944] [2021-11-09 09:42:00,531 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:42:00,532 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:42:00,533 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:42:00,533 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:42:00,533 INFO L87 Difference]: Start difference. First operand 532 states and 807 transitions. cyclomatic complexity: 276 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:00,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:42:00,553 INFO L93 Difference]: Finished difference Result 532 states and 806 transitions. [2021-11-09 09:42:00,553 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:42:00,554 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 806 transitions. [2021-11-09 09:42:00,562 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-11-09 09:42:00,568 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 806 transitions. [2021-11-09 09:42:00,569 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2021-11-09 09:42:00,570 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2021-11-09 09:42:00,570 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 806 transitions. [2021-11-09 09:42:00,571 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:42:00,572 INFO L681 BuchiCegarLoop]: Abstraction has 532 states and 806 transitions. [2021-11-09 09:42:00,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 806 transitions. [2021-11-09 09:42:00,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2021-11-09 09:42:00,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 532 states, 532 states have (on average 1.5150375939849625) internal successors, (806), 531 states have internal predecessors, (806), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:00,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 806 transitions. [2021-11-09 09:42:00,587 INFO L704 BuchiCegarLoop]: Abstraction has 532 states and 806 transitions. [2021-11-09 09:42:00,587 INFO L587 BuchiCegarLoop]: Abstraction has 532 states and 806 transitions. [2021-11-09 09:42:00,587 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-09 09:42:00,587 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 806 transitions. [2021-11-09 09:42:00,592 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-11-09 09:42:00,593 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:42:00,593 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:42:00,598 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:00,598 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:00,600 INFO L791 eck$LassoCheckResult]: Stem: 3758#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 3750#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3636#L903 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3237#L419 assume 1 == ~m_i~0;~m_st~0 := 0; 3238#L426-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3503#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3504#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3481#L441-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3482#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3697#L451-1 assume !(0 == ~M_E~0); 3698#L611-1 assume !(0 == ~T1_E~0); 3710#L616-1 assume !(0 == ~T2_E~0); 3711#L621-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3360#L626-1 assume !(0 == ~T4_E~0); 3361#L631-1 assume !(0 == ~T5_E~0); 3544#L636-1 assume !(0 == ~E_M~0); 3404#L641-1 assume !(0 == ~E_1~0); 3405#L646-1 assume !(0 == ~E_2~0); 3559#L651-1 assume !(0 == ~E_3~0); 3742#L656-1 assume !(0 == ~E_4~0); 3695#L661-1 assume 0 == ~E_5~0;~E_5~0 := 1; 3696#L666-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3723#L304 assume 1 == ~m_pc~0; 3602#L305 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3339#L315 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3340#L316 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3283#L755 assume !(0 != activate_threads_~tmp~1); 3284#L755-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3239#L323 assume !(1 == ~t1_pc~0); 3240#L323-2 is_transmit1_triggered_~__retres1~1 := 0; 3304#L334 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3305#L335 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3671#L763 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3754#L763-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3309#L342 assume 1 == ~t2_pc~0; 3310#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3427#L353 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3428#L354 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3752#L771 assume !(0 != activate_threads_~tmp___1~0); 3691#L771-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3615#L361 assume !(1 == ~t3_pc~0); 3616#L361-2 is_transmit3_triggered_~__retres1~3 := 0; 3637#L372 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3469#L373 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3470#L779 assume !(0 != activate_threads_~tmp___2~0); 3322#L779-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3323#L380 assume 1 == ~t4_pc~0; 3381#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3382#L391 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3704#L392 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3645#L787 assume !(0 != activate_threads_~tmp___3~0); 3646#L787-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3384#L399 assume !(1 == ~t5_pc~0); 3385#L399-2 is_transmit5_triggered_~__retres1~5 := 0; 3515#L410 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3714#L411 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 3505#L795 assume !(0 != activate_threads_~tmp___4~0); 3506#L795-2 assume !(1 == ~M_E~0); 3702#L679-1 assume !(1 == ~T1_E~0); 3440#L684-1 assume !(1 == ~T2_E~0); 3441#L689-1 assume !(1 == ~T3_E~0); 3626#L694-1 assume !(1 == ~T4_E~0); 3624#L699-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3625#L704-1 assume !(1 == ~E_M~0); 3601#L709-1 assume !(1 == ~E_1~0); 3550#L714-1 assume !(1 == ~E_2~0); 3551#L719-1 assume !(1 == ~E_3~0); 3687#L724-1 assume !(1 == ~E_4~0); 3349#L729-1 assume !(1 == ~E_5~0); 3333#L940-1 [2021-11-09 09:42:00,602 INFO L793 eck$LassoCheckResult]: Loop: 3333#L940-1 assume !false; 3334#L941 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 3438#L586 assume !false; 3439#L507 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3746#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3621#L496 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3622#L497 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 3610#L511 assume !(0 != eval_~tmp~0); 3611#L601 start_simulation_~kernel_st~0 := 2; 3732#L419-1 start_simulation_~kernel_st~0 := 3; 3713#L611-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3619#L611-4 assume !(0 == ~T1_E~0); 3620#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3347#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3288#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3289#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3290#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3291#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3362#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3372#L651-3 assume !(0 == ~E_3~0); 3373#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3595#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3755#L666-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3510#L304-21 assume !(1 == ~m_pc~0); 3376#L304-23 is_master_triggered_~__retres1~0 := 0; 3377#L315-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3642#L316-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3571#L755-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3572#L755-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3596#L323-21 assume 1 == ~t1_pc~0; 3252#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3253#L334-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3672#L335-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3673#L763-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3722#L763-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3736#L342-21 assume 1 == ~t2_pc~0; 3276#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3277#L353-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3640#L354-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3692#L771-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3387#L771-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3388#L361-21 assume !(1 == ~t3_pc~0); 3747#L361-23 is_transmit3_triggered_~__retres1~3 := 0; 3748#L372-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3705#L373-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3543#L779-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3281#L779-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3282#L380-21 assume !(1 == ~t4_pc~0); 3352#L380-23 is_transmit4_triggered_~__retres1~4 := 0; 3353#L391-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3414#L392-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3677#L787-21 assume !(0 != activate_threads_~tmp___3~0); 3647#L787-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3491#L399-21 assume 1 == ~t5_pc~0; 3462#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3359#L410-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3656#L411-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 3734#L795-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3745#L795-23 assume 1 == ~M_E~0;~M_E~0 := 2; 3279#L679-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3280#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3227#L689-3 assume !(1 == ~T3_E~0); 3228#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3266#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3267#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3662#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3658#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3516#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3264#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3265#L729-3 assume !(1 == ~E_5~0); 3651#L734-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3299#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3300#L496-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3314#L497-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 3315#L959 assume !(0 == start_simulation_~tmp~3); 3635#L959-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3547#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3548#L496-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3712#L497-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 3701#L914 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3460#L921 stop_simulation_#res := stop_simulation_~__retres2~0; 3461#L922 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 3663#L972 assume !(0 != start_simulation_~tmp___0~1); 3333#L940-1 [2021-11-09 09:42:00,603 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:00,603 INFO L85 PathProgramCache]: Analyzing trace with hash 1122295926, now seen corresponding path program 1 times [2021-11-09 09:42:00,604 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:00,605 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981667508] [2021-11-09 09:42:00,606 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:00,606 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:00,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:00,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:00,698 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:00,698 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1981667508] [2021-11-09 09:42:00,699 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1981667508] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:00,699 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:00,699 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:42:00,699 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1442140708] [2021-11-09 09:42:00,700 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:42:00,701 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:00,701 INFO L85 PathProgramCache]: Analyzing trace with hash -1067260745, now seen corresponding path program 2 times [2021-11-09 09:42:00,701 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:00,702 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [471683879] [2021-11-09 09:42:00,702 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:00,702 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:00,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:00,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:00,763 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:00,763 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [471683879] [2021-11-09 09:42:00,763 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [471683879] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:00,763 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:00,764 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:42:00,764 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1596633251] [2021-11-09 09:42:00,764 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:42:00,765 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:42:00,766 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:42:00,766 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:42:00,766 INFO L87 Difference]: Start difference. First operand 532 states and 806 transitions. cyclomatic complexity: 275 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:00,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:42:00,780 INFO L93 Difference]: Finished difference Result 532 states and 805 transitions. [2021-11-09 09:42:00,781 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:42:00,781 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 805 transitions. [2021-11-09 09:42:00,805 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-11-09 09:42:00,812 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 805 transitions. [2021-11-09 09:42:00,812 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2021-11-09 09:42:00,813 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2021-11-09 09:42:00,813 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 805 transitions. [2021-11-09 09:42:00,815 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:42:00,815 INFO L681 BuchiCegarLoop]: Abstraction has 532 states and 805 transitions. [2021-11-09 09:42:00,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 805 transitions. [2021-11-09 09:42:00,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2021-11-09 09:42:00,827 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 532 states, 532 states have (on average 1.513157894736842) internal successors, (805), 531 states have internal predecessors, (805), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:00,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 805 transitions. [2021-11-09 09:42:00,830 INFO L704 BuchiCegarLoop]: Abstraction has 532 states and 805 transitions. [2021-11-09 09:42:00,831 INFO L587 BuchiCegarLoop]: Abstraction has 532 states and 805 transitions. [2021-11-09 09:42:00,831 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-09 09:42:00,831 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 805 transitions. [2021-11-09 09:42:00,836 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-11-09 09:42:00,837 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:42:00,837 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:42:00,844 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:00,845 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:00,847 INFO L791 eck$LassoCheckResult]: Stem: 4829#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 4821#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4707#L903 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4308#L419 assume 1 == ~m_i~0;~m_st~0 := 0; 4309#L426-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4574#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4575#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4552#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4553#L446-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4768#L451-1 assume !(0 == ~M_E~0); 4769#L611-1 assume !(0 == ~T1_E~0); 4781#L616-1 assume !(0 == ~T2_E~0); 4782#L621-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4431#L626-1 assume !(0 == ~T4_E~0); 4432#L631-1 assume !(0 == ~T5_E~0); 4617#L636-1 assume !(0 == ~E_M~0); 4475#L641-1 assume !(0 == ~E_1~0); 4476#L646-1 assume !(0 == ~E_2~0); 4630#L651-1 assume !(0 == ~E_3~0); 4813#L656-1 assume !(0 == ~E_4~0); 4766#L661-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4767#L666-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4794#L304 assume 1 == ~m_pc~0; 4673#L305 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4410#L315 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4411#L316 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4354#L755 assume !(0 != activate_threads_~tmp~1); 4355#L755-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4310#L323 assume !(1 == ~t1_pc~0); 4311#L323-2 is_transmit1_triggered_~__retres1~1 := 0; 4375#L334 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4376#L335 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4742#L763 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4825#L763-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4382#L342 assume 1 == ~t2_pc~0; 4383#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4498#L353 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4499#L354 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4823#L771 assume !(0 != activate_threads_~tmp___1~0); 4762#L771-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4686#L361 assume !(1 == ~t3_pc~0); 4687#L361-2 is_transmit3_triggered_~__retres1~3 := 0; 4708#L372 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4540#L373 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4541#L779 assume !(0 != activate_threads_~tmp___2~0); 4393#L779-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4394#L380 assume 1 == ~t4_pc~0; 4452#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4453#L391 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4775#L392 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4716#L787 assume !(0 != activate_threads_~tmp___3~0); 4717#L787-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4455#L399 assume !(1 == ~t5_pc~0); 4456#L399-2 is_transmit5_triggered_~__retres1~5 := 0; 4586#L410 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4785#L411 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 4576#L795 assume !(0 != activate_threads_~tmp___4~0); 4577#L795-2 assume !(1 == ~M_E~0); 4773#L679-1 assume !(1 == ~T1_E~0); 4511#L684-1 assume !(1 == ~T2_E~0); 4512#L689-1 assume !(1 == ~T3_E~0); 4697#L694-1 assume !(1 == ~T4_E~0); 4695#L699-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4696#L704-1 assume !(1 == ~E_M~0); 4672#L709-1 assume !(1 == ~E_1~0); 4621#L714-1 assume !(1 == ~E_2~0); 4622#L719-1 assume !(1 == ~E_3~0); 4758#L724-1 assume !(1 == ~E_4~0); 4420#L729-1 assume !(1 == ~E_5~0); 4406#L940-1 [2021-11-09 09:42:00,847 INFO L793 eck$LassoCheckResult]: Loop: 4406#L940-1 assume !false; 4407#L941 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 4509#L586 assume !false; 4510#L507 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4817#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4692#L496 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4693#L497 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 4681#L511 assume !(0 != eval_~tmp~0); 4682#L601 start_simulation_~kernel_st~0 := 2; 4803#L419-1 start_simulation_~kernel_st~0 := 3; 4784#L611-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4690#L611-4 assume !(0 == ~T1_E~0); 4691#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4419#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4359#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4360#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4361#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4362#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4433#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4443#L651-3 assume !(0 == ~E_3~0); 4444#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4666#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4826#L666-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4581#L304-21 assume 1 == ~m_pc~0; 4582#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 4448#L315-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4714#L316-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4642#L755-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4643#L755-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4667#L323-21 assume 1 == ~t1_pc~0; 4323#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4324#L334-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4743#L335-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4744#L763-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4793#L763-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4807#L342-21 assume 1 == ~t2_pc~0; 4347#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4348#L353-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4711#L354-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4763#L771-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4458#L771-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4459#L361-21 assume !(1 == ~t3_pc~0); 4818#L361-23 is_transmit3_triggered_~__retres1~3 := 0; 4819#L372-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4776#L373-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 4616#L779-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4352#L779-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4353#L380-21 assume !(1 == ~t4_pc~0); 4423#L380-23 is_transmit4_triggered_~__retres1~4 := 0; 4424#L391-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4485#L392-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 4748#L787-21 assume !(0 != activate_threads_~tmp___3~0); 4718#L787-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4562#L399-21 assume 1 == ~t5_pc~0; 4533#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4430#L410-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4727#L411-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 4805#L795-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4816#L795-23 assume 1 == ~M_E~0;~M_E~0 := 2; 4350#L679-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4351#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4298#L689-3 assume !(1 == ~T3_E~0); 4299#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4337#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4338#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4733#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4729#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4588#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4335#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4336#L729-3 assume !(1 == ~E_5~0); 4722#L734-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4370#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4371#L496-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4385#L497-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 4386#L959 assume !(0 == start_simulation_~tmp~3); 4706#L959-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4618#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4619#L496-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4783#L497-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 4772#L914 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4531#L921 stop_simulation_#res := stop_simulation_~__retres2~0; 4532#L922 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 4734#L972 assume !(0 != start_simulation_~tmp___0~1); 4406#L940-1 [2021-11-09 09:42:00,854 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:00,854 INFO L85 PathProgramCache]: Analyzing trace with hash 443023672, now seen corresponding path program 1 times [2021-11-09 09:42:00,854 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:00,855 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [665226516] [2021-11-09 09:42:00,855 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:00,855 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:00,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:00,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:00,909 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:00,909 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [665226516] [2021-11-09 09:42:00,910 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [665226516] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:00,910 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:00,910 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:42:00,911 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2025467421] [2021-11-09 09:42:00,911 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:42:00,912 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:00,914 INFO L85 PathProgramCache]: Analyzing trace with hash 839223448, now seen corresponding path program 1 times [2021-11-09 09:42:00,915 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:00,915 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [717838720] [2021-11-09 09:42:00,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:00,916 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:00,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:00,990 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:00,990 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:00,990 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [717838720] [2021-11-09 09:42:00,991 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [717838720] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:00,992 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:00,993 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:42:00,993 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [987039642] [2021-11-09 09:42:00,994 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:42:00,994 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:42:00,995 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:42:00,995 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:42:00,995 INFO L87 Difference]: Start difference. First operand 532 states and 805 transitions. cyclomatic complexity: 274 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:01,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:42:01,035 INFO L93 Difference]: Finished difference Result 532 states and 804 transitions. [2021-11-09 09:42:01,035 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:42:01,038 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 804 transitions. [2021-11-09 09:42:01,045 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-11-09 09:42:01,052 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 804 transitions. [2021-11-09 09:42:01,052 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2021-11-09 09:42:01,053 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2021-11-09 09:42:01,053 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 804 transitions. [2021-11-09 09:42:01,054 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:42:01,054 INFO L681 BuchiCegarLoop]: Abstraction has 532 states and 804 transitions. [2021-11-09 09:42:01,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 804 transitions. [2021-11-09 09:42:01,065 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2021-11-09 09:42:01,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 532 states, 532 states have (on average 1.5112781954887218) internal successors, (804), 531 states have internal predecessors, (804), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:01,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 804 transitions. [2021-11-09 09:42:01,071 INFO L704 BuchiCegarLoop]: Abstraction has 532 states and 804 transitions. [2021-11-09 09:42:01,071 INFO L587 BuchiCegarLoop]: Abstraction has 532 states and 804 transitions. [2021-11-09 09:42:01,071 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-09 09:42:01,072 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 804 transitions. [2021-11-09 09:42:01,077 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-11-09 09:42:01,077 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:42:01,078 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:42:01,079 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:01,080 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:01,080 INFO L791 eck$LassoCheckResult]: Stem: 5900#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 5892#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5778#L903 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5379#L419 assume 1 == ~m_i~0;~m_st~0 := 0; 5380#L426-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5645#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5646#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5623#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5624#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5839#L451-1 assume !(0 == ~M_E~0); 5840#L611-1 assume !(0 == ~T1_E~0); 5852#L616-1 assume !(0 == ~T2_E~0); 5853#L621-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5502#L626-1 assume !(0 == ~T4_E~0); 5503#L631-1 assume !(0 == ~T5_E~0); 5688#L636-1 assume !(0 == ~E_M~0); 5546#L641-1 assume !(0 == ~E_1~0); 5547#L646-1 assume !(0 == ~E_2~0); 5701#L651-1 assume !(0 == ~E_3~0); 5884#L656-1 assume !(0 == ~E_4~0); 5837#L661-1 assume 0 == ~E_5~0;~E_5~0 := 1; 5838#L666-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5865#L304 assume 1 == ~m_pc~0; 5744#L305 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5481#L315 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5482#L316 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5425#L755 assume !(0 != activate_threads_~tmp~1); 5426#L755-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5381#L323 assume !(1 == ~t1_pc~0); 5382#L323-2 is_transmit1_triggered_~__retres1~1 := 0; 5446#L334 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5447#L335 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5815#L763 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5896#L763-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5453#L342 assume 1 == ~t2_pc~0; 5454#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5569#L353 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5570#L354 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5894#L771 assume !(0 != activate_threads_~tmp___1~0); 5833#L771-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5757#L361 assume !(1 == ~t3_pc~0); 5758#L361-2 is_transmit3_triggered_~__retres1~3 := 0; 5779#L372 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5611#L373 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5612#L779 assume !(0 != activate_threads_~tmp___2~0); 5464#L779-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5465#L380 assume 1 == ~t4_pc~0; 5523#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5524#L391 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5846#L392 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5787#L787 assume !(0 != activate_threads_~tmp___3~0); 5788#L787-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5526#L399 assume !(1 == ~t5_pc~0); 5527#L399-2 is_transmit5_triggered_~__retres1~5 := 0; 5657#L410 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5856#L411 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 5647#L795 assume !(0 != activate_threads_~tmp___4~0); 5648#L795-2 assume !(1 == ~M_E~0); 5844#L679-1 assume !(1 == ~T1_E~0); 5582#L684-1 assume !(1 == ~T2_E~0); 5583#L689-1 assume !(1 == ~T3_E~0); 5768#L694-1 assume !(1 == ~T4_E~0); 5766#L699-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5767#L704-1 assume !(1 == ~E_M~0); 5743#L709-1 assume !(1 == ~E_1~0); 5692#L714-1 assume !(1 == ~E_2~0); 5693#L719-1 assume !(1 == ~E_3~0); 5829#L724-1 assume !(1 == ~E_4~0); 5491#L729-1 assume !(1 == ~E_5~0); 5477#L940-1 [2021-11-09 09:42:01,081 INFO L793 eck$LassoCheckResult]: Loop: 5477#L940-1 assume !false; 5478#L941 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 5580#L586 assume !false; 5581#L507 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5888#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5763#L496 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5764#L497 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 5752#L511 assume !(0 != eval_~tmp~0); 5753#L601 start_simulation_~kernel_st~0 := 2; 5874#L419-1 start_simulation_~kernel_st~0 := 3; 5855#L611-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5761#L611-4 assume !(0 == ~T1_E~0); 5762#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5490#L621-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5430#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5431#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5432#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5433#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5504#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5514#L651-3 assume !(0 == ~E_3~0); 5515#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5737#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5897#L666-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5652#L304-21 assume 1 == ~m_pc~0; 5653#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5519#L315-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5785#L316-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5713#L755-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5714#L755-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5738#L323-21 assume 1 == ~t1_pc~0; 5394#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5395#L334-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5813#L335-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5814#L763-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5864#L763-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5878#L342-21 assume 1 == ~t2_pc~0; 5418#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5419#L353-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5782#L354-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5834#L771-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5529#L771-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5530#L361-21 assume !(1 == ~t3_pc~0); 5889#L361-23 is_transmit3_triggered_~__retres1~3 := 0; 5890#L372-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5847#L373-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5687#L779-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5423#L779-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5424#L380-21 assume !(1 == ~t4_pc~0); 5494#L380-23 is_transmit4_triggered_~__retres1~4 := 0; 5495#L391-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5556#L392-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5819#L787-21 assume !(0 != activate_threads_~tmp___3~0); 5789#L787-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5633#L399-21 assume 1 == ~t5_pc~0; 5604#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5501#L410-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5798#L411-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 5876#L795-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5887#L795-23 assume 1 == ~M_E~0;~M_E~0 := 2; 5421#L679-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5422#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5369#L689-3 assume !(1 == ~T3_E~0); 5370#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5408#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5409#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5804#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5800#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5659#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5406#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5407#L729-3 assume !(1 == ~E_5~0); 5793#L734-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5441#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5442#L496-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5456#L497-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 5457#L959 assume !(0 == start_simulation_~tmp~3); 5777#L959-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5689#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5690#L496-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5854#L497-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 5843#L914 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5602#L921 stop_simulation_#res := stop_simulation_~__retres2~0; 5603#L922 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 5805#L972 assume !(0 != start_simulation_~tmp___0~1); 5477#L940-1 [2021-11-09 09:42:01,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:01,081 INFO L85 PathProgramCache]: Analyzing trace with hash -1518550986, now seen corresponding path program 1 times [2021-11-09 09:42:01,082 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:01,083 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [663792730] [2021-11-09 09:42:01,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:01,083 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:01,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:01,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:01,156 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:01,157 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [663792730] [2021-11-09 09:42:01,157 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [663792730] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:01,157 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:01,158 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-09 09:42:01,158 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [312907669] [2021-11-09 09:42:01,159 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:42:01,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:01,159 INFO L85 PathProgramCache]: Analyzing trace with hash 839223448, now seen corresponding path program 2 times [2021-11-09 09:42:01,160 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:01,160 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [605346409] [2021-11-09 09:42:01,160 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:01,161 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:01,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:01,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:01,208 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:01,208 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [605346409] [2021-11-09 09:42:01,208 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [605346409] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:01,208 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:01,209 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:42:01,209 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1777524684] [2021-11-09 09:42:01,209 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:42:01,210 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:42:01,210 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:42:01,210 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:42:01,211 INFO L87 Difference]: Start difference. First operand 532 states and 804 transitions. cyclomatic complexity: 273 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 2 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:01,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:42:01,240 INFO L93 Difference]: Finished difference Result 532 states and 799 transitions. [2021-11-09 09:42:01,241 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:42:01,242 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 799 transitions. [2021-11-09 09:42:01,248 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-11-09 09:42:01,254 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 799 transitions. [2021-11-09 09:42:01,257 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2021-11-09 09:42:01,258 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2021-11-09 09:42:01,258 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 799 transitions. [2021-11-09 09:42:01,259 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:42:01,259 INFO L681 BuchiCegarLoop]: Abstraction has 532 states and 799 transitions. [2021-11-09 09:42:01,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 799 transitions. [2021-11-09 09:42:01,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2021-11-09 09:42:01,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 532 states, 532 states have (on average 1.5018796992481203) internal successors, (799), 531 states have internal predecessors, (799), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:01,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 799 transitions. [2021-11-09 09:42:01,273 INFO L704 BuchiCegarLoop]: Abstraction has 532 states and 799 transitions. [2021-11-09 09:42:01,273 INFO L587 BuchiCegarLoop]: Abstraction has 532 states and 799 transitions. [2021-11-09 09:42:01,273 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-09 09:42:01,274 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 799 transitions. [2021-11-09 09:42:01,278 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-11-09 09:42:01,279 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:42:01,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:42:01,281 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:01,281 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:01,281 INFO L791 eck$LassoCheckResult]: Stem: 6971#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 6963#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6849#L903 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6450#L419 assume 1 == ~m_i~0;~m_st~0 := 0; 6451#L426-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6716#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6717#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6694#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6695#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6910#L451-1 assume !(0 == ~M_E~0); 6911#L611-1 assume !(0 == ~T1_E~0); 6923#L616-1 assume !(0 == ~T2_E~0); 6924#L621-1 assume !(0 == ~T3_E~0); 6573#L626-1 assume !(0 == ~T4_E~0); 6574#L631-1 assume !(0 == ~T5_E~0); 6759#L636-1 assume !(0 == ~E_M~0); 6617#L641-1 assume !(0 == ~E_1~0); 6618#L646-1 assume !(0 == ~E_2~0); 6772#L651-1 assume !(0 == ~E_3~0); 6955#L656-1 assume !(0 == ~E_4~0); 6908#L661-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6909#L666-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6936#L304 assume 1 == ~m_pc~0; 6815#L305 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 6552#L315 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6553#L316 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6496#L755 assume !(0 != activate_threads_~tmp~1); 6497#L755-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6452#L323 assume !(1 == ~t1_pc~0); 6453#L323-2 is_transmit1_triggered_~__retres1~1 := 0; 6517#L334 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6518#L335 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6886#L763 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6967#L763-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6524#L342 assume 1 == ~t2_pc~0; 6525#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6640#L353 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6641#L354 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6965#L771 assume !(0 != activate_threads_~tmp___1~0); 6904#L771-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6828#L361 assume !(1 == ~t3_pc~0); 6829#L361-2 is_transmit3_triggered_~__retres1~3 := 0; 6850#L372 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6682#L373 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 6683#L779 assume !(0 != activate_threads_~tmp___2~0); 6535#L779-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6536#L380 assume 1 == ~t4_pc~0; 6594#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6595#L391 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6917#L392 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6858#L787 assume !(0 != activate_threads_~tmp___3~0); 6859#L787-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6597#L399 assume !(1 == ~t5_pc~0); 6598#L399-2 is_transmit5_triggered_~__retres1~5 := 0; 6728#L410 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6927#L411 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 6718#L795 assume !(0 != activate_threads_~tmp___4~0); 6719#L795-2 assume !(1 == ~M_E~0); 6915#L679-1 assume !(1 == ~T1_E~0); 6653#L684-1 assume !(1 == ~T2_E~0); 6654#L689-1 assume !(1 == ~T3_E~0); 6839#L694-1 assume !(1 == ~T4_E~0); 6837#L699-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6838#L704-1 assume !(1 == ~E_M~0); 6814#L709-1 assume !(1 == ~E_1~0); 6763#L714-1 assume !(1 == ~E_2~0); 6764#L719-1 assume !(1 == ~E_3~0); 6900#L724-1 assume !(1 == ~E_4~0); 6562#L729-1 assume !(1 == ~E_5~0); 6548#L940-1 [2021-11-09 09:42:01,282 INFO L793 eck$LassoCheckResult]: Loop: 6548#L940-1 assume !false; 6549#L941 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 6651#L586 assume !false; 6652#L507 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6959#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6834#L496 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6835#L497 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 6823#L511 assume !(0 != eval_~tmp~0); 6824#L601 start_simulation_~kernel_st~0 := 2; 6945#L419-1 start_simulation_~kernel_st~0 := 3; 6926#L611-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6832#L611-4 assume !(0 == ~T1_E~0); 6833#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6561#L621-3 assume !(0 == ~T3_E~0); 6501#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6502#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6503#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6504#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6575#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6585#L651-3 assume !(0 == ~E_3~0); 6586#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6808#L661-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6968#L666-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6723#L304-21 assume 1 == ~m_pc~0; 6724#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 6590#L315-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6856#L316-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6784#L755-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6785#L755-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6809#L323-21 assume 1 == ~t1_pc~0; 6465#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6466#L334-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6884#L335-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6885#L763-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6935#L763-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6949#L342-21 assume 1 == ~t2_pc~0; 6489#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6490#L353-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6853#L354-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6905#L771-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6600#L771-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6601#L361-21 assume !(1 == ~t3_pc~0); 6960#L361-23 is_transmit3_triggered_~__retres1~3 := 0; 6961#L372-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6918#L373-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 6758#L779-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6494#L779-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6495#L380-21 assume !(1 == ~t4_pc~0); 6567#L380-23 is_transmit4_triggered_~__retres1~4 := 0; 6568#L391-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6627#L392-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6890#L787-21 assume !(0 != activate_threads_~tmp___3~0); 6860#L787-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6704#L399-21 assume 1 == ~t5_pc~0; 6675#L400-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6572#L410-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6869#L411-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 6947#L795-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 6958#L795-23 assume 1 == ~M_E~0;~M_E~0 := 2; 6492#L679-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6493#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6440#L689-3 assume !(1 == ~T3_E~0); 6441#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6479#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6480#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6875#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6871#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6730#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6477#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6478#L729-3 assume !(1 == ~E_5~0); 6864#L734-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6512#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6513#L496-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6527#L497-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 6528#L959 assume !(0 == start_simulation_~tmp~3); 6848#L959-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6760#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6761#L496-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6925#L497-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 6914#L914 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6673#L921 stop_simulation_#res := stop_simulation_~__retres2~0; 6674#L922 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 6876#L972 assume !(0 != start_simulation_~tmp___0~1); 6548#L940-1 [2021-11-09 09:42:01,282 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:01,283 INFO L85 PathProgramCache]: Analyzing trace with hash -257633736, now seen corresponding path program 1 times [2021-11-09 09:42:01,283 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:01,283 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1869081681] [2021-11-09 09:42:01,284 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:01,284 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:01,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:01,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:01,327 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:01,328 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1869081681] [2021-11-09 09:42:01,328 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1869081681] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:01,328 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:01,329 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-09 09:42:01,329 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1400806943] [2021-11-09 09:42:01,330 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:42:01,330 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:01,330 INFO L85 PathProgramCache]: Analyzing trace with hash -1547286058, now seen corresponding path program 1 times [2021-11-09 09:42:01,331 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:01,331 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1087623096] [2021-11-09 09:42:01,331 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:01,332 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:01,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:01,382 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:01,382 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:01,382 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1087623096] [2021-11-09 09:42:01,383 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1087623096] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:01,383 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:01,383 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:42:01,384 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2065700481] [2021-11-09 09:42:01,384 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:42:01,384 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:42:01,385 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:42:01,385 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:42:01,386 INFO L87 Difference]: Start difference. First operand 532 states and 799 transitions. cyclomatic complexity: 268 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 2 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:01,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:42:01,442 INFO L93 Difference]: Finished difference Result 532 states and 786 transitions. [2021-11-09 09:42:01,443 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:42:01,443 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 532 states and 786 transitions. [2021-11-09 09:42:01,450 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-11-09 09:42:01,456 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 532 states to 532 states and 786 transitions. [2021-11-09 09:42:01,456 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2021-11-09 09:42:01,457 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2021-11-09 09:42:01,457 INFO L73 IsDeterministic]: Start isDeterministic. Operand 532 states and 786 transitions. [2021-11-09 09:42:01,459 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:42:01,459 INFO L681 BuchiCegarLoop]: Abstraction has 532 states and 786 transitions. [2021-11-09 09:42:01,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 532 states and 786 transitions. [2021-11-09 09:42:01,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 532 to 532. [2021-11-09 09:42:01,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 532 states, 532 states have (on average 1.4774436090225564) internal successors, (786), 531 states have internal predecessors, (786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:01,474 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 532 states to 532 states and 786 transitions. [2021-11-09 09:42:01,475 INFO L704 BuchiCegarLoop]: Abstraction has 532 states and 786 transitions. [2021-11-09 09:42:01,475 INFO L587 BuchiCegarLoop]: Abstraction has 532 states and 786 transitions. [2021-11-09 09:42:01,475 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-09 09:42:01,475 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 532 states and 786 transitions. [2021-11-09 09:42:01,480 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 457 [2021-11-09 09:42:01,480 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:42:01,480 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:42:01,486 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:01,487 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:01,487 INFO L791 eck$LassoCheckResult]: Stem: 8042#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 8034#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 7917#L903 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7523#L419 assume 1 == ~m_i~0;~m_st~0 := 0; 7524#L426-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7785#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7786#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7763#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7764#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7981#L451-1 assume !(0 == ~M_E~0); 7982#L611-1 assume !(0 == ~T1_E~0); 7994#L616-1 assume !(0 == ~T2_E~0); 7995#L621-1 assume !(0 == ~T3_E~0); 7644#L626-1 assume !(0 == ~T4_E~0); 7645#L631-1 assume !(0 == ~T5_E~0); 7828#L636-1 assume !(0 == ~E_M~0); 7687#L641-1 assume !(0 == ~E_1~0); 7688#L646-1 assume !(0 == ~E_2~0); 7841#L651-1 assume !(0 == ~E_3~0); 8026#L656-1 assume !(0 == ~E_4~0); 7979#L661-1 assume !(0 == ~E_5~0); 7980#L666-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8007#L304 assume 1 == ~m_pc~0; 7884#L305 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7623#L315 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7624#L316 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7567#L755 assume !(0 != activate_threads_~tmp~1); 7568#L755-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7525#L323 assume !(1 == ~t1_pc~0); 7526#L323-2 is_transmit1_triggered_~__retres1~1 := 0; 7588#L334 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7589#L335 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7956#L763 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8038#L763-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7595#L342 assume 1 == ~t2_pc~0; 7596#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7710#L353 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7711#L354 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 8036#L771 assume !(0 != activate_threads_~tmp___1~0); 7975#L771-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7896#L361 assume !(1 == ~t3_pc~0); 7897#L361-2 is_transmit3_triggered_~__retres1~3 := 0; 7918#L372 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7751#L373 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7752#L779 assume !(0 != activate_threads_~tmp___2~0); 7606#L779-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7607#L380 assume 1 == ~t4_pc~0; 7665#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7666#L391 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7988#L392 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7926#L787 assume !(0 != activate_threads_~tmp___3~0); 7927#L787-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7668#L399 assume !(1 == ~t5_pc~0); 7669#L399-2 is_transmit5_triggered_~__retres1~5 := 0; 7797#L410 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7998#L411 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 7787#L795 assume !(0 != activate_threads_~tmp___4~0); 7788#L795-2 assume !(1 == ~M_E~0); 7986#L679-1 assume !(1 == ~T1_E~0); 7723#L684-1 assume !(1 == ~T2_E~0); 7724#L689-1 assume !(1 == ~T3_E~0); 7907#L694-1 assume !(1 == ~T4_E~0); 7905#L699-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7906#L704-1 assume !(1 == ~E_M~0); 7883#L709-1 assume !(1 == ~E_1~0); 7833#L714-1 assume !(1 == ~E_2~0); 7834#L719-1 assume !(1 == ~E_3~0); 7971#L724-1 assume !(1 == ~E_4~0); 7633#L729-1 assume !(1 == ~E_5~0); 7619#L940-1 [2021-11-09 09:42:01,488 INFO L793 eck$LassoCheckResult]: Loop: 7619#L940-1 assume !false; 7620#L941 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 7721#L586 assume !false; 7722#L507 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 8030#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7902#L496 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7903#L497 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 7892#L511 assume !(0 != eval_~tmp~0); 7893#L601 start_simulation_~kernel_st~0 := 2; 8016#L419-1 start_simulation_~kernel_st~0 := 3; 7997#L611-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7900#L611-4 assume !(0 == ~T1_E~0); 7901#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7632#L621-3 assume !(0 == ~T3_E~0); 7572#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7573#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7574#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7575#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7646#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7656#L651-3 assume !(0 == ~E_3~0); 7657#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7877#L661-3 assume !(0 == ~E_5~0); 8039#L666-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7792#L304-21 assume 1 == ~m_pc~0; 7793#L305-7 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7661#L315-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7923#L316-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7853#L755-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7854#L755-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7878#L323-21 assume 1 == ~t1_pc~0; 7536#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7537#L334-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7954#L335-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7955#L763-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8006#L763-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8020#L342-21 assume 1 == ~t2_pc~0; 7560#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7561#L353-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7921#L354-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7976#L771-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7671#L771-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7672#L361-21 assume 1 == ~t3_pc~0; 8035#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8032#L372-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7989#L373-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 7827#L779-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7565#L779-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7566#L380-21 assume !(1 == ~t4_pc~0); 7638#L380-23 is_transmit4_triggered_~__retres1~4 := 0; 7639#L391-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7697#L392-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 7961#L787-21 assume !(0 != activate_threads_~tmp___3~0); 7928#L787-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7773#L399-21 assume !(1 == ~t5_pc~0); 7642#L399-23 is_transmit5_triggered_~__retres1~5 := 0; 7643#L410-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7937#L411-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 8018#L795-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 8029#L795-23 assume 1 == ~M_E~0;~M_E~0 := 2; 7563#L679-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7564#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7511#L689-3 assume !(1 == ~T3_E~0); 7512#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7550#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7551#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7944#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7939#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7799#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7548#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7549#L729-3 assume !(1 == ~E_5~0); 7932#L734-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7585#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7586#L496-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7600#L497-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 7601#L959 assume !(0 == start_simulation_~tmp~3); 7916#L959-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7830#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 7831#L496-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 7996#L497-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 7985#L914 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7742#L921 stop_simulation_#res := stop_simulation_~__retres2~0; 7743#L922 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 7945#L972 assume !(0 != start_simulation_~tmp___0~1); 7619#L940-1 [2021-11-09 09:42:01,488 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:01,489 INFO L85 PathProgramCache]: Analyzing trace with hash -273152454, now seen corresponding path program 1 times [2021-11-09 09:42:01,489 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:01,489 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1457607019] [2021-11-09 09:42:01,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:01,490 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:01,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:01,565 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:01,566 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:01,566 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1457607019] [2021-11-09 09:42:01,566 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1457607019] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:01,567 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:01,567 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-09 09:42:01,567 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [338580013] [2021-11-09 09:42:01,568 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:42:01,569 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:01,569 INFO L85 PathProgramCache]: Analyzing trace with hash 1230356372, now seen corresponding path program 1 times [2021-11-09 09:42:01,569 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:01,570 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2006452668] [2021-11-09 09:42:01,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:01,570 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:01,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:01,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:01,630 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:01,632 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2006452668] [2021-11-09 09:42:01,640 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2006452668] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:01,641 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:01,642 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-09 09:42:01,642 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1531464869] [2021-11-09 09:42:01,643 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:42:01,643 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:42:01,644 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:42:01,644 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:42:01,645 INFO L87 Difference]: Start difference. First operand 532 states and 786 transitions. cyclomatic complexity: 255 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 2 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:01,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:42:01,736 INFO L93 Difference]: Finished difference Result 973 states and 1419 transitions. [2021-11-09 09:42:01,736 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:42:01,737 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 973 states and 1419 transitions. [2021-11-09 09:42:01,751 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 898 [2021-11-09 09:42:01,765 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 973 states to 973 states and 1419 transitions. [2021-11-09 09:42:01,765 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 973 [2021-11-09 09:42:01,767 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 973 [2021-11-09 09:42:01,767 INFO L73 IsDeterministic]: Start isDeterministic. Operand 973 states and 1419 transitions. [2021-11-09 09:42:01,769 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:42:01,769 INFO L681 BuchiCegarLoop]: Abstraction has 973 states and 1419 transitions. [2021-11-09 09:42:01,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 973 states and 1419 transitions. [2021-11-09 09:42:01,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 973 to 933. [2021-11-09 09:42:01,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4619506966773848) internal successors, (1364), 932 states have internal predecessors, (1364), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:01,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1364 transitions. [2021-11-09 09:42:01,806 INFO L704 BuchiCegarLoop]: Abstraction has 933 states and 1364 transitions. [2021-11-09 09:42:01,806 INFO L587 BuchiCegarLoop]: Abstraction has 933 states and 1364 transitions. [2021-11-09 09:42:01,806 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-09 09:42:01,807 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1364 transitions. [2021-11-09 09:42:01,816 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 858 [2021-11-09 09:42:01,816 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:42:01,817 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:42:01,818 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:01,819 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:01,819 INFO L791 eck$LassoCheckResult]: Stem: 9576#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 9562#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9432#L903 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 9037#L419 assume 1 == ~m_i~0;~m_st~0 := 0; 9038#L426-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9300#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9301#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9277#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9278#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9500#L451-1 assume !(0 == ~M_E~0); 9501#L611-1 assume !(0 == ~T1_E~0); 9513#L616-1 assume !(0 == ~T2_E~0); 9514#L621-1 assume !(0 == ~T3_E~0); 9162#L626-1 assume !(0 == ~T4_E~0); 9163#L631-1 assume !(0 == ~T5_E~0); 9343#L636-1 assume !(0 == ~E_M~0); 9202#L641-1 assume !(0 == ~E_1~0); 9203#L646-1 assume !(0 == ~E_2~0); 9356#L651-1 assume !(0 == ~E_3~0); 9551#L656-1 assume !(0 == ~E_4~0); 9498#L661-1 assume !(0 == ~E_5~0); 9499#L666-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9530#L304 assume !(1 == ~m_pc~0); 9222#L304-2 is_master_triggered_~__retres1~0 := 0; 9137#L315 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9138#L316 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9084#L755 assume !(0 != activate_threads_~tmp~1); 9085#L755-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9039#L323 assume !(1 == ~t1_pc~0); 9040#L323-2 is_transmit1_triggered_~__retres1~1 := 0; 9102#L334 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9103#L335 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9475#L763 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9566#L763-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9109#L342 assume 1 == ~t2_pc~0; 9110#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9224#L353 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9225#L354 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9564#L771 assume !(0 != activate_threads_~tmp___1~0); 9494#L771-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9412#L361 assume !(1 == ~t3_pc~0); 9413#L361-2 is_transmit3_triggered_~__retres1~3 := 0; 9433#L372 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9265#L373 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 9266#L779 assume !(0 != activate_threads_~tmp___2~0); 9120#L779-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9121#L380 assume 1 == ~t4_pc~0; 9179#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9180#L391 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9507#L392 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9441#L787 assume !(0 != activate_threads_~tmp___3~0); 9442#L787-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9182#L399 assume !(1 == ~t5_pc~0); 9183#L399-2 is_transmit5_triggered_~__retres1~5 := 0; 9311#L410 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9517#L411 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 9302#L795 assume !(0 != activate_threads_~tmp___4~0); 9303#L795-2 assume !(1 == ~M_E~0); 9505#L679-1 assume !(1 == ~T1_E~0); 9237#L684-1 assume !(1 == ~T2_E~0); 9238#L689-1 assume !(1 == ~T3_E~0); 9423#L694-1 assume !(1 == ~T4_E~0); 9421#L699-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9422#L704-1 assume !(1 == ~E_M~0); 9400#L709-1 assume !(1 == ~E_1~0); 9348#L714-1 assume !(1 == ~E_2~0); 9349#L719-1 assume !(1 == ~E_3~0); 9490#L724-1 assume !(1 == ~E_4~0); 9147#L729-1 assume !(1 == ~E_5~0); 9133#L940-1 [2021-11-09 09:42:01,820 INFO L793 eck$LassoCheckResult]: Loop: 9133#L940-1 assume !false; 9134#L941 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 9235#L586 assume !false; 9236#L507 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9557#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9418#L496 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9419#L497 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 9408#L511 assume !(0 != eval_~tmp~0); 9409#L601 start_simulation_~kernel_st~0 := 2; 9539#L419-1 start_simulation_~kernel_st~0 := 3; 9516#L611-2 assume 0 == ~M_E~0;~M_E~0 := 1; 9416#L611-4 assume !(0 == ~T1_E~0); 9417#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9146#L621-3 assume !(0 == ~T3_E~0); 9086#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9087#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9088#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9089#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9156#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9170#L651-3 assume !(0 == ~E_3~0); 9171#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9394#L661-3 assume !(0 == ~E_5~0); 9567#L666-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9307#L304-21 assume !(1 == ~m_pc~0); 9174#L304-23 is_master_triggered_~__retres1~0 := 0; 9175#L315-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9438#L316-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 9369#L755-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 9370#L755-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9395#L323-21 assume 1 == ~t1_pc~0; 9050#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9051#L334-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9473#L335-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9474#L763-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9529#L763-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9543#L342-21 assume 1 == ~t2_pc~0; 9074#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9075#L353-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9436#L354-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9495#L771-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9185#L771-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9186#L361-21 assume !(1 == ~t3_pc~0); 9558#L361-23 is_transmit3_triggered_~__retres1~3 := 0; 9559#L372-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9508#L373-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 9342#L779-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9079#L779-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9080#L380-21 assume !(1 == ~t4_pc~0); 9152#L380-23 is_transmit4_triggered_~__retres1~4 := 0; 9153#L391-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9210#L392-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9480#L787-21 assume !(0 != activate_threads_~tmp___3~0); 9443#L787-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9287#L399-21 assume !(1 == ~t5_pc~0); 9157#L399-23 is_transmit5_triggered_~__retres1~5 := 0; 9158#L410-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9453#L411-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 9542#L795-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 9556#L795-23 assume 1 == ~M_E~0;~M_E~0 := 2; 9077#L679-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9078#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9025#L689-3 assume !(1 == ~T3_E~0); 9026#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9064#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9065#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9463#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9528#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9877#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9062#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9063#L729-3 assume !(1 == ~E_5~0); 9447#L734-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9099#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9100#L496-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9114#L497-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 9115#L959 assume !(0 == start_simulation_~tmp~3); 9431#L959-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 9345#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 9346#L496-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 9515#L497-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 9504#L914 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9256#L921 stop_simulation_#res := stop_simulation_~__retres2~0; 9257#L922 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 9464#L972 assume !(0 != start_simulation_~tmp___0~1); 9133#L940-1 [2021-11-09 09:42:01,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:01,821 INFO L85 PathProgramCache]: Analyzing trace with hash 2128372667, now seen corresponding path program 1 times [2021-11-09 09:42:01,821 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:01,821 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2063515767] [2021-11-09 09:42:01,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:01,822 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:01,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:01,882 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:01,882 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:01,885 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2063515767] [2021-11-09 09:42:01,885 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2063515767] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:01,886 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:01,886 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-09 09:42:01,886 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1585764431] [2021-11-09 09:42:01,887 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:42:01,887 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:01,888 INFO L85 PathProgramCache]: Analyzing trace with hash 1463325074, now seen corresponding path program 1 times [2021-11-09 09:42:01,888 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:01,888 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [58969396] [2021-11-09 09:42:01,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:01,889 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:01,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:01,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:01,950 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:01,950 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [58969396] [2021-11-09 09:42:01,951 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [58969396] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:01,951 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:01,951 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-09 09:42:01,951 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1100749145] [2021-11-09 09:42:01,952 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:42:01,952 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:42:01,953 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-09 09:42:01,953 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-09 09:42:01,954 INFO L87 Difference]: Start difference. First operand 933 states and 1364 transitions. cyclomatic complexity: 433 Second operand has 5 states, 5 states have (on average 13.8) internal successors, (69), 5 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:02,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:42:02,218 INFO L93 Difference]: Finished difference Result 2500 states and 3642 transitions. [2021-11-09 09:42:02,218 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-09 09:42:02,219 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2500 states and 3642 transitions. [2021-11-09 09:42:02,248 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2340 [2021-11-09 09:42:02,277 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2500 states to 2500 states and 3642 transitions. [2021-11-09 09:42:02,278 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2500 [2021-11-09 09:42:02,281 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2500 [2021-11-09 09:42:02,282 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2500 states and 3642 transitions. [2021-11-09 09:42:02,317 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:42:02,317 INFO L681 BuchiCegarLoop]: Abstraction has 2500 states and 3642 transitions. [2021-11-09 09:42:02,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2500 states and 3642 transitions. [2021-11-09 09:42:02,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2500 to 981. [2021-11-09 09:42:02,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 981 states, 981 states have (on average 1.4393476044852191) internal successors, (1412), 980 states have internal predecessors, (1412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:02,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 981 states to 981 states and 1412 transitions. [2021-11-09 09:42:02,353 INFO L704 BuchiCegarLoop]: Abstraction has 981 states and 1412 transitions. [2021-11-09 09:42:02,354 INFO L587 BuchiCegarLoop]: Abstraction has 981 states and 1412 transitions. [2021-11-09 09:42:02,354 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-09 09:42:02,354 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 981 states and 1412 transitions. [2021-11-09 09:42:02,363 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 903 [2021-11-09 09:42:02,363 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:42:02,363 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:42:02,365 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:02,365 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:02,366 INFO L791 eck$LassoCheckResult]: Stem: 13062#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 13040#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 12895#L903 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12483#L419 assume 1 == ~m_i~0;~m_st~0 := 0; 12484#L426-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12756#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12757#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12730#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12731#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12973#L451-1 assume !(0 == ~M_E~0); 12974#L611-1 assume !(0 == ~T1_E~0); 12987#L616-1 assume !(0 == ~T2_E~0); 12988#L621-1 assume !(0 == ~T3_E~0); 12607#L626-1 assume !(0 == ~T4_E~0); 12608#L631-1 assume !(0 == ~T5_E~0); 12797#L636-1 assume !(0 == ~E_M~0); 12652#L641-1 assume !(0 == ~E_1~0); 12653#L646-1 assume !(0 == ~E_2~0); 12813#L651-1 assume !(0 == ~E_3~0); 13031#L656-1 assume !(0 == ~E_4~0); 12971#L661-1 assume !(0 == ~E_5~0); 12972#L666-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13005#L304 assume !(1 == ~m_pc~0); 12669#L304-2 is_master_triggered_~__retres1~0 := 0; 12588#L315 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12589#L316 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 12527#L755 assume !(0 != activate_threads_~tmp~1); 12528#L755-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12485#L323 assume !(1 == ~t1_pc~0); 12486#L323-2 is_transmit1_triggered_~__retres1~1 := 0; 12550#L334 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12551#L335 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 13048#L763 assume !(0 != activate_threads_~tmp___0~0); 13049#L763-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12553#L342 assume 1 == ~t2_pc~0; 12554#L343 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 12675#L353 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12676#L354 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 13044#L771 assume !(0 != activate_threads_~tmp___1~0); 12966#L771-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12876#L361 assume !(1 == ~t3_pc~0); 12877#L361-2 is_transmit3_triggered_~__retres1~3 := 0; 12896#L372 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12718#L373 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 12719#L779 assume !(0 != activate_threads_~tmp___2~0); 12567#L779-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12568#L380 assume 1 == ~t4_pc~0; 12630#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12631#L391 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12981#L392 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 12905#L787 assume !(0 != activate_threads_~tmp___3~0); 12906#L787-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12633#L399 assume !(1 == ~t5_pc~0); 12634#L399-2 is_transmit5_triggered_~__retres1~5 := 0; 12768#L410 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12991#L411 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 12758#L795 assume !(0 != activate_threads_~tmp___4~0); 12759#L795-2 assume !(1 == ~M_E~0); 12979#L679-1 assume !(1 == ~T1_E~0); 12690#L684-1 assume !(1 == ~T2_E~0); 12691#L689-1 assume !(1 == ~T3_E~0); 12887#L694-1 assume !(1 == ~T4_E~0); 12885#L699-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12886#L704-1 assume !(1 == ~E_M~0); 12864#L709-1 assume !(1 == ~E_1~0); 12804#L714-1 assume !(1 == ~E_2~0); 12805#L719-1 assume !(1 == ~E_3~0); 12959#L724-1 assume !(1 == ~E_4~0); 12598#L729-1 assume !(1 == ~E_5~0); 12582#L940-1 [2021-11-09 09:42:02,366 INFO L793 eck$LassoCheckResult]: Loop: 12582#L940-1 assume !false; 12583#L941 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 12686#L586 assume !false; 12687#L507 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 13035#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 12882#L496 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 12883#L497 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 12871#L511 assume !(0 != eval_~tmp~0); 12872#L601 start_simulation_~kernel_st~0 := 2; 13019#L419-1 start_simulation_~kernel_st~0 := 3; 12990#L611-2 assume 0 == ~M_E~0;~M_E~0 := 1; 12880#L611-4 assume !(0 == ~T1_E~0); 12881#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12596#L621-3 assume !(0 == ~T3_E~0); 12534#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12535#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12536#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12537#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12609#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12621#L651-3 assume !(0 == ~E_3~0); 12622#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12857#L661-3 assume !(0 == ~E_5~0); 13050#L666-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12763#L304-21 assume !(1 == ~m_pc~0); 12764#L304-23 is_master_triggered_~__retres1~0 := 0; 13418#L315-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13417#L316-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13416#L755-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13415#L755-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13414#L323-21 assume 1 == ~t1_pc~0; 13412#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 13410#L334-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13408#L335-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 13406#L763-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 13405#L763-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13404#L342-21 assume 1 == ~t2_pc~0; 13402#L343-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 13401#L353-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13400#L354-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 13399#L771-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 12636#L771-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12637#L361-21 assume 1 == ~t3_pc~0; 13042#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 13037#L372-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12982#L373-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 12800#L779-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12529#L779-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12530#L380-21 assume 1 == ~t4_pc~0; 13030#L381-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12604#L391-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12661#L392-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 12949#L787-21 assume !(0 != activate_threads_~tmp___3~0); 12907#L787-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12740#L399-21 assume !(1 == ~t5_pc~0); 12610#L399-23 is_transmit5_triggered_~__retres1~5 := 0; 12611#L410-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12919#L411-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 13022#L795-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 13034#L795-23 assume 1 == ~M_E~0;~M_E~0 := 2; 12525#L679-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12526#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12475#L689-3 assume !(1 == ~T3_E~0); 12476#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12514#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12515#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12930#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12921#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12772#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12510#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12511#L729-3 assume !(1 == ~E_5~0); 12912#L734-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 12547#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 12548#L496-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 12563#L497-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 12564#L959 assume !(0 == start_simulation_~tmp~3); 12894#L959-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 12801#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 12802#L496-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 12989#L497-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 12977#L914 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12709#L921 stop_simulation_#res := stop_simulation_~__retres2~0; 12710#L922 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 12927#L972 assume !(0 != start_simulation_~tmp___0~1); 12582#L940-1 [2021-11-09 09:42:02,367 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:02,367 INFO L85 PathProgramCache]: Analyzing trace with hash -1507063107, now seen corresponding path program 1 times [2021-11-09 09:42:02,367 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:02,367 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2040993568] [2021-11-09 09:42:02,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:02,368 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:02,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:02,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:02,429 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:02,429 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2040993568] [2021-11-09 09:42:02,429 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2040993568] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:02,429 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:02,430 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:42:02,430 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1158911035] [2021-11-09 09:42:02,431 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:42:02,432 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:02,432 INFO L85 PathProgramCache]: Analyzing trace with hash 1088688788, now seen corresponding path program 1 times [2021-11-09 09:42:02,432 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:02,433 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1984302244] [2021-11-09 09:42:02,433 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:02,433 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:02,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:02,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:02,481 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:02,481 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1984302244] [2021-11-09 09:42:02,487 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1984302244] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:02,487 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:02,488 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-09 09:42:02,488 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [209467219] [2021-11-09 09:42:02,489 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:42:02,489 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:42:02,490 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-09 09:42:02,490 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-09 09:42:02,490 INFO L87 Difference]: Start difference. First operand 981 states and 1412 transitions. cyclomatic complexity: 433 Second operand has 4 states, 4 states have (on average 17.25) internal successors, (69), 3 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:02,701 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:42:02,701 INFO L93 Difference]: Finished difference Result 2246 states and 3192 transitions. [2021-11-09 09:42:02,701 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-09 09:42:02,702 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2246 states and 3192 transitions. [2021-11-09 09:42:02,729 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2118 [2021-11-09 09:42:02,754 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2246 states to 2246 states and 3192 transitions. [2021-11-09 09:42:02,755 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2246 [2021-11-09 09:42:02,758 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2246 [2021-11-09 09:42:02,759 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2246 states and 3192 transitions. [2021-11-09 09:42:02,763 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:42:02,763 INFO L681 BuchiCegarLoop]: Abstraction has 2246 states and 3192 transitions. [2021-11-09 09:42:02,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2246 states and 3192 transitions. [2021-11-09 09:42:02,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2246 to 1776. [2021-11-09 09:42:02,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1776 states, 1776 states have (on average 1.4301801801801801) internal successors, (2540), 1775 states have internal predecessors, (2540), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:02,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1776 states to 1776 states and 2540 transitions. [2021-11-09 09:42:02,820 INFO L704 BuchiCegarLoop]: Abstraction has 1776 states and 2540 transitions. [2021-11-09 09:42:02,820 INFO L587 BuchiCegarLoop]: Abstraction has 1776 states and 2540 transitions. [2021-11-09 09:42:02,821 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-09 09:42:02,821 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1776 states and 2540 transitions. [2021-11-09 09:42:02,842 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1698 [2021-11-09 09:42:02,843 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:42:02,844 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:42:02,846 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:02,846 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:02,846 INFO L791 eck$LassoCheckResult]: Stem: 16297#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 16276#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 16131#L903 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15720#L419 assume 1 == ~m_i~0;~m_st~0 := 0; 15721#L426-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15996#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15997#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15972#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15973#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16213#L451-1 assume !(0 == ~M_E~0); 16214#L611-1 assume !(0 == ~T1_E~0); 16227#L616-1 assume !(0 == ~T2_E~0); 16228#L621-1 assume !(0 == ~T3_E~0); 15845#L626-1 assume !(0 == ~T4_E~0); 15846#L631-1 assume !(0 == ~T5_E~0); 16035#L636-1 assume !(0 == ~E_M~0); 15890#L641-1 assume !(0 == ~E_1~0); 15891#L646-1 assume !(0 == ~E_2~0); 16052#L651-1 assume !(0 == ~E_3~0); 16266#L656-1 assume !(0 == ~E_4~0); 16211#L661-1 assume !(0 == ~E_5~0); 16212#L666-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16243#L304 assume !(1 == ~m_pc~0); 15907#L304-2 is_master_triggered_~__retres1~0 := 0; 15826#L315 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15827#L316 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15766#L755 assume !(0 != activate_threads_~tmp~1); 15767#L755-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15722#L323 assume !(1 == ~t1_pc~0); 15723#L323-2 is_transmit1_triggered_~__retres1~1 := 0; 16100#L334 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16183#L335 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 16184#L763 assume !(0 != activate_threads_~tmp___0~0); 16283#L763-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15793#L342 assume !(1 == ~t2_pc~0); 15794#L342-2 is_transmit2_triggered_~__retres1~2 := 0; 15913#L353 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15914#L354 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 16280#L771 assume !(0 != activate_threads_~tmp___1~0); 16207#L771-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16112#L361 assume !(1 == ~t3_pc~0); 16113#L361-2 is_transmit3_triggered_~__retres1~3 := 0; 16132#L372 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15960#L373 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 15961#L779 assume !(0 != activate_threads_~tmp___2~0); 15806#L779-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15807#L380 assume 1 == ~t4_pc~0; 15868#L381 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 15869#L391 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16220#L392 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 16143#L787 assume !(0 != activate_threads_~tmp___3~0); 16144#L787-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15871#L399 assume !(1 == ~t5_pc~0); 15872#L399-2 is_transmit5_triggered_~__retres1~5 := 0; 16008#L410 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16231#L411 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 15998#L795 assume !(0 != activate_threads_~tmp___4~0); 15999#L795-2 assume !(1 == ~M_E~0); 16219#L679-1 assume !(1 == ~T1_E~0); 15927#L684-1 assume !(1 == ~T2_E~0); 15928#L689-1 assume !(1 == ~T3_E~0); 16123#L694-1 assume !(1 == ~T4_E~0); 16121#L699-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16122#L704-1 assume !(1 == ~E_M~0); 16099#L709-1 assume !(1 == ~E_1~0); 16039#L714-1 assume !(1 == ~E_2~0); 16040#L719-1 assume !(1 == ~E_3~0); 16203#L724-1 assume !(1 == ~E_4~0); 15836#L729-1 assume !(1 == ~E_5~0); 15820#L940-1 [2021-11-09 09:42:02,847 INFO L793 eck$LassoCheckResult]: Loop: 15820#L940-1 assume !false; 15821#L941 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 15923#L586 assume !false; 15924#L507 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 16272#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 16118#L496 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 16119#L497 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 16107#L511 assume !(0 != eval_~tmp~0); 16108#L601 start_simulation_~kernel_st~0 := 2; 16255#L419-1 start_simulation_~kernel_st~0 := 3; 16230#L611-2 assume 0 == ~M_E~0;~M_E~0 := 1; 16116#L611-4 assume !(0 == ~T1_E~0); 16117#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16179#L621-3 assume !(0 == ~T3_E~0); 17368#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17366#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17365#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17364#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17363#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17362#L651-3 assume !(0 == ~E_3~0); 17361#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17360#L661-3 assume !(0 == ~E_5~0); 17359#L666-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17358#L304-21 assume !(1 == ~m_pc~0); 17357#L304-23 is_master_triggered_~__retres1~0 := 0; 16139#L315-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16140#L316-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 16065#L755-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 16066#L755-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16093#L323-21 assume 1 == ~t1_pc~0; 15737#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 15738#L334-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17308#L335-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 17307#L763-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16242#L763-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16259#L342-21 assume !(1 == ~t2_pc~0); 16287#L342-23 is_transmit2_triggered_~__retres1~2 := 0; 16135#L353-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16136#L354-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 16208#L771-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 15874#L771-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15875#L361-21 assume !(1 == ~t3_pc~0); 16273#L361-23 is_transmit3_triggered_~__retres1~3 := 0; 16274#L372-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16222#L373-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 16038#L779-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 15768#L779-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15769#L380-21 assume !(1 == ~t4_pc~0); 15841#L380-23 is_transmit4_triggered_~__retres1~4 := 0; 15842#L391-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15899#L392-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 16192#L787-21 assume !(0 != activate_threads_~tmp___3~0); 16145#L787-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15982#L399-21 assume !(1 == ~t5_pc~0); 15848#L399-23 is_transmit5_triggered_~__retres1~5 := 0; 15849#L410-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16156#L411-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 16258#L795-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 16271#L795-23 assume 1 == ~M_E~0;~M_E~0 := 2; 15764#L679-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15765#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15712#L689-3 assume !(1 == ~T3_E~0); 15713#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15751#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15752#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16168#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16161#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16012#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15749#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15750#L729-3 assume !(1 == ~E_5~0); 16150#L734-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 15786#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 15787#L496-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 15802#L497-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 15803#L959 assume !(0 == start_simulation_~tmp~3); 16130#L959-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 16043#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 16044#L496-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 16229#L497-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 16218#L914 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15948#L921 stop_simulation_#res := stop_simulation_~__retres2~0; 15949#L922 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 16169#L972 assume !(0 != start_simulation_~tmp___0~1); 15820#L940-1 [2021-11-09 09:42:02,848 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:02,848 INFO L85 PathProgramCache]: Analyzing trace with hash -455614018, now seen corresponding path program 1 times [2021-11-09 09:42:02,848 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:02,848 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1968905280] [2021-11-09 09:42:02,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:02,849 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:02,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:02,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:02,905 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:02,905 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1968905280] [2021-11-09 09:42:02,905 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1968905280] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:02,905 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:02,906 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-09 09:42:02,906 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1249714719] [2021-11-09 09:42:02,906 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:42:02,907 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:02,907 INFO L85 PathProgramCache]: Analyzing trace with hash -1398807503, now seen corresponding path program 1 times [2021-11-09 09:42:02,907 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:02,907 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1410373678] [2021-11-09 09:42:02,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:02,908 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:02,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:02,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:02,962 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:02,962 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1410373678] [2021-11-09 09:42:02,962 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1410373678] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:02,962 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:02,963 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-09 09:42:02,963 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1404758467] [2021-11-09 09:42:02,963 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:42:02,964 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:42:02,964 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:42:02,964 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:42:02,965 INFO L87 Difference]: Start difference. First operand 1776 states and 2540 transitions. cyclomatic complexity: 766 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 2 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:03,053 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:42:03,053 INFO L93 Difference]: Finished difference Result 3271 states and 4647 transitions. [2021-11-09 09:42:03,054 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:42:03,054 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3271 states and 4647 transitions. [2021-11-09 09:42:03,088 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3184 [2021-11-09 09:42:03,124 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3271 states to 3271 states and 4647 transitions. [2021-11-09 09:42:03,125 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3271 [2021-11-09 09:42:03,187 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3271 [2021-11-09 09:42:03,187 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3271 states and 4647 transitions. [2021-11-09 09:42:03,193 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:42:03,195 INFO L681 BuchiCegarLoop]: Abstraction has 3271 states and 4647 transitions. [2021-11-09 09:42:03,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3271 states and 4647 transitions. [2021-11-09 09:42:03,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3271 to 3263. [2021-11-09 09:42:03,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3263 states, 3263 states have (on average 1.4216978240882623) internal successors, (4639), 3262 states have internal predecessors, (4639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:03,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3263 states to 3263 states and 4639 transitions. [2021-11-09 09:42:03,281 INFO L704 BuchiCegarLoop]: Abstraction has 3263 states and 4639 transitions. [2021-11-09 09:42:03,281 INFO L587 BuchiCegarLoop]: Abstraction has 3263 states and 4639 transitions. [2021-11-09 09:42:03,281 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-09 09:42:03,282 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3263 states and 4639 transitions. [2021-11-09 09:42:03,304 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3176 [2021-11-09 09:42:03,304 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:42:03,305 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:42:03,306 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:03,307 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:03,307 INFO L791 eck$LassoCheckResult]: Stem: 21360#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 21337#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 21189#L903 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 20776#L419 assume 1 == ~m_i~0;~m_st~0 := 0; 20777#L426-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21046#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21047#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21022#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21023#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21268#L451-1 assume !(0 == ~M_E~0); 21269#L611-1 assume !(0 == ~T1_E~0); 21284#L616-1 assume !(0 == ~T2_E~0); 21285#L621-1 assume !(0 == ~T3_E~0); 20899#L626-1 assume !(0 == ~T4_E~0); 20900#L631-1 assume !(0 == ~T5_E~0); 21087#L636-1 assume !(0 == ~E_M~0); 20943#L641-1 assume !(0 == ~E_1~0); 20944#L646-1 assume !(0 == ~E_2~0); 21104#L651-1 assume !(0 == ~E_3~0); 21328#L656-1 assume !(0 == ~E_4~0); 21266#L661-1 assume !(0 == ~E_5~0); 21267#L666-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21300#L304 assume !(1 == ~m_pc~0); 20961#L304-2 is_master_triggered_~__retres1~0 := 0; 20879#L315 is_master_triggered_#res := is_master_triggered_~__retres1~0; 20880#L316 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 20822#L755 assume !(0 != activate_threads_~tmp~1); 20823#L755-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20778#L323 assume !(1 == ~t1_pc~0); 20779#L323-2 is_transmit1_triggered_~__retres1~1 := 0; 21154#L334 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21372#L335 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 21349#L763 assume !(0 != activate_threads_~tmp___0~0); 21350#L763-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20847#L342 assume !(1 == ~t2_pc~0); 20848#L342-2 is_transmit2_triggered_~__retres1~2 := 0; 20967#L353 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20968#L354 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 21345#L771 assume !(0 != activate_threads_~tmp___1~0); 21261#L771-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21167#L361 assume !(1 == ~t3_pc~0); 21168#L361-2 is_transmit3_triggered_~__retres1~3 := 0; 21190#L372 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21010#L373 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 21011#L779 assume !(0 != activate_threads_~tmp___2~0); 20859#L779-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20860#L380 assume !(1 == ~t4_pc~0); 21164#L380-2 is_transmit4_triggered_~__retres1~4 := 0; 21276#L391 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21277#L392 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 21197#L787 assume !(0 != activate_threads_~tmp___3~0); 21198#L787-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 20922#L399 assume !(1 == ~t5_pc~0); 20923#L399-2 is_transmit5_triggered_~__retres1~5 := 0; 21058#L410 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 21288#L411 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 21048#L795 assume !(0 != activate_threads_~tmp___4~0); 21049#L795-2 assume !(1 == ~M_E~0); 21275#L679-1 assume !(1 == ~T1_E~0); 20980#L684-1 assume !(1 == ~T2_E~0); 20981#L689-1 assume !(1 == ~T3_E~0); 21178#L694-1 assume !(1 == ~T4_E~0); 21176#L699-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21177#L704-1 assume !(1 == ~E_M~0); 21153#L709-1 assume !(1 == ~E_1~0); 21091#L714-1 assume !(1 == ~E_2~0); 21092#L719-1 assume !(1 == ~E_3~0); 21257#L724-1 assume !(1 == ~E_4~0); 20889#L729-1 assume !(1 == ~E_5~0); 20890#L940-1 [2021-11-09 09:42:03,307 INFO L793 eck$LassoCheckResult]: Loop: 20890#L940-1 assume !false; 23290#L941 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 23288#L586 assume !false; 23286#L507 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 23272#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 23270#L496 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 23268#L497 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 23265#L511 assume !(0 != eval_~tmp~0); 23266#L601 start_simulation_~kernel_st~0 := 2; 23824#L419-1 start_simulation_~kernel_st~0 := 3; 23742#L611-2 assume 0 == ~M_E~0;~M_E~0 := 1; 23505#L611-4 assume !(0 == ~T1_E~0); 23504#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23503#L621-3 assume !(0 == ~T3_E~0); 23502#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23500#L631-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23499#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23498#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23497#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23496#L651-3 assume !(0 == ~E_3~0); 23495#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23494#L661-3 assume !(0 == ~E_5~0); 23493#L666-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23492#L304-21 assume !(1 == ~m_pc~0); 23491#L304-23 is_master_triggered_~__retres1~0 := 0; 23490#L315-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23488#L316-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 23487#L755-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 23486#L755-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 23484#L323-21 assume !(1 == ~t1_pc~0); 23482#L323-23 is_transmit1_triggered_~__retres1~1 := 0; 23480#L334-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23479#L335-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 23478#L763-21 assume !(0 != activate_threads_~tmp___0~0); 23475#L763-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23473#L342-21 assume !(1 == ~t2_pc~0); 23151#L342-23 is_transmit2_triggered_~__retres1~2 := 0; 23470#L353-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23468#L354-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 23466#L771-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 23462#L771-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 23460#L361-21 assume !(1 == ~t3_pc~0); 23457#L361-23 is_transmit3_triggered_~__retres1~3 := 0; 23455#L372-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 23452#L373-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 23450#L779-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 23448#L779-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 23447#L380-21 assume !(1 == ~t4_pc~0); 23445#L380-23 is_transmit4_triggered_~__retres1~4 := 0; 23443#L391-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 23441#L392-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 23439#L787-21 assume !(0 != activate_threads_~tmp___3~0); 23437#L787-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 23434#L399-21 assume !(1 == ~t5_pc~0); 23431#L399-23 is_transmit5_triggered_~__retres1~5 := 0; 23429#L410-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 23427#L411-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 23425#L795-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 23423#L795-23 assume 1 == ~M_E~0;~M_E~0 := 2; 23421#L679-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23419#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23417#L689-3 assume !(1 == ~T3_E~0); 23415#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23413#L699-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23410#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 23408#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23406#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23404#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23402#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23400#L729-3 assume !(1 == ~E_5~0); 23398#L734-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 23393#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 23387#L496-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 23385#L497-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 23376#L959 assume !(0 == start_simulation_~tmp~3); 23374#L959-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 23364#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 23359#L496-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 23357#L497-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 23354#L914 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 23352#L921 stop_simulation_#res := stop_simulation_~__retres2~0; 23351#L922 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 23350#L972 assume !(0 != start_simulation_~tmp___0~1); 20890#L940-1 [2021-11-09 09:42:03,308 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:03,308 INFO L85 PathProgramCache]: Analyzing trace with hash 324366911, now seen corresponding path program 1 times [2021-11-09 09:42:03,308 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:03,309 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [140741059] [2021-11-09 09:42:03,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:03,309 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:03,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:03,347 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:03,347 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:03,347 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [140741059] [2021-11-09 09:42:03,347 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [140741059] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:03,348 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:03,348 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-09 09:42:03,348 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [587092175] [2021-11-09 09:42:03,349 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:42:03,349 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:03,349 INFO L85 PathProgramCache]: Analyzing trace with hash -1777086514, now seen corresponding path program 1 times [2021-11-09 09:42:03,350 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:03,350 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [137896318] [2021-11-09 09:42:03,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:03,350 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:03,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:03,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:03,396 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:03,397 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [137896318] [2021-11-09 09:42:03,397 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [137896318] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:03,397 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:03,397 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-09 09:42:03,398 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [389396345] [2021-11-09 09:42:03,398 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:42:03,398 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:42:03,399 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:42:03,399 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:42:03,399 INFO L87 Difference]: Start difference. First operand 3263 states and 4639 transitions. cyclomatic complexity: 1380 Second operand has 3 states, 3 states have (on average 23.0) internal successors, (69), 2 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:03,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:42:03,438 INFO L93 Difference]: Finished difference Result 3263 states and 4613 transitions. [2021-11-09 09:42:03,438 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:42:03,438 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3263 states and 4613 transitions. [2021-11-09 09:42:03,469 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3176 [2021-11-09 09:42:03,503 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3263 states to 3263 states and 4613 transitions. [2021-11-09 09:42:03,503 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3263 [2021-11-09 09:42:03,507 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3263 [2021-11-09 09:42:03,508 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3263 states and 4613 transitions. [2021-11-09 09:42:03,514 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:42:03,514 INFO L681 BuchiCegarLoop]: Abstraction has 3263 states and 4613 transitions. [2021-11-09 09:42:03,518 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3263 states and 4613 transitions. [2021-11-09 09:42:03,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3263 to 3263. [2021-11-09 09:42:03,589 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3263 states, 3263 states have (on average 1.4137296965982225) internal successors, (4613), 3262 states have internal predecessors, (4613), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:03,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3263 states to 3263 states and 4613 transitions. [2021-11-09 09:42:03,605 INFO L704 BuchiCegarLoop]: Abstraction has 3263 states and 4613 transitions. [2021-11-09 09:42:03,605 INFO L587 BuchiCegarLoop]: Abstraction has 3263 states and 4613 transitions. [2021-11-09 09:42:03,605 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-09 09:42:03,605 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3263 states and 4613 transitions. [2021-11-09 09:42:03,644 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3176 [2021-11-09 09:42:03,645 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:42:03,645 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:42:03,647 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:03,647 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:03,647 INFO L791 eck$LassoCheckResult]: Stem: 27901#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 27877#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 27725#L903 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 27315#L419 assume 1 == ~m_i~0;~m_st~0 := 0; 27316#L426-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27576#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27577#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27553#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27554#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27807#L451-1 assume !(0 == ~M_E~0); 27808#L611-1 assume !(0 == ~T1_E~0); 27824#L616-1 assume !(0 == ~T2_E~0); 27825#L621-1 assume !(0 == ~T3_E~0); 27439#L626-1 assume !(0 == ~T4_E~0); 27440#L631-1 assume !(0 == ~T5_E~0); 27623#L636-1 assume !(0 == ~E_M~0); 27478#L641-1 assume !(0 == ~E_1~0); 27479#L646-1 assume !(0 == ~E_2~0); 27637#L651-1 assume !(0 == ~E_3~0); 27867#L656-1 assume !(0 == ~E_4~0); 27805#L661-1 assume !(0 == ~E_5~0); 27806#L666-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27839#L304 assume !(1 == ~m_pc~0); 27498#L304-2 is_master_triggered_~__retres1~0 := 0; 27414#L315 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27415#L316 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 27362#L755 assume !(0 != activate_threads_~tmp~1); 27363#L755-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27317#L323 assume !(1 == ~t1_pc~0); 27318#L323-2 is_transmit1_triggered_~__retres1~1 := 0; 27689#L334 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27904#L335 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 27887#L763 assume !(0 != activate_threads_~tmp___0~0); 27888#L763-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27386#L342 assume !(1 == ~t2_pc~0); 27387#L342-2 is_transmit2_triggered_~__retres1~2 := 0; 27500#L353 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27501#L354 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 27884#L771 assume !(0 != activate_threads_~tmp___1~0); 27800#L771-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27703#L361 assume !(1 == ~t3_pc~0); 27704#L361-2 is_transmit3_triggered_~__retres1~3 := 0; 27726#L372 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27541#L373 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 27542#L779 assume !(0 != activate_threads_~tmp___2~0); 27396#L779-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 27397#L380 assume !(1 == ~t4_pc~0); 27700#L380-2 is_transmit4_triggered_~__retres1~4 := 0; 27816#L391 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 27817#L392 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 27737#L787 assume !(0 != activate_threads_~tmp___3~0); 27738#L787-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 27456#L399 assume !(1 == ~t5_pc~0); 27457#L399-2 is_transmit5_triggered_~__retres1~5 := 0; 27589#L410 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 27828#L411 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 27578#L795 assume !(0 != activate_threads_~tmp___4~0); 27579#L795-2 assume !(1 == ~M_E~0); 27814#L679-1 assume !(1 == ~T1_E~0); 27513#L684-1 assume !(1 == ~T2_E~0); 27514#L689-1 assume !(1 == ~T3_E~0); 27715#L694-1 assume !(1 == ~T4_E~0); 27713#L699-1 assume !(1 == ~T5_E~0); 27714#L704-1 assume !(1 == ~E_M~0); 27688#L709-1 assume !(1 == ~E_1~0); 27629#L714-1 assume !(1 == ~E_2~0); 27630#L719-1 assume !(1 == ~E_3~0); 27794#L724-1 assume !(1 == ~E_4~0); 27424#L729-1 assume !(1 == ~E_5~0); 27410#L940-1 [2021-11-09 09:42:03,648 INFO L793 eck$LassoCheckResult]: Loop: 27410#L940-1 assume !false; 27411#L941 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 27511#L586 assume !false; 27512#L507 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 27873#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 27710#L496 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 27711#L497 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 27696#L511 assume !(0 != eval_~tmp~0); 27697#L601 start_simulation_~kernel_st~0 := 2; 30486#L419-1 start_simulation_~kernel_st~0 := 3; 30485#L611-2 assume 0 == ~M_E~0;~M_E~0 := 1; 30484#L611-4 assume !(0 == ~T1_E~0); 30483#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27423#L621-3 assume !(0 == ~T3_E~0); 27364#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27365#L631-3 assume !(0 == ~T5_E~0); 27366#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 27367#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27433#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27707#L651-3 assume !(0 == ~E_3~0); 30430#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30429#L661-3 assume !(0 == ~E_5~0); 30428#L666-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30427#L304-21 assume !(1 == ~m_pc~0); 30426#L304-23 is_master_triggered_~__retres1~0 := 0; 30425#L315-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30424#L316-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 30423#L755-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 30422#L755-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30421#L323-21 assume !(1 == ~t1_pc~0); 30419#L323-23 is_transmit1_triggered_~__retres1~1 := 0; 30417#L334-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30415#L335-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 30414#L763-21 assume !(0 != activate_threads_~tmp___0~0); 30146#L763-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30145#L342-21 assume !(1 == ~t2_pc~0); 29528#L342-23 is_transmit2_triggered_~__retres1~2 := 0; 30144#L353-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30143#L354-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 30142#L771-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 30141#L771-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30140#L361-21 assume !(1 == ~t3_pc~0); 30138#L361-23 is_transmit3_triggered_~__retres1~3 := 0; 30137#L372-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30136#L373-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 30135#L779-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 30134#L779-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 30132#L380-21 assume !(1 == ~t4_pc~0); 30130#L380-23 is_transmit4_triggered_~__retres1~4 := 0; 30128#L391-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 30126#L392-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 30124#L787-21 assume !(0 != activate_threads_~tmp___3~0); 30121#L787-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 30119#L399-21 assume !(1 == ~t5_pc~0); 30116#L399-23 is_transmit5_triggered_~__retres1~5 := 0; 30114#L410-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 30112#L411-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 30110#L795-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 30108#L795-23 assume 1 == ~M_E~0;~M_E~0 := 2; 30106#L679-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30104#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30102#L689-3 assume !(1 == ~T3_E~0); 30100#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30097#L699-3 assume !(1 == ~T5_E~0); 30095#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 30093#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30091#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 30089#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30087#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 30085#L729-3 assume !(1 == ~E_5~0); 30083#L734-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 30078#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 30072#L496-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 30070#L497-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 30063#L959 assume !(0 == start_simulation_~tmp~3); 27881#L959-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 27626#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 27627#L496-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 27826#L497-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 27813#L914 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 27532#L921 stop_simulation_#res := stop_simulation_~__retres2~0; 27533#L922 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 27763#L972 assume !(0 != start_simulation_~tmp___0~1); 27410#L940-1 [2021-11-09 09:42:03,648 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:03,649 INFO L85 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 1 times [2021-11-09 09:42:03,649 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:03,652 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [685356301] [2021-11-09 09:42:03,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:03,652 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:03,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:03,675 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:42:03,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:03,756 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:42:03,758 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:03,758 INFO L85 PathProgramCache]: Analyzing trace with hash -1640794806, now seen corresponding path program 1 times [2021-11-09 09:42:03,759 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:03,759 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1980339634] [2021-11-09 09:42:03,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:03,759 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:03,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:03,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:03,808 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:03,808 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1980339634] [2021-11-09 09:42:03,808 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1980339634] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:03,809 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:03,809 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-09 09:42:03,809 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1044591124] [2021-11-09 09:42:03,810 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:42:03,810 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:42:03,811 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-09 09:42:03,811 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-09 09:42:03,811 INFO L87 Difference]: Start difference. First operand 3263 states and 4613 transitions. cyclomatic complexity: 1354 Second operand has 5 states, 5 states have (on average 16.6) internal successors, (83), 5 states have internal predecessors, (83), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:03,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:42:03,975 INFO L93 Difference]: Finished difference Result 5839 states and 8149 transitions. [2021-11-09 09:42:03,975 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-11-09 09:42:03,976 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5839 states and 8149 transitions. [2021-11-09 09:42:04,022 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5740 [2021-11-09 09:42:04,078 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5839 states to 5839 states and 8149 transitions. [2021-11-09 09:42:04,078 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5839 [2021-11-09 09:42:04,085 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5839 [2021-11-09 09:42:04,086 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5839 states and 8149 transitions. [2021-11-09 09:42:04,096 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:42:04,096 INFO L681 BuchiCegarLoop]: Abstraction has 5839 states and 8149 transitions. [2021-11-09 09:42:04,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5839 states and 8149 transitions. [2021-11-09 09:42:04,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5839 to 3287. [2021-11-09 09:42:04,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3287 states, 3287 states have (on average 1.4107088530574992) internal successors, (4637), 3286 states have internal predecessors, (4637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:04,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3287 states to 3287 states and 4637 transitions. [2021-11-09 09:42:04,206 INFO L704 BuchiCegarLoop]: Abstraction has 3287 states and 4637 transitions. [2021-11-09 09:42:04,207 INFO L587 BuchiCegarLoop]: Abstraction has 3287 states and 4637 transitions. [2021-11-09 09:42:04,207 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-09 09:42:04,207 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3287 states and 4637 transitions. [2021-11-09 09:42:04,257 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3200 [2021-11-09 09:42:04,257 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:42:04,257 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:42:04,259 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:04,259 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:04,262 INFO L791 eck$LassoCheckResult]: Stem: 37057#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 37023#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 36849#L903 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 36433#L419 assume 1 == ~m_i~0;~m_st~0 := 0; 36434#L426-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36702#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 36703#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36678#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 36679#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 36937#L451-1 assume !(0 == ~M_E~0); 36938#L611-1 assume !(0 == ~T1_E~0); 36958#L616-1 assume !(0 == ~T2_E~0); 36959#L621-1 assume !(0 == ~T3_E~0); 36559#L626-1 assume !(0 == ~T4_E~0); 36560#L631-1 assume !(0 == ~T5_E~0); 36747#L636-1 assume !(0 == ~E_M~0); 36599#L641-1 assume !(0 == ~E_1~0); 36600#L646-1 assume !(0 == ~E_2~0); 36761#L651-1 assume !(0 == ~E_3~0); 37013#L656-1 assume !(0 == ~E_4~0); 36935#L661-1 assume !(0 == ~E_5~0); 36936#L666-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 36976#L304 assume !(1 == ~m_pc~0); 36619#L304-2 is_master_triggered_~__retres1~0 := 0; 36532#L315 is_master_triggered_#res := is_master_triggered_~__retres1~0; 36533#L316 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 36480#L755 assume !(0 != activate_threads_~tmp~1); 36481#L755-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 36435#L323 assume !(1 == ~t1_pc~0); 36436#L323-2 is_transmit1_triggered_~__retres1~1 := 0; 36814#L334 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 37065#L335 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 37035#L763 assume !(0 != activate_threads_~tmp___0~0); 37036#L763-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 36504#L342 assume !(1 == ~t2_pc~0); 36505#L342-2 is_transmit2_triggered_~__retres1~2 := 0; 36621#L353 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 36622#L354 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 37031#L771 assume !(0 != activate_threads_~tmp___1~0); 36931#L771-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 36826#L361 assume !(1 == ~t3_pc~0); 36827#L361-2 is_transmit3_triggered_~__retres1~3 := 0; 36850#L372 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 36666#L373 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 36667#L779 assume !(0 != activate_threads_~tmp___2~0); 36514#L779-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 36515#L380 assume !(1 == ~t4_pc~0); 36823#L380-2 is_transmit4_triggered_~__retres1~4 := 0; 36946#L391 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 36947#L392 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 36860#L787 assume !(0 != activate_threads_~tmp___3~0); 36861#L787-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 36576#L399 assume !(1 == ~t5_pc~0); 36577#L399-2 is_transmit5_triggered_~__retres1~5 := 0; 36715#L410 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 36963#L411 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 36704#L795 assume !(0 != activate_threads_~tmp___4~0); 36705#L795-2 assume !(1 == ~M_E~0); 36944#L679-1 assume !(1 == ~T1_E~0); 36634#L684-1 assume !(1 == ~T2_E~0); 36635#L689-1 assume !(1 == ~T3_E~0); 36838#L694-1 assume !(1 == ~T4_E~0); 36836#L699-1 assume !(1 == ~T5_E~0); 36837#L704-1 assume !(1 == ~E_M~0); 36813#L709-1 assume !(1 == ~E_1~0); 36753#L714-1 assume !(1 == ~E_2~0); 36754#L719-1 assume !(1 == ~E_3~0); 36924#L724-1 assume !(1 == ~E_4~0); 36543#L729-1 assume !(1 == ~E_5~0); 36544#L940-1 [2021-11-09 09:42:04,263 INFO L793 eck$LassoCheckResult]: Loop: 36544#L940-1 assume !false; 39141#L941 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 39126#L586 assume !false; 38564#L507 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 38549#L464 assume !(0 == ~m_st~0); 38550#L468 assume !(0 == ~t1_st~0); 38553#L472 assume !(0 == ~t2_st~0); 38554#L476 assume !(0 == ~t3_st~0); 38551#L480 assume !(0 == ~t4_st~0); 38552#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 36833#L496 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 36834#L497 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 38224#L511 assume !(0 != eval_~tmp~0); 38544#L601 start_simulation_~kernel_st~0 := 2; 38717#L419-1 start_simulation_~kernel_st~0 := 3; 38716#L611-2 assume 0 == ~M_E~0;~M_E~0 := 1; 38715#L611-4 assume !(0 == ~T1_E~0); 38714#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 38713#L621-3 assume !(0 == ~T3_E~0); 38712#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38711#L631-3 assume !(0 == ~T5_E~0); 38710#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 38709#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 36830#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36567#L651-3 assume !(0 == ~E_3~0); 36568#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38707#L661-3 assume !(0 == ~E_5~0); 38706#L666-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 38705#L304-21 assume !(1 == ~m_pc~0); 38704#L304-23 is_master_triggered_~__retres1~0 := 0; 38703#L315-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 38702#L316-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 38701#L755-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 38700#L755-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 38699#L323-21 assume 1 == ~t1_pc~0; 38697#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 38695#L334-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 38693#L335-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 38691#L763-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 38690#L763-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 38689#L342-21 assume !(1 == ~t2_pc~0); 38139#L342-23 is_transmit2_triggered_~__retres1~2 := 0; 39020#L353-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 39019#L354-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 39018#L771-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 39017#L771-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 37025#L361-21 assume 1 == ~t3_pc~0; 37026#L362-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 37030#L372-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 36948#L373-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 36743#L779-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 36744#L779-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 37046#L380-21 assume !(1 == ~t4_pc~0); 37047#L380-23 is_transmit4_triggered_~__retres1~4 := 0; 39249#L391-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 39248#L392-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 39247#L787-21 assume !(0 != activate_threads_~tmp___3~0); 39246#L787-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 39245#L399-21 assume !(1 == ~t5_pc~0); 39243#L399-23 is_transmit5_triggered_~__retres1~5 := 0; 39242#L410-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 39241#L411-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 39240#L795-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 39239#L795-23 assume 1 == ~M_E~0;~M_E~0 := 2; 39238#L679-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 39237#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39236#L689-3 assume !(1 == ~T3_E~0); 39235#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39234#L699-3 assume !(1 == ~T5_E~0); 39233#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 39232#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 39231#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 39230#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 39229#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39228#L729-3 assume !(1 == ~E_5~0); 39227#L734-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 39225#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 39219#L496-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 39217#L497-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 39213#L959 assume !(0 == start_simulation_~tmp~3); 39192#L959-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 39189#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 39184#L496-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 39182#L497-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 39180#L914 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 39178#L921 stop_simulation_#res := stop_simulation_~__retres2~0; 39176#L922 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 39174#L972 assume !(0 != start_simulation_~tmp___0~1); 36544#L940-1 [2021-11-09 09:42:04,264 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:04,264 INFO L85 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 2 times [2021-11-09 09:42:04,264 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:04,265 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [57124582] [2021-11-09 09:42:04,265 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:04,265 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:04,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:04,289 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:42:04,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:04,349 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:42:04,350 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:04,350 INFO L85 PathProgramCache]: Analyzing trace with hash 215214055, now seen corresponding path program 1 times [2021-11-09 09:42:04,350 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:04,350 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [522888156] [2021-11-09 09:42:04,351 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:04,351 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:04,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:04,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:04,433 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:04,434 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [522888156] [2021-11-09 09:42:04,434 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [522888156] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:04,434 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:04,434 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-09 09:42:04,435 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [725050219] [2021-11-09 09:42:04,435 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:42:04,435 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:42:04,436 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-09 09:42:04,436 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-09 09:42:04,437 INFO L87 Difference]: Start difference. First operand 3287 states and 4637 transitions. cyclomatic complexity: 1354 Second operand has 5 states, 5 states have (on average 17.6) internal successors, (88), 5 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:04,706 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:42:04,707 INFO L93 Difference]: Finished difference Result 6487 states and 9096 transitions. [2021-11-09 09:42:04,707 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-09 09:42:04,708 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6487 states and 9096 transitions. [2021-11-09 09:42:04,766 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6392 [2021-11-09 09:42:04,814 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6487 states to 6487 states and 9096 transitions. [2021-11-09 09:42:04,815 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6487 [2021-11-09 09:42:04,824 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6487 [2021-11-09 09:42:04,824 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6487 states and 9096 transitions. [2021-11-09 09:42:04,837 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:42:04,837 INFO L681 BuchiCegarLoop]: Abstraction has 6487 states and 9096 transitions. [2021-11-09 09:42:04,846 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6487 states and 9096 transitions. [2021-11-09 09:42:04,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6487 to 3371. [2021-11-09 09:42:04,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3371 states, 3371 states have (on average 1.3930584396321566) internal successors, (4696), 3370 states have internal predecessors, (4696), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:04,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3371 states to 3371 states and 4696 transitions. [2021-11-09 09:42:04,947 INFO L704 BuchiCegarLoop]: Abstraction has 3371 states and 4696 transitions. [2021-11-09 09:42:04,947 INFO L587 BuchiCegarLoop]: Abstraction has 3371 states and 4696 transitions. [2021-11-09 09:42:04,947 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-09 09:42:04,948 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3371 states and 4696 transitions. [2021-11-09 09:42:04,965 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3284 [2021-11-09 09:42:04,966 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:42:04,966 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:42:04,968 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:04,968 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:04,968 INFO L791 eck$LassoCheckResult]: Stem: 46834#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 46802#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 46633#L903 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 46216#L419 assume 1 == ~m_i~0;~m_st~0 := 0; 46217#L426-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46491#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46492#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46466#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46467#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46726#L451-1 assume !(0 == ~M_E~0); 46727#L611-1 assume !(0 == ~T1_E~0); 46743#L616-1 assume !(0 == ~T2_E~0); 46744#L621-1 assume !(0 == ~T3_E~0); 46339#L626-1 assume !(0 == ~T4_E~0); 46340#L631-1 assume !(0 == ~T5_E~0); 46531#L636-1 assume !(0 == ~E_M~0); 46383#L641-1 assume !(0 == ~E_1~0); 46384#L646-1 assume !(0 == ~E_2~0); 46548#L651-1 assume !(0 == ~E_3~0); 46792#L656-1 assume !(0 == ~E_4~0); 46724#L661-1 assume !(0 == ~E_5~0); 46725#L666-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 46761#L304 assume !(1 == ~m_pc~0); 46403#L304-2 is_master_triggered_~__retres1~0 := 0; 46319#L315 is_master_triggered_#res := is_master_triggered_~__retres1~0; 46320#L316 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 46262#L755 assume !(0 != activate_threads_~tmp~1); 46263#L755-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 46218#L323 assume !(1 == ~t1_pc~0); 46219#L323-2 is_transmit1_triggered_~__retres1~1 := 0; 46594#L334 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 46840#L335 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 46813#L763 assume !(0 != activate_threads_~tmp___0~0); 46814#L763-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 46287#L342 assume !(1 == ~t2_pc~0); 46288#L342-2 is_transmit2_triggered_~__retres1~2 := 0; 46410#L353 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 46411#L354 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 46807#L771 assume !(0 != activate_threads_~tmp___1~0); 46719#L771-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 46607#L361 assume !(1 == ~t3_pc~0); 46608#L361-2 is_transmit3_triggered_~__retres1~3 := 0; 46635#L372 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 46454#L373 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 46455#L779 assume !(0 != activate_threads_~tmp___2~0); 46299#L779-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 46300#L380 assume !(1 == ~t4_pc~0); 46604#L380-2 is_transmit4_triggered_~__retres1~4 := 0; 46735#L391 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 46736#L392 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 46647#L787 assume !(0 != activate_threads_~tmp___3~0); 46648#L787-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 46362#L399 assume !(1 == ~t5_pc~0); 46363#L399-2 is_transmit5_triggered_~__retres1~5 := 0; 46503#L410 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 46748#L411 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 46493#L795 assume !(0 != activate_threads_~tmp___4~0); 46494#L795-2 assume !(1 == ~M_E~0); 46734#L679-1 assume !(1 == ~T1_E~0); 46423#L684-1 assume !(1 == ~T2_E~0); 46424#L689-1 assume !(1 == ~T3_E~0); 46619#L694-1 assume !(1 == ~T4_E~0); 46617#L699-1 assume !(1 == ~T5_E~0); 46618#L704-1 assume !(1 == ~E_M~0); 46593#L709-1 assume !(1 == ~E_1~0); 46535#L714-1 assume !(1 == ~E_2~0); 46536#L719-1 assume !(1 == ~E_3~0); 46712#L724-1 assume !(1 == ~E_4~0); 46329#L729-1 assume !(1 == ~E_5~0); 46330#L940-1 [2021-11-09 09:42:04,969 INFO L793 eck$LassoCheckResult]: Loop: 46330#L940-1 assume !false; 47881#L941 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 47876#L586 assume !false; 47873#L507 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 47861#L464 assume !(0 == ~m_st~0); 47862#L468 assume !(0 == ~t1_st~0); 47865#L472 assume !(0 == ~t2_st~0); 47867#L476 assume !(0 == ~t3_st~0); 47863#L480 assume !(0 == ~t4_st~0); 47864#L484 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 47866#L496 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 47384#L497 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 47385#L511 assume !(0 != eval_~tmp~0); 48323#L601 start_simulation_~kernel_st~0 := 2; 48321#L419-1 start_simulation_~kernel_st~0 := 3; 48319#L611-2 assume 0 == ~M_E~0;~M_E~0 := 1; 48317#L611-4 assume !(0 == ~T1_E~0); 48315#L616-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 48313#L621-3 assume !(0 == ~T3_E~0); 48311#L626-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 48309#L631-3 assume !(0 == ~T5_E~0); 48307#L636-3 assume 0 == ~E_M~0;~E_M~0 := 1; 48305#L641-3 assume 0 == ~E_1~0;~E_1~0 := 1; 48303#L646-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48301#L651-3 assume !(0 == ~E_3~0); 48299#L656-3 assume 0 == ~E_4~0;~E_4~0 := 1; 48297#L661-3 assume !(0 == ~E_5~0); 48295#L666-3 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 48293#L304-21 assume !(1 == ~m_pc~0); 48291#L304-23 is_master_triggered_~__retres1~0 := 0; 48289#L315-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 48287#L316-7 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 48285#L755-21 assume !(0 != activate_threads_~tmp~1); 48281#L755-23 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 48277#L323-21 assume 1 == ~t1_pc~0; 48272#L324-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 48265#L334-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 48260#L335-7 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 48066#L763-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 48067#L763-23 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 48049#L342-21 assume !(1 == ~t2_pc~0); 48048#L342-23 is_transmit2_triggered_~__retres1~2 := 0; 48047#L353-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 48046#L354-7 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 48045#L771-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 48043#L771-23 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 48041#L361-21 assume !(1 == ~t3_pc~0); 48038#L361-23 is_transmit3_triggered_~__retres1~3 := 0; 48036#L372-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 48034#L373-7 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 48032#L779-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 48030#L779-23 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 48027#L380-21 assume !(1 == ~t4_pc~0); 48025#L380-23 is_transmit4_triggered_~__retres1~4 := 0; 48023#L391-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 48021#L392-7 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 48019#L787-21 assume !(0 != activate_threads_~tmp___3~0); 48017#L787-23 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 48015#L399-21 assume !(1 == ~t5_pc~0); 48012#L399-23 is_transmit5_triggered_~__retres1~5 := 0; 48010#L410-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 48008#L411-7 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 48005#L795-21 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 48001#L795-23 assume 1 == ~M_E~0;~M_E~0 := 2; 47998#L679-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 47995#L684-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47992#L689-3 assume !(1 == ~T3_E~0); 47989#L694-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47986#L699-3 assume !(1 == ~T5_E~0); 47982#L704-3 assume 1 == ~E_M~0;~E_M~0 := 2; 47979#L709-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47976#L714-3 assume 1 == ~E_2~0;~E_2~0 := 2; 47973#L719-3 assume 1 == ~E_3~0;~E_3~0 := 2; 47969#L724-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47965#L729-3 assume !(1 == ~E_5~0); 47962#L734-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 47956#L464-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 47948#L496-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 47944#L497-1 start_simulation_#t~ret23 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret23;havoc start_simulation_#t~ret23; 47939#L959 assume !(0 == start_simulation_~tmp~3); 47937#L959-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret22, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 47927#L464-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 47920#L496-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 47915#L497-2 stop_simulation_#t~ret22 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret22;havoc stop_simulation_#t~ret22; 47910#L914 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 47903#L921 stop_simulation_#res := stop_simulation_~__retres2~0; 47899#L922 start_simulation_#t~ret24 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret24;havoc start_simulation_#t~ret24; 47894#L972 assume !(0 != start_simulation_~tmp___0~1); 46330#L940-1 [2021-11-09 09:42:04,969 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:04,970 INFO L85 PathProgramCache]: Analyzing trace with hash 2099374273, now seen corresponding path program 3 times [2021-11-09 09:42:04,970 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:04,970 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1835100724] [2021-11-09 09:42:04,971 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:04,971 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:04,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:04,983 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:42:04,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:05,016 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:42:05,017 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:05,017 INFO L85 PathProgramCache]: Analyzing trace with hash -1899625596, now seen corresponding path program 1 times [2021-11-09 09:42:05,018 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:05,018 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1680321430] [2021-11-09 09:42:05,018 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:05,018 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:05,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:05,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:05,054 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:05,054 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1680321430] [2021-11-09 09:42:05,054 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1680321430] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:05,054 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:05,055 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:42:05,055 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1556610950] [2021-11-09 09:42:05,055 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:42:05,056 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:42:05,056 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:42:05,056 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:42:05,057 INFO L87 Difference]: Start difference. First operand 3371 states and 4696 transitions. cyclomatic complexity: 1329 Second operand has 3 states, 3 states have (on average 29.333333333333332) internal successors, (88), 3 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:05,195 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:42:05,195 INFO L93 Difference]: Finished difference Result 5773 states and 7922 transitions. [2021-11-09 09:42:05,196 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:42:05,196 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5773 states and 7922 transitions. [2021-11-09 09:42:05,237 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5676 [2021-11-09 09:42:05,265 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5773 states to 5773 states and 7922 transitions. [2021-11-09 09:42:05,266 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5773 [2021-11-09 09:42:05,273 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5773 [2021-11-09 09:42:05,273 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5773 states and 7922 transitions. [2021-11-09 09:42:05,282 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:42:05,282 INFO L681 BuchiCegarLoop]: Abstraction has 5773 states and 7922 transitions. [2021-11-09 09:42:05,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5773 states and 7922 transitions. [2021-11-09 09:42:05,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5773 to 5621. [2021-11-09 09:42:05,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5621 states, 5621 states have (on average 1.3737769080234834) internal successors, (7722), 5620 states have internal predecessors, (7722), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:05,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5621 states to 5621 states and 7722 transitions. [2021-11-09 09:42:05,418 INFO L704 BuchiCegarLoop]: Abstraction has 5621 states and 7722 transitions. [2021-11-09 09:42:05,418 INFO L587 BuchiCegarLoop]: Abstraction has 5621 states and 7722 transitions. [2021-11-09 09:42:05,418 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-09 09:42:05,419 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5621 states and 7722 transitions. [2021-11-09 09:42:05,447 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5524 [2021-11-09 09:42:05,447 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:42:05,447 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:42:05,448 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:05,449 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:05,449 INFO L791 eck$LassoCheckResult]: Stem: 55974#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 55939#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 55776#L903 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 55366#L419 assume 1 == ~m_i~0;~m_st~0 := 0; 55367#L426-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55637#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55638#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55610#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55611#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 55856#L451-1 assume !(0 == ~M_E~0); 55857#L611-1 assume !(0 == ~T1_E~0); 55875#L616-1 assume !(0 == ~T2_E~0); 55876#L621-1 assume !(0 == ~T3_E~0); 55489#L626-1 assume !(0 == ~T4_E~0); 55490#L631-1 assume !(0 == ~T5_E~0); 55677#L636-1 assume !(0 == ~E_M~0); 55530#L641-1 assume !(0 == ~E_1~0); 55531#L646-1 assume !(0 == ~E_2~0); 55693#L651-1 assume !(0 == ~E_3~0); 55926#L656-1 assume !(0 == ~E_4~0); 55854#L661-1 assume !(0 == ~E_5~0); 55855#L666-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 55894#L304 assume !(1 == ~m_pc~0); 55547#L304-2 is_master_triggered_~__retres1~0 := 0; 55469#L315 is_master_triggered_#res := is_master_triggered_~__retres1~0; 55470#L316 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 55412#L755 assume !(0 != activate_threads_~tmp~1); 55413#L755-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 55368#L323 assume !(1 == ~t1_pc~0); 55369#L323-2 is_transmit1_triggered_~__retres1~1 := 0; 55743#L334 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 55982#L335 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 55952#L763 assume !(0 != activate_threads_~tmp___0~0); 55953#L763-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 55436#L342 assume !(1 == ~t2_pc~0); 55437#L342-2 is_transmit2_triggered_~__retres1~2 := 0; 55553#L353 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 55554#L354 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 55945#L771 assume !(0 != activate_threads_~tmp___1~0); 55849#L771-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 55755#L361 assume !(1 == ~t3_pc~0); 55756#L361-2 is_transmit3_triggered_~__retres1~3 := 0; 55777#L372 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 55598#L373 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 55599#L779 assume !(0 != activate_threads_~tmp___2~0); 55448#L779-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 55449#L380 assume !(1 == ~t4_pc~0); 55752#L380-2 is_transmit4_triggered_~__retres1~4 := 0; 55865#L391 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 55866#L392 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 55788#L787 assume !(0 != activate_threads_~tmp___3~0); 55789#L787-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 55511#L399 assume !(1 == ~t5_pc~0); 55512#L399-2 is_transmit5_triggered_~__retres1~5 := 0; 55648#L410 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 55879#L411 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 55639#L795 assume !(0 != activate_threads_~tmp___4~0); 55640#L795-2 assume !(1 == ~M_E~0); 55864#L679-1 assume !(1 == ~T1_E~0); 55566#L684-1 assume !(1 == ~T2_E~0); 55567#L689-1 assume !(1 == ~T3_E~0); 55768#L694-1 assume !(1 == ~T4_E~0); 55766#L699-1 assume !(1 == ~T5_E~0); 55767#L704-1 assume !(1 == ~E_M~0); 55742#L709-1 assume !(1 == ~E_1~0); 55681#L714-1 assume !(1 == ~E_2~0); 55682#L719-1 assume !(1 == ~E_3~0); 55845#L724-1 assume !(1 == ~E_4~0); 55479#L729-1 assume !(1 == ~E_5~0); 55480#L940-1 assume !false; 59178#L941 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 59177#L586 [2021-11-09 09:42:05,449 INFO L793 eck$LassoCheckResult]: Loop: 59177#L586 assume !false; 59175#L507 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 59170#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 59046#L496 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 59035#L497 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 58621#L511 assume 0 != eval_~tmp~0; 58620#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 58618#L519 assume !(0 != eval_~tmp_ndt_1~0); 58619#L516 assume !(0 == ~t1_st~0); 58855#L530 assume !(0 == ~t2_st~0); 58853#L544 assume !(0 == ~t3_st~0); 59201#L558 assume !(0 == ~t4_st~0); 59182#L572 assume !(0 == ~t5_st~0); 59177#L586 [2021-11-09 09:42:05,450 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:05,450 INFO L85 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 1 times [2021-11-09 09:42:05,450 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:05,451 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10479335] [2021-11-09 09:42:05,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:05,451 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:05,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:05,463 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:42:05,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:05,496 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:42:05,497 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:05,497 INFO L85 PathProgramCache]: Analyzing trace with hash -1634271327, now seen corresponding path program 1 times [2021-11-09 09:42:05,498 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:05,498 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [58705127] [2021-11-09 09:42:05,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:05,498 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:05,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:05,503 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:42:05,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:05,508 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:42:05,509 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:05,509 INFO L85 PathProgramCache]: Analyzing trace with hash -1605223329, now seen corresponding path program 1 times [2021-11-09 09:42:05,509 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:05,510 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [188490286] [2021-11-09 09:42:05,510 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:05,510 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:05,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:05,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:05,549 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:05,549 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [188490286] [2021-11-09 09:42:05,549 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [188490286] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:05,550 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:05,550 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:42:05,550 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [922915537] [2021-11-09 09:42:05,689 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:42:05,690 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:42:05,690 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:42:05,690 INFO L87 Difference]: Start difference. First operand 5621 states and 7722 transitions. cyclomatic complexity: 2107 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:05,862 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:42:05,873 INFO L93 Difference]: Finished difference Result 10485 states and 14302 transitions. [2021-11-09 09:42:05,885 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:42:05,885 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10485 states and 14302 transitions. [2021-11-09 09:42:05,966 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 10296 [2021-11-09 09:42:06,085 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10485 states to 10485 states and 14302 transitions. [2021-11-09 09:42:06,085 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10485 [2021-11-09 09:42:06,099 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10485 [2021-11-09 09:42:06,099 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10485 states and 14302 transitions. [2021-11-09 09:42:06,111 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:42:06,111 INFO L681 BuchiCegarLoop]: Abstraction has 10485 states and 14302 transitions. [2021-11-09 09:42:06,122 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10485 states and 14302 transitions. [2021-11-09 09:42:06,312 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10485 to 10005. [2021-11-09 09:42:06,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10005 states, 10005 states have (on average 1.3671164417791104) internal successors, (13678), 10004 states have internal predecessors, (13678), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:06,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10005 states to 10005 states and 13678 transitions. [2021-11-09 09:42:06,366 INFO L704 BuchiCegarLoop]: Abstraction has 10005 states and 13678 transitions. [2021-11-09 09:42:06,366 INFO L587 BuchiCegarLoop]: Abstraction has 10005 states and 13678 transitions. [2021-11-09 09:42:06,366 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-09 09:42:06,366 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10005 states and 13678 transitions. [2021-11-09 09:42:06,407 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 9816 [2021-11-09 09:42:06,407 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:42:06,407 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:42:06,408 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:06,409 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:06,409 INFO L791 eck$LassoCheckResult]: Stem: 72112#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 72077#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 71897#L903 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 71484#L419 assume 1 == ~m_i~0;~m_st~0 := 0; 71485#L426-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 71998#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75246#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75245#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75244#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 75243#L451-1 assume !(0 == ~M_E~0); 75242#L611-1 assume !(0 == ~T1_E~0); 75241#L616-1 assume !(0 == ~T2_E~0); 75240#L621-1 assume !(0 == ~T3_E~0); 75239#L626-1 assume !(0 == ~T4_E~0); 75238#L631-1 assume !(0 == ~T5_E~0); 75237#L636-1 assume !(0 == ~E_M~0); 75236#L641-1 assume !(0 == ~E_1~0); 75235#L646-1 assume !(0 == ~E_2~0); 75234#L651-1 assume !(0 == ~E_3~0); 75233#L656-1 assume !(0 == ~E_4~0); 75232#L661-1 assume !(0 == ~E_5~0); 75231#L666-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 75230#L304 assume !(1 == ~m_pc~0); 75229#L304-2 is_master_triggered_~__retres1~0 := 0; 75228#L315 is_master_triggered_#res := is_master_triggered_~__retres1~0; 75227#L316 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 75226#L755 assume !(0 != activate_threads_~tmp~1); 75225#L755-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 75224#L323 assume !(1 == ~t1_pc~0); 75223#L323-2 is_transmit1_triggered_~__retres1~1 := 0; 75248#L334 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 75247#L335 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 75218#L763 assume !(0 != activate_threads_~tmp___0~0); 75217#L763-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 75216#L342 assume !(1 == ~t2_pc~0); 75215#L342-2 is_transmit2_triggered_~__retres1~2 := 0; 75214#L353 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 75213#L354 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 75212#L771 assume !(0 != activate_threads_~tmp___1~0); 75211#L771-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 75210#L361 assume !(1 == ~t3_pc~0); 75208#L361-2 is_transmit3_triggered_~__retres1~3 := 0; 75207#L372 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 75206#L373 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 75205#L779 assume !(0 != activate_threads_~tmp___2~0); 75204#L779-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 75203#L380 assume !(1 == ~t4_pc~0); 75202#L380-2 is_transmit4_triggered_~__retres1~4 := 0; 75201#L391 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 75200#L392 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 75199#L787 assume !(0 != activate_threads_~tmp___3~0); 75198#L787-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 75196#L399 assume !(1 == ~t5_pc~0); 75195#L399-2 is_transmit5_triggered_~__retres1~5 := 0; 75194#L410 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 75192#L411 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 75190#L795 assume !(0 != activate_threads_~tmp___4~0); 75188#L795-2 assume !(1 == ~M_E~0); 75186#L679-1 assume !(1 == ~T1_E~0); 75184#L684-1 assume !(1 == ~T2_E~0); 75182#L689-1 assume !(1 == ~T3_E~0); 75180#L694-1 assume !(1 == ~T4_E~0); 75177#L699-1 assume !(1 == ~T5_E~0); 75175#L704-1 assume !(1 == ~E_M~0); 75173#L709-1 assume !(1 == ~E_1~0); 75171#L714-1 assume !(1 == ~E_2~0); 75169#L719-1 assume !(1 == ~E_3~0); 75167#L724-1 assume !(1 == ~E_4~0); 75165#L729-1 assume !(1 == ~E_5~0); 75163#L940-1 assume !false; 75078#L941 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 75077#L586 [2021-11-09 09:42:06,409 INFO L793 eck$LassoCheckResult]: Loop: 75077#L586 assume !false; 75074#L507 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 75071#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 75069#L496 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 75067#L497 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 75065#L511 assume 0 != eval_~tmp~0; 75060#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 75057#L519 assume !(0 != eval_~tmp_ndt_1~0); 75058#L516 assume !(0 == ~t1_st~0); 75095#L530 assume !(0 == ~t2_st~0); 75091#L544 assume !(0 == ~t3_st~0); 75086#L558 assume !(0 == ~t4_st~0); 75082#L572 assume !(0 == ~t5_st~0); 75077#L586 [2021-11-09 09:42:06,410 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:06,410 INFO L85 PathProgramCache]: Analyzing trace with hash 1942871557, now seen corresponding path program 1 times [2021-11-09 09:42:06,410 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:06,411 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1094062552] [2021-11-09 09:42:06,411 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:06,411 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:06,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:06,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:06,436 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:06,436 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1094062552] [2021-11-09 09:42:06,436 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1094062552] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:06,436 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:06,436 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:42:06,437 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1131676539] [2021-11-09 09:42:06,437 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:42:06,437 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:06,438 INFO L85 PathProgramCache]: Analyzing trace with hash -1634271327, now seen corresponding path program 2 times [2021-11-09 09:42:06,438 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:06,438 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1626400841] [2021-11-09 09:42:06,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:06,439 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:06,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:06,443 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:42:06,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:06,448 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:42:06,563 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:42:06,564 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:42:06,564 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:42:06,565 INFO L87 Difference]: Start difference. First operand 10005 states and 13678 transitions. cyclomatic complexity: 3679 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:06,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:42:06,748 INFO L93 Difference]: Finished difference Result 9933 states and 13577 transitions. [2021-11-09 09:42:06,749 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:42:06,749 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9933 states and 13577 transitions. [2021-11-09 09:42:06,910 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 9816 [2021-11-09 09:42:06,951 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9933 states to 9933 states and 13577 transitions. [2021-11-09 09:42:06,951 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9933 [2021-11-09 09:42:06,959 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9933 [2021-11-09 09:42:06,959 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9933 states and 13577 transitions. [2021-11-09 09:42:06,969 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:42:06,970 INFO L681 BuchiCegarLoop]: Abstraction has 9933 states and 13577 transitions. [2021-11-09 09:42:06,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9933 states and 13577 transitions. [2021-11-09 09:42:07,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9933 to 9933. [2021-11-09 09:42:07,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9933 states, 9933 states have (on average 1.366857948253297) internal successors, (13577), 9932 states have internal predecessors, (13577), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:07,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9933 states to 9933 states and 13577 transitions. [2021-11-09 09:42:07,282 INFO L704 BuchiCegarLoop]: Abstraction has 9933 states and 13577 transitions. [2021-11-09 09:42:07,282 INFO L587 BuchiCegarLoop]: Abstraction has 9933 states and 13577 transitions. [2021-11-09 09:42:07,282 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-09 09:42:07,282 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9933 states and 13577 transitions. [2021-11-09 09:42:07,322 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 9816 [2021-11-09 09:42:07,322 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:42:07,323 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:42:07,324 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:07,324 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:07,324 INFO L791 eck$LassoCheckResult]: Stem: 92098#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 92054#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 91851#L903 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 91428#L419 assume 1 == ~m_i~0;~m_st~0 := 0; 91429#L426-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 91703#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 91704#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 91677#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 91678#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 91948#L451-1 assume !(0 == ~M_E~0); 91949#L611-1 assume !(0 == ~T1_E~0); 91969#L616-1 assume !(0 == ~T2_E~0); 91970#L621-1 assume !(0 == ~T3_E~0); 91556#L626-1 assume !(0 == ~T4_E~0); 91557#L631-1 assume !(0 == ~T5_E~0); 91748#L636-1 assume !(0 == ~E_M~0); 91595#L641-1 assume !(0 == ~E_1~0); 91596#L646-1 assume !(0 == ~E_2~0); 91761#L651-1 assume !(0 == ~E_3~0); 92038#L656-1 assume !(0 == ~E_4~0); 91946#L661-1 assume !(0 == ~E_5~0); 91947#L666-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 91996#L304 assume !(1 == ~m_pc~0); 91616#L304-2 is_master_triggered_~__retres1~0 := 0; 91528#L315 is_master_triggered_#res := is_master_triggered_~__retres1~0; 91529#L316 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 91475#L755 assume !(0 != activate_threads_~tmp~1); 91476#L755-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 91430#L323 assume !(1 == ~t1_pc~0); 91431#L323-2 is_transmit1_triggered_~__retres1~1 := 0; 91813#L334 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 92108#L335 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 92071#L763 assume !(0 != activate_threads_~tmp___0~0); 92072#L763-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 91499#L342 assume !(1 == ~t2_pc~0); 91500#L342-2 is_transmit2_triggered_~__retres1~2 := 0; 91618#L353 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 91619#L354 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 92064#L771 assume !(0 != activate_threads_~tmp___1~0); 91942#L771-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 91827#L361 assume !(1 == ~t3_pc~0); 91828#L361-2 is_transmit3_triggered_~__retres1~3 := 0; 91852#L372 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 91665#L373 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 91666#L779 assume !(0 != activate_threads_~tmp___2~0); 91510#L779-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 91511#L380 assume !(1 == ~t4_pc~0); 91824#L380-2 is_transmit4_triggered_~__retres1~4 := 0; 91960#L391 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 91961#L392 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 91862#L787 assume !(0 != activate_threads_~tmp___3~0); 91863#L787-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 91573#L399 assume !(1 == ~t5_pc~0); 91574#L399-2 is_transmit5_triggered_~__retres1~5 := 0; 91715#L410 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 91974#L411 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 91705#L795 assume !(0 != activate_threads_~tmp___4~0); 91706#L795-2 assume !(1 == ~M_E~0); 91957#L679-1 assume !(1 == ~T1_E~0); 91632#L684-1 assume !(1 == ~T2_E~0); 91633#L689-1 assume !(1 == ~T3_E~0); 91840#L694-1 assume !(1 == ~T4_E~0); 91838#L699-1 assume !(1 == ~T5_E~0); 91839#L704-1 assume !(1 == ~E_M~0); 91812#L709-1 assume !(1 == ~E_1~0); 91753#L714-1 assume !(1 == ~E_2~0); 91754#L719-1 assume !(1 == ~E_3~0); 91936#L724-1 assume !(1 == ~E_4~0); 91539#L729-1 assume !(1 == ~E_5~0); 91540#L940-1 assume !false; 94808#L941 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 94806#L586 [2021-11-09 09:42:07,325 INFO L793 eck$LassoCheckResult]: Loop: 94806#L586 assume !false; 94804#L507 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 94802#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 94800#L496 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 94799#L497 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 94797#L511 assume 0 != eval_~tmp~0; 94795#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 94792#L519 assume !(0 != eval_~tmp_ndt_1~0); 94790#L516 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 94720#L533 assume !(0 != eval_~tmp_ndt_2~0); 94788#L530 assume !(0 == ~t2_st~0); 94821#L544 assume !(0 == ~t3_st~0); 94815#L558 assume !(0 == ~t4_st~0); 94812#L572 assume !(0 == ~t5_st~0); 94806#L586 [2021-11-09 09:42:07,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:07,326 INFO L85 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 2 times [2021-11-09 09:42:07,326 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:07,326 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1598074521] [2021-11-09 09:42:07,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:07,327 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:07,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:07,341 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:42:07,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:07,393 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:42:07,394 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:07,395 INFO L85 PathProgramCache]: Analyzing trace with hash -11527191, now seen corresponding path program 1 times [2021-11-09 09:42:07,395 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:07,395 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1693100081] [2021-11-09 09:42:07,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:07,395 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:07,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:07,400 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:42:07,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:07,411 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:42:07,413 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:07,413 INFO L85 PathProgramCache]: Analyzing trace with hash 888960747, now seen corresponding path program 1 times [2021-11-09 09:42:07,413 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:07,413 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1111499035] [2021-11-09 09:42:07,414 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:07,414 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:07,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:07,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:07,455 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:07,455 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1111499035] [2021-11-09 09:42:07,456 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1111499035] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:07,456 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:07,456 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:42:07,456 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1754412331] [2021-11-09 09:42:07,616 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:42:07,617 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:42:07,617 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:42:07,617 INFO L87 Difference]: Start difference. First operand 9933 states and 13577 transitions. cyclomatic complexity: 3650 Second operand has 3 states, 3 states have (on average 28.333333333333332) internal successors, (85), 3 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:07,829 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:42:07,829 INFO L93 Difference]: Finished difference Result 18745 states and 25501 transitions. [2021-11-09 09:42:07,830 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:42:07,830 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18745 states and 25501 transitions. [2021-11-09 09:42:07,931 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 18588 [2021-11-09 09:42:08,012 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18745 states to 18745 states and 25501 transitions. [2021-11-09 09:42:08,012 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18745 [2021-11-09 09:42:08,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18745 [2021-11-09 09:42:08,025 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18745 states and 25501 transitions. [2021-11-09 09:42:08,042 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:42:08,042 INFO L681 BuchiCegarLoop]: Abstraction has 18745 states and 25501 transitions. [2021-11-09 09:42:08,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18745 states and 25501 transitions. [2021-11-09 09:42:08,448 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18745 to 18369. [2021-11-09 09:42:08,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18369 states, 18369 states have (on average 1.3616963362186292) internal successors, (25013), 18368 states have internal predecessors, (25013), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:08,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18369 states to 18369 states and 25013 transitions. [2021-11-09 09:42:08,557 INFO L704 BuchiCegarLoop]: Abstraction has 18369 states and 25013 transitions. [2021-11-09 09:42:08,558 INFO L587 BuchiCegarLoop]: Abstraction has 18369 states and 25013 transitions. [2021-11-09 09:42:08,558 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-09 09:42:08,558 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18369 states and 25013 transitions. [2021-11-09 09:42:08,750 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 18212 [2021-11-09 09:42:08,750 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:42:08,751 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:42:08,752 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:08,752 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:08,752 INFO L791 eck$LassoCheckResult]: Stem: 120751#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 120722#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 120529#L903 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 120110#L419 assume 1 == ~m_i~0;~m_st~0 := 0; 120111#L426-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 120381#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 120382#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 120357#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 120358#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 120628#L451-1 assume !(0 == ~M_E~0); 120629#L611-1 assume !(0 == ~T1_E~0); 120647#L616-1 assume !(0 == ~T2_E~0); 120648#L621-1 assume !(0 == ~T3_E~0); 120235#L626-1 assume !(0 == ~T4_E~0); 120236#L631-1 assume !(0 == ~T5_E~0); 120422#L636-1 assume !(0 == ~E_M~0); 120277#L641-1 assume !(0 == ~E_1~0); 120278#L646-1 assume !(0 == ~E_2~0); 120438#L651-1 assume !(0 == ~E_3~0); 120710#L656-1 assume !(0 == ~E_4~0); 120626#L661-1 assume !(0 == ~E_5~0); 120627#L666-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 120674#L304 assume !(1 == ~m_pc~0); 120294#L304-2 is_master_triggered_~__retres1~0 := 0; 120215#L315 is_master_triggered_#res := is_master_triggered_~__retres1~0; 120216#L316 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 120156#L755 assume !(0 != activate_threads_~tmp~1); 120157#L755-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 120112#L323 assume !(1 == ~t1_pc~0); 120113#L323-2 is_transmit1_triggered_~__retres1~1 := 0; 120492#L334 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 120758#L335 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 120732#L763 assume !(0 != activate_threads_~tmp___0~0); 120733#L763-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 120181#L342 assume !(1 == ~t2_pc~0); 120182#L342-2 is_transmit2_triggered_~__retres1~2 := 0; 120301#L353 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 120302#L354 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 120728#L771 assume !(0 != activate_threads_~tmp___1~0); 120619#L771-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 120506#L361 assume !(1 == ~t3_pc~0); 120507#L361-2 is_transmit3_triggered_~__retres1~3 := 0; 120531#L372 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 120344#L373 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 120345#L779 assume !(0 != activate_threads_~tmp___2~0); 120194#L779-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 120195#L380 assume !(1 == ~t4_pc~0); 120503#L380-2 is_transmit4_triggered_~__retres1~4 := 0; 120638#L391 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 120639#L392 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 120542#L787 assume !(0 != activate_threads_~tmp___3~0); 120543#L787-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 120258#L399 assume !(1 == ~t5_pc~0); 120259#L399-2 is_transmit5_triggered_~__retres1~5 := 0; 120393#L410 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 120654#L411 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 120383#L795 assume !(0 != activate_threads_~tmp___4~0); 120384#L795-2 assume !(1 == ~M_E~0); 120637#L679-1 assume !(1 == ~T1_E~0); 120314#L684-1 assume !(1 == ~T2_E~0); 120315#L689-1 assume !(1 == ~T3_E~0); 120520#L694-1 assume !(1 == ~T4_E~0); 120518#L699-1 assume !(1 == ~T5_E~0); 120519#L704-1 assume !(1 == ~E_M~0); 120491#L709-1 assume !(1 == ~E_1~0); 120426#L714-1 assume !(1 == ~E_2~0); 120427#L719-1 assume !(1 == ~E_3~0); 120611#L724-1 assume !(1 == ~E_4~0); 120225#L729-1 assume !(1 == ~E_5~0); 120226#L940-1 assume !false; 131472#L941 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 131470#L586 [2021-11-09 09:42:08,753 INFO L793 eck$LassoCheckResult]: Loop: 131470#L586 assume !false; 130064#L507 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 130062#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 130060#L496 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 130058#L497 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 130057#L511 assume 0 != eval_~tmp~0; 130056#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 130053#L519 assume !(0 != eval_~tmp_ndt_1~0); 126833#L516 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 126827#L533 assume !(0 != eval_~tmp_ndt_2~0); 126763#L530 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 126760#L547 assume !(0 != eval_~tmp_ndt_3~0); 126761#L544 assume !(0 == ~t3_st~0); 128719#L558 assume !(0 == ~t4_st~0); 128543#L572 assume !(0 == ~t5_st~0); 131470#L586 [2021-11-09 09:42:08,753 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:08,753 INFO L85 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 3 times [2021-11-09 09:42:08,754 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:08,754 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [752078833] [2021-11-09 09:42:08,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:08,754 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:08,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:08,767 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:42:08,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:08,799 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:42:08,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:08,800 INFO L85 PathProgramCache]: Analyzing trace with hash -524557124, now seen corresponding path program 1 times [2021-11-09 09:42:08,800 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:08,801 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [428355539] [2021-11-09 09:42:08,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:08,801 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:08,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:08,806 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:42:08,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:08,812 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:42:08,813 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:08,813 INFO L85 PathProgramCache]: Analyzing trace with hash 1620765178, now seen corresponding path program 1 times [2021-11-09 09:42:08,813 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:08,813 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1879834353] [2021-11-09 09:42:08,814 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:08,814 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:08,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:08,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:08,854 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:08,855 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1879834353] [2021-11-09 09:42:08,855 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1879834353] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:08,855 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:08,855 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:42:08,856 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1491359153] [2021-11-09 09:42:09,118 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:42:09,118 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:42:09,119 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:42:09,119 INFO L87 Difference]: Start difference. First operand 18369 states and 25013 transitions. cyclomatic complexity: 6650 Second operand has 3 states, 3 states have (on average 28.666666666666668) internal successors, (86), 3 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:09,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:42:09,329 INFO L93 Difference]: Finished difference Result 33593 states and 45597 transitions. [2021-11-09 09:42:09,330 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:42:09,330 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33593 states and 45597 transitions. [2021-11-09 09:42:09,654 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 33356 [2021-11-09 09:42:09,806 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33593 states to 33593 states and 45597 transitions. [2021-11-09 09:42:09,806 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33593 [2021-11-09 09:42:09,829 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33593 [2021-11-09 09:42:09,829 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33593 states and 45597 transitions. [2021-11-09 09:42:09,860 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:42:09,860 INFO L681 BuchiCegarLoop]: Abstraction has 33593 states and 45597 transitions. [2021-11-09 09:42:09,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33593 states and 45597 transitions. [2021-11-09 09:42:10,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33593 to 32537. [2021-11-09 09:42:10,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32537 states, 32537 states have (on average 1.3610658634785013) internal successors, (44285), 32536 states have internal predecessors, (44285), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:10,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32537 states to 32537 states and 44285 transitions. [2021-11-09 09:42:10,629 INFO L704 BuchiCegarLoop]: Abstraction has 32537 states and 44285 transitions. [2021-11-09 09:42:10,629 INFO L587 BuchiCegarLoop]: Abstraction has 32537 states and 44285 transitions. [2021-11-09 09:42:10,629 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-09 09:42:10,629 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32537 states and 44285 transitions. [2021-11-09 09:42:11,001 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 32300 [2021-11-09 09:42:11,002 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:42:11,002 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:42:11,003 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:11,004 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:11,004 INFO L791 eck$LassoCheckResult]: Stem: 172726#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 172694#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 172509#L903 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 172080#L419 assume 1 == ~m_i~0;~m_st~0 := 0; 172081#L426-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 172351#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 172352#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 172328#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 172329#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 172613#L451-1 assume !(0 == ~M_E~0); 172614#L611-1 assume !(0 == ~T1_E~0); 172631#L616-1 assume !(0 == ~T2_E~0); 172632#L621-1 assume !(0 == ~T3_E~0); 172202#L626-1 assume !(0 == ~T4_E~0); 172203#L631-1 assume !(0 == ~T5_E~0); 172394#L636-1 assume !(0 == ~E_M~0); 172245#L641-1 assume !(0 == ~E_1~0); 172246#L646-1 assume !(0 == ~E_2~0); 172413#L651-1 assume !(0 == ~E_3~0); 172680#L656-1 assume !(0 == ~E_4~0); 172611#L661-1 assume !(0 == ~E_5~0); 172612#L666-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 172653#L304 assume !(1 == ~m_pc~0); 172263#L304-2 is_master_triggered_~__retres1~0 := 0; 172182#L315 is_master_triggered_#res := is_master_triggered_~__retres1~0; 172183#L316 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 172126#L755 assume !(0 != activate_threads_~tmp~1); 172127#L755-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 172082#L323 assume !(1 == ~t1_pc~0); 172083#L323-2 is_transmit1_triggered_~__retres1~1 := 0; 172468#L334 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 172733#L335 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 172706#L763 assume !(0 != activate_threads_~tmp___0~0); 172707#L763-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 172150#L342 assume !(1 == ~t2_pc~0); 172151#L342-2 is_transmit2_triggered_~__retres1~2 := 0; 172268#L353 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 172269#L354 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 172701#L771 assume !(0 != activate_threads_~tmp___1~0); 172606#L771-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 172480#L361 assume !(1 == ~t3_pc~0); 172481#L361-2 is_transmit3_triggered_~__retres1~3 := 0; 172511#L372 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 172315#L373 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 172316#L779 assume !(0 != activate_threads_~tmp___2~0); 172162#L779-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 172163#L380 assume !(1 == ~t4_pc~0); 172477#L380-2 is_transmit4_triggered_~__retres1~4 := 0; 172622#L391 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 172623#L392 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 172525#L787 assume !(0 != activate_threads_~tmp___3~0); 172526#L787-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 172226#L399 assume !(1 == ~t5_pc~0); 172227#L399-2 is_transmit5_triggered_~__retres1~5 := 0; 172364#L410 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 172637#L411 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 172353#L795 assume !(0 != activate_threads_~tmp___4~0); 172354#L795-2 assume !(1 == ~M_E~0); 172621#L679-1 assume !(1 == ~T1_E~0); 172281#L684-1 assume !(1 == ~T2_E~0); 172282#L689-1 assume !(1 == ~T3_E~0); 172497#L694-1 assume !(1 == ~T4_E~0); 172495#L699-1 assume !(1 == ~T5_E~0); 172496#L704-1 assume !(1 == ~E_M~0); 172467#L709-1 assume !(1 == ~E_1~0); 172400#L714-1 assume !(1 == ~E_2~0); 172401#L719-1 assume !(1 == ~E_3~0); 172599#L724-1 assume !(1 == ~E_4~0); 172192#L729-1 assume !(1 == ~E_5~0); 172193#L940-1 assume !false; 178149#L941 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 178147#L586 [2021-11-09 09:42:11,004 INFO L793 eck$LassoCheckResult]: Loop: 178147#L586 assume !false; 178145#L507 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 178142#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 178140#L496 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 178138#L497 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 178136#L511 assume 0 != eval_~tmp~0; 178132#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 178131#L519 assume !(0 != eval_~tmp_ndt_1~0); 177796#L516 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 177794#L533 assume !(0 != eval_~tmp_ndt_2~0); 177792#L530 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 174460#L547 assume !(0 != eval_~tmp_ndt_3~0); 177790#L544 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 176760#L561 assume !(0 != eval_~tmp_ndt_4~0); 178302#L558 assume !(0 == ~t4_st~0); 178153#L572 assume !(0 == ~t5_st~0); 178147#L586 [2021-11-09 09:42:11,005 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:11,005 INFO L85 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 4 times [2021-11-09 09:42:11,017 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:11,017 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1919758369] [2021-11-09 09:42:11,017 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:11,018 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:11,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:11,055 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:42:11,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:11,100 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:42:11,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:11,100 INFO L85 PathProgramCache]: Analyzing trace with hash 913205966, now seen corresponding path program 1 times [2021-11-09 09:42:11,101 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:11,101 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [437859227] [2021-11-09 09:42:11,101 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:11,101 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:11,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:11,106 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:42:11,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:11,112 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:42:11,113 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:11,113 INFO L85 PathProgramCache]: Analyzing trace with hash -1301279408, now seen corresponding path program 1 times [2021-11-09 09:42:11,113 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:11,113 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [447941043] [2021-11-09 09:42:11,114 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:11,114 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:11,126 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:11,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:11,154 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:11,154 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [447941043] [2021-11-09 09:42:11,154 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [447941043] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:11,155 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:11,155 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:42:11,155 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1522645006] [2021-11-09 09:42:11,368 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:42:11,369 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:42:11,369 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:42:11,370 INFO L87 Difference]: Start difference. First operand 32537 states and 44285 transitions. cyclomatic complexity: 11754 Second operand has 3 states, 3 states have (on average 29.0) internal successors, (87), 3 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:11,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:42:11,619 INFO L93 Difference]: Finished difference Result 41835 states and 56779 transitions. [2021-11-09 09:42:11,620 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:42:11,620 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41835 states and 56779 transitions. [2021-11-09 09:42:11,996 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 41582 [2021-11-09 09:42:12,291 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41835 states to 41835 states and 56779 transitions. [2021-11-09 09:42:12,291 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41835 [2021-11-09 09:42:12,318 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41835 [2021-11-09 09:42:12,318 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41835 states and 56779 transitions. [2021-11-09 09:42:12,361 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:42:12,361 INFO L681 BuchiCegarLoop]: Abstraction has 41835 states and 56779 transitions. [2021-11-09 09:42:12,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41835 states and 56779 transitions. [2021-11-09 09:42:12,915 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41835 to 41195. [2021-11-09 09:42:12,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41195 states, 41195 states have (on average 1.3581017113727394) internal successors, (55947), 41194 states have internal predecessors, (55947), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:13,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41195 states to 41195 states and 55947 transitions. [2021-11-09 09:42:13,116 INFO L704 BuchiCegarLoop]: Abstraction has 41195 states and 55947 transitions. [2021-11-09 09:42:13,116 INFO L587 BuchiCegarLoop]: Abstraction has 41195 states and 55947 transitions. [2021-11-09 09:42:13,117 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-09 09:42:13,117 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41195 states and 55947 transitions. [2021-11-09 09:42:13,314 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 40942 [2021-11-09 09:42:13,314 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:42:13,314 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:42:13,316 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:13,316 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:13,316 INFO L791 eck$LassoCheckResult]: Stem: 247139#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 247101#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 246887#L903 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 246460#L419 assume 1 == ~m_i~0;~m_st~0 := 0; 246461#L426-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 246732#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 246733#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 246708#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 246709#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 246997#L451-1 assume !(0 == ~M_E~0); 246998#L611-1 assume !(0 == ~T1_E~0); 247016#L616-1 assume !(0 == ~T2_E~0); 247017#L621-1 assume !(0 == ~T3_E~0); 246584#L626-1 assume !(0 == ~T4_E~0); 246585#L631-1 assume !(0 == ~T5_E~0); 246772#L636-1 assume !(0 == ~E_M~0); 246629#L641-1 assume !(0 == ~E_1~0); 246630#L646-1 assume !(0 == ~E_2~0); 246791#L651-1 assume !(0 == ~E_3~0); 247086#L656-1 assume !(0 == ~E_4~0); 246995#L661-1 assume !(0 == ~E_5~0); 246996#L666-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 247046#L304 assume !(1 == ~m_pc~0); 246647#L304-2 is_master_triggered_~__retres1~0 := 0; 246563#L315 is_master_triggered_#res := is_master_triggered_~__retres1~0; 246564#L316 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 246506#L755 assume !(0 != activate_threads_~tmp~1); 246507#L755-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 246462#L323 assume !(1 == ~t1_pc~0); 246463#L323-2 is_transmit1_triggered_~__retres1~1 := 0; 246844#L334 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 247150#L335 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 247115#L763 assume !(0 != activate_threads_~tmp___0~0); 247116#L763-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 246531#L342 assume !(1 == ~t2_pc~0); 246532#L342-2 is_transmit2_triggered_~__retres1~2 := 0; 246652#L353 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 246653#L354 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 247110#L771 assume !(0 != activate_threads_~tmp___1~0); 246990#L771-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 246858#L361 assume !(1 == ~t3_pc~0); 246859#L361-2 is_transmit3_triggered_~__retres1~3 := 0; 246889#L372 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 246696#L373 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 246697#L779 assume !(0 != activate_threads_~tmp___2~0); 246543#L779-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 246544#L380 assume !(1 == ~t4_pc~0); 246855#L380-2 is_transmit4_triggered_~__retres1~4 := 0; 247007#L391 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 247008#L392 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 246901#L787 assume !(0 != activate_threads_~tmp___3~0); 246902#L787-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 246607#L399 assume !(1 == ~t5_pc~0); 246608#L399-2 is_transmit5_triggered_~__retres1~5 := 0; 246744#L410 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 247024#L411 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 246734#L795 assume !(0 != activate_threads_~tmp___4~0); 246735#L795-2 assume !(1 == ~M_E~0); 247006#L679-1 assume !(1 == ~T1_E~0); 246666#L684-1 assume !(1 == ~T2_E~0); 246667#L689-1 assume !(1 == ~T3_E~0); 246874#L694-1 assume !(1 == ~T4_E~0); 246872#L699-1 assume !(1 == ~T5_E~0); 246873#L704-1 assume !(1 == ~E_M~0); 246843#L709-1 assume !(1 == ~E_1~0); 246779#L714-1 assume !(1 == ~E_2~0); 246780#L719-1 assume !(1 == ~E_3~0); 246981#L724-1 assume !(1 == ~E_4~0); 246574#L729-1 assume !(1 == ~E_5~0); 246575#L940-1 assume !false; 258702#L941 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 258703#L586 [2021-11-09 09:42:13,317 INFO L793 eck$LassoCheckResult]: Loop: 258703#L586 assume !false; 258697#L507 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 258698#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 258690#L496 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 258691#L497 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 258685#L511 assume 0 != eval_~tmp~0; 258686#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 261325#L519 assume !(0 != eval_~tmp_ndt_1~0); 255015#L516 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 252089#L533 assume !(0 != eval_~tmp_ndt_2~0); 251237#L530 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 251230#L547 assume !(0 != eval_~tmp_ndt_3~0); 251231#L544 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 254879#L561 assume !(0 != eval_~tmp_ndt_4~0); 255069#L558 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet14;havoc eval_#t~nondet14; 258709#L575 assume !(0 != eval_~tmp_ndt_5~0); 258707#L572 assume !(0 == ~t5_st~0); 258703#L586 [2021-11-09 09:42:13,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:13,318 INFO L85 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 5 times [2021-11-09 09:42:13,318 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:13,318 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [840664762] [2021-11-09 09:42:13,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:13,319 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:13,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:13,332 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:42:13,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:13,369 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:42:13,370 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:13,370 INFO L85 PathProgramCache]: Analyzing trace with hash -1755558441, now seen corresponding path program 1 times [2021-11-09 09:42:13,370 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:13,371 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [293222206] [2021-11-09 09:42:13,371 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:13,371 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:13,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:13,383 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:42:13,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:13,390 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:42:13,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:13,391 INFO L85 PathProgramCache]: Analyzing trace with hash -1685128299, now seen corresponding path program 1 times [2021-11-09 09:42:13,391 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:13,391 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [854915578] [2021-11-09 09:42:13,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:13,392 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:13,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:42:13,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:42:13,436 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:42:13,436 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [854915578] [2021-11-09 09:42:13,437 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [854915578] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:42:13,437 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:42:13,437 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-09 09:42:13,437 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [553001075] [2021-11-09 09:42:13,658 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:42:13,659 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:42:13,659 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:42:13,660 INFO L87 Difference]: Start difference. First operand 41195 states and 55947 transitions. cyclomatic complexity: 14758 Second operand has 3 states, 2 states have (on average 44.0) internal successors, (88), 3 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:14,305 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:42:14,305 INFO L93 Difference]: Finished difference Result 71639 states and 97183 transitions. [2021-11-09 09:42:14,306 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:42:14,306 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71639 states and 97183 transitions. [2021-11-09 09:42:14,715 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 71210 [2021-11-09 09:42:14,937 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71639 states to 71639 states and 97183 transitions. [2021-11-09 09:42:14,937 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 71639 [2021-11-09 09:42:14,988 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 71639 [2021-11-09 09:42:14,988 INFO L73 IsDeterministic]: Start isDeterministic. Operand 71639 states and 97183 transitions. [2021-11-09 09:42:15,580 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:42:15,593 INFO L681 BuchiCegarLoop]: Abstraction has 71639 states and 97183 transitions. [2021-11-09 09:42:15,679 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71639 states and 97183 transitions. [2021-11-09 09:42:16,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71639 to 71063. [2021-11-09 09:42:16,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 71063 states, 71063 states have (on average 1.3594556942431364) internal successors, (96607), 71062 states have internal predecessors, (96607), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:42:17,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71063 states to 71063 states and 96607 transitions. [2021-11-09 09:42:17,043 INFO L704 BuchiCegarLoop]: Abstraction has 71063 states and 96607 transitions. [2021-11-09 09:42:17,043 INFO L587 BuchiCegarLoop]: Abstraction has 71063 states and 96607 transitions. [2021-11-09 09:42:17,043 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-09 09:42:17,043 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71063 states and 96607 transitions. [2021-11-09 09:42:17,258 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 70634 [2021-11-09 09:42:17,258 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:42:17,258 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:42:17,261 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:17,262 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:42:17,262 INFO L791 eck$LassoCheckResult]: Stem: 359981#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~token~0 := 0;~local~0 := 0; 359937#L-1 havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 359732#L903 havoc start_simulation_#t~ret23, start_simulation_#t~ret24, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 359302#L419 assume 1 == ~m_i~0;~m_st~0 := 0; 359303#L426-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 359583#L431-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 359584#L436-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 359558#L441-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 359559#L446-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 359838#L451-1 assume !(0 == ~M_E~0); 359839#L611-1 assume !(0 == ~T1_E~0); 359856#L616-1 assume !(0 == ~T2_E~0); 359857#L621-1 assume !(0 == ~T3_E~0); 359427#L626-1 assume !(0 == ~T4_E~0); 359428#L631-1 assume !(0 == ~T5_E~0); 359625#L636-1 assume !(0 == ~E_M~0); 359472#L641-1 assume !(0 == ~E_1~0); 359473#L646-1 assume !(0 == ~E_2~0); 359642#L651-1 assume !(0 == ~E_3~0); 359920#L656-1 assume !(0 == ~E_4~0); 359836#L661-1 assume !(0 == ~E_5~0); 359837#L666-1 havoc activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 359882#L304 assume !(1 == ~m_pc~0); 359492#L304-2 is_master_triggered_~__retres1~0 := 0; 359405#L315 is_master_triggered_#res := is_master_triggered_~__retres1~0; 359406#L316 activate_threads_#t~ret16 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 359348#L755 assume !(0 != activate_threads_~tmp~1); 359349#L755-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 359304#L323 assume !(1 == ~t1_pc~0); 359305#L323-2 is_transmit1_triggered_~__retres1~1 := 0; 359693#L334 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 359990#L335 activate_threads_#t~ret17 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 359955#L763 assume !(0 != activate_threads_~tmp___0~0); 359956#L763-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 359372#L342 assume !(1 == ~t2_pc~0); 359373#L342-2 is_transmit2_triggered_~__retres1~2 := 0; 359497#L353 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 359498#L354 activate_threads_#t~ret18 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 359946#L771 assume !(0 != activate_threads_~tmp___1~0); 359831#L771-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 359705#L361 assume !(1 == ~t3_pc~0); 359706#L361-2 is_transmit3_triggered_~__retres1~3 := 0; 359735#L372 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 359544#L373 activate_threads_#t~ret19 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 359545#L779 assume !(0 != activate_threads_~tmp___2~0); 359385#L779-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 359386#L380 assume !(1 == ~t4_pc~0); 359702#L380-2 is_transmit4_triggered_~__retres1~4 := 0; 359847#L391 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 359848#L392 activate_threads_#t~ret20 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 359747#L787 assume !(0 != activate_threads_~tmp___3~0); 359748#L787-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 359450#L399 assume !(1 == ~t5_pc~0); 359451#L399-2 is_transmit5_triggered_~__retres1~5 := 0; 359595#L410 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 359862#L411 activate_threads_#t~ret21 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 359585#L795 assume !(0 != activate_threads_~tmp___4~0); 359586#L795-2 assume !(1 == ~M_E~0); 359846#L679-1 assume !(1 == ~T1_E~0); 359510#L684-1 assume !(1 == ~T2_E~0); 359511#L689-1 assume !(1 == ~T3_E~0); 359720#L694-1 assume !(1 == ~T4_E~0); 359718#L699-1 assume !(1 == ~T5_E~0); 359719#L704-1 assume !(1 == ~E_M~0); 359692#L709-1 assume !(1 == ~E_1~0); 359630#L714-1 assume !(1 == ~E_2~0); 359631#L719-1 assume !(1 == ~E_3~0); 359825#L724-1 assume !(1 == ~E_4~0); 359417#L729-1 assume !(1 == ~E_5~0); 359418#L940-1 assume !false; 382455#L941 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret9, eval_#t~nondet10, eval_~tmp_ndt_1~0, eval_#t~nondet11, eval_~tmp_ndt_2~0, eval_#t~nondet12, eval_~tmp_ndt_3~0, eval_#t~nondet13, eval_~tmp_ndt_4~0, eval_#t~nondet14, eval_~tmp_ndt_5~0, eval_#t~nondet15, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 382453#L586 [2021-11-09 09:42:17,262 INFO L793 eck$LassoCheckResult]: Loop: 382453#L586 assume !false; 382451#L507 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 382448#L464 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 382447#L496 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 382446#L497 eval_#t~ret9 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret9;havoc eval_#t~ret9; 382444#L511 assume 0 != eval_~tmp~0; 382442#L511-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 382439#L519 assume !(0 != eval_~tmp_ndt_1~0); 382437#L516 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 379511#L533 assume !(0 != eval_~tmp_ndt_2~0); 382436#L530 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 380775#L547 assume !(0 != eval_~tmp_ndt_3~0); 383330#L544 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet13;havoc eval_#t~nondet13; 383306#L561 assume !(0 != eval_~tmp_ndt_4~0); 383328#L558 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet14;havoc eval_#t~nondet14; 387016#L575 assume !(0 != eval_~tmp_ndt_5~0); 382461#L572 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet15;havoc eval_#t~nondet15; 382456#L589 assume !(0 != eval_~tmp_ndt_6~0); 382453#L586 [2021-11-09 09:42:17,263 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:17,263 INFO L85 PathProgramCache]: Analyzing trace with hash -1135942013, now seen corresponding path program 6 times [2021-11-09 09:42:17,263 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:17,264 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1653837212] [2021-11-09 09:42:17,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:17,264 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:17,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:17,276 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:42:17,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:17,307 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:42:17,307 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:17,307 INFO L85 PathProgramCache]: Analyzing trace with hash 1412259251, now seen corresponding path program 1 times [2021-11-09 09:42:17,308 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:17,308 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [733204303] [2021-11-09 09:42:17,308 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:17,308 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:17,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:17,313 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:42:17,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:17,319 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:42:17,319 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:42:17,319 INFO L85 PathProgramCache]: Analyzing trace with hash -699373643, now seen corresponding path program 1 times [2021-11-09 09:42:17,320 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:42:17,320 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [863989453] [2021-11-09 09:42:17,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:42:17,320 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:42:17,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:17,333 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:42:17,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:42:17,372 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:42:20,650 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 09.11 09:42:20 BoogieIcfgContainer [2021-11-09 09:42:20,650 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-11-09 09:42:20,651 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-11-09 09:42:20,651 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-11-09 09:42:20,652 INFO L275 PluginConnector]: Witness Printer initialized [2021-11-09 09:42:20,652 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 09:41:59" (3/4) ... [2021-11-09 09:42:20,655 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-11-09 09:42:20,740 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_505d4f12-3627-4247-8bc7-397770d253d9/bin/uautomizer-IVEQpCNsaX/witness.graphml [2021-11-09 09:42:20,741 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-11-09 09:42:20,743 INFO L168 Benchmark]: Toolchain (without parser) took 24200.14 ms. Allocated memory was 104.9 MB in the beginning and 10.4 GB in the end (delta: 10.3 GB). Free memory was 71.7 MB in the beginning and 9.5 GB in the end (delta: -9.5 GB). Peak memory consumption was 785.3 MB. Max. memory is 16.1 GB. [2021-11-09 09:42:20,743 INFO L168 Benchmark]: CDTParser took 0.34 ms. Allocated memory is still 104.9 MB. Free memory is still 60.8 MB. There was no memory consumed. Max. memory is 16.1 GB. [2021-11-09 09:42:20,744 INFO L168 Benchmark]: CACSL2BoogieTranslator took 622.83 ms. Allocated memory is still 104.9 MB. Free memory was 71.6 MB in the beginning and 75.9 MB in the end (delta: -4.3 MB). Peak memory consumption was 10.5 MB. Max. memory is 16.1 GB. [2021-11-09 09:42:20,744 INFO L168 Benchmark]: Boogie Procedure Inliner took 154.76 ms. Allocated memory is still 104.9 MB. Free memory was 75.9 MB in the beginning and 71.0 MB in the end (delta: 4.9 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-11-09 09:42:20,745 INFO L168 Benchmark]: Boogie Preprocessor took 127.08 ms. Allocated memory is still 104.9 MB. Free memory was 70.6 MB in the beginning and 66.4 MB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-11-09 09:42:20,746 INFO L168 Benchmark]: RCFGBuilder took 1649.34 ms. Allocated memory was 104.9 MB in the beginning and 132.1 MB in the end (delta: 27.3 MB). Free memory was 66.0 MB in the beginning and 77.2 MB in the end (delta: -11.2 MB). Peak memory consumption was 26.6 MB. Max. memory is 16.1 GB. [2021-11-09 09:42:20,746 INFO L168 Benchmark]: BuchiAutomizer took 21536.28 ms. Allocated memory was 132.1 MB in the beginning and 10.4 GB in the end (delta: 10.2 GB). Free memory was 77.2 MB in the beginning and 9.5 GB in the end (delta: -9.5 GB). Peak memory consumption was 996.2 MB. Max. memory is 16.1 GB. [2021-11-09 09:42:20,747 INFO L168 Benchmark]: Witness Printer took 89.84 ms. Allocated memory is still 10.4 GB. Free memory was 9.5 GB in the beginning and 9.5 GB in the end (delta: 4.2 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-11-09 09:42:20,749 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.34 ms. Allocated memory is still 104.9 MB. Free memory is still 60.8 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 622.83 ms. Allocated memory is still 104.9 MB. Free memory was 71.6 MB in the beginning and 75.9 MB in the end (delta: -4.3 MB). Peak memory consumption was 10.5 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 154.76 ms. Allocated memory is still 104.9 MB. Free memory was 75.9 MB in the beginning and 71.0 MB in the end (delta: 4.9 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 127.08 ms. Allocated memory is still 104.9 MB. Free memory was 70.6 MB in the beginning and 66.4 MB in the end (delta: 4.2 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * RCFGBuilder took 1649.34 ms. Allocated memory was 104.9 MB in the beginning and 132.1 MB in the end (delta: 27.3 MB). Free memory was 66.0 MB in the beginning and 77.2 MB in the end (delta: -11.2 MB). Peak memory consumption was 26.6 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 21536.28 ms. Allocated memory was 132.1 MB in the beginning and 10.4 GB in the end (delta: 10.2 GB). Free memory was 77.2 MB in the beginning and 9.5 GB in the end (delta: -9.5 GB). Peak memory consumption was 996.2 MB. Max. memory is 16.1 GB. * Witness Printer took 89.84 ms. Allocated memory is still 10.4 GB. Free memory was 9.5 GB in the beginning and 9.5 GB in the end (delta: 4.2 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 21 terminating modules (21 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.21 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 71063 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 21.4s and 22 iterations. TraceHistogramMax:1. Analysis of lassos took 7.5s. Construction of modules took 0.8s. Büchi inclusion checks took 2.4s. Highest rank in rank-based complementation 0. Minimization of det autom 21. Minimization of nondet autom 0. Automata minimization 4.8s AutomataMinimizationTime, 21 MinimizatonAttempts, 10985 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 3.0s Buchi closure took 0.2s. Biggest automaton had 71063 states and ocurred in iteration 21. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 17322 SDtfs, 20056 SDslu, 15514 SDs, 0 SdLazy, 537 SolverSat, 285 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.8s Time LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc5 concLT0 SILN1 SILU0 SILI12 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 506]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=16208} State at position 1 is {__retres1=0, NULL=0, t3_st=0, token=0, NULL=16208, tmp=1, t5_i=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, \result=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6c1b8741=0, tmp___2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7b2a0e65=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@470c1051=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4823d2b3=0, NULL=0, tmp___0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@b5ff956=0, t3_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@51831c07=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6112b8f9=0, tmp=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@46bbb212=0, m_pc=0, tmp___4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3d48fcfe=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7887ecb3=0, NULL=16210, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2cf2c23e=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6238c52e=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@76266090=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, t5_st=0, __retres1=1, E_2=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@11d9f02e=0, E_4=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@b9c90c4=0, T1_E=2, NULL=16211, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=16209, T5_E=2, t2_i=1, T4_E=2, t3_i=1, t4_st=0, m_i=1, t1_st=0, tmp_ndt_5=0, t5_pc=0, local=0, t2_pc=0, tmp___3=0, E_M=2, tmp___1=0, T3_E=2, t1_i=1, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 506]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int m_pc = 0; [L25] int t1_pc = 0; [L26] int t2_pc = 0; [L27] int t3_pc = 0; [L28] int t4_pc = 0; [L29] int t5_pc = 0; [L30] int m_st ; [L31] int t1_st ; [L32] int t2_st ; [L33] int t3_st ; [L34] int t4_st ; [L35] int t5_st ; [L36] int m_i ; [L37] int t1_i ; [L38] int t2_i ; [L39] int t3_i ; [L40] int t4_i ; [L41] int t5_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int E_M = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; [L61] int token ; [L63] int local ; [L985] int __retres1 ; [L896] m_i = 1 [L897] t1_i = 1 [L898] t2_i = 1 [L899] t3_i = 1 [L900] t4_i = 1 [L901] t5_i = 1 [L926] int kernel_st ; [L927] int tmp ; [L928] int tmp___0 ; [L932] kernel_st = 0 [L426] COND TRUE m_i == 1 [L427] m_st = 0 [L431] COND TRUE t1_i == 1 [L432] t1_st = 0 [L436] COND TRUE t2_i == 1 [L437] t2_st = 0 [L441] COND TRUE t3_i == 1 [L442] t3_st = 0 [L446] COND TRUE t4_i == 1 [L447] t4_st = 0 [L451] COND TRUE t5_i == 1 [L452] t5_st = 0 [L611] COND FALSE !(M_E == 0) [L616] COND FALSE !(T1_E == 0) [L621] COND FALSE !(T2_E == 0) [L626] COND FALSE !(T3_E == 0) [L631] COND FALSE !(T4_E == 0) [L636] COND FALSE !(T5_E == 0) [L641] COND FALSE !(E_M == 0) [L646] COND FALSE !(E_1 == 0) [L651] COND FALSE !(E_2 == 0) [L656] COND FALSE !(E_3 == 0) [L661] COND FALSE !(E_4 == 0) [L666] COND FALSE !(E_5 == 0) [L744] int tmp ; [L745] int tmp___0 ; [L746] int tmp___1 ; [L747] int tmp___2 ; [L748] int tmp___3 ; [L749] int tmp___4 ; [L301] int __retres1 ; [L304] COND FALSE !(m_pc == 1) [L314] __retres1 = 0 [L316] return (__retres1); [L753] tmp = is_master_triggered() [L755] COND FALSE !(\read(tmp)) [L320] int __retres1 ; [L323] COND FALSE !(t1_pc == 1) [L333] __retres1 = 0 [L335] return (__retres1); [L761] tmp___0 = is_transmit1_triggered() [L763] COND FALSE !(\read(tmp___0)) [L339] int __retres1 ; [L342] COND FALSE !(t2_pc == 1) [L352] __retres1 = 0 [L354] return (__retres1); [L769] tmp___1 = is_transmit2_triggered() [L771] COND FALSE !(\read(tmp___1)) [L358] int __retres1 ; [L361] COND FALSE !(t3_pc == 1) [L371] __retres1 = 0 [L373] return (__retres1); [L777] tmp___2 = is_transmit3_triggered() [L779] COND FALSE !(\read(tmp___2)) [L377] int __retres1 ; [L380] COND FALSE !(t4_pc == 1) [L390] __retres1 = 0 [L392] return (__retres1); [L785] tmp___3 = is_transmit4_triggered() [L787] COND FALSE !(\read(tmp___3)) [L396] int __retres1 ; [L399] COND FALSE !(t5_pc == 1) [L409] __retres1 = 0 [L411] return (__retres1); [L793] tmp___4 = is_transmit5_triggered() [L795] COND FALSE !(\read(tmp___4)) [L679] COND FALSE !(M_E == 1) [L684] COND FALSE !(T1_E == 1) [L689] COND FALSE !(T2_E == 1) [L694] COND FALSE !(T3_E == 1) [L699] COND FALSE !(T4_E == 1) [L704] COND FALSE !(T5_E == 1) [L709] COND FALSE !(E_M == 1) [L714] COND FALSE !(E_1 == 1) [L719] COND FALSE !(E_2 == 1) [L724] COND FALSE !(E_3 == 1) [L729] COND FALSE !(E_4 == 1) [L734] COND FALSE !(E_5 == 1) [L940] COND TRUE 1 [L943] kernel_st = 1 [L502] int tmp ; Loop: [L506] COND TRUE 1 [L461] int __retres1 ; [L464] COND TRUE m_st == 0 [L465] __retres1 = 1 [L497] return (__retres1); [L509] tmp = exists_runnable_thread() [L511] COND TRUE \read(tmp) [L516] COND TRUE m_st == 0 [L517] int tmp_ndt_1; [L518] tmp_ndt_1 = __VERIFIER_nondet_int() [L519] COND FALSE !(\read(tmp_ndt_1)) [L530] COND TRUE t1_st == 0 [L531] int tmp_ndt_2; [L532] tmp_ndt_2 = __VERIFIER_nondet_int() [L533] COND FALSE !(\read(tmp_ndt_2)) [L544] COND TRUE t2_st == 0 [L545] int tmp_ndt_3; [L546] tmp_ndt_3 = __VERIFIER_nondet_int() [L547] COND FALSE !(\read(tmp_ndt_3)) [L558] COND TRUE t3_st == 0 [L559] int tmp_ndt_4; [L560] tmp_ndt_4 = __VERIFIER_nondet_int() [L561] COND FALSE !(\read(tmp_ndt_4)) [L572] COND TRUE t4_st == 0 [L573] int tmp_ndt_5; [L574] tmp_ndt_5 = __VERIFIER_nondet_int() [L575] COND FALSE !(\read(tmp_ndt_5)) [L586] COND TRUE t5_st == 0 [L587] int tmp_ndt_6; [L588] tmp_ndt_6 = __VERIFIER_nondet_int() [L589] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-11-09 09:42:20,822 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_505d4f12-3627-4247-8bc7-397770d253d9/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)