./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.07.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f8e1c903 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9bf73aa2-5be3-4b1b-9b35-aea3da129735/bin/uautomizer-IVEQpCNsaX/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9bf73aa2-5be3-4b1b-9b35-aea3da129735/bin/uautomizer-IVEQpCNsaX/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9bf73aa2-5be3-4b1b-9b35-aea3da129735/bin/uautomizer-IVEQpCNsaX/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9bf73aa2-5be3-4b1b-9b35-aea3da129735/bin/uautomizer-IVEQpCNsaX/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.07.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9bf73aa2-5be3-4b1b-9b35-aea3da129735/bin/uautomizer-IVEQpCNsaX/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9bf73aa2-5be3-4b1b-9b35-aea3da129735/bin/uautomizer-IVEQpCNsaX --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a6baa92d18991a792383fc99c5c300f37f700ba00714b15a3dbe7d2191a67ca9 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-f8e1c90 [2021-11-09 09:34:56,364 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-09 09:34:56,366 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-09 09:34:56,417 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-09 09:34:56,417 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-09 09:34:56,419 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-09 09:34:56,421 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-09 09:34:56,427 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-09 09:34:56,430 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-09 09:34:56,431 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-09 09:34:56,432 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-09 09:34:56,433 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-09 09:34:56,434 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-09 09:34:56,435 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-09 09:34:56,437 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-09 09:34:56,438 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-09 09:34:56,439 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-09 09:34:56,441 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-09 09:34:56,443 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-09 09:34:56,445 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-09 09:34:56,447 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-09 09:34:56,449 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-09 09:34:56,451 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-09 09:34:56,451 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-09 09:34:56,455 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-09 09:34:56,456 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-09 09:34:56,456 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-09 09:34:56,457 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-09 09:34:56,458 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-09 09:34:56,459 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-09 09:34:56,460 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-09 09:34:56,461 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-09 09:34:56,461 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-09 09:34:56,462 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-09 09:34:56,464 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-09 09:34:56,464 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-09 09:34:56,465 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-09 09:34:56,465 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-09 09:34:56,466 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-09 09:34:56,467 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-09 09:34:56,468 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-09 09:34:56,469 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9bf73aa2-5be3-4b1b-9b35-aea3da129735/bin/uautomizer-IVEQpCNsaX/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-09 09:34:56,498 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-09 09:34:56,498 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-09 09:34:56,498 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-09 09:34:56,499 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-09 09:34:56,500 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-09 09:34:56,500 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-09 09:34:56,501 INFO L138 SettingsManager]: * Use SBE=true [2021-11-09 09:34:56,501 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-09 09:34:56,501 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-09 09:34:56,502 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-09 09:34:56,502 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-09 09:34:56,503 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-09 09:34:56,503 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-09 09:34:56,503 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-09 09:34:56,504 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-09 09:34:56,504 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-09 09:34:56,504 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-09 09:34:56,505 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-09 09:34:56,505 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-09 09:34:56,505 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-09 09:34:56,509 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-09 09:34:56,509 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-09 09:34:56,510 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-09 09:34:56,510 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-09 09:34:56,510 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-09 09:34:56,511 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-09 09:34:56,513 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-09 09:34:56,513 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-09 09:34:56,514 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-09 09:34:56,514 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-09 09:34:56,515 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-09 09:34:56,515 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-09 09:34:56,516 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-09 09:34:56,516 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9bf73aa2-5be3-4b1b-9b35-aea3da129735/bin/uautomizer-IVEQpCNsaX/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9bf73aa2-5be3-4b1b-9b35-aea3da129735/bin/uautomizer-IVEQpCNsaX Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a6baa92d18991a792383fc99c5c300f37f700ba00714b15a3dbe7d2191a67ca9 [2021-11-09 09:34:56,795 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-09 09:34:56,817 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-09 09:34:56,820 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-09 09:34:56,821 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-09 09:34:56,822 INFO L275 PluginConnector]: CDTParser initialized [2021-11-09 09:34:56,823 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9bf73aa2-5be3-4b1b-9b35-aea3da129735/bin/uautomizer-IVEQpCNsaX/../../sv-benchmarks/c/systemc/token_ring.07.cil-1.c [2021-11-09 09:34:56,882 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9bf73aa2-5be3-4b1b-9b35-aea3da129735/bin/uautomizer-IVEQpCNsaX/data/115e36375/86111ce84a5f45b89a650360e79d2389/FLAGde28836b9 [2021-11-09 09:34:57,395 INFO L306 CDTParser]: Found 1 translation units. [2021-11-09 09:34:57,395 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9bf73aa2-5be3-4b1b-9b35-aea3da129735/sv-benchmarks/c/systemc/token_ring.07.cil-1.c [2021-11-09 09:34:57,407 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9bf73aa2-5be3-4b1b-9b35-aea3da129735/bin/uautomizer-IVEQpCNsaX/data/115e36375/86111ce84a5f45b89a650360e79d2389/FLAGde28836b9 [2021-11-09 09:34:57,726 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9bf73aa2-5be3-4b1b-9b35-aea3da129735/bin/uautomizer-IVEQpCNsaX/data/115e36375/86111ce84a5f45b89a650360e79d2389 [2021-11-09 09:34:57,728 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-09 09:34:57,730 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-09 09:34:57,731 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-09 09:34:57,731 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-09 09:34:57,749 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-09 09:34:57,749 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 09:34:57" (1/1) ... [2021-11-09 09:34:57,750 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1007aeba and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:34:57, skipping insertion in model container [2021-11-09 09:34:57,751 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 09:34:57" (1/1) ... [2021-11-09 09:34:57,759 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-09 09:34:57,819 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-09 09:34:57,990 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9bf73aa2-5be3-4b1b-9b35-aea3da129735/sv-benchmarks/c/systemc/token_ring.07.cil-1.c[671,684] [2021-11-09 09:34:58,083 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-09 09:34:58,095 INFO L203 MainTranslator]: Completed pre-run [2021-11-09 09:34:58,106 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9bf73aa2-5be3-4b1b-9b35-aea3da129735/sv-benchmarks/c/systemc/token_ring.07.cil-1.c[671,684] [2021-11-09 09:34:58,159 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-09 09:34:58,179 INFO L208 MainTranslator]: Completed translation [2021-11-09 09:34:58,179 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:34:58 WrapperNode [2021-11-09 09:34:58,179 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-09 09:34:58,181 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-09 09:34:58,181 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-09 09:34:58,181 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-09 09:34:58,188 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:34:58" (1/1) ... [2021-11-09 09:34:58,199 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:34:58" (1/1) ... [2021-11-09 09:34:58,288 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-09 09:34:58,289 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-09 09:34:58,289 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-09 09:34:58,289 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-09 09:34:58,298 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:34:58" (1/1) ... [2021-11-09 09:34:58,298 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:34:58" (1/1) ... [2021-11-09 09:34:58,307 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:34:58" (1/1) ... [2021-11-09 09:34:58,308 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:34:58" (1/1) ... [2021-11-09 09:34:58,339 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:34:58" (1/1) ... [2021-11-09 09:34:58,368 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:34:58" (1/1) ... [2021-11-09 09:34:58,375 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:34:58" (1/1) ... [2021-11-09 09:34:58,387 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-09 09:34:58,388 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-09 09:34:58,388 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-09 09:34:58,388 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-09 09:34:58,389 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:34:58" (1/1) ... [2021-11-09 09:34:58,397 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 09:34:58,411 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9bf73aa2-5be3-4b1b-9b35-aea3da129735/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 09:34:58,436 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9bf73aa2-5be3-4b1b-9b35-aea3da129735/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 09:34:58,450 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_9bf73aa2-5be3-4b1b-9b35-aea3da129735/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-09 09:34:58,490 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-09 09:34:58,490 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-09 09:34:58,490 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-09 09:34:58,491 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-09 09:35:00,114 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-09 09:35:00,114 INFO L299 CfgBuilder]: Removed 278 assume(true) statements. [2021-11-09 09:35:00,117 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 09:35:00 BoogieIcfgContainer [2021-11-09 09:35:00,118 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-09 09:35:00,119 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-09 09:35:00,119 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-09 09:35:00,122 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-09 09:35:00,123 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-09 09:35:00,124 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 09.11 09:34:57" (1/3) ... [2021-11-09 09:35:00,125 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@35c17040 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 09:35:00, skipping insertion in model container [2021-11-09 09:35:00,125 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-09 09:35:00,126 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 09:34:58" (2/3) ... [2021-11-09 09:35:00,126 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@35c17040 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 09:35:00, skipping insertion in model container [2021-11-09 09:35:00,126 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-09 09:35:00,126 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 09:35:00" (3/3) ... [2021-11-09 09:35:00,128 INFO L389 chiAutomizerObserver]: Analyzing ICFG token_ring.07.cil-1.c [2021-11-09 09:35:00,172 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-09 09:35:00,172 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-09 09:35:00,173 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-09 09:35:00,173 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-09 09:35:00,173 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-09 09:35:00,173 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-09 09:35:00,173 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-09 09:35:00,173 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-09 09:35:00,209 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 812 states, 811 states have (on average 1.5339087546239212) internal successors, (1244), 811 states have internal predecessors, (1244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:00,270 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 709 [2021-11-09 09:35:00,271 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:00,271 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:00,286 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:00,286 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:00,287 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-09 09:35:00,289 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 812 states, 811 states have (on average 1.5339087546239212) internal successors, (1244), 811 states have internal predecessors, (1244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:00,301 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 709 [2021-11-09 09:35:00,302 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:00,302 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:00,307 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:00,308 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:00,316 INFO L791 eck$LassoCheckResult]: Stem: 403#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 733#L-1true havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 299#L1141true havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 259#L529true assume !(1 == ~m_i~0);~m_st~0 := 2; 559#L536-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 246#L541-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 145#L546-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 615#L551-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 134#L556-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 567#L561-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 550#L566-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 353#L571-1true assume !(0 == ~M_E~0); 350#L769-1true assume 0 == ~T1_E~0;~T1_E~0 := 1; 395#L774-1true assume !(0 == ~T2_E~0); 652#L779-1true assume !(0 == ~T3_E~0); 530#L784-1true assume !(0 == ~T4_E~0); 349#L789-1true assume !(0 == ~T5_E~0); 448#L794-1true assume !(0 == ~T6_E~0); 791#L799-1true assume !(0 == ~T7_E~0); 355#L804-1true assume !(0 == ~E_M~0); 385#L809-1true assume 0 == ~E_1~0;~E_1~0 := 1; 560#L814-1true assume !(0 == ~E_2~0); 9#L819-1true assume !(0 == ~E_3~0); 181#L824-1true assume !(0 == ~E_4~0); 781#L829-1true assume !(0 == ~E_5~0); 649#L834-1true assume !(0 == ~E_6~0); 67#L839-1true assume !(0 == ~E_7~0); 454#L844-1true havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 305#L376true assume !(1 == ~m_pc~0); 303#L376-2true is_master_triggered_~__retres1~0 := 0; 741#L387true is_master_triggered_#res := is_master_triggered_~__retres1~0; 614#L388true activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 45#L955true assume !(0 != activate_threads_~tmp~1); 240#L955-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 371#L395true assume 1 == ~t1_pc~0; 58#L396true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 531#L406true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12#L407true activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 574#L963true assume !(0 != activate_threads_~tmp___0~0); 311#L963-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 801#L414true assume !(1 == ~t2_pc~0); 558#L414-2true is_transmit2_triggered_~__retres1~2 := 0; 789#L425true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 173#L426true activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 556#L971true assume !(0 != activate_threads_~tmp___1~0); 666#L971-2true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 243#L433true assume 1 == ~t3_pc~0; 205#L434true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 676#L444true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 223#L445true activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 495#L979true assume !(0 != activate_threads_~tmp___2~0); 53#L979-2true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 756#L452true assume 1 == ~t4_pc~0; 735#L453true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 339#L463true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 394#L464true activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 673#L987true assume !(0 != activate_threads_~tmp___3~0); 150#L987-2true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 434#L471true assume !(1 == ~t5_pc~0); 701#L471-2true is_transmit5_triggered_~__retres1~5 := 0; 140#L482true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 386#L483true activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 787#L995true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 637#L995-2true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 710#L490true assume 1 == ~t6_pc~0; 596#L491true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 344#L501true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 438#L502true activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 346#L1003true assume !(0 != activate_threads_~tmp___5~0); 249#L1003-2true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 228#L509true assume !(1 == ~t7_pc~0); 561#L509-2true is_transmit7_triggered_~__retres1~7 := 0; 118#L520true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 671#L521true activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 152#L1011true assume !(0 != activate_threads_~tmp___6~0); 675#L1011-2true assume !(1 == ~M_E~0); 813#L857-1true assume !(1 == ~T1_E~0); 188#L862-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 193#L867-1true assume !(1 == ~T3_E~0); 244#L872-1true assume !(1 == ~T4_E~0); 412#L877-1true assume !(1 == ~T5_E~0); 595#L882-1true assume !(1 == ~T6_E~0); 718#L887-1true assume !(1 == ~T7_E~0); 469#L892-1true assume !(1 == ~E_M~0); 683#L897-1true assume !(1 == ~E_1~0); 200#L902-1true assume 1 == ~E_2~0;~E_2~0 := 2; 485#L907-1true assume !(1 == ~E_3~0); 424#L912-1true assume !(1 == ~E_4~0); 417#L917-1true assume !(1 == ~E_5~0); 657#L922-1true assume !(1 == ~E_6~0); 764#L927-1true assume !(1 == ~E_7~0); 391#L1178-1true [2021-11-09 09:35:00,319 INFO L793 eck$LassoCheckResult]: Loop: 391#L1178-1true assume !false; 399#L1179true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 222#L744true assume false; 338#L759true start_simulation_~kernel_st~0 := 2; 85#L529-1true start_simulation_~kernel_st~0 := 3; 369#L769-2true assume 0 == ~M_E~0;~M_E~0 := 1; 529#L769-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 376#L774-3true assume !(0 == ~T2_E~0); 94#L779-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 16#L784-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 804#L789-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 10#L794-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 33#L799-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 156#L804-3true assume 0 == ~E_M~0;~E_M~0 := 1; 307#L809-3true assume 0 == ~E_1~0;~E_1~0 := 1; 31#L814-3true assume !(0 == ~E_2~0); 540#L819-3true assume 0 == ~E_3~0;~E_3~0 := 1; 498#L824-3true assume 0 == ~E_4~0;~E_4~0 := 1; 490#L829-3true assume 0 == ~E_5~0;~E_5~0 := 1; 189#L834-3true assume 0 == ~E_6~0;~E_6~0 := 1; 447#L839-3true assume 0 == ~E_7~0;~E_7~0 := 1; 569#L844-3true havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 709#L376-27true assume !(1 == ~m_pc~0); 792#L376-29true is_master_triggered_~__retres1~0 := 0; 374#L387-9true is_master_triggered_#res := is_master_triggered_~__retres1~0; 475#L388-9true activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 667#L955-27true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 797#L955-29true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 782#L395-27true assume !(1 == ~t1_pc~0); 254#L395-29true is_transmit1_triggered_~__retres1~1 := 0; 190#L406-9true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 506#L407-9true activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 368#L963-27true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 247#L963-29true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 632#L414-27true assume 1 == ~t2_pc~0; 794#L415-9true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 416#L425-9true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 645#L426-9true activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 293#L971-27true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 38#L971-29true havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 80#L433-27true assume 1 == ~t3_pc~0; 707#L434-9true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 251#L444-9true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 770#L445-9true activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 120#L979-27true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 734#L979-29true havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 721#L452-27true assume 1 == ~t4_pc~0; 810#L453-9true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 534#L463-9true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 660#L464-9true activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 627#L987-27true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 636#L987-29true havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 34#L471-27true assume !(1 == ~t5_pc~0); 198#L471-29true is_transmit5_triggered_~__retres1~5 := 0; 798#L482-9true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 568#L483-9true activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 436#L995-27true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 372#L995-29true havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 304#L490-27true assume !(1 == ~t6_pc~0); 588#L490-29true is_transmit6_triggered_~__retres1~6 := 0; 126#L501-9true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 601#L502-9true activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 423#L1003-27true assume !(0 != activate_threads_~tmp___5~0); 692#L1003-29true havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 20#L509-27true assume 1 == ~t7_pc~0; 329#L510-9true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 522#L520-9true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 327#L521-9true activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 322#L1011-27true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 777#L1011-29true assume 1 == ~M_E~0;~M_E~0 := 2; 335#L857-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 761#L862-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 712#L867-3true assume !(1 == ~T3_E~0); 252#L872-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 328#L877-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 742#L882-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 364#L887-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 105#L892-3true assume 1 == ~E_M~0;~E_M~0 := 2; 519#L897-3true assume 1 == ~E_1~0;~E_1~0 := 2; 800#L902-3true assume 1 == ~E_2~0;~E_2~0 := 2; 199#L907-3true assume !(1 == ~E_3~0); 285#L912-3true assume 1 == ~E_4~0;~E_4~0 := 2; 554#L917-3true assume 1 == ~E_5~0;~E_5~0 := 2; 255#L922-3true assume 1 == ~E_6~0;~E_6~0 := 2; 133#L927-3true assume 1 == ~E_7~0;~E_7~0 := 2; 206#L932-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 57#L584-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 451#L626-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 773#L627-1true start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 236#L1197true assume !(0 == start_simulation_~tmp~3); 171#L1197-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 83#L584-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 241#L626-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 35#L627-2true stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 723#L1152true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 515#L1159true stop_simulation_#res := stop_simulation_~__retres2~0; 620#L1160true start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 26#L1210true assume !(0 != start_simulation_~tmp___0~1); 391#L1178-1true [2021-11-09 09:35:00,325 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:00,326 INFO L85 PathProgramCache]: Analyzing trace with hash -1537628007, now seen corresponding path program 1 times [2021-11-09 09:35:00,335 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:00,335 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [518639120] [2021-11-09 09:35:00,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:00,337 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:00,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:00,564 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:00,565 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:00,565 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [518639120] [2021-11-09 09:35:00,567 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [518639120] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:00,567 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:00,568 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:00,570 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [870917006] [2021-11-09 09:35:00,586 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:00,587 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:00,587 INFO L85 PathProgramCache]: Analyzing trace with hash -205257655, now seen corresponding path program 1 times [2021-11-09 09:35:00,588 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:00,588 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [906752556] [2021-11-09 09:35:00,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:00,588 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:00,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:00,654 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:00,654 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:00,654 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [906752556] [2021-11-09 09:35:00,654 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [906752556] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:00,655 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:00,655 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-09 09:35:00,655 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1088703800] [2021-11-09 09:35:00,657 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:00,658 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:00,676 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:35:00,677 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:35:00,680 INFO L87 Difference]: Start difference. First operand has 812 states, 811 states have (on average 1.5339087546239212) internal successors, (1244), 811 states have internal predecessors, (1244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:00,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:00,757 INFO L93 Difference]: Finished difference Result 812 states and 1222 transitions. [2021-11-09 09:35:00,758 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:35:00,759 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 812 states and 1222 transitions. [2021-11-09 09:35:00,772 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2021-11-09 09:35:00,789 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 812 states to 807 states and 1217 transitions. [2021-11-09 09:35:00,790 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 807 [2021-11-09 09:35:00,793 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 807 [2021-11-09 09:35:00,794 INFO L73 IsDeterministic]: Start isDeterministic. Operand 807 states and 1217 transitions. [2021-11-09 09:35:00,803 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:00,803 INFO L681 BuchiCegarLoop]: Abstraction has 807 states and 1217 transitions. [2021-11-09 09:35:00,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 807 states and 1217 transitions. [2021-11-09 09:35:00,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 807 to 807. [2021-11-09 09:35:00,891 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 807 states, 807 states have (on average 1.5080545229244113) internal successors, (1217), 806 states have internal predecessors, (1217), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:00,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 807 states to 807 states and 1217 transitions. [2021-11-09 09:35:00,896 INFO L704 BuchiCegarLoop]: Abstraction has 807 states and 1217 transitions. [2021-11-09 09:35:00,896 INFO L587 BuchiCegarLoop]: Abstraction has 807 states and 1217 transitions. [2021-11-09 09:35:00,896 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-09 09:35:00,896 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 807 states and 1217 transitions. [2021-11-09 09:35:00,902 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2021-11-09 09:35:00,903 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:00,903 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:00,905 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:00,906 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:00,906 INFO L791 eck$LassoCheckResult]: Stem: 2256#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2257#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2142#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2093#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 2094#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2077#L541-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1920#L546-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1921#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1902#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1903#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2370#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2201#L571-1 assume !(0 == ~M_E~0); 2197#L769-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2198#L774-1 assume !(0 == ~T2_E~0); 2250#L779-1 assume !(0 == ~T3_E~0); 2358#L784-1 assume !(0 == ~T4_E~0); 2195#L789-1 assume !(0 == ~T5_E~0); 2196#L794-1 assume !(0 == ~T6_E~0); 2302#L799-1 assume !(0 == ~T7_E~0); 2203#L804-1 assume !(0 == ~E_M~0); 2204#L809-1 assume 0 == ~E_1~0;~E_1~0 := 1; 2242#L814-1 assume !(0 == ~E_2~0); 1646#L819-1 assume !(0 == ~E_3~0); 1647#L824-1 assume !(0 == ~E_4~0); 1989#L829-1 assume !(0 == ~E_5~0); 2413#L834-1 assume !(0 == ~E_6~0); 1776#L839-1 assume !(0 == ~E_7~0); 1777#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2147#L376 assume !(1 == ~m_pc~0); 2134#L376-2 is_master_triggered_~__retres1~0 := 0; 2135#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2396#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1727#L955 assume !(0 != activate_threads_~tmp~1); 1728#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2072#L395 assume 1 == ~t1_pc~0; 1753#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1754#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1652#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1653#L963 assume !(0 != activate_threads_~tmp___0~0); 2151#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2152#L414 assume !(1 == ~t2_pc~0); 1780#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 1779#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1975#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1976#L971 assume !(0 != activate_threads_~tmp___1~0); 2372#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2073#L433 assume 1 == ~t3_pc~0; 2019#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1891#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2049#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 2050#L979 assume !(0 != activate_threads_~tmp___2~0); 1744#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1745#L452 assume 1 == ~t4_pc~0; 2434#L453 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1899#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2183#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 2249#L987 assume !(0 != activate_threads_~tmp___3~0); 1931#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1932#L471 assume !(1 == ~t5_pc~0); 2291#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 1914#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1915#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 2243#L995 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2405#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2406#L490 assume 1 == ~t6_pc~0; 2389#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 2150#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2190#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 2193#L1003 assume !(0 != activate_threads_~tmp___5~0); 2081#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2054#L509 assume !(1 == ~t7_pc~0); 2055#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 1872#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1873#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1936#L1011 assume !(0 != activate_threads_~tmp___6~0); 1937#L1011-2 assume !(1 == ~M_E~0); 2423#L857-1 assume !(1 == ~T1_E~0); 1996#L862-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1997#L867-1 assume !(1 == ~T3_E~0); 2002#L872-1 assume !(1 == ~T4_E~0); 2074#L877-1 assume !(1 == ~T5_E~0); 2267#L882-1 assume !(1 == ~T6_E~0); 2388#L887-1 assume !(1 == ~T7_E~0); 2316#L892-1 assume !(1 == ~E_M~0); 2317#L897-1 assume !(1 == ~E_1~0); 2012#L902-1 assume 1 == ~E_2~0;~E_2~0 := 2; 2013#L907-1 assume !(1 == ~E_3~0); 2284#L912-1 assume !(1 == ~E_4~0); 2275#L917-1 assume !(1 == ~E_5~0); 2276#L922-1 assume !(1 == ~E_6~0); 2416#L927-1 assume !(1 == ~E_7~0); 1685#L1178-1 [2021-11-09 09:35:00,907 INFO L793 eck$LassoCheckResult]: Loop: 1685#L1178-1 assume !false; 2246#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 2047#L744 assume !false; 2048#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 2117#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1718#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1918#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 2362#L641 assume !(0 != eval_~tmp~0); 2182#L759 start_simulation_~kernel_st~0 := 2; 1813#L529-1 start_simulation_~kernel_st~0 := 3; 1814#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2221#L769-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2232#L774-3 assume !(0 == ~T2_E~0); 1830#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1661#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1662#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1648#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1649#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1700#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1945#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1696#L814-3 assume !(0 == ~E_2~0); 1697#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2338#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2333#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1998#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1999#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2301#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2378#L376-27 assume 1 == ~m_pc~0; 2280#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 2227#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2228#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2320#L955-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2419#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2439#L395-27 assume 1 == ~t1_pc~0; 2435#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2000#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2001#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2220#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2078#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2079#L414-27 assume 1 == ~t2_pc~0; 2403#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2273#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2274#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 2137#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1710#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1711#L433-27 assume !(1 == ~t3_pc~0); 1801#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 2083#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2084#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1875#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1876#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2432#L452-27 assume 1 == ~t4_pc~0; 2433#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2240#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2361#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 2399#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2400#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1701#L471-27 assume 1 == ~t5_pc~0; 1702#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2009#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2377#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 2294#L995-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2223#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2146#L490-27 assume 1 == ~t6_pc~0; 2051#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 1887#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1888#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 2282#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 2283#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1670#L509-27 assume 1 == ~t7_pc~0; 1671#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 2053#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2172#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 2163#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 2164#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 2178#L857-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2179#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2431#L867-3 assume !(1 == ~T3_E~0); 2085#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2086#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2173#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2213#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1850#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1851#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2353#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2010#L907-3 assume !(1 == ~E_3~0); 2011#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2126#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2090#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1900#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1901#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1751#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1659#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 2304#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 2064#L1197 assume !(0 == start_simulation_~tmp~3); 1971#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1809#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1774#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1704#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 1705#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2350#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 2351#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 1684#L1210 assume !(0 != start_simulation_~tmp___0~1); 1685#L1178-1 [2021-11-09 09:35:00,907 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:00,908 INFO L85 PathProgramCache]: Analyzing trace with hash -542934309, now seen corresponding path program 1 times [2021-11-09 09:35:00,908 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:00,908 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [658720267] [2021-11-09 09:35:00,908 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:00,908 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:00,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:01,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:01,007 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:01,007 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [658720267] [2021-11-09 09:35:01,008 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [658720267] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:01,008 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:01,008 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:01,008 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1750315799] [2021-11-09 09:35:01,009 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:01,009 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:01,010 INFO L85 PathProgramCache]: Analyzing trace with hash -1432956101, now seen corresponding path program 1 times [2021-11-09 09:35:01,010 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:01,010 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1130732405] [2021-11-09 09:35:01,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:01,011 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:01,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:01,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:01,131 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:01,131 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1130732405] [2021-11-09 09:35:01,131 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1130732405] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:01,132 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:01,132 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:01,132 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [561688671] [2021-11-09 09:35:01,133 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:01,133 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:01,134 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:35:01,134 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:35:01,134 INFO L87 Difference]: Start difference. First operand 807 states and 1217 transitions. cyclomatic complexity: 411 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:01,165 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:01,166 INFO L93 Difference]: Finished difference Result 807 states and 1216 transitions. [2021-11-09 09:35:01,166 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:35:01,167 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 807 states and 1216 transitions. [2021-11-09 09:35:01,178 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2021-11-09 09:35:01,185 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 807 states to 807 states and 1216 transitions. [2021-11-09 09:35:01,186 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 807 [2021-11-09 09:35:01,187 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 807 [2021-11-09 09:35:01,187 INFO L73 IsDeterministic]: Start isDeterministic. Operand 807 states and 1216 transitions. [2021-11-09 09:35:01,188 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:01,188 INFO L681 BuchiCegarLoop]: Abstraction has 807 states and 1216 transitions. [2021-11-09 09:35:01,190 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 807 states and 1216 transitions. [2021-11-09 09:35:01,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 807 to 807. [2021-11-09 09:35:01,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 807 states, 807 states have (on average 1.506815365551425) internal successors, (1216), 806 states have internal predecessors, (1216), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:01,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 807 states to 807 states and 1216 transitions. [2021-11-09 09:35:01,212 INFO L704 BuchiCegarLoop]: Abstraction has 807 states and 1216 transitions. [2021-11-09 09:35:01,212 INFO L587 BuchiCegarLoop]: Abstraction has 807 states and 1216 transitions. [2021-11-09 09:35:01,212 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-09 09:35:01,212 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 807 states and 1216 transitions. [2021-11-09 09:35:01,223 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2021-11-09 09:35:01,223 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:01,223 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:01,233 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:01,233 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:01,236 INFO L791 eck$LassoCheckResult]: Stem: 3877#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 3878#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3763#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3714#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 3715#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3698#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3541#L546-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3542#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3523#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3524#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3991#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3822#L571-1 assume !(0 == ~M_E~0); 3818#L769-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3819#L774-1 assume !(0 == ~T2_E~0); 3871#L779-1 assume !(0 == ~T3_E~0); 3979#L784-1 assume !(0 == ~T4_E~0); 3816#L789-1 assume !(0 == ~T5_E~0); 3817#L794-1 assume !(0 == ~T6_E~0); 3923#L799-1 assume !(0 == ~T7_E~0); 3824#L804-1 assume !(0 == ~E_M~0); 3825#L809-1 assume 0 == ~E_1~0;~E_1~0 := 1; 3863#L814-1 assume !(0 == ~E_2~0); 3267#L819-1 assume !(0 == ~E_3~0); 3268#L824-1 assume !(0 == ~E_4~0); 3610#L829-1 assume !(0 == ~E_5~0); 4034#L834-1 assume !(0 == ~E_6~0); 3397#L839-1 assume !(0 == ~E_7~0); 3398#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3768#L376 assume !(1 == ~m_pc~0); 3755#L376-2 is_master_triggered_~__retres1~0 := 0; 3756#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4017#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3348#L955 assume !(0 != activate_threads_~tmp~1); 3349#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3693#L395 assume 1 == ~t1_pc~0; 3374#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3375#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3273#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3274#L963 assume !(0 != activate_threads_~tmp___0~0); 3772#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3773#L414 assume !(1 == ~t2_pc~0); 3401#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 3400#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3596#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3597#L971 assume !(0 != activate_threads_~tmp___1~0); 3993#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3694#L433 assume 1 == ~t3_pc~0; 3640#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3512#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3670#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3671#L979 assume !(0 != activate_threads_~tmp___2~0); 3365#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3366#L452 assume 1 == ~t4_pc~0; 4055#L453 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3520#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3804#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 3870#L987 assume !(0 != activate_threads_~tmp___3~0); 3552#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3553#L471 assume !(1 == ~t5_pc~0); 3912#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 3535#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3536#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 3864#L995 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4026#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4027#L490 assume 1 == ~t6_pc~0; 4010#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3771#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3811#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 3814#L1003 assume !(0 != activate_threads_~tmp___5~0); 3702#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3675#L509 assume !(1 == ~t7_pc~0); 3676#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 3493#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3494#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 3557#L1011 assume !(0 != activate_threads_~tmp___6~0); 3558#L1011-2 assume !(1 == ~M_E~0); 4044#L857-1 assume !(1 == ~T1_E~0); 3617#L862-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3618#L867-1 assume !(1 == ~T3_E~0); 3623#L872-1 assume !(1 == ~T4_E~0); 3695#L877-1 assume !(1 == ~T5_E~0); 3888#L882-1 assume !(1 == ~T6_E~0); 4009#L887-1 assume !(1 == ~T7_E~0); 3937#L892-1 assume !(1 == ~E_M~0); 3938#L897-1 assume !(1 == ~E_1~0); 3633#L902-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3634#L907-1 assume !(1 == ~E_3~0); 3905#L912-1 assume !(1 == ~E_4~0); 3896#L917-1 assume !(1 == ~E_5~0); 3897#L922-1 assume !(1 == ~E_6~0); 4037#L927-1 assume !(1 == ~E_7~0); 3306#L1178-1 [2021-11-09 09:35:01,238 INFO L793 eck$LassoCheckResult]: Loop: 3306#L1178-1 assume !false; 3867#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 3668#L744 assume !false; 3669#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 3738#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3339#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 3539#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 3983#L641 assume !(0 != eval_~tmp~0); 3803#L759 start_simulation_~kernel_st~0 := 2; 3434#L529-1 start_simulation_~kernel_st~0 := 3; 3435#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3842#L769-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3853#L774-3 assume !(0 == ~T2_E~0); 3451#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3282#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3283#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3269#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3270#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3321#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3566#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3317#L814-3 assume !(0 == ~E_2~0); 3318#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3959#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3954#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3619#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3620#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3922#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3999#L376-27 assume 1 == ~m_pc~0; 3901#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3848#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3849#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3941#L955-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4040#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4060#L395-27 assume 1 == ~t1_pc~0; 4056#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3621#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3622#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3841#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3699#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3700#L414-27 assume 1 == ~t2_pc~0; 4024#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3894#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3895#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 3758#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3331#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3332#L433-27 assume !(1 == ~t3_pc~0); 3422#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 3704#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3705#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 3496#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3497#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4053#L452-27 assume !(1 == ~t4_pc~0); 3860#L452-29 is_transmit4_triggered_~__retres1~4 := 0; 3861#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3982#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 4020#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4021#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3322#L471-27 assume 1 == ~t5_pc~0; 3323#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3630#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3998#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 3915#L995-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3844#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3767#L490-27 assume 1 == ~t6_pc~0; 3672#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3508#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3509#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 3903#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 3904#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3291#L509-27 assume 1 == ~t7_pc~0; 3292#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 3674#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3793#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 3784#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 3785#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 3799#L857-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3800#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4052#L867-3 assume !(1 == ~T3_E~0); 3706#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3707#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3794#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3834#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3471#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3472#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3974#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3631#L907-3 assume !(1 == ~E_3~0); 3632#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3747#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3711#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3521#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3522#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 3372#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3280#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 3925#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 3685#L1197 assume !(0 == start_simulation_~tmp~3); 3592#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 3430#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3395#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 3325#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 3326#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3971#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 3972#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 3305#L1210 assume !(0 != start_simulation_~tmp___0~1); 3306#L1178-1 [2021-11-09 09:35:01,239 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:01,239 INFO L85 PathProgramCache]: Analyzing trace with hash 1415640477, now seen corresponding path program 1 times [2021-11-09 09:35:01,239 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:01,239 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [72804127] [2021-11-09 09:35:01,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:01,241 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:01,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:01,315 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:01,315 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:01,316 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [72804127] [2021-11-09 09:35:01,316 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [72804127] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:01,316 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:01,316 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:01,316 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1800441050] [2021-11-09 09:35:01,317 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:01,317 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:01,317 INFO L85 PathProgramCache]: Analyzing trace with hash -2134524326, now seen corresponding path program 1 times [2021-11-09 09:35:01,318 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:01,318 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [114812079] [2021-11-09 09:35:01,318 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:01,318 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:01,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:01,394 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:01,402 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:01,402 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [114812079] [2021-11-09 09:35:01,402 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [114812079] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:01,402 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:01,403 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:01,403 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [697282966] [2021-11-09 09:35:01,403 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:01,404 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:01,404 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:35:01,404 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:35:01,405 INFO L87 Difference]: Start difference. First operand 807 states and 1216 transitions. cyclomatic complexity: 410 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:01,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:01,423 INFO L93 Difference]: Finished difference Result 807 states and 1215 transitions. [2021-11-09 09:35:01,423 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:35:01,423 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 807 states and 1215 transitions. [2021-11-09 09:35:01,431 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2021-11-09 09:35:01,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 807 states to 807 states and 1215 transitions. [2021-11-09 09:35:01,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 807 [2021-11-09 09:35:01,439 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 807 [2021-11-09 09:35:01,439 INFO L73 IsDeterministic]: Start isDeterministic. Operand 807 states and 1215 transitions. [2021-11-09 09:35:01,441 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:01,441 INFO L681 BuchiCegarLoop]: Abstraction has 807 states and 1215 transitions. [2021-11-09 09:35:01,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 807 states and 1215 transitions. [2021-11-09 09:35:01,455 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 807 to 807. [2021-11-09 09:35:01,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 807 states, 807 states have (on average 1.5055762081784387) internal successors, (1215), 806 states have internal predecessors, (1215), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:01,461 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 807 states to 807 states and 1215 transitions. [2021-11-09 09:35:01,461 INFO L704 BuchiCegarLoop]: Abstraction has 807 states and 1215 transitions. [2021-11-09 09:35:01,462 INFO L587 BuchiCegarLoop]: Abstraction has 807 states and 1215 transitions. [2021-11-09 09:35:01,462 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-09 09:35:01,462 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 807 states and 1215 transitions. [2021-11-09 09:35:01,467 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2021-11-09 09:35:01,467 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:01,467 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:01,469 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:01,470 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:01,470 INFO L791 eck$LassoCheckResult]: Stem: 5498#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 5499#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5384#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 5338#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 5339#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5319#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5162#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5163#L551-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5144#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5145#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5612#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5444#L571-1 assume !(0 == ~M_E~0); 5441#L769-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5442#L774-1 assume !(0 == ~T2_E~0); 5492#L779-1 assume !(0 == ~T3_E~0); 5600#L784-1 assume !(0 == ~T4_E~0); 5437#L789-1 assume !(0 == ~T5_E~0); 5438#L794-1 assume !(0 == ~T6_E~0); 5544#L799-1 assume !(0 == ~T7_E~0); 5445#L804-1 assume !(0 == ~E_M~0); 5446#L809-1 assume 0 == ~E_1~0;~E_1~0 := 1; 5485#L814-1 assume !(0 == ~E_2~0); 4892#L819-1 assume !(0 == ~E_3~0); 4893#L824-1 assume !(0 == ~E_4~0); 5231#L829-1 assume !(0 == ~E_5~0); 5655#L834-1 assume !(0 == ~E_6~0); 5018#L839-1 assume !(0 == ~E_7~0); 5019#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5389#L376 assume !(1 == ~m_pc~0); 5376#L376-2 is_master_triggered_~__retres1~0 := 0; 5377#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5638#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4969#L955 assume !(0 != activate_threads_~tmp~1); 4970#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5314#L395 assume 1 == ~t1_pc~0; 4995#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4996#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4894#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4895#L963 assume !(0 != activate_threads_~tmp___0~0); 5393#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5394#L414 assume !(1 == ~t2_pc~0); 5022#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 5021#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5217#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5218#L971 assume !(0 != activate_threads_~tmp___1~0); 5614#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5315#L433 assume 1 == ~t3_pc~0; 5261#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5133#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5291#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5292#L979 assume !(0 != activate_threads_~tmp___2~0); 4986#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4987#L452 assume 1 == ~t4_pc~0; 5676#L453 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5141#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5425#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 5491#L987 assume !(0 != activate_threads_~tmp___3~0); 5173#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5174#L471 assume !(1 == ~t5_pc~0); 5533#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 5156#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5157#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 5484#L995 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5647#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5648#L490 assume 1 == ~t6_pc~0; 5631#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 5392#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5432#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 5435#L1003 assume !(0 != activate_threads_~tmp___5~0); 5323#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5296#L509 assume !(1 == ~t7_pc~0); 5297#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 5114#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5115#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 5178#L1011 assume !(0 != activate_threads_~tmp___6~0); 5179#L1011-2 assume !(1 == ~M_E~0); 5665#L857-1 assume !(1 == ~T1_E~0); 5238#L862-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5239#L867-1 assume !(1 == ~T3_E~0); 5244#L872-1 assume !(1 == ~T4_E~0); 5316#L877-1 assume !(1 == ~T5_E~0); 5509#L882-1 assume !(1 == ~T6_E~0); 5630#L887-1 assume !(1 == ~T7_E~0); 5558#L892-1 assume !(1 == ~E_M~0); 5559#L897-1 assume !(1 == ~E_1~0); 5254#L902-1 assume 1 == ~E_2~0;~E_2~0 := 2; 5255#L907-1 assume !(1 == ~E_3~0); 5526#L912-1 assume !(1 == ~E_4~0); 5517#L917-1 assume !(1 == ~E_5~0); 5518#L922-1 assume !(1 == ~E_6~0); 5658#L927-1 assume !(1 == ~E_7~0); 4927#L1178-1 [2021-11-09 09:35:01,470 INFO L793 eck$LassoCheckResult]: Loop: 4927#L1178-1 assume !false; 5488#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 5289#L744 assume !false; 5290#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 5359#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 4960#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 5160#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 5604#L641 assume !(0 != eval_~tmp~0); 5424#L759 start_simulation_~kernel_st~0 := 2; 5055#L529-1 start_simulation_~kernel_st~0 := 3; 5056#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 5463#L769-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5474#L774-3 assume !(0 == ~T2_E~0); 5072#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4903#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4904#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4888#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4889#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4942#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5187#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4938#L814-3 assume !(0 == ~E_2~0); 4939#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5580#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5575#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5240#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5241#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5543#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5620#L376-27 assume 1 == ~m_pc~0; 5522#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5469#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5470#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5562#L955-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5661#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5681#L395-27 assume !(1 == ~t1_pc~0); 5331#L395-29 is_transmit1_triggered_~__retres1~1 := 0; 5242#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5243#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5462#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5320#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5321#L414-27 assume 1 == ~t2_pc~0; 5645#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5515#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5516#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 5379#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4952#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4953#L433-27 assume !(1 == ~t3_pc~0); 5043#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 5325#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5326#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 5117#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5118#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5674#L452-27 assume !(1 == ~t4_pc~0); 5481#L452-29 is_transmit4_triggered_~__retres1~4 := 0; 5482#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5603#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 5641#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5642#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4943#L471-27 assume 1 == ~t5_pc~0; 4944#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5251#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5619#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 5536#L995-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5465#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5388#L490-27 assume 1 == ~t6_pc~0; 5293#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 5129#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5130#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 5524#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 5525#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4912#L509-27 assume 1 == ~t7_pc~0; 4913#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 5295#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5414#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 5405#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 5406#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 5420#L857-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5421#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5673#L867-3 assume !(1 == ~T3_E~0); 5327#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5328#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5415#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5455#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5092#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5093#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5595#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5252#L907-3 assume !(1 == ~E_3~0); 5253#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5368#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5332#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5142#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5143#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 4993#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 4901#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 5546#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 5306#L1197 assume !(0 == start_simulation_~tmp~3); 5213#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 5051#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 5016#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 4946#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 4947#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5592#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 5593#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 4926#L1210 assume !(0 != start_simulation_~tmp___0~1); 4927#L1178-1 [2021-11-09 09:35:01,471 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:01,471 INFO L85 PathProgramCache]: Analyzing trace with hash -460842341, now seen corresponding path program 1 times [2021-11-09 09:35:01,471 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:01,472 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [406094878] [2021-11-09 09:35:01,472 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:01,472 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:01,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:01,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:01,527 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:01,527 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [406094878] [2021-11-09 09:35:01,528 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [406094878] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:01,528 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:01,528 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:01,528 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [99630044] [2021-11-09 09:35:01,529 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:01,529 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:01,529 INFO L85 PathProgramCache]: Analyzing trace with hash -1227767879, now seen corresponding path program 1 times [2021-11-09 09:35:01,530 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:01,530 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1862921874] [2021-11-09 09:35:01,530 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:01,530 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:01,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:01,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:01,590 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:01,590 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1862921874] [2021-11-09 09:35:01,590 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1862921874] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:01,590 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:01,590 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:01,591 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [947316205] [2021-11-09 09:35:01,591 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:01,591 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:01,592 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:35:01,592 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:35:01,592 INFO L87 Difference]: Start difference. First operand 807 states and 1215 transitions. cyclomatic complexity: 409 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:01,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:01,609 INFO L93 Difference]: Finished difference Result 807 states and 1214 transitions. [2021-11-09 09:35:01,610 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:35:01,610 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 807 states and 1214 transitions. [2021-11-09 09:35:01,617 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2021-11-09 09:35:01,624 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 807 states to 807 states and 1214 transitions. [2021-11-09 09:35:01,624 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 807 [2021-11-09 09:35:01,625 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 807 [2021-11-09 09:35:01,625 INFO L73 IsDeterministic]: Start isDeterministic. Operand 807 states and 1214 transitions. [2021-11-09 09:35:01,626 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:01,627 INFO L681 BuchiCegarLoop]: Abstraction has 807 states and 1214 transitions. [2021-11-09 09:35:01,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 807 states and 1214 transitions. [2021-11-09 09:35:01,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 807 to 807. [2021-11-09 09:35:01,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 807 states, 807 states have (on average 1.5043370508054523) internal successors, (1214), 806 states have internal predecessors, (1214), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:01,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 807 states to 807 states and 1214 transitions. [2021-11-09 09:35:01,645 INFO L704 BuchiCegarLoop]: Abstraction has 807 states and 1214 transitions. [2021-11-09 09:35:01,645 INFO L587 BuchiCegarLoop]: Abstraction has 807 states and 1214 transitions. [2021-11-09 09:35:01,645 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-09 09:35:01,645 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 807 states and 1214 transitions. [2021-11-09 09:35:01,650 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2021-11-09 09:35:01,650 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:01,651 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:01,652 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:01,653 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:01,653 INFO L791 eck$LassoCheckResult]: Stem: 7119#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 7120#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 7005#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6956#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 6957#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6940#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6783#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6784#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6765#L556-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6766#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7233#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7065#L571-1 assume !(0 == ~M_E~0); 7060#L769-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7061#L774-1 assume !(0 == ~T2_E~0); 7113#L779-1 assume !(0 == ~T3_E~0); 7221#L784-1 assume !(0 == ~T4_E~0); 7058#L789-1 assume !(0 == ~T5_E~0); 7059#L794-1 assume !(0 == ~T6_E~0); 7165#L799-1 assume !(0 == ~T7_E~0); 7066#L804-1 assume !(0 == ~E_M~0); 7067#L809-1 assume 0 == ~E_1~0;~E_1~0 := 1; 7105#L814-1 assume !(0 == ~E_2~0); 6511#L819-1 assume !(0 == ~E_3~0); 6512#L824-1 assume !(0 == ~E_4~0); 6852#L829-1 assume !(0 == ~E_5~0); 7276#L834-1 assume !(0 == ~E_6~0); 6639#L839-1 assume !(0 == ~E_7~0); 6640#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7010#L376 assume !(1 == ~m_pc~0); 6999#L376-2 is_master_triggered_~__retres1~0 := 0; 7000#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7259#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6592#L955 assume !(0 != activate_threads_~tmp~1); 6593#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6935#L395 assume 1 == ~t1_pc~0; 6616#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6617#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6517#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6518#L963 assume !(0 != activate_threads_~tmp___0~0); 7015#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7016#L414 assume !(1 == ~t2_pc~0); 6643#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 6642#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6838#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 6839#L971 assume !(0 != activate_threads_~tmp___1~0); 7235#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6936#L433 assume 1 == ~t3_pc~0; 6882#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6756#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6914#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6915#L979 assume !(0 != activate_threads_~tmp___2~0); 6607#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6608#L452 assume 1 == ~t4_pc~0; 7297#L453 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6762#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7047#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 7112#L987 assume !(0 != activate_threads_~tmp___3~0); 6794#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6795#L471 assume !(1 == ~t5_pc~0); 7154#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 6777#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6778#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 7106#L995 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7268#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7269#L490 assume 1 == ~t6_pc~0; 7253#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7013#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7053#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 7056#L1003 assume !(0 != activate_threads_~tmp___5~0); 6946#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6917#L509 assume !(1 == ~t7_pc~0); 6918#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 6739#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 6740#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 6799#L1011 assume !(0 != activate_threads_~tmp___6~0); 6800#L1011-2 assume !(1 == ~M_E~0); 7286#L857-1 assume !(1 == ~T1_E~0); 6859#L862-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6860#L867-1 assume !(1 == ~T3_E~0); 6865#L872-1 assume !(1 == ~T4_E~0); 6937#L877-1 assume !(1 == ~T5_E~0); 7130#L882-1 assume !(1 == ~T6_E~0); 7251#L887-1 assume !(1 == ~T7_E~0); 7179#L892-1 assume !(1 == ~E_M~0); 7180#L897-1 assume !(1 == ~E_1~0); 6877#L902-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6878#L907-1 assume !(1 == ~E_3~0); 7149#L912-1 assume !(1 == ~E_4~0); 7138#L917-1 assume !(1 == ~E_5~0); 7139#L922-1 assume !(1 == ~E_6~0); 7279#L927-1 assume !(1 == ~E_7~0); 6548#L1178-1 [2021-11-09 09:35:01,653 INFO L793 eck$LassoCheckResult]: Loop: 6548#L1178-1 assume !false; 7109#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 6910#L744 assume !false; 6911#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 6980#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 6581#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 6781#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 7227#L641 assume !(0 != eval_~tmp~0); 7045#L759 start_simulation_~kernel_st~0 := 2; 6676#L529-1 start_simulation_~kernel_st~0 := 3; 6677#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7085#L769-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7095#L774-3 assume !(0 == ~T2_E~0); 6693#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6524#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6525#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6513#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6514#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6563#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6809#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6559#L814-3 assume !(0 == ~E_2~0); 6560#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7202#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7196#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6861#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6862#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7164#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7241#L376-27 assume 1 == ~m_pc~0; 7143#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7090#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7091#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7183#L955-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7282#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7302#L395-27 assume 1 == ~t1_pc~0; 7298#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6863#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6864#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7083#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6941#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6942#L414-27 assume 1 == ~t2_pc~0; 7266#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7136#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7137#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 6996#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6573#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6574#L433-27 assume !(1 == ~t3_pc~0); 6664#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 6944#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6945#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 6735#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6736#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7295#L452-27 assume 1 == ~t4_pc~0; 7296#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7103#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7224#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 7262#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7263#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6564#L471-27 assume 1 == ~t5_pc~0; 6565#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6869#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7240#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 7157#L995-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7086#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7009#L490-27 assume 1 == ~t6_pc~0; 6912#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 6750#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6751#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 7145#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 7146#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6533#L509-27 assume 1 == ~t7_pc~0; 6534#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 6916#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 7035#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 7026#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 7027#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 7041#L857-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7042#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7294#L867-3 assume !(1 == ~T3_E~0); 6948#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6949#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7036#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7076#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6711#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6712#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7216#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6873#L907-3 assume !(1 == ~E_3~0); 6874#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6989#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6952#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6763#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6764#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 6614#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 6520#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 7167#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 6927#L1197 assume !(0 == start_simulation_~tmp~3); 6834#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 6672#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 6637#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 6567#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 6568#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7213#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 7214#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 6547#L1210 assume !(0 != start_simulation_~tmp___0~1); 6548#L1178-1 [2021-11-09 09:35:01,654 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:01,654 INFO L85 PathProgramCache]: Analyzing trace with hash 1418288605, now seen corresponding path program 1 times [2021-11-09 09:35:01,654 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:01,655 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1679280044] [2021-11-09 09:35:01,655 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:01,655 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:01,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:01,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:01,696 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:01,696 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1679280044] [2021-11-09 09:35:01,696 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1679280044] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:01,696 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:01,697 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:01,697 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [619216769] [2021-11-09 09:35:01,697 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:01,698 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:01,698 INFO L85 PathProgramCache]: Analyzing trace with hash -1432956101, now seen corresponding path program 2 times [2021-11-09 09:35:01,698 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:01,699 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1368153529] [2021-11-09 09:35:01,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:01,699 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:01,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:01,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:01,751 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:01,751 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1368153529] [2021-11-09 09:35:01,751 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1368153529] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:01,752 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:01,752 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:01,752 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [178982545] [2021-11-09 09:35:01,753 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:01,753 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:01,754 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:35:01,754 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:35:01,754 INFO L87 Difference]: Start difference. First operand 807 states and 1214 transitions. cyclomatic complexity: 408 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:01,772 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:01,772 INFO L93 Difference]: Finished difference Result 807 states and 1213 transitions. [2021-11-09 09:35:01,773 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:35:01,773 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 807 states and 1213 transitions. [2021-11-09 09:35:01,780 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2021-11-09 09:35:01,787 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 807 states to 807 states and 1213 transitions. [2021-11-09 09:35:01,788 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 807 [2021-11-09 09:35:01,789 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 807 [2021-11-09 09:35:01,789 INFO L73 IsDeterministic]: Start isDeterministic. Operand 807 states and 1213 transitions. [2021-11-09 09:35:01,790 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:01,791 INFO L681 BuchiCegarLoop]: Abstraction has 807 states and 1213 transitions. [2021-11-09 09:35:01,792 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 807 states and 1213 transitions. [2021-11-09 09:35:01,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 807 to 807. [2021-11-09 09:35:01,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 807 states, 807 states have (on average 1.503097893432466) internal successors, (1213), 806 states have internal predecessors, (1213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:01,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 807 states to 807 states and 1213 transitions. [2021-11-09 09:35:01,812 INFO L704 BuchiCegarLoop]: Abstraction has 807 states and 1213 transitions. [2021-11-09 09:35:01,812 INFO L587 BuchiCegarLoop]: Abstraction has 807 states and 1213 transitions. [2021-11-09 09:35:01,812 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-09 09:35:01,812 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 807 states and 1213 transitions. [2021-11-09 09:35:01,835 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2021-11-09 09:35:01,835 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:01,835 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:01,837 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:01,837 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:01,838 INFO L791 eck$LassoCheckResult]: Stem: 8740#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 8741#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8626#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8577#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 8578#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8561#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8404#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8405#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8386#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8387#L561-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8854#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8685#L571-1 assume !(0 == ~M_E~0); 8681#L769-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8682#L774-1 assume !(0 == ~T2_E~0); 8734#L779-1 assume !(0 == ~T3_E~0); 8842#L784-1 assume !(0 == ~T4_E~0); 8679#L789-1 assume !(0 == ~T5_E~0); 8680#L794-1 assume !(0 == ~T6_E~0); 8786#L799-1 assume !(0 == ~T7_E~0); 8687#L804-1 assume !(0 == ~E_M~0); 8688#L809-1 assume 0 == ~E_1~0;~E_1~0 := 1; 8726#L814-1 assume !(0 == ~E_2~0); 8130#L819-1 assume !(0 == ~E_3~0); 8131#L824-1 assume !(0 == ~E_4~0); 8473#L829-1 assume !(0 == ~E_5~0); 8897#L834-1 assume !(0 == ~E_6~0); 8260#L839-1 assume !(0 == ~E_7~0); 8261#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8631#L376 assume !(1 == ~m_pc~0); 8618#L376-2 is_master_triggered_~__retres1~0 := 0; 8619#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8880#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8211#L955 assume !(0 != activate_threads_~tmp~1); 8212#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8556#L395 assume 1 == ~t1_pc~0; 8237#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8238#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8136#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 8137#L963 assume !(0 != activate_threads_~tmp___0~0); 8635#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8636#L414 assume !(1 == ~t2_pc~0); 8264#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 8263#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8459#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 8460#L971 assume !(0 != activate_threads_~tmp___1~0); 8856#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8557#L433 assume 1 == ~t3_pc~0; 8503#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8375#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8533#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 8534#L979 assume !(0 != activate_threads_~tmp___2~0); 8228#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8229#L452 assume 1 == ~t4_pc~0; 8918#L453 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8383#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8667#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 8733#L987 assume !(0 != activate_threads_~tmp___3~0); 8415#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8416#L471 assume !(1 == ~t5_pc~0); 8775#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 8398#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8399#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 8727#L995 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 8889#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8890#L490 assume 1 == ~t6_pc~0; 8873#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 8634#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8674#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 8677#L1003 assume !(0 != activate_threads_~tmp___5~0); 8565#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8538#L509 assume !(1 == ~t7_pc~0); 8539#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 8356#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8357#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 8420#L1011 assume !(0 != activate_threads_~tmp___6~0); 8421#L1011-2 assume !(1 == ~M_E~0); 8907#L857-1 assume !(1 == ~T1_E~0); 8480#L862-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8481#L867-1 assume !(1 == ~T3_E~0); 8486#L872-1 assume !(1 == ~T4_E~0); 8558#L877-1 assume !(1 == ~T5_E~0); 8751#L882-1 assume !(1 == ~T6_E~0); 8872#L887-1 assume !(1 == ~T7_E~0); 8800#L892-1 assume !(1 == ~E_M~0); 8801#L897-1 assume !(1 == ~E_1~0); 8496#L902-1 assume 1 == ~E_2~0;~E_2~0 := 2; 8497#L907-1 assume !(1 == ~E_3~0); 8768#L912-1 assume !(1 == ~E_4~0); 8759#L917-1 assume !(1 == ~E_5~0); 8760#L922-1 assume !(1 == ~E_6~0); 8900#L927-1 assume !(1 == ~E_7~0); 8169#L1178-1 [2021-11-09 09:35:01,838 INFO L793 eck$LassoCheckResult]: Loop: 8169#L1178-1 assume !false; 8730#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 8531#L744 assume !false; 8532#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 8601#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 8202#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 8402#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 8846#L641 assume !(0 != eval_~tmp~0); 8666#L759 start_simulation_~kernel_st~0 := 2; 8297#L529-1 start_simulation_~kernel_st~0 := 3; 8298#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 8705#L769-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8716#L774-3 assume !(0 == ~T2_E~0); 8314#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8145#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8146#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8132#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8133#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8184#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8429#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8180#L814-3 assume !(0 == ~E_2~0); 8181#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8822#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8817#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8482#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8483#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8785#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8862#L376-27 assume 1 == ~m_pc~0; 8764#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 8711#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8712#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8804#L955-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8903#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8923#L395-27 assume 1 == ~t1_pc~0; 8919#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8484#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8485#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 8704#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8562#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8563#L414-27 assume 1 == ~t2_pc~0; 8887#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8757#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8758#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 8621#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8194#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8195#L433-27 assume !(1 == ~t3_pc~0); 8285#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 8567#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8568#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 8359#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8360#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8916#L452-27 assume !(1 == ~t4_pc~0); 8723#L452-29 is_transmit4_triggered_~__retres1~4 := 0; 8724#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8845#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 8883#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 8884#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8185#L471-27 assume 1 == ~t5_pc~0; 8186#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8493#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8861#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 8778#L995-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 8707#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8630#L490-27 assume 1 == ~t6_pc~0; 8535#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 8371#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8372#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 8766#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 8767#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8154#L509-27 assume 1 == ~t7_pc~0; 8155#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 8537#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8656#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 8647#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 8648#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 8662#L857-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8663#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8915#L867-3 assume !(1 == ~T3_E~0); 8569#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8570#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8657#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8697#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8334#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8335#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8837#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8494#L907-3 assume !(1 == ~E_3~0); 8495#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8610#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8574#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8384#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8385#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 8235#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 8143#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 8788#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 8548#L1197 assume !(0 == start_simulation_~tmp~3); 8455#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 8293#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 8258#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 8188#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 8189#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 8834#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 8835#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 8168#L1210 assume !(0 != start_simulation_~tmp___0~1); 8169#L1178-1 [2021-11-09 09:35:01,839 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:01,840 INFO L85 PathProgramCache]: Analyzing trace with hash 93432411, now seen corresponding path program 1 times [2021-11-09 09:35:01,840 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:01,841 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1399382741] [2021-11-09 09:35:01,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:01,841 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:01,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:01,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:01,900 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:01,900 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1399382741] [2021-11-09 09:35:01,901 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1399382741] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:01,901 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:01,902 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:01,902 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1295771778] [2021-11-09 09:35:01,903 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:01,904 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:01,904 INFO L85 PathProgramCache]: Analyzing trace with hash -2134524326, now seen corresponding path program 2 times [2021-11-09 09:35:01,905 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:01,906 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1299060911] [2021-11-09 09:35:01,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:01,906 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:01,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:01,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:01,960 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:01,965 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1299060911] [2021-11-09 09:35:01,966 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1299060911] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:01,966 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:01,966 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:01,966 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1754276621] [2021-11-09 09:35:01,967 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:01,968 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:01,970 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:35:01,970 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:35:01,971 INFO L87 Difference]: Start difference. First operand 807 states and 1213 transitions. cyclomatic complexity: 407 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:01,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:01,990 INFO L93 Difference]: Finished difference Result 807 states and 1212 transitions. [2021-11-09 09:35:01,991 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:35:01,991 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 807 states and 1212 transitions. [2021-11-09 09:35:01,999 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2021-11-09 09:35:02,007 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 807 states to 807 states and 1212 transitions. [2021-11-09 09:35:02,013 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 807 [2021-11-09 09:35:02,014 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 807 [2021-11-09 09:35:02,014 INFO L73 IsDeterministic]: Start isDeterministic. Operand 807 states and 1212 transitions. [2021-11-09 09:35:02,016 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:02,016 INFO L681 BuchiCegarLoop]: Abstraction has 807 states and 1212 transitions. [2021-11-09 09:35:02,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 807 states and 1212 transitions. [2021-11-09 09:35:02,031 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 807 to 807. [2021-11-09 09:35:02,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 807 states, 807 states have (on average 1.5018587360594795) internal successors, (1212), 806 states have internal predecessors, (1212), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:02,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 807 states to 807 states and 1212 transitions. [2021-11-09 09:35:02,038 INFO L704 BuchiCegarLoop]: Abstraction has 807 states and 1212 transitions. [2021-11-09 09:35:02,039 INFO L587 BuchiCegarLoop]: Abstraction has 807 states and 1212 transitions. [2021-11-09 09:35:02,039 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-09 09:35:02,039 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 807 states and 1212 transitions. [2021-11-09 09:35:02,045 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2021-11-09 09:35:02,045 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:02,045 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:02,047 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:02,047 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:02,048 INFO L791 eck$LassoCheckResult]: Stem: 10361#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 10362#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10247#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10198#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 10199#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10182#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10025#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10026#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10007#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10008#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10475#L566-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10306#L571-1 assume !(0 == ~M_E~0); 10302#L769-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10303#L774-1 assume !(0 == ~T2_E~0); 10355#L779-1 assume !(0 == ~T3_E~0); 10463#L784-1 assume !(0 == ~T4_E~0); 10300#L789-1 assume !(0 == ~T5_E~0); 10301#L794-1 assume !(0 == ~T6_E~0); 10407#L799-1 assume !(0 == ~T7_E~0); 10308#L804-1 assume !(0 == ~E_M~0); 10309#L809-1 assume 0 == ~E_1~0;~E_1~0 := 1; 10347#L814-1 assume !(0 == ~E_2~0); 9751#L819-1 assume !(0 == ~E_3~0); 9752#L824-1 assume !(0 == ~E_4~0); 10094#L829-1 assume !(0 == ~E_5~0); 10518#L834-1 assume !(0 == ~E_6~0); 9881#L839-1 assume !(0 == ~E_7~0); 9882#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10252#L376 assume !(1 == ~m_pc~0); 10239#L376-2 is_master_triggered_~__retres1~0 := 0; 10240#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10501#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9832#L955 assume !(0 != activate_threads_~tmp~1); 9833#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10177#L395 assume 1 == ~t1_pc~0; 9858#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9859#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9757#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9758#L963 assume !(0 != activate_threads_~tmp___0~0); 10256#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10257#L414 assume !(1 == ~t2_pc~0); 9885#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 9884#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10080#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 10081#L971 assume !(0 != activate_threads_~tmp___1~0); 10477#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10178#L433 assume 1 == ~t3_pc~0; 10124#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9996#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10154#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 10155#L979 assume !(0 != activate_threads_~tmp___2~0); 9849#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9850#L452 assume 1 == ~t4_pc~0; 10539#L453 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 10004#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10288#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 10354#L987 assume !(0 != activate_threads_~tmp___3~0); 10036#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10037#L471 assume !(1 == ~t5_pc~0); 10396#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 10019#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10020#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 10348#L995 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 10510#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10511#L490 assume 1 == ~t6_pc~0; 10494#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 10255#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10295#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 10298#L1003 assume !(0 != activate_threads_~tmp___5~0); 10186#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 10159#L509 assume !(1 == ~t7_pc~0); 10160#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 9977#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 9978#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 10041#L1011 assume !(0 != activate_threads_~tmp___6~0); 10042#L1011-2 assume !(1 == ~M_E~0); 10528#L857-1 assume !(1 == ~T1_E~0); 10101#L862-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10102#L867-1 assume !(1 == ~T3_E~0); 10107#L872-1 assume !(1 == ~T4_E~0); 10179#L877-1 assume !(1 == ~T5_E~0); 10372#L882-1 assume !(1 == ~T6_E~0); 10493#L887-1 assume !(1 == ~T7_E~0); 10421#L892-1 assume !(1 == ~E_M~0); 10422#L897-1 assume !(1 == ~E_1~0); 10117#L902-1 assume 1 == ~E_2~0;~E_2~0 := 2; 10118#L907-1 assume !(1 == ~E_3~0); 10389#L912-1 assume !(1 == ~E_4~0); 10380#L917-1 assume !(1 == ~E_5~0); 10381#L922-1 assume !(1 == ~E_6~0); 10521#L927-1 assume !(1 == ~E_7~0); 9790#L1178-1 [2021-11-09 09:35:02,048 INFO L793 eck$LassoCheckResult]: Loop: 9790#L1178-1 assume !false; 10351#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 10152#L744 assume !false; 10153#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 10222#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 9823#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 10023#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 10467#L641 assume !(0 != eval_~tmp~0); 10287#L759 start_simulation_~kernel_st~0 := 2; 9918#L529-1 start_simulation_~kernel_st~0 := 3; 9919#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 10326#L769-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10337#L774-3 assume !(0 == ~T2_E~0); 9935#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9766#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9767#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9753#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9754#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9805#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10050#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9801#L814-3 assume !(0 == ~E_2~0); 9802#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10443#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10438#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10103#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10104#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10406#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10483#L376-27 assume 1 == ~m_pc~0; 10385#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 10332#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10333#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10425#L955-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10524#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10544#L395-27 assume !(1 == ~t1_pc~0); 10194#L395-29 is_transmit1_triggered_~__retres1~1 := 0; 10105#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10106#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 10325#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10183#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10184#L414-27 assume 1 == ~t2_pc~0; 10508#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10378#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10379#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 10242#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9815#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9816#L433-27 assume !(1 == ~t3_pc~0); 9906#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 10188#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10189#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 9980#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9981#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10537#L452-27 assume !(1 == ~t4_pc~0); 10344#L452-29 is_transmit4_triggered_~__retres1~4 := 0; 10345#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10466#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 10504#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10505#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9806#L471-27 assume !(1 == ~t5_pc~0); 9808#L471-29 is_transmit5_triggered_~__retres1~5 := 0; 10114#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10482#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 10399#L995-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 10328#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10251#L490-27 assume 1 == ~t6_pc~0; 10156#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 9992#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9993#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 10387#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 10388#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9775#L509-27 assume 1 == ~t7_pc~0; 9776#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 10158#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10277#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 10268#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 10269#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 10283#L857-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10284#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10536#L867-3 assume !(1 == ~T3_E~0); 10190#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10191#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10278#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10318#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9955#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9956#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10458#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10115#L907-3 assume !(1 == ~E_3~0); 10116#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10231#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10195#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10005#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10006#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 9856#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 9764#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 10409#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 10169#L1197 assume !(0 == start_simulation_~tmp~3); 10076#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 9914#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 9879#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 9809#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 9810#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 10455#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 10456#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 9789#L1210 assume !(0 != start_simulation_~tmp___0~1); 9790#L1178-1 [2021-11-09 09:35:02,049 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:02,049 INFO L85 PathProgramCache]: Analyzing trace with hash -1473325539, now seen corresponding path program 1 times [2021-11-09 09:35:02,049 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:02,050 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1301322050] [2021-11-09 09:35:02,050 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:02,052 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:02,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:02,084 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:02,084 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:02,084 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1301322050] [2021-11-09 09:35:02,085 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1301322050] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:02,085 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:02,085 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:02,085 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1265912511] [2021-11-09 09:35:02,086 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:02,086 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:02,087 INFO L85 PathProgramCache]: Analyzing trace with hash 1759194648, now seen corresponding path program 1 times [2021-11-09 09:35:02,087 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:02,087 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [302869394] [2021-11-09 09:35:02,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:02,088 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:02,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:02,143 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:02,143 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:02,143 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [302869394] [2021-11-09 09:35:02,144 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [302869394] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:02,144 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:02,144 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:02,145 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [40821649] [2021-11-09 09:35:02,145 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:02,145 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:02,146 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:35:02,146 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:35:02,147 INFO L87 Difference]: Start difference. First operand 807 states and 1212 transitions. cyclomatic complexity: 406 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:02,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:02,172 INFO L93 Difference]: Finished difference Result 807 states and 1211 transitions. [2021-11-09 09:35:02,172 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:35:02,173 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 807 states and 1211 transitions. [2021-11-09 09:35:02,180 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2021-11-09 09:35:02,188 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 807 states to 807 states and 1211 transitions. [2021-11-09 09:35:02,188 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 807 [2021-11-09 09:35:02,189 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 807 [2021-11-09 09:35:02,190 INFO L73 IsDeterministic]: Start isDeterministic. Operand 807 states and 1211 transitions. [2021-11-09 09:35:02,193 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:02,194 INFO L681 BuchiCegarLoop]: Abstraction has 807 states and 1211 transitions. [2021-11-09 09:35:02,197 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 807 states and 1211 transitions. [2021-11-09 09:35:02,211 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 807 to 807. [2021-11-09 09:35:02,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 807 states, 807 states have (on average 1.500619578686493) internal successors, (1211), 806 states have internal predecessors, (1211), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:02,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 807 states to 807 states and 1211 transitions. [2021-11-09 09:35:02,217 INFO L704 BuchiCegarLoop]: Abstraction has 807 states and 1211 transitions. [2021-11-09 09:35:02,217 INFO L587 BuchiCegarLoop]: Abstraction has 807 states and 1211 transitions. [2021-11-09 09:35:02,217 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-09 09:35:02,217 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 807 states and 1211 transitions. [2021-11-09 09:35:02,223 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2021-11-09 09:35:02,223 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:02,224 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:02,226 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:02,226 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:02,226 INFO L791 eck$LassoCheckResult]: Stem: 11982#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 11983#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 11868#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 11819#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 11820#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11803#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11646#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11647#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11628#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11629#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12096#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 11927#L571-1 assume !(0 == ~M_E~0); 11923#L769-1 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11924#L774-1 assume !(0 == ~T2_E~0); 11976#L779-1 assume !(0 == ~T3_E~0); 12084#L784-1 assume !(0 == ~T4_E~0); 11921#L789-1 assume !(0 == ~T5_E~0); 11922#L794-1 assume !(0 == ~T6_E~0); 12028#L799-1 assume !(0 == ~T7_E~0); 11929#L804-1 assume !(0 == ~E_M~0); 11930#L809-1 assume 0 == ~E_1~0;~E_1~0 := 1; 11968#L814-1 assume !(0 == ~E_2~0); 11372#L819-1 assume !(0 == ~E_3~0); 11373#L824-1 assume !(0 == ~E_4~0); 11715#L829-1 assume !(0 == ~E_5~0); 12139#L834-1 assume !(0 == ~E_6~0); 11502#L839-1 assume !(0 == ~E_7~0); 11503#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11873#L376 assume !(1 == ~m_pc~0); 11860#L376-2 is_master_triggered_~__retres1~0 := 0; 11861#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12122#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 11453#L955 assume !(0 != activate_threads_~tmp~1); 11454#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11798#L395 assume 1 == ~t1_pc~0; 11479#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 11480#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11378#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 11379#L963 assume !(0 != activate_threads_~tmp___0~0); 11877#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11878#L414 assume !(1 == ~t2_pc~0); 11506#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 11505#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11701#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 11702#L971 assume !(0 != activate_threads_~tmp___1~0); 12098#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11799#L433 assume 1 == ~t3_pc~0; 11745#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11617#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11775#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 11776#L979 assume !(0 != activate_threads_~tmp___2~0); 11470#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11471#L452 assume 1 == ~t4_pc~0; 12160#L453 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 11625#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11909#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 11975#L987 assume !(0 != activate_threads_~tmp___3~0); 11657#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11658#L471 assume !(1 == ~t5_pc~0); 12017#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 11640#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11641#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 11969#L995 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 12131#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12132#L490 assume 1 == ~t6_pc~0; 12115#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 11876#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11916#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 11919#L1003 assume !(0 != activate_threads_~tmp___5~0); 11807#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11780#L509 assume !(1 == ~t7_pc~0); 11781#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 11598#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 11599#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 11662#L1011 assume !(0 != activate_threads_~tmp___6~0); 11663#L1011-2 assume !(1 == ~M_E~0); 12149#L857-1 assume !(1 == ~T1_E~0); 11722#L862-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11723#L867-1 assume !(1 == ~T3_E~0); 11728#L872-1 assume !(1 == ~T4_E~0); 11800#L877-1 assume !(1 == ~T5_E~0); 11993#L882-1 assume !(1 == ~T6_E~0); 12114#L887-1 assume !(1 == ~T7_E~0); 12042#L892-1 assume !(1 == ~E_M~0); 12043#L897-1 assume !(1 == ~E_1~0); 11738#L902-1 assume 1 == ~E_2~0;~E_2~0 := 2; 11739#L907-1 assume !(1 == ~E_3~0); 12010#L912-1 assume !(1 == ~E_4~0); 12001#L917-1 assume !(1 == ~E_5~0); 12002#L922-1 assume !(1 == ~E_6~0); 12142#L927-1 assume !(1 == ~E_7~0); 11411#L1178-1 [2021-11-09 09:35:02,227 INFO L793 eck$LassoCheckResult]: Loop: 11411#L1178-1 assume !false; 11972#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 11773#L744 assume !false; 11774#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 11843#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 11444#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 11644#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 12088#L641 assume !(0 != eval_~tmp~0); 11908#L759 start_simulation_~kernel_st~0 := 2; 11539#L529-1 start_simulation_~kernel_st~0 := 3; 11540#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 11947#L769-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11958#L774-3 assume !(0 == ~T2_E~0); 11556#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11387#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11388#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11374#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11375#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11426#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11671#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11422#L814-3 assume !(0 == ~E_2~0); 11423#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12064#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12059#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11724#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11725#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12027#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12104#L376-27 assume 1 == ~m_pc~0; 12006#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 11953#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11954#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 12046#L955-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12145#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12165#L395-27 assume 1 == ~t1_pc~0; 12161#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 11726#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11727#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 11946#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11804#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11805#L414-27 assume 1 == ~t2_pc~0; 12129#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 11999#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12000#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 11863#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 11436#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11437#L433-27 assume !(1 == ~t3_pc~0); 11527#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 11809#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11810#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 11601#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 11602#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12158#L452-27 assume !(1 == ~t4_pc~0); 11965#L452-29 is_transmit4_triggered_~__retres1~4 := 0; 11966#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12087#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 12125#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12126#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11427#L471-27 assume 1 == ~t5_pc~0; 11428#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 11735#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12103#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 12020#L995-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 11949#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11872#L490-27 assume 1 == ~t6_pc~0; 11777#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 11613#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11614#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 12008#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 12009#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11396#L509-27 assume 1 == ~t7_pc~0; 11397#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 11779#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 11898#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 11889#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 11890#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 11904#L857-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11905#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12157#L867-3 assume !(1 == ~T3_E~0); 11811#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11812#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11899#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11939#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11576#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11577#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12079#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11736#L907-3 assume !(1 == ~E_3~0); 11737#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11852#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11816#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11626#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11627#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 11477#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 11385#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 12030#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 11790#L1197 assume !(0 == start_simulation_~tmp~3); 11697#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 11535#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 11500#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 11430#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 11431#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12076#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 12077#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 11410#L1210 assume !(0 != start_simulation_~tmp___0~1); 11411#L1178-1 [2021-11-09 09:35:02,227 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:02,228 INFO L85 PathProgramCache]: Analyzing trace with hash -415487461, now seen corresponding path program 1 times [2021-11-09 09:35:02,228 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:02,228 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1563158192] [2021-11-09 09:35:02,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:02,229 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:02,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:02,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:02,266 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:02,266 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1563158192] [2021-11-09 09:35:02,267 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1563158192] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:02,267 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:02,267 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-09 09:35:02,267 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1986272961] [2021-11-09 09:35:02,268 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:02,269 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:02,269 INFO L85 PathProgramCache]: Analyzing trace with hash -2134524326, now seen corresponding path program 3 times [2021-11-09 09:35:02,269 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:02,269 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [895488563] [2021-11-09 09:35:02,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:02,270 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:02,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:02,312 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:02,312 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:02,313 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [895488563] [2021-11-09 09:35:02,318 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [895488563] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:02,320 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:02,321 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:02,321 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [406982490] [2021-11-09 09:35:02,321 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:02,322 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:02,322 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:35:02,322 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:35:02,323 INFO L87 Difference]: Start difference. First operand 807 states and 1211 transitions. cyclomatic complexity: 405 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 2 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:02,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:02,345 INFO L93 Difference]: Finished difference Result 807 states and 1206 transitions. [2021-11-09 09:35:02,345 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:35:02,347 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 807 states and 1206 transitions. [2021-11-09 09:35:02,356 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2021-11-09 09:35:02,363 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 807 states to 807 states and 1206 transitions. [2021-11-09 09:35:02,363 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 807 [2021-11-09 09:35:02,364 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 807 [2021-11-09 09:35:02,364 INFO L73 IsDeterministic]: Start isDeterministic. Operand 807 states and 1206 transitions. [2021-11-09 09:35:02,366 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:02,366 INFO L681 BuchiCegarLoop]: Abstraction has 807 states and 1206 transitions. [2021-11-09 09:35:02,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 807 states and 1206 transitions. [2021-11-09 09:35:02,379 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 807 to 807. [2021-11-09 09:35:02,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 807 states, 807 states have (on average 1.4944237918215613) internal successors, (1206), 806 states have internal predecessors, (1206), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:02,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 807 states to 807 states and 1206 transitions. [2021-11-09 09:35:02,386 INFO L704 BuchiCegarLoop]: Abstraction has 807 states and 1206 transitions. [2021-11-09 09:35:02,386 INFO L587 BuchiCegarLoop]: Abstraction has 807 states and 1206 transitions. [2021-11-09 09:35:02,387 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-09 09:35:02,387 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 807 states and 1206 transitions. [2021-11-09 09:35:02,392 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 708 [2021-11-09 09:35:02,392 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:02,392 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:02,394 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:02,394 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:02,394 INFO L791 eck$LassoCheckResult]: Stem: 13603#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 13604#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 13489#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 13443#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 13444#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13424#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13267#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13268#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13249#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13250#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13717#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13549#L571-1 assume !(0 == ~M_E~0); 13546#L769-1 assume !(0 == ~T1_E~0); 13547#L774-1 assume !(0 == ~T2_E~0); 13597#L779-1 assume !(0 == ~T3_E~0); 13705#L784-1 assume !(0 == ~T4_E~0); 13542#L789-1 assume !(0 == ~T5_E~0); 13543#L794-1 assume !(0 == ~T6_E~0); 13649#L799-1 assume !(0 == ~T7_E~0); 13550#L804-1 assume !(0 == ~E_M~0); 13551#L809-1 assume 0 == ~E_1~0;~E_1~0 := 1; 13589#L814-1 assume !(0 == ~E_2~0); 12997#L819-1 assume !(0 == ~E_3~0); 12998#L824-1 assume !(0 == ~E_4~0); 13336#L829-1 assume !(0 == ~E_5~0); 13760#L834-1 assume !(0 == ~E_6~0); 13123#L839-1 assume !(0 == ~E_7~0); 13124#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13494#L376 assume !(1 == ~m_pc~0); 13484#L376-2 is_master_triggered_~__retres1~0 := 0; 13485#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13743#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 13076#L955 assume !(0 != activate_threads_~tmp~1); 13077#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13419#L395 assume 1 == ~t1_pc~0; 13100#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 13101#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13001#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 13002#L963 assume !(0 != activate_threads_~tmp___0~0); 13499#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13500#L414 assume !(1 == ~t2_pc~0); 13127#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 13126#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13322#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 13323#L971 assume !(0 != activate_threads_~tmp___1~0); 13720#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13420#L433 assume 1 == ~t3_pc~0; 13366#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 13240#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13398#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 13399#L979 assume !(0 != activate_threads_~tmp___2~0); 13091#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13092#L452 assume 1 == ~t4_pc~0; 13781#L453 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 13246#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13531#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 13596#L987 assume !(0 != activate_threads_~tmp___3~0); 13278#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13279#L471 assume !(1 == ~t5_pc~0); 13638#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 13261#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13262#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 13590#L995 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 13752#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13753#L490 assume 1 == ~t6_pc~0; 13737#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 13497#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 13539#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 13541#L1003 assume !(0 != activate_threads_~tmp___5~0); 13431#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 13401#L509 assume !(1 == ~t7_pc~0); 13402#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 13224#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 13225#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 13283#L1011 assume !(0 != activate_threads_~tmp___6~0); 13284#L1011-2 assume !(1 == ~M_E~0); 13770#L857-1 assume !(1 == ~T1_E~0); 13343#L862-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13344#L867-1 assume !(1 == ~T3_E~0); 13349#L872-1 assume !(1 == ~T4_E~0); 13421#L877-1 assume !(1 == ~T5_E~0); 13614#L882-1 assume !(1 == ~T6_E~0); 13735#L887-1 assume !(1 == ~T7_E~0); 13663#L892-1 assume !(1 == ~E_M~0); 13664#L897-1 assume !(1 == ~E_1~0); 13361#L902-1 assume 1 == ~E_2~0;~E_2~0 := 2; 13362#L907-1 assume !(1 == ~E_3~0); 13633#L912-1 assume !(1 == ~E_4~0); 13622#L917-1 assume !(1 == ~E_5~0); 13623#L922-1 assume !(1 == ~E_6~0); 13763#L927-1 assume !(1 == ~E_7~0); 13032#L1178-1 [2021-11-09 09:35:02,395 INFO L793 eck$LassoCheckResult]: Loop: 13032#L1178-1 assume !false; 13593#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 13394#L744 assume !false; 13395#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 13464#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 13065#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 13265#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 13711#L641 assume !(0 != eval_~tmp~0); 13529#L759 start_simulation_~kernel_st~0 := 2; 13160#L529-1 start_simulation_~kernel_st~0 := 3; 13161#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 13568#L769-4 assume !(0 == ~T1_E~0); 13579#L774-3 assume !(0 == ~T2_E~0); 13177#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13008#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13009#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12993#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12994#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13047#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13292#L809-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13043#L814-3 assume !(0 == ~E_2~0); 13044#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13685#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13680#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13345#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13346#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13648#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13725#L376-27 assume 1 == ~m_pc~0; 13627#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 13574#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13575#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 13667#L955-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13766#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13786#L395-27 assume 1 == ~t1_pc~0; 13782#L396-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 13347#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13348#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 13567#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 13425#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13426#L414-27 assume 1 == ~t2_pc~0; 13750#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 13620#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13621#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 13481#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13057#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13058#L433-27 assume !(1 == ~t3_pc~0); 13148#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 13429#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13430#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 13220#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 13221#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13779#L452-27 assume !(1 == ~t4_pc~0); 13586#L452-29 is_transmit4_triggered_~__retres1~4 := 0; 13587#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13708#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 13746#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 13747#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13048#L471-27 assume 1 == ~t5_pc~0; 13049#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 13356#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13724#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 13641#L995-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 13570#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13493#L490-27 assume 1 == ~t6_pc~0; 13396#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 13234#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 13235#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 13629#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 13630#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 13017#L509-27 assume 1 == ~t7_pc~0; 13018#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 13400#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 13519#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 13510#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 13511#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 13525#L857-3 assume !(1 == ~T1_E~0); 13526#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13778#L867-3 assume !(1 == ~T3_E~0); 13432#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13433#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13520#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13560#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13197#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13198#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13700#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13357#L907-3 assume !(1 == ~E_3~0); 13358#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13473#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13437#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13247#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13248#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 13098#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 13006#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 13651#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 13411#L1197 assume !(0 == start_simulation_~tmp~3); 13318#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 13156#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 13121#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 13051#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 13052#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 13697#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 13698#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 13031#L1210 assume !(0 != start_simulation_~tmp___0~1); 13032#L1178-1 [2021-11-09 09:35:02,395 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:02,395 INFO L85 PathProgramCache]: Analyzing trace with hash -175247715, now seen corresponding path program 1 times [2021-11-09 09:35:02,396 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:02,396 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1434084419] [2021-11-09 09:35:02,396 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:02,396 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:02,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:02,438 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:02,438 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:02,441 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1434084419] [2021-11-09 09:35:02,441 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1434084419] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:02,441 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:02,441 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:02,441 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1705342886] [2021-11-09 09:35:02,442 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:02,442 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:02,442 INFO L85 PathProgramCache]: Analyzing trace with hash 1622469590, now seen corresponding path program 1 times [2021-11-09 09:35:02,443 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:02,443 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [884694619] [2021-11-09 09:35:02,443 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:02,443 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:02,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:02,514 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:02,514 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:02,514 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [884694619] [2021-11-09 09:35:02,514 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [884694619] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:02,514 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:02,515 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:02,515 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1234598712] [2021-11-09 09:35:02,515 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:02,515 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:02,516 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-09 09:35:02,516 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-09 09:35:02,516 INFO L87 Difference]: Start difference. First operand 807 states and 1206 transitions. cyclomatic complexity: 400 Second operand has 4 states, 4 states have (on average 22.75) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:02,713 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:02,713 INFO L93 Difference]: Finished difference Result 1410 states and 2107 transitions. [2021-11-09 09:35:02,714 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-09 09:35:02,714 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1410 states and 2107 transitions. [2021-11-09 09:35:02,726 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1298 [2021-11-09 09:35:02,738 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1410 states to 1410 states and 2107 transitions. [2021-11-09 09:35:02,738 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1410 [2021-11-09 09:35:02,740 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1410 [2021-11-09 09:35:02,740 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1410 states and 2107 transitions. [2021-11-09 09:35:02,743 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:02,743 INFO L681 BuchiCegarLoop]: Abstraction has 1410 states and 2107 transitions. [2021-11-09 09:35:02,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1410 states and 2107 transitions. [2021-11-09 09:35:02,774 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1410 to 1404. [2021-11-09 09:35:02,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1404 states, 1404 states have (on average 1.495014245014245) internal successors, (2099), 1403 states have internal predecessors, (2099), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:02,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1404 states to 1404 states and 2099 transitions. [2021-11-09 09:35:02,784 INFO L704 BuchiCegarLoop]: Abstraction has 1404 states and 2099 transitions. [2021-11-09 09:35:02,784 INFO L587 BuchiCegarLoop]: Abstraction has 1404 states and 2099 transitions. [2021-11-09 09:35:02,784 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-09 09:35:02,784 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1404 states and 2099 transitions. [2021-11-09 09:35:02,793 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1298 [2021-11-09 09:35:02,793 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:02,793 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:02,795 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:02,795 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:02,796 INFO L791 eck$LassoCheckResult]: Stem: 15848#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 15849#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 15724#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 15673#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 15674#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15656#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15494#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15495#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15476#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15477#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15979#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 15788#L571-1 assume !(0 == ~M_E~0); 15783#L769-1 assume !(0 == ~T1_E~0); 15784#L774-1 assume !(0 == ~T2_E~0); 15841#L779-1 assume !(0 == ~T3_E~0); 15963#L784-1 assume !(0 == ~T4_E~0); 15781#L789-1 assume !(0 == ~T5_E~0); 15782#L794-1 assume !(0 == ~T6_E~0); 15896#L799-1 assume !(0 == ~T7_E~0); 15789#L804-1 assume !(0 == ~E_M~0); 15790#L809-1 assume !(0 == ~E_1~0); 15830#L814-1 assume !(0 == ~E_2~0); 15222#L819-1 assume !(0 == ~E_3~0); 15223#L824-1 assume !(0 == ~E_4~0); 15567#L829-1 assume !(0 == ~E_5~0); 16024#L834-1 assume !(0 == ~E_6~0); 15350#L839-1 assume !(0 == ~E_7~0); 15351#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15729#L376 assume !(1 == ~m_pc~0); 15718#L376-2 is_master_triggered_~__retres1~0 := 0; 15719#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16005#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 15303#L955 assume !(0 != activate_threads_~tmp~1); 15304#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15651#L395 assume 1 == ~t1_pc~0; 15327#L396 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 15328#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15228#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 15229#L963 assume !(0 != activate_threads_~tmp___0~0); 15735#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15736#L414 assume !(1 == ~t2_pc~0); 15354#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 15353#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15553#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 15554#L971 assume !(0 != activate_threads_~tmp___1~0); 15981#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15652#L433 assume 1 == ~t3_pc~0; 15597#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 15467#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15630#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 15631#L979 assume !(0 != activate_threads_~tmp___2~0); 15318#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15319#L452 assume 1 == ~t4_pc~0; 16051#L453 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 15473#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15770#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 15840#L987 assume !(0 != activate_threads_~tmp___3~0); 15506#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15507#L471 assume !(1 == ~t5_pc~0); 15884#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 15488#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15489#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 15831#L995 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 16015#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 16016#L490 assume 1 == ~t6_pc~0; 15999#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 15733#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 15776#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 15779#L1003 assume !(0 != activate_threads_~tmp___5~0); 15662#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 15633#L509 assume !(1 == ~t7_pc~0); 15634#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 15450#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 15451#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 15511#L1011 assume !(0 != activate_threads_~tmp___6~0); 15512#L1011-2 assume !(1 == ~M_E~0); 16035#L857-1 assume !(1 == ~T1_E~0); 15574#L862-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15575#L867-1 assume !(1 == ~T3_E~0); 15580#L872-1 assume !(1 == ~T4_E~0); 15653#L877-1 assume !(1 == ~T5_E~0); 15860#L882-1 assume !(1 == ~T6_E~0); 15997#L887-1 assume !(1 == ~T7_E~0); 15914#L892-1 assume 1 == ~E_M~0;~E_M~0 := 2; 15915#L897-1 assume !(1 == ~E_1~0); 16039#L902-1 assume 1 == ~E_2~0;~E_2~0 := 2; 15931#L907-1 assume !(1 == ~E_3~0); 15879#L912-1 assume !(1 == ~E_4~0); 15868#L917-1 assume !(1 == ~E_5~0); 15869#L922-1 assume !(1 == ~E_6~0); 16027#L927-1 assume !(1 == ~E_7~0); 15259#L1178-1 [2021-11-09 09:35:02,796 INFO L793 eck$LassoCheckResult]: Loop: 15259#L1178-1 assume !false; 15837#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 15835#L744 assume !false; 16078#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 16076#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 16069#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 16068#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 15970#L641 assume !(0 != eval_~tmp~0); 15767#L759 start_simulation_~kernel_st~0 := 2; 15768#L529-1 start_simulation_~kernel_st~0 := 3; 15809#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 15810#L769-4 assume !(0 == ~T1_E~0); 15820#L774-3 assume !(0 == ~T2_E~0); 15406#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15235#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15236#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15224#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15225#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15274#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15730#L809-3 assume !(0 == ~E_1~0); 15272#L814-3 assume !(0 == ~E_2~0); 15273#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15939#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15933#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15578#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15579#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15895#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15987#L376-27 assume 1 == ~m_pc~0; 15873#L377-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 15818#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15819#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 15919#L955-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 16031#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16061#L395-27 assume !(1 == ~t1_pc~0); 15668#L395-29 is_transmit1_triggered_~__retres1~1 := 0; 15576#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15577#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 15944#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16475#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16474#L414-27 assume 1 == ~t2_pc~0; 16472#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 16471#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16470#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 16469#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 16468#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16467#L433-27 assume !(1 == ~t3_pc~0); 16465#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 16464#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16463#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 16409#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 16408#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16406#L452-27 assume 1 == ~t4_pc~0; 16403#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 16401#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16400#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 16399#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 16398#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16397#L471-27 assume !(1 == ~t5_pc~0); 16395#L471-29 is_transmit5_triggered_~__retres1~5 := 0; 16394#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16393#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 16392#L995-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 16391#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 16390#L490-27 assume 1 == ~t6_pc~0; 16388#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 16387#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16386#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 16385#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 16384#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 16383#L509-27 assume 1 == ~t7_pc~0; 16381#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 16380#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 16379#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 16378#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 16377#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 15763#L857-3 assume !(1 == ~T1_E~0); 15764#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16044#L867-3 assume !(1 == ~T3_E~0); 15664#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15665#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16052#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15800#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15422#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15423#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15956#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15588#L907-3 assume !(1 == ~E_3~0); 15589#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16273#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16271#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15474#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15475#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 15598#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 15899#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 15900#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 16057#L1197 assume !(0 == start_simulation_~tmp~3); 16245#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 15383#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 15348#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 15278#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 15279#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15952#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 15953#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 15258#L1210 assume !(0 != start_simulation_~tmp___0~1); 15259#L1178-1 [2021-11-09 09:35:02,797 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:02,797 INFO L85 PathProgramCache]: Analyzing trace with hash -333251743, now seen corresponding path program 1 times [2021-11-09 09:35:02,797 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:02,797 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1078470271] [2021-11-09 09:35:02,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:02,798 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:02,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:02,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:02,850 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:02,850 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1078470271] [2021-11-09 09:35:02,850 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1078470271] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:02,850 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:02,851 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:02,851 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1259685270] [2021-11-09 09:35:02,852 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:02,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:02,853 INFO L85 PathProgramCache]: Analyzing trace with hash 43658547, now seen corresponding path program 1 times [2021-11-09 09:35:02,853 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:02,853 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1720775622] [2021-11-09 09:35:02,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:02,853 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:02,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:02,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:02,908 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:02,908 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1720775622] [2021-11-09 09:35:02,908 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1720775622] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:02,908 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:02,909 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:02,909 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [830347638] [2021-11-09 09:35:02,909 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:02,909 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:02,910 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-09 09:35:02,910 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-09 09:35:02,910 INFO L87 Difference]: Start difference. First operand 1404 states and 2099 transitions. cyclomatic complexity: 697 Second operand has 4 states, 4 states have (on average 22.75) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:03,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:03,141 INFO L93 Difference]: Finished difference Result 3815 states and 5617 transitions. [2021-11-09 09:35:03,141 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-09 09:35:03,142 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3815 states and 5617 transitions. [2021-11-09 09:35:03,177 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3645 [2021-11-09 09:35:03,210 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3815 states to 3815 states and 5617 transitions. [2021-11-09 09:35:03,210 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3815 [2021-11-09 09:35:03,217 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3815 [2021-11-09 09:35:03,217 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3815 states and 5617 transitions. [2021-11-09 09:35:03,223 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:03,223 INFO L681 BuchiCegarLoop]: Abstraction has 3815 states and 5617 transitions. [2021-11-09 09:35:03,227 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3815 states and 5617 transitions. [2021-11-09 09:35:03,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3815 to 3656. [2021-11-09 09:35:03,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3656 states, 3656 states have (on average 1.4764770240700218) internal successors, (5398), 3655 states have internal predecessors, (5398), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:03,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3656 states to 3656 states and 5398 transitions. [2021-11-09 09:35:03,366 INFO L704 BuchiCegarLoop]: Abstraction has 3656 states and 5398 transitions. [2021-11-09 09:35:03,366 INFO L587 BuchiCegarLoop]: Abstraction has 3656 states and 5398 transitions. [2021-11-09 09:35:03,367 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-09 09:35:03,367 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3656 states and 5398 transitions. [2021-11-09 09:35:03,386 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3547 [2021-11-09 09:35:03,386 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:03,386 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:03,388 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:03,388 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:03,388 INFO L791 eck$LassoCheckResult]: Stem: 21094#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 21095#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 20954#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 20907#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 20908#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20890#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20724#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20725#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20704#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20705#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21243#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 21028#L571-1 assume !(0 == ~M_E~0); 21024#L769-1 assume !(0 == ~T1_E~0); 21025#L774-1 assume !(0 == ~T2_E~0); 21086#L779-1 assume !(0 == ~T3_E~0); 21223#L784-1 assume !(0 == ~T4_E~0); 21022#L789-1 assume !(0 == ~T5_E~0); 21023#L794-1 assume !(0 == ~T6_E~0); 21146#L799-1 assume !(0 == ~T7_E~0); 21031#L804-1 assume !(0 == ~E_M~0); 21032#L809-1 assume !(0 == ~E_1~0); 21074#L814-1 assume !(0 == ~E_2~0); 20449#L819-1 assume !(0 == ~E_3~0); 20450#L824-1 assume !(0 == ~E_4~0); 20796#L829-1 assume !(0 == ~E_5~0); 21318#L834-1 assume !(0 == ~E_6~0); 20574#L839-1 assume !(0 == ~E_7~0); 20575#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20964#L376 assume !(1 == ~m_pc~0); 20959#L376-2 is_master_triggered_~__retres1~0 := 0; 20960#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21289#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 20528#L955 assume !(0 != activate_threads_~tmp~1); 20529#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20885#L395 assume !(1 == ~t1_pc~0); 21054#L395-2 is_transmit1_triggered_~__retres1~1 := 0; 21201#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20455#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 20456#L963 assume !(0 != activate_threads_~tmp___0~0); 20969#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20970#L414 assume !(1 == ~t2_pc~0); 20578#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 20577#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20783#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 20784#L971 assume !(0 != activate_threads_~tmp___1~0); 21246#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20886#L433 assume 1 == ~t3_pc~0; 20829#L434 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 20693#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20861#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 20862#L979 assume !(0 != activate_threads_~tmp___2~0); 20545#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20546#L452 assume 1 == ~t4_pc~0; 21370#L453 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 20701#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21009#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 21085#L987 assume !(0 != activate_threads_~tmp___3~0); 20736#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 20737#L471 assume !(1 == ~t5_pc~0); 21133#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 20717#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 20718#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 21075#L995 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 21306#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 21307#L490 assume 1 == ~t6_pc~0; 21274#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 20968#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 21016#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 21019#L1003 assume !(0 != activate_threads_~tmp___5~0); 20894#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 20867#L509 assume !(1 == ~t7_pc~0); 20868#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 20672#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 20673#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 20741#L1011 assume !(0 != activate_threads_~tmp___6~0); 20742#L1011-2 assume !(1 == ~M_E~0); 21333#L857-1 assume !(1 == ~T1_E~0); 20803#L862-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20804#L867-1 assume !(1 == ~T3_E~0); 20809#L872-1 assume !(1 == ~T4_E~0); 20887#L877-1 assume !(1 == ~T5_E~0); 21108#L882-1 assume !(1 == ~T6_E~0); 21273#L887-1 assume !(1 == ~T7_E~0); 21163#L892-1 assume 1 == ~E_M~0;~E_M~0 := 2; 21164#L897-1 assume !(1 == ~E_1~0); 21341#L902-1 assume 1 == ~E_2~0;~E_2~0 := 2; 21184#L907-1 assume !(1 == ~E_3~0); 21185#L912-1 assume !(1 == ~E_4~0); 21117#L917-1 assume !(1 == ~E_5~0); 21118#L922-1 assume !(1 == ~E_6~0); 21389#L927-1 assume !(1 == ~E_7~0); 20487#L1178-1 [2021-11-09 09:35:03,389 INFO L793 eck$LassoCheckResult]: Loop: 20487#L1178-1 assume !false; 21080#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 20859#L744 assume !false; 20860#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 20931#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 20519#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 21308#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 21309#L641 assume !(0 != eval_~tmp~0); 21008#L759 start_simulation_~kernel_st~0 := 2; 20611#L529-1 start_simulation_~kernel_st~0 := 3; 20612#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 21052#L769-4 assume !(0 == ~T1_E~0); 21064#L774-3 assume !(0 == ~T2_E~0); 20629#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20464#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20465#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20451#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20452#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20501#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 20965#L809-3 assume !(0 == ~E_1~0); 20497#L814-3 assume !(0 == ~E_2~0); 20498#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21192#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21187#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20805#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20806#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21145#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21253#L376-27 assume !(1 == ~m_pc~0); 21356#L376-29 is_master_triggered_~__retres1~0 := 0; 21059#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21060#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 21169#L955-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 21328#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 21399#L395-27 assume !(1 == ~t1_pc~0); 20903#L395-29 is_transmit1_triggered_~__retres1~1 := 0; 20807#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20808#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 21051#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 20891#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20892#L414-27 assume 1 == ~t2_pc~0; 21302#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 21115#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21116#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 20949#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 20511#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20512#L433-27 assume !(1 == ~t3_pc~0); 20599#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 20897#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20898#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 20677#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 20678#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21365#L452-27 assume 1 == ~t4_pc~0; 21366#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 22716#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22715#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 22714#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 22713#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22712#L471-27 assume !(1 == ~t5_pc~0); 20816#L471-29 is_transmit5_triggered_~__retres1~5 := 0; 20817#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 21252#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 21136#L995-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 21137#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 22579#L490-27 assume 1 == ~t6_pc~0; 22577#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 22576#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 22575#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 22574#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 22553#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 22552#L509-27 assume 1 == ~t7_pc~0; 22550#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 22549#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 22548#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 22547#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 22546#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 22545#L857-3 assume !(1 == ~T1_E~0); 22543#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22541#L867-3 assume !(1 == ~T3_E~0); 22539#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22537#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22535#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 22532#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22531#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21210#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21211#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20818#L907-3 assume !(1 == ~E_3~0); 20819#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20941#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20904#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20702#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20703#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 20552#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 20462#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 21148#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 20877#L1197 assume !(0 == start_simulation_~tmp~3); 20779#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 20607#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 20572#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 20505#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 20506#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 21206#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 21207#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 20486#L1210 assume !(0 != start_simulation_~tmp___0~1); 20487#L1178-1 [2021-11-09 09:35:03,390 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:03,390 INFO L85 PathProgramCache]: Analyzing trace with hash -92984414, now seen corresponding path program 1 times [2021-11-09 09:35:03,390 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:03,390 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [599880462] [2021-11-09 09:35:03,390 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:03,391 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:03,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:03,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:03,442 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:03,442 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [599880462] [2021-11-09 09:35:03,442 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [599880462] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:03,442 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:03,442 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:03,442 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [417488819] [2021-11-09 09:35:03,443 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:03,443 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:03,443 INFO L85 PathProgramCache]: Analyzing trace with hash 122776402, now seen corresponding path program 1 times [2021-11-09 09:35:03,444 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:03,444 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [477941439] [2021-11-09 09:35:03,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:03,444 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:03,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:03,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:03,482 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:03,483 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [477941439] [2021-11-09 09:35:03,483 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [477941439] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:03,483 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:03,483 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:03,483 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1955380618] [2021-11-09 09:35:03,484 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:03,484 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:03,484 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-09 09:35:03,485 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-09 09:35:03,485 INFO L87 Difference]: Start difference. First operand 3656 states and 5398 transitions. cyclomatic complexity: 1746 Second operand has 4 states, 4 states have (on average 22.75) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:03,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:03,727 INFO L93 Difference]: Finished difference Result 10167 states and 14847 transitions. [2021-11-09 09:35:03,728 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-09 09:35:03,728 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10167 states and 14847 transitions. [2021-11-09 09:35:03,794 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9910 [2021-11-09 09:35:03,872 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10167 states to 10167 states and 14847 transitions. [2021-11-09 09:35:03,872 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10167 [2021-11-09 09:35:03,884 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10167 [2021-11-09 09:35:03,884 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10167 states and 14847 transitions. [2021-11-09 09:35:03,984 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:03,984 INFO L681 BuchiCegarLoop]: Abstraction has 10167 states and 14847 transitions. [2021-11-09 09:35:03,993 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10167 states and 14847 transitions. [2021-11-09 09:35:04,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10167 to 9818. [2021-11-09 09:35:04,228 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9818 states, 9818 states have (on average 1.4640456304746383) internal successors, (14374), 9817 states have internal predecessors, (14374), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:04,258 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9818 states to 9818 states and 14374 transitions. [2021-11-09 09:35:04,259 INFO L704 BuchiCegarLoop]: Abstraction has 9818 states and 14374 transitions. [2021-11-09 09:35:04,259 INFO L587 BuchiCegarLoop]: Abstraction has 9818 states and 14374 transitions. [2021-11-09 09:35:04,259 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-09 09:35:04,259 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9818 states and 14374 transitions. [2021-11-09 09:35:04,368 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9700 [2021-11-09 09:35:04,368 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:04,368 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:04,370 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:04,371 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:04,371 INFO L791 eck$LassoCheckResult]: Stem: 34939#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 34940#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 34795#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 34741#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 34742#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34723#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34555#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34556#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34537#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34538#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35091#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34869#L571-1 assume !(0 == ~M_E~0); 34864#L769-1 assume !(0 == ~T1_E~0); 34865#L774-1 assume !(0 == ~T2_E~0); 34930#L779-1 assume !(0 == ~T3_E~0); 35071#L784-1 assume !(0 == ~T4_E~0); 34862#L789-1 assume !(0 == ~T5_E~0); 34863#L794-1 assume !(0 == ~T6_E~0); 34993#L799-1 assume !(0 == ~T7_E~0); 34871#L804-1 assume !(0 == ~E_M~0); 34872#L809-1 assume !(0 == ~E_1~0); 34918#L814-1 assume !(0 == ~E_2~0); 34282#L819-1 assume !(0 == ~E_3~0); 34283#L824-1 assume !(0 == ~E_4~0); 34628#L829-1 assume !(0 == ~E_5~0); 35173#L834-1 assume !(0 == ~E_6~0); 34406#L839-1 assume !(0 == ~E_7~0); 34407#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 34804#L376 assume !(1 == ~m_pc~0); 34799#L376-2 is_master_triggered_~__retres1~0 := 0; 34800#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 35136#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 34361#L955 assume !(0 != activate_threads_~tmp~1); 34362#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 34718#L395 assume !(1 == ~t1_pc~0); 34895#L395-2 is_transmit1_triggered_~__retres1~1 := 0; 35049#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 34288#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 34289#L963 assume !(0 != activate_threads_~tmp___0~0); 34811#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 34812#L414 assume !(1 == ~t2_pc~0); 34410#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 34409#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 34615#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 34616#L971 assume !(0 != activate_threads_~tmp___1~0); 35096#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 34719#L433 assume !(1 == ~t3_pc~0); 34527#L433-2 is_transmit3_triggered_~__retres1~3 := 0; 34528#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 34693#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 34694#L979 assume !(0 != activate_threads_~tmp___2~0); 34377#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 34378#L452 assume 1 == ~t4_pc~0; 35229#L453 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 34534#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 34848#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 34929#L987 assume !(0 != activate_threads_~tmp___3~0); 34566#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 34567#L471 assume !(1 == ~t5_pc~0); 34977#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 34549#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 34550#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 34919#L995 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 35158#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 35159#L490 assume 1 == ~t6_pc~0; 35120#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 34810#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 34855#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 34859#L1003 assume !(0 != activate_threads_~tmp___5~0); 34727#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 34700#L509 assume !(1 == ~t7_pc~0); 34701#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 34506#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 34507#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 34571#L1011 assume !(0 != activate_threads_~tmp___6~0); 34572#L1011-2 assume !(1 == ~M_E~0); 35193#L857-1 assume !(1 == ~T1_E~0); 34637#L862-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34638#L867-1 assume !(1 == ~T3_E~0); 34643#L872-1 assume !(1 == ~T4_E~0); 34720#L877-1 assume !(1 == ~T5_E~0); 34950#L882-1 assume !(1 == ~T6_E~0); 35119#L887-1 assume !(1 == ~T7_E~0); 35010#L892-1 assume 1 == ~E_M~0;~E_M~0 := 2; 35011#L897-1 assume !(1 == ~E_1~0); 35199#L902-1 assume 1 == ~E_2~0;~E_2~0 := 2; 35031#L907-1 assume !(1 == ~E_3~0); 35032#L912-1 assume !(1 == ~E_4~0); 34958#L917-1 assume !(1 == ~E_5~0); 34959#L922-1 assume !(1 == ~E_6~0); 35252#L927-1 assume !(1 == ~E_7~0); 35253#L1178-1 [2021-11-09 09:35:04,372 INFO L793 eck$LassoCheckResult]: Loop: 35253#L1178-1 assume !false; 34934#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 34691#L744 assume !false; 34692#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 34764#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 43720#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 35160#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 35161#L641 assume !(0 != eval_~tmp~0); 43677#L759 start_simulation_~kernel_st~0 := 2; 34444#L529-1 start_simulation_~kernel_st~0 := 3; 34445#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 35069#L769-4 assume !(0 == ~T1_E~0); 35070#L774-3 assume !(0 == ~T2_E~0); 34461#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 34462#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35274#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35275#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 34334#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 34335#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 34806#L809-3 assume !(0 == ~E_1~0); 34807#L814-3 assume !(0 == ~E_2~0); 35081#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35082#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43222#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 43223#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 43137#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 43138#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 43133#L376-27 assume !(1 == ~m_pc~0); 43134#L376-29 is_master_triggered_~__retres1~0 := 0; 43129#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 43130#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 43125#L955-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 43126#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 35262#L395-27 assume !(1 == ~t1_pc~0); 35263#L395-29 is_transmit1_triggered_~__retres1~1 := 0; 34641#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 34642#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 34890#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 34891#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 35148#L414-27 assume 1 == ~t2_pc~0; 35149#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 34956#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 34957#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 34785#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 34786#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 34432#L433-27 assume !(1 == ~t3_pc~0); 34433#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 34729#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 34730#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 34511#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 34512#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 35221#L452-27 assume 1 == ~t4_pc~0; 35222#L453-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 35074#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 35075#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 35139#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 35140#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 34336#L471-27 assume 1 == ~t5_pc~0; 34337#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 35270#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 35271#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 34981#L995-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 34982#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 34801#L490-27 assume !(1 == ~t6_pc~0); 34802#L490-29 is_transmit6_triggered_~__retres1~6 := 0; 34521#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 34522#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 34965#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 34966#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 34306#L509-27 assume 1 == ~t7_pc~0; 34307#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 35062#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 35063#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 34824#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 34825#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 34842#L857-3 assume !(1 == ~T1_E~0); 34843#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35215#L867-3 assume !(1 == ~T3_E~0); 35216#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34835#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34836#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34885#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34886#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35058#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35059#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 34652#L907-3 assume !(1 == ~E_3~0); 34653#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35094#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35095#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 34535#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 34536#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 34384#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 34293#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 35257#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 35258#L1197 assume !(0 == start_simulation_~tmp~3); 34610#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 34611#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 43736#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 43735#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 43734#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 43733#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 43732#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 43731#L1210 assume !(0 != start_simulation_~tmp___0~1); 35253#L1178-1 [2021-11-09 09:35:04,372 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:04,372 INFO L85 PathProgramCache]: Analyzing trace with hash -966462109, now seen corresponding path program 1 times [2021-11-09 09:35:04,373 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:04,373 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [773007876] [2021-11-09 09:35:04,373 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:04,373 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:04,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:04,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:04,414 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:04,415 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [773007876] [2021-11-09 09:35:04,415 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [773007876] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:04,415 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:04,415 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-09 09:35:04,417 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1058079825] [2021-11-09 09:35:04,417 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:04,418 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:04,418 INFO L85 PathProgramCache]: Analyzing trace with hash 1830772370, now seen corresponding path program 1 times [2021-11-09 09:35:04,418 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:04,418 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1681588601] [2021-11-09 09:35:04,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:04,419 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:04,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:04,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:04,455 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:04,456 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1681588601] [2021-11-09 09:35:04,456 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1681588601] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:04,456 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:04,456 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:04,456 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1740207516] [2021-11-09 09:35:04,457 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:04,457 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:04,458 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:35:04,458 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:35:04,458 INFO L87 Difference]: Start difference. First operand 9818 states and 14374 transitions. cyclomatic complexity: 4564 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 2 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:04,634 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:04,635 INFO L93 Difference]: Finished difference Result 18425 states and 26869 transitions. [2021-11-09 09:35:04,635 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:35:04,636 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18425 states and 26869 transitions. [2021-11-09 09:35:04,750 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18257 [2021-11-09 09:35:04,839 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18425 states to 18425 states and 26869 transitions. [2021-11-09 09:35:04,840 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18425 [2021-11-09 09:35:04,860 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18425 [2021-11-09 09:35:04,860 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18425 states and 26869 transitions. [2021-11-09 09:35:04,885 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:04,885 INFO L681 BuchiCegarLoop]: Abstraction has 18425 states and 26869 transitions. [2021-11-09 09:35:04,903 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18425 states and 26869 transitions. [2021-11-09 09:35:05,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18425 to 18389. [2021-11-09 09:35:05,296 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18389 states, 18389 states have (on average 1.4591875577791071) internal successors, (26833), 18388 states have internal predecessors, (26833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:05,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18389 states to 18389 states and 26833 transitions. [2021-11-09 09:35:05,357 INFO L704 BuchiCegarLoop]: Abstraction has 18389 states and 26833 transitions. [2021-11-09 09:35:05,357 INFO L587 BuchiCegarLoop]: Abstraction has 18389 states and 26833 transitions. [2021-11-09 09:35:05,357 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-09 09:35:05,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18389 states and 26833 transitions. [2021-11-09 09:35:05,559 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18221 [2021-11-09 09:35:05,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:05,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:05,561 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:05,561 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:05,561 INFO L791 eck$LassoCheckResult]: Stem: 63195#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 63196#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 63055#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 62999#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 63000#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 62980#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 62806#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 62807#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 62787#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 62788#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 63354#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 63134#L571-1 assume !(0 == ~M_E~0); 63130#L769-1 assume !(0 == ~T1_E~0); 63131#L774-1 assume !(0 == ~T2_E~0); 63190#L779-1 assume !(0 == ~T3_E~0); 63334#L784-1 assume !(0 == ~T4_E~0); 63128#L789-1 assume !(0 == ~T5_E~0); 63129#L794-1 assume !(0 == ~T6_E~0); 63253#L799-1 assume !(0 == ~T7_E~0); 63137#L804-1 assume !(0 == ~E_M~0); 63138#L809-1 assume !(0 == ~E_1~0); 63178#L814-1 assume !(0 == ~E_2~0); 62532#L819-1 assume !(0 == ~E_3~0); 62533#L824-1 assume !(0 == ~E_4~0); 62878#L829-1 assume !(0 == ~E_5~0); 63431#L834-1 assume !(0 == ~E_6~0); 62655#L839-1 assume !(0 == ~E_7~0); 62656#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 63063#L376 assume !(1 == ~m_pc~0); 63060#L376-2 is_master_triggered_~__retres1~0 := 0; 63061#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 63401#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 62610#L955 assume !(0 != activate_threads_~tmp~1); 62611#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 62975#L395 assume !(1 == ~t1_pc~0); 63159#L395-2 is_transmit1_triggered_~__retres1~1 := 0; 63315#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 62538#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 62539#L963 assume !(0 != activate_threads_~tmp___0~0); 63070#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 63071#L414 assume !(1 == ~t2_pc~0); 62659#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 62658#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 62865#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 62866#L971 assume !(0 != activate_threads_~tmp___1~0); 63357#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 62976#L433 assume !(1 == ~t3_pc~0); 62774#L433-2 is_transmit3_triggered_~__retres1~3 := 0; 62775#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 62950#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 62951#L979 assume !(0 != activate_threads_~tmp___2~0); 62626#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 62627#L452 assume !(1 == ~t4_pc~0); 62783#L452-2 is_transmit4_triggered_~__retres1~4 := 0; 62784#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 63113#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 63189#L987 assume !(0 != activate_threads_~tmp___3~0); 62817#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 62818#L471 assume !(1 == ~t5_pc~0); 63238#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 62800#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 62801#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 63179#L995 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 63420#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 63421#L490 assume 1 == ~t6_pc~0; 63389#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 63069#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 63120#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 63124#L1003 assume !(0 != activate_threads_~tmp___5~0); 62984#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 62955#L509 assume !(1 == ~t7_pc~0); 62956#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 62754#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 62755#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 62822#L1011 assume !(0 != activate_threads_~tmp___6~0); 62823#L1011-2 assume !(1 == ~M_E~0); 63449#L857-1 assume !(1 == ~T1_E~0); 62889#L862-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 62890#L867-1 assume !(1 == ~T3_E~0); 62895#L872-1 assume !(1 == ~T4_E~0); 62977#L877-1 assume !(1 == ~T5_E~0); 63208#L882-1 assume !(1 == ~T6_E~0); 63388#L887-1 assume !(1 == ~T7_E~0); 63273#L892-1 assume 1 == ~E_M~0;~E_M~0 := 2; 63274#L897-1 assume !(1 == ~E_1~0); 62908#L902-1 assume 1 == ~E_2~0;~E_2~0 := 2; 62909#L907-1 assume !(1 == ~E_3~0); 63225#L912-1 assume !(1 == ~E_4~0); 63216#L917-1 assume !(1 == ~E_5~0); 63217#L922-1 assume !(1 == ~E_6~0); 63437#L927-1 assume !(1 == ~E_7~0); 63507#L1178-1 [2021-11-09 09:35:05,562 INFO L793 eck$LassoCheckResult]: Loop: 63507#L1178-1 assume !false; 71129#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 71120#L744 assume !false; 70861#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 69294#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 69285#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 69283#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 69280#L641 assume !(0 != eval_~tmp~0); 69281#L759 start_simulation_~kernel_st~0 := 2; 71779#L529-1 start_simulation_~kernel_st~0 := 3; 71778#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 71777#L769-4 assume !(0 == ~T1_E~0); 71776#L774-3 assume !(0 == ~T2_E~0); 71775#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 71773#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 71771#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 71769#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 71767#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 71765#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 71763#L809-3 assume !(0 == ~E_1~0); 71761#L814-3 assume !(0 == ~E_2~0); 71759#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 71757#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 71755#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 71753#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 71751#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 71749#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 71747#L376-27 assume !(1 == ~m_pc~0); 71745#L376-29 is_master_triggered_~__retres1~0 := 0; 71743#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 71741#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 71739#L955-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 71737#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 71735#L395-27 assume !(1 == ~t1_pc~0); 71733#L395-29 is_transmit1_triggered_~__retres1~1 := 0; 71731#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 71729#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 71727#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 71725#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 71724#L414-27 assume 1 == ~t2_pc~0; 71721#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 71719#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 71717#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 71715#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 71713#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 71710#L433-27 assume !(1 == ~t3_pc~0); 71708#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 71706#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 71704#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 71702#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 71700#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 71698#L452-27 assume !(1 == ~t4_pc~0); 71696#L452-29 is_transmit4_triggered_~__retres1~4 := 0; 71694#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 71692#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 71690#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 71688#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 71687#L471-27 assume !(1 == ~t5_pc~0); 71685#L471-29 is_transmit5_triggered_~__retres1~5 := 0; 71684#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 71683#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 71682#L995-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 71680#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 71678#L490-27 assume 1 == ~t6_pc~0; 71675#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 71669#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 71662#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 71623#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 71220#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 71217#L509-27 assume !(1 == ~t7_pc~0); 71215#L509-29 is_transmit7_triggered_~__retres1~7 := 0; 71212#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 71210#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 71208#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 71206#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 71204#L857-3 assume !(1 == ~T1_E~0); 71202#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 71200#L867-3 assume !(1 == ~T3_E~0); 71198#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 71196#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 71194#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 71192#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 71190#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 70794#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 70792#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 71186#L907-3 assume !(1 == ~E_3~0); 71184#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 71181#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 71179#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 71177#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 71175#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 71173#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 71164#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 71161#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 71158#L1197 assume !(0 == start_simulation_~tmp~3); 71155#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 71153#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 71144#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 71142#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 71139#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 71137#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 71135#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 71132#L1210 assume !(0 != start_simulation_~tmp___0~1); 63507#L1178-1 [2021-11-09 09:35:05,562 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:05,563 INFO L85 PathProgramCache]: Analyzing trace with hash -1923390492, now seen corresponding path program 1 times [2021-11-09 09:35:05,565 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:05,565 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [788251827] [2021-11-09 09:35:05,565 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:05,565 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:05,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:05,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:05,610 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:05,610 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [788251827] [2021-11-09 09:35:05,610 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [788251827] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:05,610 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:05,610 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-09 09:35:05,610 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2012256544] [2021-11-09 09:35:05,611 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:05,612 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:05,612 INFO L85 PathProgramCache]: Analyzing trace with hash 2087525200, now seen corresponding path program 1 times [2021-11-09 09:35:05,612 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:05,612 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1768912152] [2021-11-09 09:35:05,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:05,612 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:05,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:05,646 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:05,646 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:05,646 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1768912152] [2021-11-09 09:35:05,646 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1768912152] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:05,646 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:05,647 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:05,647 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [847178017] [2021-11-09 09:35:05,647 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:05,648 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:05,648 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-09 09:35:05,648 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-09 09:35:05,649 INFO L87 Difference]: Start difference. First operand 18389 states and 26833 transitions. cyclomatic complexity: 8460 Second operand has 5 states, 5 states have (on average 18.2) internal successors, (91), 5 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:06,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:06,142 INFO L93 Difference]: Finished difference Result 44677 states and 65863 transitions. [2021-11-09 09:35:06,142 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-09 09:35:06,142 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44677 states and 65863 transitions. [2021-11-09 09:35:06,652 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 44306 [2021-11-09 09:35:06,971 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44677 states to 44677 states and 65863 transitions. [2021-11-09 09:35:06,972 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44677 [2021-11-09 09:35:07,013 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44677 [2021-11-09 09:35:07,014 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44677 states and 65863 transitions. [2021-11-09 09:35:07,082 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:07,083 INFO L681 BuchiCegarLoop]: Abstraction has 44677 states and 65863 transitions. [2021-11-09 09:35:07,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44677 states and 65863 transitions. [2021-11-09 09:35:07,581 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44677 to 19136. [2021-11-09 09:35:07,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19136 states, 19136 states have (on average 1.44126254180602) internal successors, (27580), 19135 states have internal predecessors, (27580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:07,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19136 states to 19136 states and 27580 transitions. [2021-11-09 09:35:07,667 INFO L704 BuchiCegarLoop]: Abstraction has 19136 states and 27580 transitions. [2021-11-09 09:35:07,667 INFO L587 BuchiCegarLoop]: Abstraction has 19136 states and 27580 transitions. [2021-11-09 09:35:07,667 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-09 09:35:07,668 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19136 states and 27580 transitions. [2021-11-09 09:35:07,745 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18965 [2021-11-09 09:35:07,745 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:07,745 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:07,747 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:07,747 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:07,748 INFO L791 eck$LassoCheckResult]: Stem: 126306#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 126307#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 126152#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 126087#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 126088#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 126069#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 125890#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 125891#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 125869#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 125870#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 126490#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 126230#L571-1 assume !(0 == ~M_E~0); 126225#L769-1 assume !(0 == ~T1_E~0); 126226#L774-1 assume !(0 == ~T2_E~0); 126296#L779-1 assume !(0 == ~T3_E~0); 126466#L784-1 assume !(0 == ~T4_E~0); 126223#L789-1 assume !(0 == ~T5_E~0); 126224#L794-1 assume !(0 == ~T6_E~0); 126367#L799-1 assume !(0 == ~T7_E~0); 126233#L804-1 assume !(0 == ~E_M~0); 126234#L809-1 assume !(0 == ~E_1~0); 126282#L814-1 assume !(0 == ~E_2~0); 125611#L819-1 assume !(0 == ~E_3~0); 125612#L824-1 assume !(0 == ~E_4~0); 125962#L829-1 assume !(0 == ~E_5~0); 126594#L834-1 assume !(0 == ~E_6~0); 125737#L839-1 assume !(0 == ~E_7~0); 125738#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 126161#L376 assume !(1 == ~m_pc~0); 126158#L376-2 is_master_triggered_~__retres1~0 := 0; 126159#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 126559#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 125691#L955 assume !(0 != activate_threads_~tmp~1); 125692#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 126063#L395 assume !(1 == ~t1_pc~0); 126258#L395-2 is_transmit1_triggered_~__retres1~1 := 0; 126444#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 125617#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 125618#L963 assume !(0 != activate_threads_~tmp___0~0); 126168#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 126169#L414 assume !(1 == ~t2_pc~0); 125741#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 125740#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 125948#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 125949#L971 assume !(0 != activate_threads_~tmp___1~0); 126494#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 126065#L433 assume !(1 == ~t3_pc~0); 125857#L433-2 is_transmit3_triggered_~__retres1~3 := 0; 125858#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 126034#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 126035#L979 assume !(0 != activate_threads_~tmp___2~0); 125708#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 125709#L452 assume !(1 == ~t4_pc~0); 125865#L452-2 is_transmit4_triggered_~__retres1~4 := 0; 125866#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 126209#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 126295#L987 assume !(0 != activate_threads_~tmp___3~0); 125902#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 125903#L471 assume !(1 == ~t5_pc~0); 126352#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 125883#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 125884#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 126721#L995 assume !(0 != activate_threads_~tmp___4~0); 126583#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 126584#L490 assume 1 == ~t6_pc~0; 126534#L491 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 126165#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 126216#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 126220#L1003 assume !(0 != activate_threads_~tmp___5~0); 126073#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 126041#L509 assume !(1 == ~t7_pc~0); 126042#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 125837#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 125838#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 125907#L1011 assume !(0 != activate_threads_~tmp___6~0); 125908#L1011-2 assume !(1 == ~M_E~0); 126617#L857-1 assume !(1 == ~T1_E~0); 125973#L862-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 125974#L867-1 assume !(1 == ~T3_E~0); 125979#L872-1 assume !(1 == ~T4_E~0); 126066#L877-1 assume !(1 == ~T5_E~0); 126321#L882-1 assume !(1 == ~T6_E~0); 126533#L887-1 assume !(1 == ~T7_E~0); 126388#L892-1 assume 1 == ~E_M~0;~E_M~0 := 2; 126389#L897-1 assume !(1 == ~E_1~0); 126628#L902-1 assume 1 == ~E_2~0;~E_2~0 := 2; 132954#L907-1 assume !(1 == ~E_3~0); 126339#L912-1 assume !(1 == ~E_4~0); 126340#L917-1 assume !(1 == ~E_5~0); 126603#L922-1 assume !(1 == ~E_6~0); 126604#L927-1 assume !(1 == ~E_7~0); 126703#L1178-1 [2021-11-09 09:35:07,748 INFO L793 eck$LassoCheckResult]: Loop: 126703#L1178-1 assume !false; 135340#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 135333#L744 assume !false; 135331#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 135276#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 135267#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 135264#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 135260#L641 assume !(0 != eval_~tmp~0); 135261#L759 start_simulation_~kernel_st~0 := 2; 135809#L529-1 start_simulation_~kernel_st~0 := 3; 135807#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 135805#L769-4 assume !(0 == ~T1_E~0); 135803#L774-3 assume !(0 == ~T2_E~0); 135802#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 135799#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 135797#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 135795#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 135786#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 135784#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 135782#L809-3 assume !(0 == ~E_1~0); 135780#L814-3 assume !(0 == ~E_2~0); 135778#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 135768#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 135759#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 135752#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 135746#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 135744#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 135743#L376-27 assume !(1 == ~m_pc~0); 135742#L376-29 is_master_triggered_~__retres1~0 := 0; 135741#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 135740#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 135739#L955-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 135738#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 135737#L395-27 assume !(1 == ~t1_pc~0); 135736#L395-29 is_transmit1_triggered_~__retres1~1 := 0; 135735#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 135734#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 135733#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 135732#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 135731#L414-27 assume !(1 == ~t2_pc~0); 135730#L414-29 is_transmit2_triggered_~__retres1~2 := 0; 135728#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 135727#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 135726#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 135725#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 135724#L433-27 assume !(1 == ~t3_pc~0); 135723#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 135722#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 135721#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 135720#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 135719#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 135718#L452-27 assume !(1 == ~t4_pc~0); 135717#L452-29 is_transmit4_triggered_~__retres1~4 := 0; 135716#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 135715#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 135714#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 135713#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 135712#L471-27 assume 1 == ~t5_pc~0; 135710#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 135708#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 135706#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 135704#L995-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 135702#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 135701#L490-27 assume 1 == ~t6_pc~0; 135699#L491-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 135698#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 135657#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 135655#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 135653#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 135650#L509-27 assume !(1 == ~t7_pc~0); 135648#L509-29 is_transmit7_triggered_~__retres1~7 := 0; 135645#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 135643#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 135641#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 135639#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 135636#L857-3 assume !(1 == ~T1_E~0); 135634#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 135632#L867-3 assume !(1 == ~T3_E~0); 135630#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 135628#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 135626#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 135624#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 135622#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 133313#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 133306#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 135618#L907-3 assume !(1 == ~E_3~0); 135616#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 135614#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 135613#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 135572#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 135568#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 135526#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 135513#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 135508#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 135501#L1197 assume !(0 == start_simulation_~tmp~3); 135457#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 135439#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 135427#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 135419#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 135415#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 135410#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 135366#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 135357#L1210 assume !(0 != start_simulation_~tmp___0~1); 126703#L1178-1 [2021-11-09 09:35:07,749 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:07,749 INFO L85 PathProgramCache]: Analyzing trace with hash -537187098, now seen corresponding path program 1 times [2021-11-09 09:35:07,749 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:07,750 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [902620306] [2021-11-09 09:35:07,750 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:07,750 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:07,761 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:07,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:07,790 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:07,790 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [902620306] [2021-11-09 09:35:07,791 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [902620306] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:07,791 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:07,791 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:07,791 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1347398586] [2021-11-09 09:35:07,792 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:07,792 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:07,792 INFO L85 PathProgramCache]: Analyzing trace with hash -194518640, now seen corresponding path program 1 times [2021-11-09 09:35:07,792 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:07,793 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [632378004] [2021-11-09 09:35:07,794 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:07,794 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:07,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:07,837 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:07,837 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:07,837 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [632378004] [2021-11-09 09:35:07,837 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [632378004] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:07,838 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:07,838 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:07,838 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1416331413] [2021-11-09 09:35:07,838 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:07,839 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:07,841 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-09 09:35:07,841 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-09 09:35:07,841 INFO L87 Difference]: Start difference. First operand 19136 states and 27580 transitions. cyclomatic complexity: 8460 Second operand has 4 states, 4 states have (on average 22.75) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:08,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:08,353 INFO L93 Difference]: Finished difference Result 52945 states and 75795 transitions. [2021-11-09 09:35:08,354 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-09 09:35:08,354 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52945 states and 75795 transitions. [2021-11-09 09:35:08,841 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 52023 [2021-11-09 09:35:09,204 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52945 states to 52945 states and 75795 transitions. [2021-11-09 09:35:09,204 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 52945 [2021-11-09 09:35:09,228 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 52945 [2021-11-09 09:35:09,228 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52945 states and 75795 transitions. [2021-11-09 09:35:09,290 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:09,290 INFO L681 BuchiCegarLoop]: Abstraction has 52945 states and 75795 transitions. [2021-11-09 09:35:09,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52945 states and 75795 transitions. [2021-11-09 09:35:09,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52945 to 51801. [2021-11-09 09:35:10,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51801 states, 51801 states have (on average 1.4347792513658038) internal successors, (74323), 51800 states have internal predecessors, (74323), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:10,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51801 states to 51801 states and 74323 transitions. [2021-11-09 09:35:10,147 INFO L704 BuchiCegarLoop]: Abstraction has 51801 states and 74323 transitions. [2021-11-09 09:35:10,147 INFO L587 BuchiCegarLoop]: Abstraction has 51801 states and 74323 transitions. [2021-11-09 09:35:10,147 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-09 09:35:10,147 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51801 states and 74323 transitions. [2021-11-09 09:35:10,525 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 51519 [2021-11-09 09:35:10,526 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:10,526 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:10,528 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:10,528 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:10,529 INFO L791 eck$LassoCheckResult]: Stem: 198366#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 198367#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 198222#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 198164#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 198165#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 198147#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 197975#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 197976#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 197957#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 197958#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 198545#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 198295#L571-1 assume !(0 == ~M_E~0); 198290#L769-1 assume !(0 == ~T1_E~0); 198291#L774-1 assume !(0 == ~T2_E~0); 198359#L779-1 assume !(0 == ~T3_E~0); 198526#L784-1 assume !(0 == ~T4_E~0); 198288#L789-1 assume !(0 == ~T5_E~0); 198289#L794-1 assume !(0 == ~T6_E~0); 198430#L799-1 assume !(0 == ~T7_E~0); 198297#L804-1 assume !(0 == ~E_M~0); 198298#L809-1 assume !(0 == ~E_1~0); 198344#L814-1 assume !(0 == ~E_2~0); 197702#L819-1 assume !(0 == ~E_3~0); 197703#L824-1 assume !(0 == ~E_4~0); 198047#L829-1 assume !(0 == ~E_5~0); 198638#L834-1 assume !(0 == ~E_6~0); 197827#L839-1 assume !(0 == ~E_7~0); 197828#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 198231#L376 assume !(1 == ~m_pc~0); 198227#L376-2 is_master_triggered_~__retres1~0 := 0; 198228#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 198601#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 197781#L955 assume !(0 != activate_threads_~tmp~1); 197782#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 198141#L395 assume !(1 == ~t1_pc~0); 198321#L395-2 is_transmit1_triggered_~__retres1~1 := 0; 198500#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 197708#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 197709#L963 assume !(0 != activate_threads_~tmp___0~0); 198238#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 198239#L414 assume !(1 == ~t2_pc~0); 197831#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 197830#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 198034#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 198035#L971 assume !(0 != activate_threads_~tmp___1~0); 198550#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 198143#L433 assume !(1 == ~t3_pc~0); 197944#L433-2 is_transmit3_triggered_~__retres1~3 := 0; 197945#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 198113#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 198114#L979 assume !(0 != activate_threads_~tmp___2~0); 197797#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 197798#L452 assume !(1 == ~t4_pc~0); 197953#L452-2 is_transmit4_triggered_~__retres1~4 := 0; 197954#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 198275#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 198358#L987 assume !(0 != activate_threads_~tmp___3~0); 197986#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 197987#L471 assume !(1 == ~t5_pc~0); 198407#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 198678#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 198345#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 198346#L995 assume !(0 != activate_threads_~tmp___4~0); 198623#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 198624#L490 assume !(1 == ~t6_pc~0); 198236#L490-2 is_transmit6_triggered_~__retres1~6 := 0; 198237#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 198282#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 198285#L1003 assume !(0 != activate_threads_~tmp___5~0); 198151#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 198120#L509 assume !(1 == ~t7_pc~0); 198121#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 197924#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 197925#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 197991#L1011 assume !(0 != activate_threads_~tmp___6~0); 197992#L1011-2 assume !(1 == ~M_E~0); 198654#L857-1 assume !(1 == ~T1_E~0); 198055#L862-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 198056#L867-1 assume !(1 == ~T3_E~0); 198061#L872-1 assume !(1 == ~T4_E~0); 198144#L877-1 assume !(1 == ~T5_E~0); 198379#L882-1 assume !(1 == ~T6_E~0); 198578#L887-1 assume !(1 == ~T7_E~0); 198447#L892-1 assume 1 == ~E_M~0;~E_M~0 := 2; 198448#L897-1 assume !(1 == ~E_1~0); 198665#L902-1 assume 1 == ~E_2~0;~E_2~0 := 2; 198474#L907-1 assume !(1 == ~E_3~0); 198475#L912-1 assume !(1 == ~E_4~0); 198387#L917-1 assume !(1 == ~E_5~0); 198388#L922-1 assume !(1 == ~E_6~0); 198735#L927-1 assume !(1 == ~E_7~0); 198736#L1178-1 [2021-11-09 09:35:10,529 INFO L793 eck$LassoCheckResult]: Loop: 198736#L1178-1 assume !false; 218239#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 218229#L744 assume !false; 218221#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 217481#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 217474#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 217470#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 217467#L641 assume !(0 != eval_~tmp~0); 217468#L759 start_simulation_~kernel_st~0 := 2; 218658#L529-1 start_simulation_~kernel_st~0 := 3; 218656#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 218654#L769-4 assume !(0 == ~T1_E~0); 218652#L774-3 assume !(0 == ~T2_E~0); 218650#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 218648#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 218646#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 218644#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 218642#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 218641#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 218640#L809-3 assume !(0 == ~E_1~0); 218639#L814-3 assume !(0 == ~E_2~0); 218638#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 218637#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 218636#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 218635#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 218634#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 218633#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 218632#L376-27 assume !(1 == ~m_pc~0); 218631#L376-29 is_master_triggered_~__retres1~0 := 0; 218629#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 218628#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 218625#L955-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 218622#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 218621#L395-27 assume !(1 == ~t1_pc~0); 218620#L395-29 is_transmit1_triggered_~__retres1~1 := 0; 218618#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 218619#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 233682#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 218611#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 218612#L414-27 assume 1 == ~t2_pc~0; 218582#L415-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 218583#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 218576#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 218577#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 218569#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 218570#L433-27 assume !(1 == ~t3_pc~0); 218563#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 218564#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 218557#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 218558#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 218551#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 218552#L452-27 assume !(1 == ~t4_pc~0); 218545#L452-29 is_transmit4_triggered_~__retres1~4 := 0; 218546#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 218539#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 218540#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 218533#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 218534#L471-27 assume 1 == ~t5_pc~0; 218527#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 218528#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 218623#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 218624#L995-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 218508#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 218509#L490-27 assume !(1 == ~t6_pc~0); 218501#L490-29 is_transmit6_triggered_~__retres1~6 := 0; 218502#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 218494#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 218495#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 218489#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 218490#L509-27 assume !(1 == ~t7_pc~0); 218483#L509-29 is_transmit7_triggered_~__retres1~7 := 0; 218482#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 218475#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 218476#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 218468#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 218469#L857-3 assume !(1 == ~T1_E~0); 218461#L862-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 218462#L867-3 assume !(1 == ~T3_E~0); 218455#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 218456#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 218448#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 218449#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 218443#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 217781#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 218438#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 218439#L907-3 assume !(1 == ~E_3~0); 218432#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 218433#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 218427#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 218428#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 218421#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 218422#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 230099#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 230098#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 230097#L1197 assume !(0 == start_simulation_~tmp~3); 218402#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 218403#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 224467#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 224466#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 224465#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 224464#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 224463#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 224462#L1210 assume !(0 != start_simulation_~tmp___0~1); 198736#L1178-1 [2021-11-09 09:35:10,531 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:10,531 INFO L85 PathProgramCache]: Analyzing trace with hash 2085262567, now seen corresponding path program 1 times [2021-11-09 09:35:10,531 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:10,532 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1662510330] [2021-11-09 09:35:10,532 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:10,532 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:10,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:10,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:10,587 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:10,587 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1662510330] [2021-11-09 09:35:10,588 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1662510330] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:10,588 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:10,588 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-09 09:35:10,588 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [365782270] [2021-11-09 09:35:10,589 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:10,589 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:10,589 INFO L85 PathProgramCache]: Analyzing trace with hash -499446128, now seen corresponding path program 1 times [2021-11-09 09:35:10,589 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:10,590 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1770459068] [2021-11-09 09:35:10,590 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:10,590 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:10,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:10,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:10,626 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:10,626 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1770459068] [2021-11-09 09:35:10,626 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1770459068] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:10,627 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:10,628 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:10,628 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1783502580] [2021-11-09 09:35:10,628 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:10,629 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:10,629 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:35:10,629 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:35:10,629 INFO L87 Difference]: Start difference. First operand 51801 states and 74323 transitions. cyclomatic complexity: 22554 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 2 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:10,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:10,917 INFO L93 Difference]: Finished difference Result 51801 states and 73997 transitions. [2021-11-09 09:35:10,918 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:35:10,918 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51801 states and 73997 transitions. [2021-11-09 09:35:11,367 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 51519 [2021-11-09 09:35:11,522 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51801 states to 51801 states and 73997 transitions. [2021-11-09 09:35:11,522 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51801 [2021-11-09 09:35:11,555 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51801 [2021-11-09 09:35:11,555 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51801 states and 73997 transitions. [2021-11-09 09:35:11,617 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:11,617 INFO L681 BuchiCegarLoop]: Abstraction has 51801 states and 73997 transitions. [2021-11-09 09:35:11,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51801 states and 73997 transitions. [2021-11-09 09:35:12,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51801 to 51801. [2021-11-09 09:35:12,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51801 states, 51801 states have (on average 1.4284859365649312) internal successors, (73997), 51800 states have internal predecessors, (73997), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:12,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51801 states to 51801 states and 73997 transitions. [2021-11-09 09:35:12,514 INFO L704 BuchiCegarLoop]: Abstraction has 51801 states and 73997 transitions. [2021-11-09 09:35:12,514 INFO L587 BuchiCegarLoop]: Abstraction has 51801 states and 73997 transitions. [2021-11-09 09:35:12,514 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-09 09:35:12,514 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51801 states and 73997 transitions. [2021-11-09 09:35:12,657 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 51519 [2021-11-09 09:35:12,657 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:12,657 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:12,659 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:12,659 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:12,659 INFO L791 eck$LassoCheckResult]: Stem: 301960#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 301961#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 301823#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 301771#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 301772#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 301752#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 301581#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 301582#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 301563#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 301564#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 302116#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 301897#L571-1 assume !(0 == ~M_E~0); 301894#L769-1 assume !(0 == ~T1_E~0); 301895#L774-1 assume !(0 == ~T2_E~0); 301955#L779-1 assume !(0 == ~T3_E~0); 302097#L784-1 assume !(0 == ~T4_E~0); 301889#L789-1 assume !(0 == ~T5_E~0); 301890#L794-1 assume !(0 == ~T6_E~0); 302022#L799-1 assume !(0 == ~T7_E~0); 301898#L804-1 assume !(0 == ~E_M~0); 301899#L809-1 assume !(0 == ~E_1~0); 301943#L814-1 assume !(0 == ~E_2~0); 301315#L819-1 assume !(0 == ~E_3~0); 301316#L824-1 assume !(0 == ~E_4~0); 301652#L829-1 assume !(0 == ~E_5~0); 302181#L834-1 assume !(0 == ~E_6~0); 301433#L839-1 assume !(0 == ~E_7~0); 301434#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 301831#L376 assume !(1 == ~m_pc~0); 301827#L376-2 is_master_triggered_~__retres1~0 := 0; 301828#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 302154#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 301391#L955 assume !(0 != activate_threads_~tmp~1); 301392#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 301745#L395 assume !(1 == ~t1_pc~0); 301918#L395-2 is_transmit1_triggered_~__retres1~1 := 0; 302081#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 301319#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 301320#L963 assume !(0 != activate_threads_~tmp___0~0); 301839#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 301840#L414 assume !(1 == ~t2_pc~0); 301437#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 301436#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 301639#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 301640#L971 assume !(0 != activate_threads_~tmp___1~0); 302120#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 301748#L433 assume !(1 == ~t3_pc~0); 301553#L433-2 is_transmit3_triggered_~__retres1~3 := 0; 301554#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 301720#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 301721#L979 assume !(0 != activate_threads_~tmp___2~0); 301405#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 301406#L452 assume !(1 == ~t4_pc~0); 301559#L452-2 is_transmit4_triggered_~__retres1~4 := 0; 301560#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 301875#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 301954#L987 assume !(0 != activate_threads_~tmp___3~0); 301592#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 301593#L471 assume !(1 == ~t5_pc~0); 302004#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 302228#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 301944#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 301945#L995 assume !(0 != activate_threads_~tmp___4~0); 302168#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 302169#L490 assume !(1 == ~t6_pc~0); 301835#L490-2 is_transmit6_triggered_~__retres1~6 := 0; 301836#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 301884#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 301887#L1003 assume !(0 != activate_threads_~tmp___5~0); 301759#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 301724#L509 assume !(1 == ~t7_pc~0); 301725#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 301538#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 301539#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 301597#L1011 assume !(0 != activate_threads_~tmp___6~0); 301598#L1011-2 assume !(1 == ~M_E~0); 302204#L857-1 assume !(1 == ~T1_E~0); 301660#L862-1 assume !(1 == ~T2_E~0); 301661#L867-1 assume !(1 == ~T3_E~0); 301666#L872-1 assume !(1 == ~T4_E~0); 301749#L877-1 assume !(1 == ~T5_E~0); 301974#L882-1 assume !(1 == ~T6_E~0); 302141#L887-1 assume !(1 == ~T7_E~0); 302041#L892-1 assume 1 == ~E_M~0;~E_M~0 := 2; 302042#L897-1 assume !(1 == ~E_1~0); 301680#L902-1 assume 1 == ~E_2~0;~E_2~0 := 2; 301681#L907-1 assume !(1 == ~E_3~0); 301995#L912-1 assume !(1 == ~E_4~0); 301996#L917-1 assume !(1 == ~E_5~0); 302186#L922-1 assume !(1 == ~E_6~0); 302187#L927-1 assume !(1 == ~E_7~0); 305362#L1178-1 [2021-11-09 09:35:12,660 INFO L793 eck$LassoCheckResult]: Loop: 305362#L1178-1 assume !false; 305352#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 305341#L744 assume !false; 305340#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 305322#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 305311#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 305304#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 305295#L641 assume !(0 != eval_~tmp~0); 305296#L759 start_simulation_~kernel_st~0 := 2; 326250#L529-1 start_simulation_~kernel_st~0 := 3; 326248#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 326246#L769-4 assume !(0 == ~T1_E~0); 326244#L774-3 assume !(0 == ~T2_E~0); 326242#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 326240#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 326238#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 326237#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 326236#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 326234#L804-3 assume 0 == ~E_M~0;~E_M~0 := 1; 326233#L809-3 assume !(0 == ~E_1~0); 326232#L814-3 assume !(0 == ~E_2~0); 326230#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 326228#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 326226#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 326223#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 326221#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 326219#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 326207#L376-27 assume !(1 == ~m_pc~0); 325782#L376-29 is_master_triggered_~__retres1~0 := 0; 325781#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 325780#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 325779#L955-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 325778#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 325777#L395-27 assume !(1 == ~t1_pc~0); 325776#L395-29 is_transmit1_triggered_~__retres1~1 := 0; 325775#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 325773#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 325770#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 325768#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 325766#L414-27 assume !(1 == ~t2_pc~0); 325764#L414-29 is_transmit2_triggered_~__retres1~2 := 0; 325760#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 325756#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 325754#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 325751#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 325748#L433-27 assume !(1 == ~t3_pc~0); 325745#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 325743#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 325741#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 325738#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 325736#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 325734#L452-27 assume !(1 == ~t4_pc~0); 325732#L452-29 is_transmit4_triggered_~__retres1~4 := 0; 325730#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 323992#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 323991#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 323989#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 323988#L471-27 assume !(1 == ~t5_pc~0); 323986#L471-29 is_transmit5_triggered_~__retres1~5 := 0; 323984#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 323982#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 323981#L995-27 assume !(0 != activate_threads_~tmp___4~0); 323978#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 323976#L490-27 assume !(1 == ~t6_pc~0); 323974#L490-29 is_transmit6_triggered_~__retres1~6 := 0; 323973#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 323972#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 323971#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 323970#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 323969#L509-27 assume !(1 == ~t7_pc~0); 323968#L509-29 is_transmit7_triggered_~__retres1~7 := 0; 323966#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 323965#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 323964#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 323963#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 323962#L857-3 assume !(1 == ~T1_E~0); 323961#L862-3 assume !(1 == ~T2_E~0); 323960#L867-3 assume !(1 == ~T3_E~0); 323959#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 323957#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 323740#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 323738#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 323735#L892-3 assume 1 == ~E_M~0;~E_M~0 := 2; 322762#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 305752#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 305745#L907-3 assume !(1 == ~E_3~0); 305739#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 305733#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 305729#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 305724#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 305720#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 305522#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 305509#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 305502#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 305489#L1197 assume !(0 == start_simulation_~tmp~3); 305478#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 305435#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 305421#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 305414#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 305405#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 305399#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 305391#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 305382#L1210 assume !(0 != start_simulation_~tmp___0~1); 305362#L1178-1 [2021-11-09 09:35:12,660 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:12,660 INFO L85 PathProgramCache]: Analyzing trace with hash 1074145317, now seen corresponding path program 1 times [2021-11-09 09:35:12,660 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:12,661 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [820713460] [2021-11-09 09:35:12,661 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:12,661 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:12,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:12,691 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:12,692 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:12,692 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [820713460] [2021-11-09 09:35:12,692 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [820713460] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:12,692 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:12,692 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-09 09:35:12,693 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1040637249] [2021-11-09 09:35:12,693 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:12,693 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:12,693 INFO L85 PathProgramCache]: Analyzing trace with hash 1068842318, now seen corresponding path program 1 times [2021-11-09 09:35:12,694 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:12,694 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1160970719] [2021-11-09 09:35:12,694 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:12,694 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:12,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:12,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:12,903 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:12,903 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1160970719] [2021-11-09 09:35:12,904 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1160970719] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:12,904 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:12,904 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:12,904 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [905243126] [2021-11-09 09:35:12,905 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:12,905 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:12,905 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:35:12,905 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:35:12,906 INFO L87 Difference]: Start difference. First operand 51801 states and 73997 transitions. cyclomatic complexity: 22228 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 2 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:13,138 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:13,138 INFO L93 Difference]: Finished difference Result 51800 states and 73516 transitions. [2021-11-09 09:35:13,138 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:35:13,138 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51800 states and 73516 transitions. [2021-11-09 09:35:13,354 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 51519 [2021-11-09 09:35:13,543 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51800 states to 51800 states and 73516 transitions. [2021-11-09 09:35:13,543 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51800 [2021-11-09 09:35:13,578 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51800 [2021-11-09 09:35:13,579 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51800 states and 73516 transitions. [2021-11-09 09:35:13,644 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:13,644 INFO L681 BuchiCegarLoop]: Abstraction has 51800 states and 73516 transitions. [2021-11-09 09:35:13,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51800 states and 73516 transitions. [2021-11-09 09:35:13,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51800 to 28010. [2021-11-09 09:35:13,985 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28010 states, 28010 states have (on average 1.41146019278829) internal successors, (39535), 28009 states have internal predecessors, (39535), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:14,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28010 states to 28010 states and 39535 transitions. [2021-11-09 09:35:14,057 INFO L704 BuchiCegarLoop]: Abstraction has 28010 states and 39535 transitions. [2021-11-09 09:35:14,057 INFO L587 BuchiCegarLoop]: Abstraction has 28010 states and 39535 transitions. [2021-11-09 09:35:14,057 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-09 09:35:14,057 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28010 states and 39535 transitions. [2021-11-09 09:35:14,356 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27789 [2021-11-09 09:35:14,356 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:14,356 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:14,358 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:14,358 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:14,358 INFO L791 eck$LassoCheckResult]: Stem: 405572#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 405573#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 405436#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 405378#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 405379#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 405362#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 405192#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 405193#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 405173#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 405174#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 405731#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 405509#L571-1 assume !(0 == ~M_E~0); 405504#L769-1 assume !(0 == ~T1_E~0); 405505#L774-1 assume !(0 == ~T2_E~0); 405566#L779-1 assume !(0 == ~T3_E~0); 405712#L784-1 assume !(0 == ~T4_E~0); 405502#L789-1 assume !(0 == ~T5_E~0); 405503#L794-1 assume !(0 == ~T6_E~0); 405632#L799-1 assume !(0 == ~T7_E~0); 405510#L804-1 assume !(0 == ~E_M~0); 405511#L809-1 assume !(0 == ~E_1~0); 405553#L814-1 assume !(0 == ~E_2~0); 404919#L819-1 assume !(0 == ~E_3~0); 404920#L824-1 assume !(0 == ~E_4~0); 405261#L829-1 assume !(0 == ~E_5~0); 405814#L834-1 assume !(0 == ~E_6~0); 405040#L839-1 assume !(0 == ~E_7~0); 405041#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 405444#L376 assume !(1 == ~m_pc~0); 405440#L376-2 is_master_triggered_~__retres1~0 := 0; 405441#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 405782#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 404996#L955 assume !(0 != activate_threads_~tmp~1); 404997#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 405356#L395 assume !(1 == ~t1_pc~0); 405530#L395-2 is_transmit1_triggered_~__retres1~1 := 0; 405695#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 404925#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 404926#L963 assume !(0 != activate_threads_~tmp___0~0); 405451#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 405452#L414 assume !(1 == ~t2_pc~0); 405044#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 405043#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 405247#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 405248#L971 assume !(0 != activate_threads_~tmp___1~0); 405736#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 405358#L433 assume !(1 == ~t3_pc~0); 405163#L433-2 is_transmit3_triggered_~__retres1~3 := 0; 405164#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 405328#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 405329#L979 assume !(0 != activate_threads_~tmp___2~0); 405012#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 405013#L452 assume !(1 == ~t4_pc~0); 405169#L452-2 is_transmit4_triggered_~__retres1~4 := 0; 405170#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 405489#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 405565#L987 assume !(0 != activate_threads_~tmp___3~0); 405203#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 405204#L471 assume !(1 == ~t5_pc~0); 405613#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 405857#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 405554#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 405555#L995 assume !(0 != activate_threads_~tmp___4~0); 405801#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 405802#L490 assume !(1 == ~t6_pc~0); 405449#L490-2 is_transmit6_triggered_~__retres1~6 := 0; 405450#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 405495#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 405498#L1003 assume !(0 != activate_threads_~tmp___5~0); 405368#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 405338#L509 assume !(1 == ~t7_pc~0); 405339#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 405143#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 405144#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 405208#L1011 assume !(0 != activate_threads_~tmp___6~0); 405209#L1011-2 assume !(1 == ~M_E~0); 405835#L857-1 assume !(1 == ~T1_E~0); 405273#L862-1 assume !(1 == ~T2_E~0); 405274#L867-1 assume !(1 == ~T3_E~0); 405281#L872-1 assume !(1 == ~T4_E~0); 405359#L877-1 assume !(1 == ~T5_E~0); 405585#L882-1 assume !(1 == ~T6_E~0); 405763#L887-1 assume !(1 == ~T7_E~0); 405653#L892-1 assume !(1 == ~E_M~0); 405654#L897-1 assume !(1 == ~E_1~0); 405291#L902-1 assume 1 == ~E_2~0;~E_2~0 := 2; 405292#L907-1 assume !(1 == ~E_3~0); 405604#L912-1 assume !(1 == ~E_4~0); 405593#L917-1 assume !(1 == ~E_5~0); 405594#L922-1 assume !(1 == ~E_6~0); 405817#L927-1 assume !(1 == ~E_7~0); 405897#L1178-1 [2021-11-09 09:35:14,359 INFO L793 eck$LassoCheckResult]: Loop: 405897#L1178-1 assume !false; 412820#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 412814#L744 assume !false; 412812#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 412800#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 412791#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 412789#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 412786#L641 assume !(0 != eval_~tmp~0); 412787#L759 start_simulation_~kernel_st~0 := 2; 415440#L529-1 start_simulation_~kernel_st~0 := 3; 415439#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 415438#L769-4 assume !(0 == ~T1_E~0); 415437#L774-3 assume !(0 == ~T2_E~0); 415436#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 415435#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 415434#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 415433#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 415432#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 415431#L804-3 assume !(0 == ~E_M~0); 415430#L809-3 assume !(0 == ~E_1~0); 415429#L814-3 assume !(0 == ~E_2~0); 415428#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 415427#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 415426#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 415425#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 415424#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 415423#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 415422#L376-27 assume !(1 == ~m_pc~0); 415420#L376-29 is_master_triggered_~__retres1~0 := 0; 415418#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 415416#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 415414#L955-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 415412#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 415410#L395-27 assume !(1 == ~t1_pc~0); 415408#L395-29 is_transmit1_triggered_~__retres1~1 := 0; 415406#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 415404#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 415401#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 415398#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 415395#L414-27 assume !(1 == ~t2_pc~0); 415392#L414-29 is_transmit2_triggered_~__retres1~2 := 0; 415388#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 415385#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 415382#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 415379#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 415376#L433-27 assume !(1 == ~t3_pc~0); 411099#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 411100#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 411093#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 411094#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 411088#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 411089#L452-27 assume !(1 == ~t4_pc~0); 411082#L452-29 is_transmit4_triggered_~__retres1~4 := 0; 411083#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 411076#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 411077#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 411070#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 411071#L471-27 assume !(1 == ~t5_pc~0); 411061#L471-29 is_transmit5_triggered_~__retres1~5 := 0; 411062#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 411055#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 411056#L995-27 assume !(0 != activate_threads_~tmp___4~0); 411046#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 411047#L490-27 assume !(1 == ~t6_pc~0); 411040#L490-29 is_transmit6_triggered_~__retres1~6 := 0; 411041#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 411033#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 411034#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 411027#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 411028#L509-27 assume !(1 == ~t7_pc~0); 411021#L509-29 is_transmit7_triggered_~__retres1~7 := 0; 411020#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 411013#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 411014#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 411007#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 411008#L857-3 assume !(1 == ~T1_E~0); 411000#L862-3 assume !(1 == ~T2_E~0); 411001#L867-3 assume !(1 == ~T3_E~0); 410994#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 410995#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 410988#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 410989#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 410982#L892-3 assume !(1 == ~E_M~0); 410983#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 410976#L902-3 assume 1 == ~E_2~0;~E_2~0 := 2; 410977#L907-3 assume !(1 == ~E_3~0); 410970#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 410971#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 410964#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 410965#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 410958#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 410959#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 413069#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 413068#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 413066#L1197 assume !(0 == start_simulation_~tmp~3); 413064#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 410937#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 410926#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 410927#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 412828#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 412826#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 412824#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 412822#L1210 assume !(0 != start_simulation_~tmp___0~1); 405897#L1178-1 [2021-11-09 09:35:14,359 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:14,359 INFO L85 PathProgramCache]: Analyzing trace with hash 264798691, now seen corresponding path program 1 times [2021-11-09 09:35:14,360 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:14,360 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1717132485] [2021-11-09 09:35:14,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:14,360 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:14,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:14,391 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:14,391 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:14,391 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1717132485] [2021-11-09 09:35:14,391 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1717132485] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:14,392 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:14,392 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-09 09:35:14,392 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1008643859] [2021-11-09 09:35:14,392 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:14,393 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:14,393 INFO L85 PathProgramCache]: Analyzing trace with hash -926940334, now seen corresponding path program 1 times [2021-11-09 09:35:14,393 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:14,393 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1324916731] [2021-11-09 09:35:14,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:14,393 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:14,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:14,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:14,421 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:14,422 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1324916731] [2021-11-09 09:35:14,422 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1324916731] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:14,422 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:14,422 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:14,422 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [871845999] [2021-11-09 09:35:14,423 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:14,423 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:14,423 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:35:14,423 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:35:14,424 INFO L87 Difference]: Start difference. First operand 28010 states and 39535 transitions. cyclomatic complexity: 11541 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 2 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:14,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:14,536 INFO L93 Difference]: Finished difference Result 28010 states and 39021 transitions. [2021-11-09 09:35:14,537 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:35:14,537 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28010 states and 39021 transitions. [2021-11-09 09:35:14,638 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27789 [2021-11-09 09:35:14,719 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28010 states to 28010 states and 39021 transitions. [2021-11-09 09:35:14,719 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28010 [2021-11-09 09:35:14,737 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28010 [2021-11-09 09:35:14,737 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28010 states and 39021 transitions. [2021-11-09 09:35:14,754 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:14,754 INFO L681 BuchiCegarLoop]: Abstraction has 28010 states and 39021 transitions. [2021-11-09 09:35:14,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28010 states and 39021 transitions. [2021-11-09 09:35:14,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28010 to 28010. [2021-11-09 09:35:14,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28010 states, 28010 states have (on average 1.3931096037129596) internal successors, (39021), 28009 states have internal predecessors, (39021), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:15,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28010 states to 28010 states and 39021 transitions. [2021-11-09 09:35:15,033 INFO L704 BuchiCegarLoop]: Abstraction has 28010 states and 39021 transitions. [2021-11-09 09:35:15,033 INFO L587 BuchiCegarLoop]: Abstraction has 28010 states and 39021 transitions. [2021-11-09 09:35:15,033 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-09 09:35:15,033 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28010 states and 39021 transitions. [2021-11-09 09:35:15,100 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27789 [2021-11-09 09:35:15,100 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:15,100 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:15,101 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:15,101 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:15,102 INFO L791 eck$LassoCheckResult]: Stem: 461591#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 461592#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 461456#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 461400#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 461401#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 461381#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 461213#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 461214#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 461194#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 461195#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 461745#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 461527#L571-1 assume !(0 == ~M_E~0); 461523#L769-1 assume !(0 == ~T1_E~0); 461524#L774-1 assume !(0 == ~T2_E~0); 461583#L779-1 assume !(0 == ~T3_E~0); 461726#L784-1 assume !(0 == ~T4_E~0); 461521#L789-1 assume !(0 == ~T5_E~0); 461522#L794-1 assume !(0 == ~T6_E~0); 461649#L799-1 assume !(0 == ~T7_E~0); 461529#L804-1 assume !(0 == ~E_M~0); 461530#L809-1 assume !(0 == ~E_1~0); 461570#L814-1 assume !(0 == ~E_2~0); 460946#L819-1 assume !(0 == ~E_3~0); 460947#L824-1 assume !(0 == ~E_4~0); 461281#L829-1 assume !(0 == ~E_5~0); 461826#L834-1 assume !(0 == ~E_6~0); 461067#L839-1 assume !(0 == ~E_7~0); 461068#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 461465#L376 assume !(1 == ~m_pc~0); 461461#L376-2 is_master_triggered_~__retres1~0 := 0; 461462#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 461793#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 461024#L955 assume !(0 != activate_threads_~tmp~1); 461025#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 461374#L395 assume !(1 == ~t1_pc~0); 461549#L395-2 is_transmit1_triggered_~__retres1~1 := 0; 461710#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 460952#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 460953#L963 assume !(0 != activate_threads_~tmp___0~0); 461472#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 461473#L414 assume !(1 == ~t2_pc~0); 461070#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 461750#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 461268#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 461269#L971 assume !(0 != activate_threads_~tmp___1~0); 461748#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 461377#L433 assume !(1 == ~t3_pc~0); 461181#L433-2 is_transmit3_triggered_~__retres1~3 := 0; 461182#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 461348#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 461349#L979 assume !(0 != activate_threads_~tmp___2~0); 461040#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 461041#L452 assume !(1 == ~t4_pc~0); 461190#L452-2 is_transmit4_triggered_~__retres1~4 := 0; 461191#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 461506#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 461582#L987 assume !(0 != activate_threads_~tmp___3~0); 461224#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 461225#L471 assume !(1 == ~t5_pc~0); 461629#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 461857#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 461571#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 461572#L995 assume !(0 != activate_threads_~tmp___4~0); 461813#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 461814#L490 assume !(1 == ~t6_pc~0); 461469#L490-2 is_transmit6_triggered_~__retres1~6 := 0; 461470#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 461513#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 461516#L1003 assume !(0 != activate_threads_~tmp___5~0); 461385#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 461356#L509 assume !(1 == ~t7_pc~0); 461357#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 461164#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 461165#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 461229#L1011 assume !(0 != activate_threads_~tmp___6~0); 461230#L1011-2 assume !(1 == ~M_E~0); 461839#L857-1 assume !(1 == ~T1_E~0); 461290#L862-1 assume !(1 == ~T2_E~0); 461291#L867-1 assume !(1 == ~T3_E~0); 461296#L872-1 assume !(1 == ~T4_E~0); 461378#L877-1 assume !(1 == ~T5_E~0); 461604#L882-1 assume !(1 == ~T6_E~0); 461780#L887-1 assume !(1 == ~T7_E~0); 461670#L892-1 assume !(1 == ~E_M~0); 461671#L897-1 assume !(1 == ~E_1~0); 461307#L902-1 assume !(1 == ~E_2~0); 461308#L907-1 assume !(1 == ~E_3~0); 461623#L912-1 assume !(1 == ~E_4~0); 461613#L917-1 assume !(1 == ~E_5~0); 461614#L922-1 assume !(1 == ~E_6~0); 461829#L927-1 assume !(1 == ~E_7~0); 461895#L1178-1 [2021-11-09 09:35:15,102 INFO L793 eck$LassoCheckResult]: Loop: 461895#L1178-1 assume !false; 487465#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 487460#L744 assume !false; 487457#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 487386#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 487378#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 487376#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 487372#L641 assume !(0 != eval_~tmp~0); 487373#L759 start_simulation_~kernel_st~0 := 2; 488197#L529-1 start_simulation_~kernel_st~0 := 3; 488191#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 488185#L769-4 assume !(0 == ~T1_E~0); 488180#L774-3 assume !(0 == ~T2_E~0); 488174#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 488168#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 488163#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 488158#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 488155#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 488148#L804-3 assume !(0 == ~E_M~0); 488142#L809-3 assume !(0 == ~E_1~0); 488135#L814-3 assume !(0 == ~E_2~0); 488129#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 488123#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 488116#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 488094#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 487886#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 487885#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 487884#L376-27 assume !(1 == ~m_pc~0); 487883#L376-29 is_master_triggered_~__retres1~0 := 0; 487882#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 487880#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 487878#L955-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 487876#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 487874#L395-27 assume !(1 == ~t1_pc~0); 487872#L395-29 is_transmit1_triggered_~__retres1~1 := 0; 487871#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 487869#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 487867#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 487865#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 487863#L414-27 assume !(1 == ~t2_pc~0); 487859#L414-29 is_transmit2_triggered_~__retres1~2 := 0; 487857#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 487855#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 487853#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 487851#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 487849#L433-27 assume !(1 == ~t3_pc~0); 487839#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 487835#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 487830#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 487825#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 487820#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 487816#L452-27 assume !(1 == ~t4_pc~0); 487812#L452-29 is_transmit4_triggered_~__retres1~4 := 0; 487807#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 487802#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 487797#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 487791#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 487785#L471-27 assume 1 == ~t5_pc~0; 487783#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 487784#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 487841#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 487761#L995-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 487759#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 487757#L490-27 assume !(1 == ~t6_pc~0); 487755#L490-29 is_transmit6_triggered_~__retres1~6 := 0; 487753#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 487751#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 487749#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 487747#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 487745#L509-27 assume !(1 == ~t7_pc~0); 487743#L509-29 is_transmit7_triggered_~__retres1~7 := 0; 487740#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 487738#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 487736#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 487734#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 487732#L857-3 assume !(1 == ~T1_E~0); 487730#L862-3 assume !(1 == ~T2_E~0); 487728#L867-3 assume !(1 == ~T3_E~0); 487724#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 487722#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 487720#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 487718#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 487715#L892-3 assume !(1 == ~E_M~0); 487713#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 487711#L902-3 assume !(1 == ~E_2~0); 487709#L907-3 assume !(1 == ~E_3~0); 487707#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 487705#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 487703#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 487701#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 487699#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 487696#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 487687#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 487685#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 487489#L1197 assume !(0 == start_simulation_~tmp~3); 487484#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 487482#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 487474#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 487473#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 487472#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 487471#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 487470#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 487468#L1210 assume !(0 != start_simulation_~tmp___0~1); 461895#L1178-1 [2021-11-09 09:35:15,103 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:15,103 INFO L85 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 1 times [2021-11-09 09:35:15,103 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:15,103 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [694331535] [2021-11-09 09:35:15,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:15,103 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:15,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:15,115 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:15,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:15,179 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:15,179 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:15,180 INFO L85 PathProgramCache]: Analyzing trace with hash -1556025801, now seen corresponding path program 1 times [2021-11-09 09:35:15,180 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:15,180 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1089797239] [2021-11-09 09:35:15,180 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:15,180 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:15,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:15,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:15,206 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:15,206 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1089797239] [2021-11-09 09:35:15,207 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1089797239] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:15,207 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:15,207 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:15,207 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [382593495] [2021-11-09 09:35:15,207 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:15,208 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:15,208 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:35:15,208 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:35:15,208 INFO L87 Difference]: Start difference. First operand 28010 states and 39021 transitions. cyclomatic complexity: 11027 Second operand has 3 states, 3 states have (on average 34.333333333333336) internal successors, (103), 3 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:15,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:15,525 INFO L93 Difference]: Finished difference Result 31957 states and 44411 transitions. [2021-11-09 09:35:15,525 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:35:15,526 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31957 states and 44411 transitions. [2021-11-09 09:35:15,640 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 31666 [2021-11-09 09:35:15,702 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31957 states to 31957 states and 44411 transitions. [2021-11-09 09:35:15,702 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31957 [2021-11-09 09:35:15,717 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31957 [2021-11-09 09:35:15,717 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31957 states and 44411 transitions. [2021-11-09 09:35:15,735 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:15,736 INFO L681 BuchiCegarLoop]: Abstraction has 31957 states and 44411 transitions. [2021-11-09 09:35:15,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31957 states and 44411 transitions. [2021-11-09 09:35:15,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31957 to 31957. [2021-11-09 09:35:15,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31957 states, 31957 states have (on average 1.3897111743905874) internal successors, (44411), 31956 states have internal predecessors, (44411), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:16,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31957 states to 31957 states and 44411 transitions. [2021-11-09 09:35:16,032 INFO L704 BuchiCegarLoop]: Abstraction has 31957 states and 44411 transitions. [2021-11-09 09:35:16,032 INFO L587 BuchiCegarLoop]: Abstraction has 31957 states and 44411 transitions. [2021-11-09 09:35:16,032 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-09 09:35:16,033 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31957 states and 44411 transitions. [2021-11-09 09:35:16,103 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 31666 [2021-11-09 09:35:16,103 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:16,103 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:16,105 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:16,105 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:16,106 INFO L791 eck$LassoCheckResult]: Stem: 521574#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 521575#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 521431#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 521371#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 521372#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 521353#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 521188#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 521189#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 521169#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 521170#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 521744#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 521505#L571-1 assume !(0 == ~M_E~0); 521500#L769-1 assume !(0 == ~T1_E~0); 521501#L774-1 assume !(0 == ~T2_E~0); 521566#L779-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 521722#L784-1 assume !(0 == ~T4_E~0); 521723#L789-1 assume !(0 == ~T5_E~0); 522000#L794-1 assume !(0 == ~T6_E~0); 521999#L799-1 assume !(0 == ~T7_E~0); 521508#L804-1 assume !(0 == ~E_M~0); 521509#L809-1 assume !(0 == ~E_1~0); 521751#L814-1 assume !(0 == ~E_2~0); 521752#L819-1 assume !(0 == ~E_3~0); 521259#L824-1 assume !(0 == ~E_4~0); 521260#L829-1 assume !(0 == ~E_5~0); 521949#L834-1 assume !(0 == ~E_6~0); 521041#L839-1 assume !(0 == ~E_7~0); 521042#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 521644#L376 assume !(1 == ~m_pc~0); 521436#L376-2 is_master_triggered_~__retres1~0 := 0; 521437#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 521797#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 521798#L955 assume !(0 != activate_threads_~tmp~1); 521996#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 521533#L395 assume !(1 == ~t1_pc~0); 521534#L395-2 is_transmit1_triggered_~__retres1~1 := 0; 521700#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 521994#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 521767#L963 assume !(0 != activate_threads_~tmp___0~0); 521768#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 521992#L414 assume !(1 == ~t2_pc~0); 521991#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 521990#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 521243#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 521244#L971 assume !(0 != activate_threads_~tmp___1~0); 521748#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 521988#L433 assume !(1 == ~t3_pc~0); 521987#L433-2 is_transmit3_triggered_~__retres1~3 := 0; 521862#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 521320#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 521321#L979 assume !(0 != activate_threads_~tmp___2~0); 521012#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 521013#L452 assume !(1 == ~t4_pc~0); 521983#L452-2 is_transmit4_triggered_~__retres1~4 := 0; 521483#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 521484#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 521565#L987 assume !(0 != activate_threads_~tmp___3~0); 521199#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 521200#L471 assume !(1 == ~t5_pc~0); 521618#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 521181#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 521182#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 521976#L995 assume !(0 != activate_threads_~tmp___4~0); 521821#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 521822#L490 assume !(1 == ~t6_pc~0); 521446#L490-2 is_transmit6_triggered_~__retres1~6 := 0; 521447#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 521491#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 521494#L1003 assume !(0 != activate_threads_~tmp___5~0); 521357#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 521328#L509 assume !(1 == ~t7_pc~0); 521329#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 521137#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 521138#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 521204#L1011 assume !(0 != activate_threads_~tmp___6~0); 521205#L1011-2 assume !(1 == ~M_E~0); 521861#L857-1 assume !(1 == ~T1_E~0); 521268#L862-1 assume !(1 == ~T2_E~0); 521269#L867-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 521274#L872-1 assume !(1 == ~T4_E~0); 521350#L877-1 assume !(1 == ~T5_E~0); 521587#L882-1 assume !(1 == ~T6_E~0); 521782#L887-1 assume !(1 == ~T7_E~0); 521660#L892-1 assume !(1 == ~E_M~0); 521661#L897-1 assume !(1 == ~E_1~0); 521285#L902-1 assume !(1 == ~E_2~0); 521286#L907-1 assume !(1 == ~E_3~0); 521605#L912-1 assume !(1 == ~E_4~0); 521596#L917-1 assume !(1 == ~E_5~0); 521597#L922-1 assume !(1 == ~E_6~0); 521843#L927-1 assume !(1 == ~E_7~0); 521941#L1178-1 [2021-11-09 09:35:16,106 INFO L793 eck$LassoCheckResult]: Loop: 521941#L1178-1 assume !false; 541518#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 541512#L744 assume !false; 541510#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 541483#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 541475#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 541474#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 541472#L641 assume !(0 != eval_~tmp~0); 541473#L759 start_simulation_~kernel_st~0 := 2; 541727#L529-1 start_simulation_~kernel_st~0 := 3; 541725#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 541723#L769-4 assume !(0 == ~T1_E~0); 541721#L774-3 assume !(0 == ~T2_E~0); 541718#L779-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 541716#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 541714#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 541712#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 541709#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 541707#L804-3 assume !(0 == ~E_M~0); 541705#L809-3 assume !(0 == ~E_1~0); 541703#L814-3 assume !(0 == ~E_2~0); 541701#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 541699#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 541697#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 541696#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 541695#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 541694#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 541693#L376-27 assume !(1 == ~m_pc~0); 541691#L376-29 is_master_triggered_~__retres1~0 := 0; 541690#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 541689#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 541688#L955-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 541687#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 541685#L395-27 assume !(1 == ~t1_pc~0); 541683#L395-29 is_transmit1_triggered_~__retres1~1 := 0; 541681#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 541679#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 541677#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 541675#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 541673#L414-27 assume !(1 == ~t2_pc~0); 541670#L414-29 is_transmit2_triggered_~__retres1~2 := 0; 541668#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 541666#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 541664#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 541662#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 541659#L433-27 assume !(1 == ~t3_pc~0); 541657#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 541655#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 541653#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 541651#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 541649#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 541647#L452-27 assume !(1 == ~t4_pc~0); 541645#L452-29 is_transmit4_triggered_~__retres1~4 := 0; 541643#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 541641#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 541639#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 541637#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 541635#L471-27 assume 1 == ~t5_pc~0; 541632#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 541630#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 541628#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 541621#L995-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 541619#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 541617#L490-27 assume !(1 == ~t6_pc~0); 541615#L490-29 is_transmit6_triggered_~__retres1~6 := 0; 541612#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 541610#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 541608#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 541606#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 541604#L509-27 assume 1 == ~t7_pc~0; 541601#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 541599#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 541597#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 541595#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 541592#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 541590#L857-3 assume !(1 == ~T1_E~0); 541588#L862-3 assume !(1 == ~T2_E~0); 541586#L867-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 541583#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 541581#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 541579#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 541577#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 541575#L892-3 assume !(1 == ~E_M~0); 541573#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 541571#L902-3 assume !(1 == ~E_2~0); 541569#L907-3 assume !(1 == ~E_3~0); 541567#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 541565#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 541563#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 541561#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 541559#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 541557#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 541548#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 541547#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 541545#L1197 assume !(0 == start_simulation_~tmp~3); 541542#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 541540#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 541531#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 541529#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 541527#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 541525#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 541523#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 541521#L1210 assume !(0 != start_simulation_~tmp___0~1); 521941#L1178-1 [2021-11-09 09:35:16,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:16,107 INFO L85 PathProgramCache]: Analyzing trace with hash 881797405, now seen corresponding path program 1 times [2021-11-09 09:35:16,107 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:16,107 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1535140686] [2021-11-09 09:35:16,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:16,107 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:16,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:16,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:16,129 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:16,129 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1535140686] [2021-11-09 09:35:16,129 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1535140686] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:16,129 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:16,129 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-09 09:35:16,129 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1752604035] [2021-11-09 09:35:16,130 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:16,130 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:16,130 INFO L85 PathProgramCache]: Analyzing trace with hash 10584858, now seen corresponding path program 1 times [2021-11-09 09:35:16,130 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:16,131 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [312575400] [2021-11-09 09:35:16,131 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:16,131 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:16,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:16,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:16,157 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:16,158 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [312575400] [2021-11-09 09:35:16,158 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [312575400] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:16,158 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:16,158 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:16,158 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1527868473] [2021-11-09 09:35:16,159 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:16,159 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:16,159 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:35:16,159 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:35:16,160 INFO L87 Difference]: Start difference. First operand 31957 states and 44411 transitions. cyclomatic complexity: 12470 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 2 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:16,586 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:16,586 INFO L93 Difference]: Finished difference Result 28010 states and 38857 transitions. [2021-11-09 09:35:16,586 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:35:16,586 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28010 states and 38857 transitions. [2021-11-09 09:35:16,672 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27789 [2021-11-09 09:35:16,721 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28010 states to 28010 states and 38857 transitions. [2021-11-09 09:35:16,721 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28010 [2021-11-09 09:35:16,731 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28010 [2021-11-09 09:35:16,731 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28010 states and 38857 transitions. [2021-11-09 09:35:16,740 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:16,740 INFO L681 BuchiCegarLoop]: Abstraction has 28010 states and 38857 transitions. [2021-11-09 09:35:16,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28010 states and 38857 transitions. [2021-11-09 09:35:16,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28010 to 28010. [2021-11-09 09:35:16,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28010 states, 28010 states have (on average 1.3872545519457338) internal successors, (38857), 28009 states have internal predecessors, (38857), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:16,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28010 states to 28010 states and 38857 transitions. [2021-11-09 09:35:16,982 INFO L704 BuchiCegarLoop]: Abstraction has 28010 states and 38857 transitions. [2021-11-09 09:35:16,982 INFO L587 BuchiCegarLoop]: Abstraction has 28010 states and 38857 transitions. [2021-11-09 09:35:16,982 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-09 09:35:16,982 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28010 states and 38857 transitions. [2021-11-09 09:35:17,044 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27789 [2021-11-09 09:35:17,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:17,044 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:17,045 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:17,045 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:17,046 INFO L791 eck$LassoCheckResult]: Stem: 581532#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 581533#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 581400#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 581341#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 581342#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 581324#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 581160#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 581161#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 581142#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 581143#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 581682#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 581469#L571-1 assume !(0 == ~M_E~0); 581465#L769-1 assume !(0 == ~T1_E~0); 581466#L774-1 assume !(0 == ~T2_E~0); 581525#L779-1 assume !(0 == ~T3_E~0); 581663#L784-1 assume !(0 == ~T4_E~0); 581463#L789-1 assume !(0 == ~T5_E~0); 581464#L794-1 assume !(0 == ~T6_E~0); 581588#L799-1 assume !(0 == ~T7_E~0); 581471#L804-1 assume !(0 == ~E_M~0); 581472#L809-1 assume !(0 == ~E_1~0); 581512#L814-1 assume !(0 == ~E_2~0); 580893#L819-1 assume !(0 == ~E_3~0); 580894#L824-1 assume !(0 == ~E_4~0); 581228#L829-1 assume !(0 == ~E_5~0); 581752#L834-1 assume !(0 == ~E_6~0); 581013#L839-1 assume !(0 == ~E_7~0); 581014#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 581408#L376 assume !(1 == ~m_pc~0); 581404#L376-2 is_master_triggered_~__retres1~0 := 0; 581405#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 581719#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 580970#L955 assume !(0 != activate_threads_~tmp~1); 580971#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 581318#L395 assume !(1 == ~t1_pc~0); 581492#L395-2 is_transmit1_triggered_~__retres1~1 := 0; 581647#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 580899#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 580900#L963 assume !(0 != activate_threads_~tmp___0~0); 581415#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 581416#L414 assume !(1 == ~t2_pc~0); 581016#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 581687#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 581215#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 581216#L971 assume !(0 != activate_threads_~tmp___1~0); 581685#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 581320#L433 assume !(1 == ~t3_pc~0); 581129#L433-2 is_transmit3_triggered_~__retres1~3 := 0; 581130#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 581293#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 581294#L979 assume !(0 != activate_threads_~tmp___2~0); 580986#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 580987#L452 assume !(1 == ~t4_pc~0); 581138#L452-2 is_transmit4_triggered_~__retres1~4 := 0; 581139#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 581449#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 581524#L987 assume !(0 != activate_threads_~tmp___3~0); 581171#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 581172#L471 assume !(1 == ~t5_pc~0); 581570#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 581786#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 581513#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 581514#L995 assume !(0 != activate_threads_~tmp___4~0); 581738#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 581739#L490 assume !(1 == ~t6_pc~0); 581413#L490-2 is_transmit6_triggered_~__retres1~6 := 0; 581414#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 581456#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 581459#L1003 assume !(0 != activate_threads_~tmp___5~0); 581328#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 581299#L509 assume !(1 == ~t7_pc~0); 581300#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 581109#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 581110#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 581176#L1011 assume !(0 != activate_threads_~tmp___6~0); 581177#L1011-2 assume !(1 == ~M_E~0); 581765#L857-1 assume !(1 == ~T1_E~0); 581236#L862-1 assume !(1 == ~T2_E~0); 581237#L867-1 assume !(1 == ~T3_E~0); 581242#L872-1 assume !(1 == ~T4_E~0); 581321#L877-1 assume !(1 == ~T5_E~0); 581544#L882-1 assume !(1 == ~T6_E~0); 581707#L887-1 assume !(1 == ~T7_E~0); 581608#L892-1 assume !(1 == ~E_M~0); 581609#L897-1 assume !(1 == ~E_1~0); 581255#L902-1 assume !(1 == ~E_2~0); 581256#L907-1 assume !(1 == ~E_3~0); 581560#L912-1 assume !(1 == ~E_4~0); 581552#L917-1 assume !(1 == ~E_5~0); 581553#L922-1 assume !(1 == ~E_6~0); 581756#L927-1 assume !(1 == ~E_7~0); 581825#L1178-1 [2021-11-09 09:35:17,046 INFO L793 eck$LassoCheckResult]: Loop: 581825#L1178-1 assume !false; 599286#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 599280#L744 assume !false; 599278#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 599272#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 599264#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 599263#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 599261#L641 assume !(0 != eval_~tmp~0); 599262#L759 start_simulation_~kernel_st~0 := 2; 599489#L529-1 start_simulation_~kernel_st~0 := 3; 599488#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 599487#L769-4 assume !(0 == ~T1_E~0); 599486#L774-3 assume !(0 == ~T2_E~0); 599485#L779-3 assume !(0 == ~T3_E~0); 599484#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 599482#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 599480#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 599478#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 599476#L804-3 assume !(0 == ~E_M~0); 599474#L809-3 assume !(0 == ~E_1~0); 599472#L814-3 assume !(0 == ~E_2~0); 599470#L819-3 assume 0 == ~E_3~0;~E_3~0 := 1; 599468#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 599466#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 599464#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 599462#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 599460#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 599457#L376-27 assume !(1 == ~m_pc~0); 599455#L376-29 is_master_triggered_~__retres1~0 := 0; 599453#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 599451#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 599449#L955-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 599447#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 599445#L395-27 assume !(1 == ~t1_pc~0); 599443#L395-29 is_transmit1_triggered_~__retres1~1 := 0; 599441#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 599439#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 599437#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 599435#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 599433#L414-27 assume !(1 == ~t2_pc~0); 599430#L414-29 is_transmit2_triggered_~__retres1~2 := 0; 599428#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 599426#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 599424#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 599422#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 599418#L433-27 assume !(1 == ~t3_pc~0); 599416#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 599414#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 599412#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 599409#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 599407#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 599405#L452-27 assume !(1 == ~t4_pc~0); 599403#L452-29 is_transmit4_triggered_~__retres1~4 := 0; 599401#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 599399#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 599397#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 599395#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 599393#L471-27 assume !(1 == ~t5_pc~0); 599388#L471-29 is_transmit5_triggered_~__retres1~5 := 0; 599386#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 599384#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 599382#L995-27 assume !(0 != activate_threads_~tmp___4~0); 599379#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 599377#L490-27 assume !(1 == ~t6_pc~0); 599375#L490-29 is_transmit6_triggered_~__retres1~6 := 0; 599373#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 599371#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 599369#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 599367#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 599365#L509-27 assume !(1 == ~t7_pc~0); 599363#L509-29 is_transmit7_triggered_~__retres1~7 := 0; 599360#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 599358#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 599356#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 599354#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 599352#L857-3 assume !(1 == ~T1_E~0); 599350#L862-3 assume !(1 == ~T2_E~0); 599349#L867-3 assume !(1 == ~T3_E~0); 599348#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 599347#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 599346#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 599345#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 599344#L892-3 assume !(1 == ~E_M~0); 599343#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 599342#L902-3 assume !(1 == ~E_2~0); 599341#L907-3 assume !(1 == ~E_3~0); 599340#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 599338#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 599336#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 599334#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 599332#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 599330#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 599321#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 599318#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 599314#L1197 assume !(0 == start_simulation_~tmp~3); 599311#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 599309#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 599300#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 599298#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 599295#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 599293#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 599291#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 599289#L1210 assume !(0 != start_simulation_~tmp___0~1); 581825#L1178-1 [2021-11-09 09:35:17,047 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:17,047 INFO L85 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 2 times [2021-11-09 09:35:17,047 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:17,047 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1376545004] [2021-11-09 09:35:17,047 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:17,048 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:17,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:17,058 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:17,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:17,101 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:17,101 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:17,102 INFO L85 PathProgramCache]: Analyzing trace with hash -738820846, now seen corresponding path program 1 times [2021-11-09 09:35:17,102 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:17,102 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1810656022] [2021-11-09 09:35:17,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:17,102 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:17,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:17,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:17,128 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:17,128 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1810656022] [2021-11-09 09:35:17,128 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1810656022] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:17,128 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:17,129 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:17,129 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [786618335] [2021-11-09 09:35:17,129 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:17,129 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:17,130 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:35:17,130 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:35:17,130 INFO L87 Difference]: Start difference. First operand 28010 states and 38857 transitions. cyclomatic complexity: 10863 Second operand has 3 states, 3 states have (on average 34.333333333333336) internal successors, (103), 3 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:17,313 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:17,313 INFO L93 Difference]: Finished difference Result 43669 states and 60264 transitions. [2021-11-09 09:35:17,313 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:35:17,314 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43669 states and 60264 transitions. [2021-11-09 09:35:17,814 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 43282 [2021-11-09 09:35:17,903 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43669 states to 43669 states and 60264 transitions. [2021-11-09 09:35:17,903 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43669 [2021-11-09 09:35:17,922 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43669 [2021-11-09 09:35:17,922 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43669 states and 60264 transitions. [2021-11-09 09:35:17,940 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:17,940 INFO L681 BuchiCegarLoop]: Abstraction has 43669 states and 60264 transitions. [2021-11-09 09:35:17,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43669 states and 60264 transitions. [2021-11-09 09:35:18,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43669 to 43633. [2021-11-09 09:35:18,288 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43633 states, 43633 states have (on average 1.3803314005454588) internal successors, (60228), 43632 states have internal predecessors, (60228), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:18,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43633 states to 43633 states and 60228 transitions. [2021-11-09 09:35:18,370 INFO L704 BuchiCegarLoop]: Abstraction has 43633 states and 60228 transitions. [2021-11-09 09:35:18,370 INFO L587 BuchiCegarLoop]: Abstraction has 43633 states and 60228 transitions. [2021-11-09 09:35:18,370 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-09 09:35:18,370 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43633 states and 60228 transitions. [2021-11-09 09:35:18,482 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 43246 [2021-11-09 09:35:18,482 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:18,482 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:18,484 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:18,484 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:18,484 INFO L791 eck$LassoCheckResult]: Stem: 653222#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 653223#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 653083#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 653029#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 653030#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 653011#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 652848#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 652849#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 652829#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 652830#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 653382#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 653154#L571-1 assume !(0 == ~M_E~0); 653150#L769-1 assume !(0 == ~T1_E~0); 653151#L774-1 assume !(0 == ~T2_E~0); 653215#L779-1 assume !(0 == ~T3_E~0); 653361#L784-1 assume !(0 == ~T4_E~0); 653148#L789-1 assume !(0 == ~T5_E~0); 653149#L794-1 assume !(0 == ~T6_E~0); 653284#L799-1 assume !(0 == ~T7_E~0); 653156#L804-1 assume !(0 == ~E_M~0); 653157#L809-1 assume !(0 == ~E_1~0); 653202#L814-1 assume !(0 == ~E_2~0); 652578#L819-1 assume 0 == ~E_3~0;~E_3~0 := 1; 652579#L824-1 assume !(0 == ~E_4~0); 652916#L829-1 assume !(0 == ~E_5~0); 653535#L834-1 assume !(0 == ~E_6~0); 652699#L839-1 assume !(0 == ~E_7~0); 652700#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 653289#L376 assume !(1 == ~m_pc~0); 653087#L376-2 is_master_triggered_~__retres1~0 := 0; 653088#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 653427#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 653428#L955 assume !(0 != activate_threads_~tmp~1); 653583#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 653177#L395 assume !(1 == ~t1_pc~0); 653178#L395-2 is_transmit1_triggered_~__retres1~1 := 0; 653342#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 653362#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 653404#L963 assume !(0 != activate_threads_~tmp___0~0); 653405#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 653545#L414 assume !(1 == ~t2_pc~0); 652702#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 653579#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 652903#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 652904#L971 assume !(0 != activate_threads_~tmp___1~0); 653467#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 653007#L433 assume !(1 == ~t3_pc~0); 652816#L433-2 is_transmit3_triggered_~__retres1~3 := 0; 652817#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 653576#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 653575#L979 assume !(0 != activate_threads_~tmp___2~0); 653574#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 653525#L452 assume !(1 == ~t4_pc~0); 652825#L452-2 is_transmit4_triggered_~__retres1~4 := 0; 652826#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 653213#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 653214#L987 assume !(0 != activate_threads_~tmp___3~0); 652859#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 652860#L471 assume !(1 == ~t5_pc~0); 653265#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 652841#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 652842#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 653539#L995 assume !(0 != activate_threads_~tmp___4~0); 653540#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 653501#L490 assume !(1 == ~t6_pc~0); 653502#L490-2 is_transmit6_triggered_~__retres1~6 := 0; 653141#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 653142#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 653271#L1003 assume !(0 != activate_threads_~tmp___5~0); 653565#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 653564#L509 assume !(1 == ~t7_pc~0); 653562#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 653561#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 653560#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 653559#L1011 assume !(0 != activate_threads_~tmp___6~0); 653558#L1011-2 assume !(1 == ~M_E~0); 653557#L857-1 assume !(1 == ~T1_E~0); 653556#L862-1 assume !(1 == ~T2_E~0); 653555#L867-1 assume !(1 == ~T3_E~0); 653554#L872-1 assume !(1 == ~T4_E~0); 653553#L877-1 assume !(1 == ~T5_E~0); 653552#L882-1 assume !(1 == ~T6_E~0); 653551#L887-1 assume !(1 == ~T7_E~0); 653550#L892-1 assume !(1 == ~E_M~0); 653549#L897-1 assume !(1 == ~E_1~0); 652940#L902-1 assume !(1 == ~E_2~0); 652941#L907-1 assume 1 == ~E_3~0;~E_3~0 := 2; 653253#L912-1 assume !(1 == ~E_4~0); 653244#L917-1 assume !(1 == ~E_5~0); 653245#L922-1 assume !(1 == ~E_6~0); 653461#L927-1 assume !(1 == ~E_7~0); 653530#L1178-1 [2021-11-09 09:35:18,485 INFO L793 eck$LassoCheckResult]: Loop: 653530#L1178-1 assume !false; 657919#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 657914#L744 assume !false; 657913#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 657857#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 657846#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 657840#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 657443#L641 assume !(0 != eval_~tmp~0); 657444#L759 start_simulation_~kernel_st~0 := 2; 688581#L529-1 start_simulation_~kernel_st~0 := 3; 688168#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 688163#L769-4 assume !(0 == ~T1_E~0); 688162#L774-3 assume !(0 == ~T2_E~0); 688053#L779-3 assume !(0 == ~T3_E~0); 688052#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 688044#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 688042#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 688040#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 688039#L804-3 assume !(0 == ~E_M~0); 688038#L809-3 assume !(0 == ~E_1~0); 688036#L814-3 assume !(0 == ~E_2~0); 688035#L819-3 assume !(0 == ~E_3~0); 658459#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 658457#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 658454#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 658451#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 658448#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 658445#L376-27 assume !(1 == ~m_pc~0); 658442#L376-29 is_master_triggered_~__retres1~0 := 0; 658439#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 658436#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 658433#L955-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 658429#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 658425#L395-27 assume !(1 == ~t1_pc~0); 658421#L395-29 is_transmit1_triggered_~__retres1~1 := 0; 658417#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 658413#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 658409#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 658405#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 658401#L414-27 assume !(1 == ~t2_pc~0); 658396#L414-29 is_transmit2_triggered_~__retres1~2 := 0; 658391#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 658392#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 688993#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 688987#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 688980#L433-27 assume !(1 == ~t3_pc~0); 688972#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 688964#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 658363#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 658358#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 658359#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 688051#L452-27 assume !(1 == ~t4_pc~0); 688043#L452-29 is_transmit4_triggered_~__retres1~4 := 0; 688041#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 658337#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 658338#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 688037#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 658322#L471-27 assume !(1 == ~t5_pc~0); 658314#L471-29 is_transmit5_triggered_~__retres1~5 := 0; 658305#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 658306#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 658286#L995-27 assume !(0 != activate_threads_~tmp___4~0); 658285#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 658273#L490-27 assume !(1 == ~t6_pc~0); 658274#L490-29 is_transmit6_triggered_~__retres1~6 := 0; 658259#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 658260#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 658245#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 658246#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 679792#L509-27 assume !(1 == ~t7_pc~0); 679794#L509-29 is_transmit7_triggered_~__retres1~7 := 0; 679787#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 679788#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 679783#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 679784#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 679779#L857-3 assume !(1 == ~T1_E~0); 679780#L862-3 assume !(1 == ~T2_E~0); 679775#L867-3 assume !(1 == ~T3_E~0); 679776#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 679771#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 679772#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 679767#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 679768#L892-3 assume !(1 == ~E_M~0); 679763#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 679764#L902-3 assume !(1 == ~E_2~0); 658153#L907-3 assume !(1 == ~E_3~0); 658154#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 658141#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 658142#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 658130#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 658131#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 658121#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 658110#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 658105#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 658106#L1197 assume !(0 == start_simulation_~tmp~3); 658094#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 658095#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 657966#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 657967#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 657951#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 657952#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 657940#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 657941#L1210 assume !(0 != start_simulation_~tmp___0~1); 653530#L1178-1 [2021-11-09 09:35:18,485 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:18,486 INFO L85 PathProgramCache]: Analyzing trace with hash 812836125, now seen corresponding path program 1 times [2021-11-09 09:35:18,486 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:18,486 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [411667844] [2021-11-09 09:35:18,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:18,486 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:18,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:18,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:18,511 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:18,511 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [411667844] [2021-11-09 09:35:18,511 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [411667844] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:18,512 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:18,512 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-09 09:35:18,512 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [781630826] [2021-11-09 09:35:18,512 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:18,513 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:18,513 INFO L85 PathProgramCache]: Analyzing trace with hash 827937104, now seen corresponding path program 1 times [2021-11-09 09:35:18,513 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:18,513 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1050160536] [2021-11-09 09:35:18,513 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:18,514 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:18,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:18,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:18,545 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:18,546 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1050160536] [2021-11-09 09:35:18,546 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1050160536] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:18,546 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:18,546 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-09 09:35:18,546 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [560998343] [2021-11-09 09:35:18,547 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:18,547 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:18,547 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:35:18,547 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:35:18,548 INFO L87 Difference]: Start difference. First operand 43633 states and 60228 transitions. cyclomatic complexity: 16611 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 2 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:18,682 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:18,682 INFO L93 Difference]: Finished difference Result 27992 states and 38538 transitions. [2021-11-09 09:35:18,682 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:35:18,683 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 27992 states and 38538 transitions. [2021-11-09 09:35:18,796 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27771 [2021-11-09 09:35:18,865 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 27992 states to 27992 states and 38538 transitions. [2021-11-09 09:35:18,865 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27992 [2021-11-09 09:35:18,879 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27992 [2021-11-09 09:35:18,879 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27992 states and 38538 transitions. [2021-11-09 09:35:18,893 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:18,893 INFO L681 BuchiCegarLoop]: Abstraction has 27992 states and 38538 transitions. [2021-11-09 09:35:18,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27992 states and 38538 transitions. [2021-11-09 09:35:19,406 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27992 to 27992. [2021-11-09 09:35:19,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27992 states, 27992 states have (on average 1.376750500142898) internal successors, (38538), 27991 states have internal predecessors, (38538), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:19,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27992 states to 27992 states and 38538 transitions. [2021-11-09 09:35:19,471 INFO L704 BuchiCegarLoop]: Abstraction has 27992 states and 38538 transitions. [2021-11-09 09:35:19,471 INFO L587 BuchiCegarLoop]: Abstraction has 27992 states and 38538 transitions. [2021-11-09 09:35:19,471 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-09 09:35:19,471 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27992 states and 38538 transitions. [2021-11-09 09:35:19,537 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27771 [2021-11-09 09:35:19,537 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:19,537 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:19,538 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:19,539 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:19,539 INFO L791 eck$LassoCheckResult]: Stem: 724854#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 724855#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 724719#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 724663#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 724664#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 724645#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 724477#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 724478#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 724460#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 724461#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 725012#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 724791#L571-1 assume !(0 == ~M_E~0); 724784#L769-1 assume !(0 == ~T1_E~0); 724785#L774-1 assume !(0 == ~T2_E~0); 724848#L779-1 assume !(0 == ~T3_E~0); 724993#L784-1 assume !(0 == ~T4_E~0); 724782#L789-1 assume !(0 == ~T5_E~0); 724783#L794-1 assume !(0 == ~T6_E~0); 724913#L799-1 assume !(0 == ~T7_E~0); 724792#L804-1 assume !(0 == ~E_M~0); 724793#L809-1 assume !(0 == ~E_1~0); 724836#L814-1 assume !(0 == ~E_2~0); 724212#L819-1 assume !(0 == ~E_3~0); 724213#L824-1 assume !(0 == ~E_4~0); 724546#L829-1 assume !(0 == ~E_5~0); 725081#L834-1 assume !(0 == ~E_6~0); 724332#L839-1 assume !(0 == ~E_7~0); 724333#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 724727#L376 assume !(1 == ~m_pc~0); 724723#L376-2 is_master_triggered_~__retres1~0 := 0; 724724#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 725056#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 724289#L955 assume !(0 != activate_threads_~tmp~1); 724290#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 724639#L395 assume !(1 == ~t1_pc~0); 724814#L395-2 is_transmit1_triggered_~__retres1~1 := 0; 724977#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 724218#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 724219#L963 assume !(0 != activate_threads_~tmp___0~0); 724734#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 724735#L414 assume !(1 == ~t2_pc~0); 724335#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 725018#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 724533#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 724534#L971 assume !(0 != activate_threads_~tmp___1~0); 725016#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 724641#L433 assume !(1 == ~t3_pc~0); 724450#L433-2 is_transmit3_triggered_~__retres1~3 := 0; 724451#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 724612#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 724613#L979 assume !(0 != activate_threads_~tmp___2~0); 724305#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 724306#L452 assume !(1 == ~t4_pc~0); 724456#L452-2 is_transmit4_triggered_~__retres1~4 := 0; 724457#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 724768#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 724847#L987 assume !(0 != activate_threads_~tmp___3~0); 724488#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 724489#L471 assume !(1 == ~t5_pc~0); 724892#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 725110#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 724837#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 724838#L995 assume !(0 != activate_threads_~tmp___4~0); 725071#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 725072#L490 assume !(1 == ~t6_pc~0); 724732#L490-2 is_transmit6_triggered_~__retres1~6 := 0; 724733#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 724776#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 724779#L1003 assume !(0 != activate_threads_~tmp___5~0); 724649#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 724618#L509 assume !(1 == ~t7_pc~0); 724619#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 724429#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 724430#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 724493#L1011 assume !(0 != activate_threads_~tmp___6~0); 724494#L1011-2 assume !(1 == ~M_E~0); 725093#L857-1 assume !(1 == ~T1_E~0); 724555#L862-1 assume !(1 == ~T2_E~0); 724556#L867-1 assume !(1 == ~T3_E~0); 724561#L872-1 assume !(1 == ~T4_E~0); 724642#L877-1 assume !(1 == ~T5_E~0); 724866#L882-1 assume !(1 == ~T6_E~0); 725039#L887-1 assume !(1 == ~T7_E~0); 724935#L892-1 assume !(1 == ~E_M~0); 724936#L897-1 assume !(1 == ~E_1~0); 724573#L902-1 assume !(1 == ~E_2~0); 724574#L907-1 assume !(1 == ~E_3~0); 724886#L912-1 assume !(1 == ~E_4~0); 724874#L917-1 assume !(1 == ~E_5~0); 724875#L922-1 assume !(1 == ~E_6~0); 725085#L927-1 assume !(1 == ~E_7~0); 725148#L1178-1 [2021-11-09 09:35:19,539 INFO L793 eck$LassoCheckResult]: Loop: 725148#L1178-1 assume !false; 749126#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 749120#L744 assume !false; 749118#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 740090#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 740081#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 740078#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 740074#L641 assume !(0 != eval_~tmp~0); 740075#L759 start_simulation_~kernel_st~0 := 2; 749319#L529-1 start_simulation_~kernel_st~0 := 3; 749317#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 749315#L769-4 assume !(0 == ~T1_E~0); 749313#L774-3 assume !(0 == ~T2_E~0); 749311#L779-3 assume !(0 == ~T3_E~0); 749309#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 749307#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 749305#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 749303#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 749301#L804-3 assume !(0 == ~E_M~0); 749299#L809-3 assume !(0 == ~E_1~0); 749297#L814-3 assume !(0 == ~E_2~0); 749295#L819-3 assume !(0 == ~E_3~0); 749293#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 749291#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 749289#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 749287#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 749286#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 749282#L376-27 assume !(1 == ~m_pc~0); 749280#L376-29 is_master_triggered_~__retres1~0 := 0; 749278#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 749276#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 749273#L955-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 749271#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 749269#L395-27 assume !(1 == ~t1_pc~0); 749267#L395-29 is_transmit1_triggered_~__retres1~1 := 0; 749265#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 749263#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 749261#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 749259#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 749257#L414-27 assume !(1 == ~t2_pc~0); 749253#L414-29 is_transmit2_triggered_~__retres1~2 := 0; 749251#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 749249#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 749247#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 749246#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 749242#L433-27 assume !(1 == ~t3_pc~0); 749240#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 749239#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 749238#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 749237#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 749235#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 749230#L452-27 assume !(1 == ~t4_pc~0); 749227#L452-29 is_transmit4_triggered_~__retres1~4 := 0; 749226#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 749225#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 749224#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 749223#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 749222#L471-27 assume 1 == ~t5_pc~0; 749221#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 749219#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 749217#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 749214#L995-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 749213#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 749212#L490-27 assume !(1 == ~t6_pc~0); 749211#L490-29 is_transmit6_triggered_~__retres1~6 := 0; 749210#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 749209#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 749208#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 749207#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 749206#L509-27 assume 1 == ~t7_pc~0; 749203#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 749201#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 749199#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 749197#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 749195#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 749192#L857-3 assume !(1 == ~T1_E~0); 749190#L862-3 assume !(1 == ~T2_E~0); 749188#L867-3 assume !(1 == ~T3_E~0); 749186#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 749184#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 749182#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 749180#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 749178#L892-3 assume !(1 == ~E_M~0); 749176#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 749174#L902-3 assume !(1 == ~E_2~0); 749172#L907-3 assume !(1 == ~E_3~0); 749170#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 749168#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 749166#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 749164#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 749162#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 749160#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 749151#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 749149#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 749148#L1197 assume !(0 == start_simulation_~tmp~3); 749146#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 749145#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 749137#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 749135#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 749133#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 749131#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 749129#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 749127#L1210 assume !(0 != start_simulation_~tmp___0~1); 725148#L1178-1 [2021-11-09 09:35:19,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:19,540 INFO L85 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 3 times [2021-11-09 09:35:19,540 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:19,540 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1608139006] [2021-11-09 09:35:19,541 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:19,541 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:19,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:19,550 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:19,560 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:19,587 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:19,588 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:19,588 INFO L85 PathProgramCache]: Analyzing trace with hash -778521644, now seen corresponding path program 1 times [2021-11-09 09:35:19,588 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:19,589 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1012583959] [2021-11-09 09:35:19,589 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:19,589 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:19,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:19,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:19,626 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:19,626 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1012583959] [2021-11-09 09:35:19,627 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1012583959] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:19,627 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:19,627 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-09 09:35:19,627 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1171194926] [2021-11-09 09:35:19,627 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:19,628 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:19,628 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-09 09:35:19,628 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-09 09:35:19,628 INFO L87 Difference]: Start difference. First operand 27992 states and 38538 transitions. cyclomatic complexity: 10562 Second operand has 5 states, 5 states have (on average 20.6) internal successors, (103), 5 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:19,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:19,887 INFO L93 Difference]: Finished difference Result 50444 states and 68697 transitions. [2021-11-09 09:35:19,888 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-11-09 09:35:19,888 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 50444 states and 68697 transitions. [2021-11-09 09:35:20,074 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 50099 [2021-11-09 09:35:20,182 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 50444 states to 50444 states and 68697 transitions. [2021-11-09 09:35:20,182 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 50444 [2021-11-09 09:35:20,205 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 50444 [2021-11-09 09:35:20,205 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50444 states and 68697 transitions. [2021-11-09 09:35:20,225 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:20,225 INFO L681 BuchiCegarLoop]: Abstraction has 50444 states and 68697 transitions. [2021-11-09 09:35:20,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50444 states and 68697 transitions. [2021-11-09 09:35:20,906 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50444 to 28154. [2021-11-09 09:35:20,927 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28154 states, 28154 states have (on average 1.3745826525538112) internal successors, (38700), 28153 states have internal predecessors, (38700), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:20,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28154 states to 28154 states and 38700 transitions. [2021-11-09 09:35:20,975 INFO L704 BuchiCegarLoop]: Abstraction has 28154 states and 38700 transitions. [2021-11-09 09:35:20,975 INFO L587 BuchiCegarLoop]: Abstraction has 28154 states and 38700 transitions. [2021-11-09 09:35:20,975 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-11-09 09:35:20,975 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28154 states and 38700 transitions. [2021-11-09 09:35:21,038 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27933 [2021-11-09 09:35:21,038 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:21,039 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:21,040 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:21,040 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:21,040 INFO L791 eck$LassoCheckResult]: Stem: 803306#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 803307#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 803166#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 803114#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 803115#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 803096#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 802931#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 802932#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 802913#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 802914#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 803461#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 803238#L571-1 assume !(0 == ~M_E~0); 803231#L769-1 assume !(0 == ~T1_E~0); 803232#L774-1 assume !(0 == ~T2_E~0); 803299#L779-1 assume !(0 == ~T3_E~0); 803442#L784-1 assume !(0 == ~T4_E~0); 803229#L789-1 assume !(0 == ~T5_E~0); 803230#L794-1 assume !(0 == ~T6_E~0); 803366#L799-1 assume !(0 == ~T7_E~0); 803239#L804-1 assume !(0 == ~E_M~0); 803240#L809-1 assume !(0 == ~E_1~0); 803287#L814-1 assume !(0 == ~E_2~0); 802664#L819-1 assume !(0 == ~E_3~0); 802665#L824-1 assume !(0 == ~E_4~0); 803000#L829-1 assume !(0 == ~E_5~0); 803538#L834-1 assume !(0 == ~E_6~0); 802785#L839-1 assume !(0 == ~E_7~0); 802786#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 803174#L376 assume !(1 == ~m_pc~0); 803170#L376-2 is_master_triggered_~__retres1~0 := 0; 803171#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 803504#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 802742#L955 assume !(0 != activate_threads_~tmp~1); 802743#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 803090#L395 assume !(1 == ~t1_pc~0); 803264#L395-2 is_transmit1_triggered_~__retres1~1 := 0; 803424#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 802670#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 802671#L963 assume !(0 != activate_threads_~tmp___0~0); 803179#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 803180#L414 assume !(1 == ~t2_pc~0); 802788#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 803465#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 802986#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 802987#L971 assume !(0 != activate_threads_~tmp___1~0); 803463#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 803092#L433 assume !(1 == ~t3_pc~0); 802903#L433-2 is_transmit3_triggered_~__retres1~3 := 0; 802904#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 803065#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 803066#L979 assume !(0 != activate_threads_~tmp___2~0); 802758#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 802759#L452 assume !(1 == ~t4_pc~0); 802909#L452-2 is_transmit4_triggered_~__retres1~4 := 0; 802910#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 803215#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 803298#L987 assume !(0 != activate_threads_~tmp___3~0); 802942#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 802943#L471 assume !(1 == ~t5_pc~0); 803347#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 803574#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 803288#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 803289#L995 assume !(0 != activate_threads_~tmp___4~0); 803521#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 803522#L490 assume !(1 == ~t6_pc~0); 803177#L490-2 is_transmit6_triggered_~__retres1~6 := 0; 803178#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 803221#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 803224#L1003 assume !(0 != activate_threads_~tmp___5~0); 803102#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 803071#L509 assume !(1 == ~t7_pc~0); 803072#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 802887#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 802888#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 802947#L1011 assume !(0 != activate_threads_~tmp___6~0); 802948#L1011-2 assume !(1 == ~M_E~0); 803554#L857-1 assume !(1 == ~T1_E~0); 803010#L862-1 assume !(1 == ~T2_E~0); 803011#L867-1 assume !(1 == ~T3_E~0); 803016#L872-1 assume !(1 == ~T4_E~0); 803093#L877-1 assume !(1 == ~T5_E~0); 803319#L882-1 assume !(1 == ~T6_E~0); 803487#L887-1 assume !(1 == ~T7_E~0); 803386#L892-1 assume !(1 == ~E_M~0); 803387#L897-1 assume !(1 == ~E_1~0); 803027#L902-1 assume !(1 == ~E_2~0); 803028#L907-1 assume !(1 == ~E_3~0); 803339#L912-1 assume !(1 == ~E_4~0); 803327#L917-1 assume !(1 == ~E_5~0); 803328#L922-1 assume !(1 == ~E_6~0); 803542#L927-1 assume !(1 == ~E_7~0); 803609#L1178-1 [2021-11-09 09:35:21,040 INFO L793 eck$LassoCheckResult]: Loop: 803609#L1178-1 assume !false; 818975#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 818897#L744 assume !false; 818894#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 818890#L584 assume !(0 == ~m_st~0); 818891#L588 assume !(0 == ~t1_st~0); 818886#L592 assume !(0 == ~t2_st~0); 818887#L596 assume !(0 == ~t3_st~0); 818889#L600 assume !(0 == ~t4_st~0); 818884#L604 assume !(0 == ~t5_st~0); 818885#L608 assume !(0 == ~t6_st~0); 818888#L612 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 818892#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 809700#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 809701#L641 assume !(0 != eval_~tmp~0); 819132#L759 start_simulation_~kernel_st~0 := 2; 819131#L529-1 start_simulation_~kernel_st~0 := 3; 819130#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 819129#L769-4 assume !(0 == ~T1_E~0); 819128#L774-3 assume !(0 == ~T2_E~0); 819127#L779-3 assume !(0 == ~T3_E~0); 819126#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 819125#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 819124#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 819123#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 819122#L804-3 assume !(0 == ~E_M~0); 819121#L809-3 assume !(0 == ~E_1~0); 819120#L814-3 assume !(0 == ~E_2~0); 819119#L819-3 assume !(0 == ~E_3~0); 819118#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 819117#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 819116#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 819115#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 819114#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 819113#L376-27 assume !(1 == ~m_pc~0); 819112#L376-29 is_master_triggered_~__retres1~0 := 0; 819111#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 819110#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 819109#L955-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 819108#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 819107#L395-27 assume !(1 == ~t1_pc~0); 819106#L395-29 is_transmit1_triggered_~__retres1~1 := 0; 819105#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 819104#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 819103#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 819102#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 819101#L414-27 assume !(1 == ~t2_pc~0); 819099#L414-29 is_transmit2_triggered_~__retres1~2 := 0; 819098#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 819097#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 819096#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 819095#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 819094#L433-27 assume !(1 == ~t3_pc~0); 819093#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 819092#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 819091#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 819090#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 819089#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 819088#L452-27 assume !(1 == ~t4_pc~0); 819087#L452-29 is_transmit4_triggered_~__retres1~4 := 0; 819086#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 819085#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 819084#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 819083#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 819082#L471-27 assume 1 == ~t5_pc~0; 819080#L472-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 819078#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 819076#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 819074#L995-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 819073#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 819072#L490-27 assume !(1 == ~t6_pc~0); 819071#L490-29 is_transmit6_triggered_~__retres1~6 := 0; 819070#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 819069#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 819068#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 819067#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 819066#L509-27 assume 1 == ~t7_pc~0; 819064#L510-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 819063#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 819062#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 819061#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 819060#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 819059#L857-3 assume !(1 == ~T1_E~0); 819058#L862-3 assume !(1 == ~T2_E~0); 819057#L867-3 assume !(1 == ~T3_E~0); 819056#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 819055#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 819054#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 819053#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 819052#L892-3 assume !(1 == ~E_M~0); 819051#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 819050#L902-3 assume !(1 == ~E_2~0); 819049#L907-3 assume !(1 == ~E_3~0); 819048#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 819047#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 819046#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 819045#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 819044#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 819043#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 819032#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 819028#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 819023#L1197 assume !(0 == start_simulation_~tmp~3); 819019#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 819018#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 819007#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 819004#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 819000#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 818997#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 818992#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 818987#L1210 assume !(0 != start_simulation_~tmp___0~1); 803609#L1178-1 [2021-11-09 09:35:21,041 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:21,041 INFO L85 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 4 times [2021-11-09 09:35:21,041 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:21,041 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [834104747] [2021-11-09 09:35:21,042 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:21,042 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:21,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:21,062 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:21,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:21,101 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:21,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:21,102 INFO L85 PathProgramCache]: Analyzing trace with hash -768606392, now seen corresponding path program 1 times [2021-11-09 09:35:21,103 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:21,104 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [818178078] [2021-11-09 09:35:21,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:21,104 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:21,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:21,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:21,169 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:21,169 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [818178078] [2021-11-09 09:35:21,169 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [818178078] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:21,169 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:21,169 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-09 09:35:21,170 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1504661789] [2021-11-09 09:35:21,170 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:21,170 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:21,170 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-09 09:35:21,171 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-09 09:35:21,171 INFO L87 Difference]: Start difference. First operand 28154 states and 38700 transitions. cyclomatic complexity: 10562 Second operand has 5 states, 5 states have (on average 22.0) internal successors, (110), 5 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:21,410 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:21,411 INFO L93 Difference]: Finished difference Result 32554 states and 44780 transitions. [2021-11-09 09:35:21,411 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-09 09:35:21,411 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32554 states and 44780 transitions. [2021-11-09 09:35:21,512 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 32301 [2021-11-09 09:35:21,577 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32554 states to 32554 states and 44780 transitions. [2021-11-09 09:35:21,577 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32554 [2021-11-09 09:35:21,592 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32554 [2021-11-09 09:35:21,592 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32554 states and 44780 transitions. [2021-11-09 09:35:21,605 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:21,605 INFO L681 BuchiCegarLoop]: Abstraction has 32554 states and 44780 transitions. [2021-11-09 09:35:21,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32554 states and 44780 transitions. [2021-11-09 09:35:21,800 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32554 to 28202. [2021-11-09 09:35:21,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28202 states, 28202 states have (on average 1.3614637259768811) internal successors, (38396), 28201 states have internal predecessors, (38396), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:21,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28202 states to 28202 states and 38396 transitions. [2021-11-09 09:35:21,860 INFO L704 BuchiCegarLoop]: Abstraction has 28202 states and 38396 transitions. [2021-11-09 09:35:21,861 INFO L587 BuchiCegarLoop]: Abstraction has 28202 states and 38396 transitions. [2021-11-09 09:35:21,861 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-11-09 09:35:21,861 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28202 states and 38396 transitions. [2021-11-09 09:35:21,923 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 27981 [2021-11-09 09:35:21,923 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:21,923 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:21,924 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:21,924 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:21,925 INFO L791 eck$LassoCheckResult]: Stem: 864084#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 864085#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 863931#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 863860#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 863861#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 863842#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 863659#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 863660#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 863639#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 863640#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 864280#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 864016#L571-1 assume !(0 == ~M_E~0); 864011#L769-1 assume !(0 == ~T1_E~0); 864012#L774-1 assume !(0 == ~T2_E~0); 864075#L779-1 assume !(0 == ~T3_E~0); 864260#L784-1 assume !(0 == ~T4_E~0); 864009#L789-1 assume !(0 == ~T5_E~0); 864010#L794-1 assume !(0 == ~T6_E~0); 864149#L799-1 assume !(0 == ~T7_E~0); 864017#L804-1 assume !(0 == ~E_M~0); 864018#L809-1 assume !(0 == ~E_1~0); 864061#L814-1 assume !(0 == ~E_2~0); 863387#L819-1 assume !(0 == ~E_3~0); 863388#L824-1 assume !(0 == ~E_4~0); 863735#L829-1 assume !(0 == ~E_5~0); 864381#L834-1 assume !(0 == ~E_6~0); 863511#L839-1 assume !(0 == ~E_7~0); 863512#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 863940#L376 assume !(1 == ~m_pc~0); 863936#L376-2 is_master_triggered_~__retres1~0 := 0; 863937#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 864337#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 863463#L955 assume !(0 != activate_threads_~tmp~1); 863464#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 863834#L395 assume !(1 == ~t1_pc~0); 864039#L395-2 is_transmit1_triggered_~__retres1~1 := 0; 864233#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 863391#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 863392#L963 assume !(0 != activate_threads_~tmp___0~0); 863948#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 863949#L414 assume !(1 == ~t2_pc~0); 863514#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 864287#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 863719#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 863720#L971 assume !(0 != activate_threads_~tmp___1~0); 864285#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 863838#L433 assume !(1 == ~t3_pc~0); 863629#L433-2 is_transmit3_triggered_~__retres1~3 := 0; 863630#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 863806#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 863807#L979 assume !(0 != activate_threads_~tmp___2~0); 863481#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 863482#L452 assume !(1 == ~t4_pc~0); 863635#L452-2 is_transmit4_triggered_~__retres1~4 := 0; 863636#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 863995#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 864074#L987 assume !(0 != activate_threads_~tmp___3~0); 863670#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 863671#L471 assume !(1 == ~t5_pc~0); 864130#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 864437#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 864062#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 864063#L995 assume !(0 != activate_threads_~tmp___4~0); 864362#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 864363#L490 assume !(1 == ~t6_pc~0); 863945#L490-2 is_transmit6_triggered_~__retres1~6 := 0; 863946#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 864002#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 864005#L1003 assume !(0 != activate_threads_~tmp___5~0); 863848#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 863811#L509 assume !(1 == ~t7_pc~0); 863812#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 863614#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 863615#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 863675#L1011 assume !(0 != activate_threads_~tmp___6~0); 863676#L1011-2 assume !(1 == ~M_E~0); 864407#L857-1 assume !(1 == ~T1_E~0); 863744#L862-1 assume !(1 == ~T2_E~0); 863745#L867-1 assume !(1 == ~T3_E~0); 863751#L872-1 assume !(1 == ~T4_E~0); 863839#L877-1 assume !(1 == ~T5_E~0); 864097#L882-1 assume !(1 == ~T6_E~0); 864323#L887-1 assume !(1 == ~T7_E~0); 864175#L892-1 assume !(1 == ~E_M~0); 864176#L897-1 assume !(1 == ~E_1~0); 863763#L902-1 assume !(1 == ~E_2~0); 863764#L907-1 assume !(1 == ~E_3~0); 864121#L912-1 assume !(1 == ~E_4~0); 864107#L917-1 assume !(1 == ~E_5~0); 864108#L922-1 assume !(1 == ~E_6~0); 864391#L927-1 assume !(1 == ~E_7~0); 864500#L1178-1 [2021-11-09 09:35:21,925 INFO L793 eck$LassoCheckResult]: Loop: 864500#L1178-1 assume !false; 875075#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 875064#L744 assume !false; 875065#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 875059#L584 assume !(0 == ~m_st~0); 875060#L588 assume !(0 == ~t1_st~0); 875055#L592 assume !(0 == ~t2_st~0); 875056#L596 assume !(0 == ~t3_st~0); 875058#L600 assume !(0 == ~t4_st~0); 875052#L604 assume !(0 == ~t5_st~0); 875054#L608 assume !(0 == ~t6_st~0); 875057#L612 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 875061#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 875046#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 875047#L641 assume !(0 != eval_~tmp~0); 875491#L759 start_simulation_~kernel_st~0 := 2; 875492#L529-1 start_simulation_~kernel_st~0 := 3; 875487#L769-2 assume 0 == ~M_E~0;~M_E~0 := 1; 875488#L769-4 assume !(0 == ~T1_E~0); 875483#L774-3 assume !(0 == ~T2_E~0); 875484#L779-3 assume !(0 == ~T3_E~0); 875479#L784-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 875480#L789-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 875475#L794-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 875476#L799-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 875471#L804-3 assume !(0 == ~E_M~0); 875472#L809-3 assume !(0 == ~E_1~0); 875467#L814-3 assume !(0 == ~E_2~0); 875468#L819-3 assume !(0 == ~E_3~0); 875463#L824-3 assume 0 == ~E_4~0;~E_4~0 := 1; 875464#L829-3 assume 0 == ~E_5~0;~E_5~0 := 1; 875459#L834-3 assume 0 == ~E_6~0;~E_6~0 := 1; 875460#L839-3 assume 0 == ~E_7~0;~E_7~0 := 1; 875455#L844-3 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 875456#L376-27 assume !(1 == ~m_pc~0); 875451#L376-29 is_master_triggered_~__retres1~0 := 0; 875452#L387-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 875447#L388-9 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 875448#L955-27 assume !(0 != activate_threads_~tmp~1); 875441#L955-29 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 875442#L395-27 assume !(1 == ~t1_pc~0); 875434#L395-29 is_transmit1_triggered_~__retres1~1 := 0; 875435#L406-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 875426#L407-9 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 875427#L963-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 875418#L963-29 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 875419#L414-27 assume !(1 == ~t2_pc~0); 875410#L414-29 is_transmit2_triggered_~__retres1~2 := 0; 875411#L425-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 875402#L426-9 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 875403#L971-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 875394#L971-29 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 875395#L433-27 assume !(1 == ~t3_pc~0); 875387#L433-29 is_transmit3_triggered_~__retres1~3 := 0; 875388#L444-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 875381#L445-9 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 875382#L979-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 875375#L979-29 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 875376#L452-27 assume !(1 == ~t4_pc~0); 875369#L452-29 is_transmit4_triggered_~__retres1~4 := 0; 875370#L463-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 875363#L464-9 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 875364#L987-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 875357#L987-29 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 875358#L471-27 assume !(1 == ~t5_pc~0); 875349#L471-29 is_transmit5_triggered_~__retres1~5 := 0; 875350#L482-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 875337#L483-9 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 875338#L995-27 assume !(0 != activate_threads_~tmp___4~0); 875326#L995-29 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 875327#L490-27 assume !(1 == ~t6_pc~0); 875317#L490-29 is_transmit6_triggered_~__retres1~6 := 0; 875318#L501-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 875307#L502-9 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 875308#L1003-27 assume !(0 != activate_threads_~tmp___5~0); 875298#L1003-29 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 875299#L509-27 assume !(1 == ~t7_pc~0); 875289#L509-29 is_transmit7_triggered_~__retres1~7 := 0; 875288#L520-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 875278#L521-9 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 875279#L1011-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 875268#L1011-29 assume 1 == ~M_E~0;~M_E~0 := 2; 875269#L857-3 assume !(1 == ~T1_E~0); 875257#L862-3 assume !(1 == ~T2_E~0); 875258#L867-3 assume !(1 == ~T3_E~0); 875247#L872-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 875248#L877-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 875237#L882-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 875238#L887-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 875225#L892-3 assume !(1 == ~E_M~0); 875226#L897-3 assume 1 == ~E_1~0;~E_1~0 := 2; 875212#L902-3 assume !(1 == ~E_2~0); 875213#L907-3 assume !(1 == ~E_3~0); 875200#L912-3 assume 1 == ~E_4~0;~E_4~0 := 2; 875201#L917-3 assume 1 == ~E_5~0;~E_5~0 := 2; 875188#L922-3 assume 1 == ~E_6~0;~E_6~0 := 2; 875189#L927-3 assume 1 == ~E_7~0;~E_7~0 := 2; 875174#L932-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 875175#L584-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 875123#L626-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 875124#L627-1 start_simulation_#t~ret26 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret26;havoc start_simulation_#t~ret26; 875113#L1197 assume !(0 == start_simulation_~tmp~3); 875109#L1197-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret25, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 875110#L584-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 880586#L626-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 880585#L627-2 stop_simulation_#t~ret25 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret25;havoc stop_simulation_#t~ret25; 880584#L1152 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 880583#L1159 stop_simulation_#res := stop_simulation_~__retres2~0; 880582#L1160 start_simulation_#t~ret27 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret27;havoc start_simulation_#t~ret27; 880581#L1210 assume !(0 != start_simulation_~tmp___0~1); 864500#L1178-1 [2021-11-09 09:35:21,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:21,926 INFO L85 PathProgramCache]: Analyzing trace with hash 322056993, now seen corresponding path program 5 times [2021-11-09 09:35:21,926 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:21,926 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [522548260] [2021-11-09 09:35:21,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:21,926 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:21,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:21,939 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:21,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:21,980 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:21,981 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:21,981 INFO L85 PathProgramCache]: Analyzing trace with hash 914753154, now seen corresponding path program 1 times [2021-11-09 09:35:21,981 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:21,981 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [583801259] [2021-11-09 09:35:21,982 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:21,982 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:21,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:22,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:22,015 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:22,015 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [583801259] [2021-11-09 09:35:22,016 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [583801259] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:22,016 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:22,016 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:22,016 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [770527717] [2021-11-09 09:35:22,018 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 09:35:22,018 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:22,019 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:35:22,019 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:35:22,019 INFO L87 Difference]: Start difference. First operand 28202 states and 38396 transitions. cyclomatic complexity: 10210 Second operand has 3 states, 3 states have (on average 36.666666666666664) internal successors, (110), 3 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:22,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:22,389 INFO L93 Difference]: Finished difference Result 44361 states and 59551 transitions. [2021-11-09 09:35:22,389 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:35:22,389 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44361 states and 59551 transitions. [2021-11-09 09:35:22,536 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 44084 [2021-11-09 09:35:22,621 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44361 states to 44361 states and 59551 transitions. [2021-11-09 09:35:22,621 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44361 [2021-11-09 09:35:22,641 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44361 [2021-11-09 09:35:22,641 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44361 states and 59551 transitions. [2021-11-09 09:35:22,657 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:22,657 INFO L681 BuchiCegarLoop]: Abstraction has 44361 states and 59551 transitions. [2021-11-09 09:35:22,675 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44361 states and 59551 transitions. [2021-11-09 09:35:22,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44361 to 44361. [2021-11-09 09:35:22,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44361 states, 44361 states have (on average 1.3424178895877008) internal successors, (59551), 44360 states have internal predecessors, (59551), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:22,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44361 states to 44361 states and 59551 transitions. [2021-11-09 09:35:22,996 INFO L704 BuchiCegarLoop]: Abstraction has 44361 states and 59551 transitions. [2021-11-09 09:35:22,997 INFO L587 BuchiCegarLoop]: Abstraction has 44361 states and 59551 transitions. [2021-11-09 09:35:22,997 INFO L425 BuchiCegarLoop]: ======== Iteration 25============ [2021-11-09 09:35:22,997 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44361 states and 59551 transitions. [2021-11-09 09:35:23,099 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 44084 [2021-11-09 09:35:23,099 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:23,099 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:23,100 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:23,100 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:23,101 INFO L791 eck$LassoCheckResult]: Stem: 936587#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 936588#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 936456#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 936403#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 936404#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 936382#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 936218#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 936219#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 936200#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 936201#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 936741#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 936525#L571-1 assume !(0 == ~M_E~0); 936522#L769-1 assume !(0 == ~T1_E~0); 936523#L774-1 assume !(0 == ~T2_E~0); 936580#L779-1 assume !(0 == ~T3_E~0); 936723#L784-1 assume !(0 == ~T4_E~0); 936518#L789-1 assume !(0 == ~T5_E~0); 936519#L794-1 assume !(0 == ~T6_E~0); 936647#L799-1 assume !(0 == ~T7_E~0); 936526#L804-1 assume !(0 == ~E_M~0); 936527#L809-1 assume !(0 == ~E_1~0); 936568#L814-1 assume !(0 == ~E_2~0); 935958#L819-1 assume !(0 == ~E_3~0); 935959#L824-1 assume !(0 == ~E_4~0); 936285#L829-1 assume !(0 == ~E_5~0); 936820#L834-1 assume !(0 == ~E_6~0); 936074#L839-1 assume !(0 == ~E_7~0); 936075#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 936464#L376 assume !(1 == ~m_pc~0); 936460#L376-2 is_master_triggered_~__retres1~0 := 0; 936461#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 936784#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 936031#L955 assume !(0 != activate_threads_~tmp~1); 936032#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 936376#L395 assume !(1 == ~t1_pc~0); 936546#L395-2 is_transmit1_triggered_~__retres1~1 := 0; 936710#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 935962#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 935963#L963 assume !(0 != activate_threads_~tmp___0~0); 936470#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 936471#L414 assume !(1 == ~t2_pc~0); 936077#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 936745#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 936272#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 936273#L971 assume !(0 != activate_threads_~tmp___1~0); 936744#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 936378#L433 assume !(1 == ~t3_pc~0); 936190#L433-2 is_transmit3_triggered_~__retres1~3 := 0; 936191#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 936354#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 936355#L979 assume !(0 != activate_threads_~tmp___2~0); 936047#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 936048#L452 assume !(1 == ~t4_pc~0); 936196#L452-2 is_transmit4_triggered_~__retres1~4 := 0; 936197#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 936504#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 936579#L987 assume !(0 != activate_threads_~tmp___3~0); 936229#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 936230#L471 assume !(1 == ~t5_pc~0); 936627#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 936856#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 936569#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 936570#L995 assume !(0 != activate_threads_~tmp___4~0); 936802#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 936803#L490 assume !(1 == ~t6_pc~0); 936468#L490-2 is_transmit6_triggered_~__retres1~6 := 0; 936469#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 936512#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 936516#L1003 assume !(0 != activate_threads_~tmp___5~0); 936389#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 936358#L509 assume !(1 == ~t7_pc~0); 936359#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 936176#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 936177#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 936234#L1011 assume !(0 != activate_threads_~tmp___6~0); 936235#L1011-2 assume !(1 == ~M_E~0); 936836#L857-1 assume !(1 == ~T1_E~0); 936294#L862-1 assume !(1 == ~T2_E~0); 936295#L867-1 assume !(1 == ~T3_E~0); 936300#L872-1 assume !(1 == ~T4_E~0); 936379#L877-1 assume !(1 == ~T5_E~0); 936598#L882-1 assume !(1 == ~T6_E~0); 936774#L887-1 assume !(1 == ~T7_E~0); 936667#L892-1 assume !(1 == ~E_M~0); 936668#L897-1 assume !(1 == ~E_1~0); 936311#L902-1 assume !(1 == ~E_2~0); 936312#L907-1 assume !(1 == ~E_3~0); 936619#L912-1 assume !(1 == ~E_4~0); 936606#L917-1 assume !(1 == ~E_5~0); 936607#L922-1 assume !(1 == ~E_6~0); 936824#L927-1 assume !(1 == ~E_7~0); 936889#L1178-1 assume !false; 939275#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 939276#L744 [2021-11-09 09:35:23,101 INFO L793 eck$LassoCheckResult]: Loop: 939276#L744 assume !false; 952412#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 952409#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 952407#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 952405#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 952403#L641 assume 0 != eval_~tmp~0; 952400#L641-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 952398#L649 assume !(0 != eval_~tmp_ndt_1~0); 952393#L646 assume !(0 == ~t1_st~0); 952339#L660 assume !(0 == ~t2_st~0); 952334#L674 assume !(0 == ~t3_st~0); 952154#L688 assume !(0 == ~t4_st~0); 952149#L702 assume !(0 == ~t5_st~0); 939280#L716 assume !(0 == ~t6_st~0); 939278#L730 assume !(0 == ~t7_st~0); 939276#L744 [2021-11-09 09:35:23,101 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:23,101 INFO L85 PathProgramCache]: Analyzing trace with hash 259139107, now seen corresponding path program 1 times [2021-11-09 09:35:23,101 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:23,102 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1110288933] [2021-11-09 09:35:23,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:23,102 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:23,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:23,113 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:23,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:23,150 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:23,151 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:23,151 INFO L85 PathProgramCache]: Analyzing trace with hash 1325025558, now seen corresponding path program 1 times [2021-11-09 09:35:23,151 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:23,151 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1251873018] [2021-11-09 09:35:23,151 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:23,151 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:23,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:23,154 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:23,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:23,159 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:23,159 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:23,159 INFO L85 PathProgramCache]: Analyzing trace with hash -912860492, now seen corresponding path program 1 times [2021-11-09 09:35:23,160 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:23,160 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [290428805] [2021-11-09 09:35:23,160 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:23,160 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:23,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:23,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:23,190 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:23,190 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [290428805] [2021-11-09 09:35:23,190 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [290428805] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:23,190 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:23,190 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:23,190 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [884468510] [2021-11-09 09:35:23,310 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:23,311 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:35:23,311 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:35:23,311 INFO L87 Difference]: Start difference. First operand 44361 states and 59551 transitions. cyclomatic complexity: 15220 Second operand has 3 states, 3 states have (on average 36.0) internal successors, (108), 3 states have internal predecessors, (108), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:23,827 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:23,827 INFO L93 Difference]: Finished difference Result 85193 states and 113344 transitions. [2021-11-09 09:35:23,827 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:35:23,827 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 85193 states and 113344 transitions. [2021-11-09 09:35:24,205 INFO L131 ngComponentsAnalysis]: Automaton has 46 accepting balls. 81992 [2021-11-09 09:35:24,385 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 85193 states to 85193 states and 113344 transitions. [2021-11-09 09:35:24,385 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 85193 [2021-11-09 09:35:24,419 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 85193 [2021-11-09 09:35:24,419 INFO L73 IsDeterministic]: Start isDeterministic. Operand 85193 states and 113344 transitions. [2021-11-09 09:35:24,454 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:24,454 INFO L681 BuchiCegarLoop]: Abstraction has 85193 states and 113344 transitions. [2021-11-09 09:35:24,488 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85193 states and 113344 transitions. [2021-11-09 09:35:25,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85193 to 83531. [2021-11-09 09:35:25,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 83531 states, 83531 states have (on average 1.3309789180064886) internal successors, (111178), 83530 states have internal predecessors, (111178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:25,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83531 states to 83531 states and 111178 transitions. [2021-11-09 09:35:25,740 INFO L704 BuchiCegarLoop]: Abstraction has 83531 states and 111178 transitions. [2021-11-09 09:35:25,740 INFO L587 BuchiCegarLoop]: Abstraction has 83531 states and 111178 transitions. [2021-11-09 09:35:25,740 INFO L425 BuchiCegarLoop]: ======== Iteration 26============ [2021-11-09 09:35:25,740 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 83531 states and 111178 transitions. [2021-11-09 09:35:25,932 INFO L131 ngComponentsAnalysis]: Automaton has 46 accepting balls. 80330 [2021-11-09 09:35:25,932 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:25,932 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:25,933 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:25,933 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:25,934 INFO L791 eck$LassoCheckResult]: Stem: 1066169#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1066170#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1066024#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1065969#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 1065970#L536-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 1065949#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1065950#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1066408#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1066409#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1066366#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1066367#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1066102#L571-1 assume !(0 == ~M_E~0); 1066103#L769-1 assume !(0 == ~T1_E~0); 1066161#L774-1 assume !(0 == ~T2_E~0); 1066162#L779-1 assume !(0 == ~T3_E~0); 1066323#L784-1 assume !(0 == ~T4_E~0); 1066324#L789-1 assume !(0 == ~T5_E~0); 1066235#L794-1 assume !(0 == ~T6_E~0); 1066236#L799-1 assume !(0 == ~T7_E~0); 1066104#L804-1 assume !(0 == ~E_M~0); 1066105#L809-1 assume !(0 == ~E_1~0); 1066357#L814-1 assume !(0 == ~E_2~0); 1066358#L819-1 assume !(0 == ~E_3~0); 1065850#L824-1 assume !(0 == ~E_4~0); 1065851#L829-1 assume !(0 == ~E_5~0); 1066438#L834-1 assume !(0 == ~E_6~0); 1066439#L839-1 assume !(0 == ~E_7~0); 1066242#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1066243#L376 assume !(1 == ~m_pc~0); 1066028#L376-2 is_master_triggered_~__retres1~0 := 0; 1066029#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1066406#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1066407#L955 assume !(0 != activate_threads_~tmp~1); 1065939#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1065940#L395 assume !(1 == ~t1_pc~0); 1066303#L395-2 is_transmit1_triggered_~__retres1~1 := 0; 1066304#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1065522#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1065523#L963 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1066377#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1066552#L414 assume !(1 == ~t2_pc~0); 1065639#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 1066545#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1066546#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1066350#L971 assume !(0 != activate_threads_~tmp___1~0); 1066351#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1065943#L433 assume !(1 == ~t3_pc~0); 1065944#L433-2 is_transmit3_triggered_~__retres1~3 := 0; 1066468#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1066469#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1066290#L979 assume !(0 != activate_threads_~tmp___2~0); 1066291#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1066526#L452 assume !(1 == ~t4_pc~0); 1066527#L452-2 is_transmit4_triggered_~__retres1~4 := 0; 1066080#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1066081#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1066464#L987 assume !(0 != activate_threads_~tmp___3~0); 1066465#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1066212#L471 assume !(1 == ~t5_pc~0); 1066213#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 1066489#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1066149#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1066150#L995 assume !(0 != activate_threads_~tmp___4~0); 1066425#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1066426#L490 assume !(1 == ~t6_pc~0); 1066038#L490-2 is_transmit6_triggered_~__retres1~6 := 0; 1066039#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1066087#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1066090#L1003 assume !(0 != activate_threads_~tmp___5~0); 1066091#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1065921#L509 assume !(1 == ~t7_pc~0); 1065922#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 1065738#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1065739#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1065800#L1011 assume !(0 != activate_threads_~tmp___6~0); 1065801#L1011-2 assume !(1 == ~M_E~0); 1066553#L857-1 assume !(1 == ~T1_E~0); 1066554#L862-1 assume !(1 == ~T2_E~0); 1065865#L867-1 assume !(1 == ~T3_E~0); 1065866#L872-1 assume !(1 == ~T4_E~0); 1066180#L877-1 assume !(1 == ~T5_E~0); 1066181#L882-1 assume !(1 == ~T6_E~0); 1066497#L887-1 assume !(1 == ~T7_E~0); 1066498#L892-1 assume !(1 == ~E_M~0); 1066477#L897-1 assume !(1 == ~E_1~0); 1066478#L902-1 assume !(1 == ~E_2~0); 1066280#L907-1 assume !(1 == ~E_3~0); 1066281#L912-1 assume !(1 == ~E_4~0); 1066189#L917-1 assume !(1 == ~E_5~0); 1066190#L922-1 assume !(1 == ~E_6~0); 1066533#L927-1 assume !(1 == ~E_7~0); 1066534#L1178-1 assume !false; 1129991#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 1129992#L744 [2021-11-09 09:35:25,934 INFO L793 eck$LassoCheckResult]: Loop: 1129992#L744 assume !false; 1130588#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1130585#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1130583#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1130581#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1130579#L641 assume 0 != eval_~tmp~0; 1130573#L641-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 1125957#L649 assume !(0 != eval_~tmp_ndt_1~0); 1091488#L646 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 1091485#L663 assume !(0 != eval_~tmp_ndt_2~0); 1091486#L660 assume !(0 == ~t2_st~0); 1098144#L674 assume !(0 == ~t3_st~0); 1098141#L688 assume !(0 == ~t4_st~0); 1124014#L702 assume !(0 == ~t5_st~0); 1130596#L716 assume !(0 == ~t6_st~0); 1130594#L730 assume !(0 == ~t7_st~0); 1129992#L744 [2021-11-09 09:35:25,934 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:25,934 INFO L85 PathProgramCache]: Analyzing trace with hash -1898379869, now seen corresponding path program 1 times [2021-11-09 09:35:25,935 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:25,935 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1520535506] [2021-11-09 09:35:25,935 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:25,935 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:25,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:25,957 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:25,958 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:25,958 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1520535506] [2021-11-09 09:35:25,958 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1520535506] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:25,958 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:25,958 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:25,958 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1028884362] [2021-11-09 09:35:25,959 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 09:35:25,959 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:25,959 INFO L85 PathProgramCache]: Analyzing trace with hash 958375116, now seen corresponding path program 1 times [2021-11-09 09:35:25,959 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:25,959 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308473339] [2021-11-09 09:35:25,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:25,960 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:25,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:25,963 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:25,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:25,968 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:26,109 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:26,109 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:35:26,109 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:35:26,110 INFO L87 Difference]: Start difference. First operand 83531 states and 111178 transitions. cyclomatic complexity: 27693 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:26,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:26,408 INFO L93 Difference]: Finished difference Result 67327 states and 89594 transitions. [2021-11-09 09:35:26,408 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:35:26,408 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67327 states and 89594 transitions. [2021-11-09 09:35:26,681 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 66918 [2021-11-09 09:35:26,825 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67327 states to 67327 states and 89594 transitions. [2021-11-09 09:35:26,825 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67327 [2021-11-09 09:35:26,857 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67327 [2021-11-09 09:35:26,857 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67327 states and 89594 transitions. [2021-11-09 09:35:26,884 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:26,884 INFO L681 BuchiCegarLoop]: Abstraction has 67327 states and 89594 transitions. [2021-11-09 09:35:26,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67327 states and 89594 transitions. [2021-11-09 09:35:27,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67327 to 67327. [2021-11-09 09:35:27,998 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67327 states, 67327 states have (on average 1.330729127987286) internal successors, (89594), 67326 states have internal predecessors, (89594), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:28,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67327 states to 67327 states and 89594 transitions. [2021-11-09 09:35:28,115 INFO L704 BuchiCegarLoop]: Abstraction has 67327 states and 89594 transitions. [2021-11-09 09:35:28,115 INFO L587 BuchiCegarLoop]: Abstraction has 67327 states and 89594 transitions. [2021-11-09 09:35:28,115 INFO L425 BuchiCegarLoop]: ======== Iteration 27============ [2021-11-09 09:35:28,115 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67327 states and 89594 transitions. [2021-11-09 09:35:28,279 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 66918 [2021-11-09 09:35:28,279 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:28,280 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:28,280 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:28,280 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:28,281 INFO L791 eck$LassoCheckResult]: Stem: 1217017#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1217018#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1216885#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1216832#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 1216833#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1216812#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1216645#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1216646#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1216628#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1216629#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1217161#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1216953#L571-1 assume !(0 == ~M_E~0); 1216950#L769-1 assume !(0 == ~T1_E~0); 1216951#L774-1 assume !(0 == ~T2_E~0); 1217010#L779-1 assume !(0 == ~T3_E~0); 1217141#L784-1 assume !(0 == ~T4_E~0); 1216946#L789-1 assume !(0 == ~T5_E~0); 1216947#L794-1 assume !(0 == ~T6_E~0); 1217071#L799-1 assume !(0 == ~T7_E~0); 1216954#L804-1 assume !(0 == ~E_M~0); 1216955#L809-1 assume !(0 == ~E_1~0); 1216997#L814-1 assume !(0 == ~E_2~0); 1216384#L819-1 assume !(0 == ~E_3~0); 1216385#L824-1 assume !(0 == ~E_4~0); 1216713#L829-1 assume !(0 == ~E_5~0); 1217237#L834-1 assume !(0 == ~E_6~0); 1216501#L839-1 assume !(0 == ~E_7~0); 1216502#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1216893#L376 assume !(1 == ~m_pc~0); 1216889#L376-2 is_master_triggered_~__retres1~0 := 0; 1216890#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1217202#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1216459#L955 assume !(0 != activate_threads_~tmp~1); 1216460#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1216806#L395 assume !(1 == ~t1_pc~0); 1216976#L395-2 is_transmit1_triggered_~__retres1~1 := 0; 1217129#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1216388#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1216389#L963 assume !(0 != activate_threads_~tmp___0~0); 1216899#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1216900#L414 assume !(1 == ~t2_pc~0); 1216504#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 1217165#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1216700#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1216701#L971 assume !(0 != activate_threads_~tmp___1~0); 1217164#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1216808#L433 assume !(1 == ~t3_pc~0); 1216618#L433-2 is_transmit3_triggered_~__retres1~3 := 0; 1216619#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1216782#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1216783#L979 assume !(0 != activate_threads_~tmp___2~0); 1216474#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1216475#L452 assume !(1 == ~t4_pc~0); 1216624#L452-2 is_transmit4_triggered_~__retres1~4 := 0; 1216625#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1216931#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1217009#L987 assume !(0 != activate_threads_~tmp___3~0); 1216656#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1216657#L471 assume !(1 == ~t5_pc~0); 1217057#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 1217271#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1216998#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1216999#L995 assume !(0 != activate_threads_~tmp___4~0); 1217221#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1217222#L490 assume !(1 == ~t6_pc~0); 1216896#L490-2 is_transmit6_triggered_~__retres1~6 := 0; 1216897#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1216939#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1216943#L1003 assume !(0 != activate_threads_~tmp___5~0); 1216819#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1216787#L509 assume !(1 == ~t7_pc~0); 1216788#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 1216604#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1216605#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1216661#L1011 assume !(0 != activate_threads_~tmp___6~0); 1216662#L1011-2 assume !(1 == ~M_E~0); 1217251#L857-1 assume !(1 == ~T1_E~0); 1216723#L862-1 assume !(1 == ~T2_E~0); 1216724#L867-1 assume !(1 == ~T3_E~0); 1216730#L872-1 assume !(1 == ~T4_E~0); 1216809#L877-1 assume !(1 == ~T5_E~0); 1217030#L882-1 assume !(1 == ~T6_E~0); 1217189#L887-1 assume !(1 == ~T7_E~0); 1217091#L892-1 assume !(1 == ~E_M~0); 1217092#L897-1 assume !(1 == ~E_1~0); 1216744#L902-1 assume !(1 == ~E_2~0); 1216745#L907-1 assume !(1 == ~E_3~0); 1217050#L912-1 assume !(1 == ~E_4~0); 1217038#L917-1 assume !(1 == ~E_5~0); 1217039#L922-1 assume !(1 == ~E_6~0); 1217241#L927-1 assume !(1 == ~E_7~0); 1217319#L1178-1 assume !false; 1257920#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 1257908#L744 [2021-11-09 09:35:28,281 INFO L793 eck$LassoCheckResult]: Loop: 1257908#L744 assume !false; 1257903#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1256137#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1256138#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1268160#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1268159#L641 assume 0 != eval_~tmp~0; 1268158#L641-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 1268157#L649 assume !(0 != eval_~tmp_ndt_1~0); 1245771#L646 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 1234970#L663 assume !(0 != eval_~tmp_ndt_2~0); 1234971#L660 assume !(0 == ~t2_st~0); 1251121#L674 assume !(0 == ~t3_st~0); 1250123#L688 assume !(0 == ~t4_st~0); 1257931#L702 assume !(0 == ~t5_st~0); 1257926#L716 assume !(0 == ~t6_st~0); 1257919#L730 assume !(0 == ~t7_st~0); 1257908#L744 [2021-11-09 09:35:28,282 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:28,282 INFO L85 PathProgramCache]: Analyzing trace with hash 259139107, now seen corresponding path program 2 times [2021-11-09 09:35:28,282 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:28,282 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [117549161] [2021-11-09 09:35:28,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:28,283 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:28,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:28,292 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:28,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:28,329 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:28,330 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:28,330 INFO L85 PathProgramCache]: Analyzing trace with hash 958375116, now seen corresponding path program 2 times [2021-11-09 09:35:28,330 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:28,330 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [659355031] [2021-11-09 09:35:28,330 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:28,330 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:28,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:28,333 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:28,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:28,337 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:28,338 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:28,338 INFO L85 PathProgramCache]: Analyzing trace with hash 303384302, now seen corresponding path program 1 times [2021-11-09 09:35:28,338 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:28,338 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [303418716] [2021-11-09 09:35:28,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:28,339 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:28,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:28,375 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:28,376 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:28,376 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [303418716] [2021-11-09 09:35:28,376 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [303418716] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:28,376 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:28,376 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:28,376 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [266805706] [2021-11-09 09:35:28,509 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:28,510 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:35:28,510 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:35:28,510 INFO L87 Difference]: Start difference. First operand 67327 states and 89594 transitions. cyclomatic complexity: 22297 Second operand has 3 states, 3 states have (on average 36.333333333333336) internal successors, (109), 3 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:28,939 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:28,940 INFO L93 Difference]: Finished difference Result 128193 states and 169988 transitions. [2021-11-09 09:35:28,940 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:35:28,940 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128193 states and 169988 transitions. [2021-11-09 09:35:30,098 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 127474 [2021-11-09 09:35:30,344 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128193 states to 128193 states and 169988 transitions. [2021-11-09 09:35:30,344 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128193 [2021-11-09 09:35:30,385 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128193 [2021-11-09 09:35:30,385 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128193 states and 169988 transitions. [2021-11-09 09:35:30,423 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:30,423 INFO L681 BuchiCegarLoop]: Abstraction has 128193 states and 169988 transitions. [2021-11-09 09:35:30,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128193 states and 169988 transitions. [2021-11-09 09:35:31,677 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128193 to 121203. [2021-11-09 09:35:31,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 121203 states, 121203 states have (on average 1.3284984695098305) internal successors, (161018), 121202 states have internal predecessors, (161018), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:32,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 121203 states to 121203 states and 161018 transitions. [2021-11-09 09:35:32,046 INFO L704 BuchiCegarLoop]: Abstraction has 121203 states and 161018 transitions. [2021-11-09 09:35:32,046 INFO L587 BuchiCegarLoop]: Abstraction has 121203 states and 161018 transitions. [2021-11-09 09:35:32,046 INFO L425 BuchiCegarLoop]: ======== Iteration 28============ [2021-11-09 09:35:32,046 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 121203 states and 161018 transitions. [2021-11-09 09:35:32,448 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 120484 [2021-11-09 09:35:32,448 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:32,448 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:32,449 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:32,449 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:32,449 INFO L791 eck$LassoCheckResult]: Stem: 1412565#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1412566#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1412427#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1412370#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 1412371#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1412350#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1412173#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1412174#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1412154#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1412155#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1412736#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1412502#L571-1 assume !(0 == ~M_E~0); 1412499#L769-1 assume !(0 == ~T1_E~0); 1412500#L774-1 assume !(0 == ~T2_E~0); 1412557#L779-1 assume !(0 == ~T3_E~0); 1412715#L784-1 assume !(0 == ~T4_E~0); 1412495#L789-1 assume !(0 == ~T5_E~0); 1412496#L794-1 assume !(0 == ~T6_E~0); 1412627#L799-1 assume !(0 == ~T7_E~0); 1412503#L804-1 assume !(0 == ~E_M~0); 1412504#L809-1 assume !(0 == ~E_1~0); 1412546#L814-1 assume !(0 == ~E_2~0); 1411912#L819-1 assume !(0 == ~E_3~0); 1411913#L824-1 assume !(0 == ~E_4~0); 1412244#L829-1 assume !(0 == ~E_5~0); 1412816#L834-1 assume !(0 == ~E_6~0); 1412029#L839-1 assume !(0 == ~E_7~0); 1412030#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1412437#L376 assume !(1 == ~m_pc~0); 1412433#L376-2 is_master_triggered_~__retres1~0 := 0; 1412434#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1412783#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1411987#L955 assume !(0 != activate_threads_~tmp~1); 1411988#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1412343#L395 assume !(1 == ~t1_pc~0); 1412526#L395-2 is_transmit1_triggered_~__retres1~1 := 0; 1412699#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1411916#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1411917#L963 assume !(0 != activate_threads_~tmp___0~0); 1412445#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1412446#L414 assume !(1 == ~t2_pc~0); 1412032#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 1412740#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1412231#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1412232#L971 assume !(0 != activate_threads_~tmp___1~0); 1412739#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1412346#L433 assume !(1 == ~t3_pc~0); 1412144#L433-2 is_transmit3_triggered_~__retres1~3 := 0; 1412145#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1412316#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1412317#L979 assume !(0 != activate_threads_~tmp___2~0); 1412002#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1412003#L452 assume !(1 == ~t4_pc~0); 1412150#L452-2 is_transmit4_triggered_~__retres1~4 := 0; 1412151#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1412482#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1412556#L987 assume !(0 != activate_threads_~tmp___3~0); 1412184#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1412185#L471 assume !(1 == ~t5_pc~0); 1412608#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 1412859#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1412547#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1412548#L995 assume !(0 != activate_threads_~tmp___4~0); 1412803#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1412804#L490 assume !(1 == ~t6_pc~0); 1412442#L490-2 is_transmit6_triggered_~__retres1~6 := 0; 1412443#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1412490#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1412494#L1003 assume !(0 != activate_threads_~tmp___5~0); 1412357#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1412320#L509 assume !(1 == ~t7_pc~0); 1412321#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 1412129#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1412130#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1412189#L1011 assume !(0 != activate_threads_~tmp___6~0); 1412190#L1011-2 assume !(1 == ~M_E~0); 1412836#L857-1 assume !(1 == ~T1_E~0); 1412254#L862-1 assume !(1 == ~T2_E~0); 1412255#L867-1 assume !(1 == ~T3_E~0); 1412261#L872-1 assume !(1 == ~T4_E~0); 1412347#L877-1 assume !(1 == ~T5_E~0); 1412579#L882-1 assume !(1 == ~T6_E~0); 1412769#L887-1 assume !(1 == ~T7_E~0); 1412652#L892-1 assume !(1 == ~E_M~0); 1412653#L897-1 assume !(1 == ~E_1~0); 1412275#L902-1 assume !(1 == ~E_2~0); 1412276#L907-1 assume !(1 == ~E_3~0); 1412598#L912-1 assume !(1 == ~E_4~0); 1412587#L917-1 assume !(1 == ~E_5~0); 1412588#L922-1 assume !(1 == ~E_6~0); 1412823#L927-1 assume !(1 == ~E_7~0); 1412901#L1178-1 assume !false; 1524208#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 1524204#L744 [2021-11-09 09:35:32,450 INFO L793 eck$LassoCheckResult]: Loop: 1524204#L744 assume !false; 1524203#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1524197#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1524195#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1524193#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1524191#L641 assume 0 != eval_~tmp~0; 1524188#L641-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 1524185#L649 assume !(0 != eval_~tmp_ndt_1~0); 1524186#L646 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 1446919#L663 assume !(0 != eval_~tmp_ndt_2~0); 1446920#L660 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 1472540#L677 assume !(0 != eval_~tmp_ndt_3~0); 1490791#L674 assume !(0 == ~t3_st~0); 1490787#L688 assume !(0 == ~t4_st~0); 1490781#L702 assume !(0 == ~t5_st~0); 1490776#L716 assume !(0 == ~t6_st~0); 1490775#L730 assume !(0 == ~t7_st~0); 1524204#L744 [2021-11-09 09:35:32,450 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:32,450 INFO L85 PathProgramCache]: Analyzing trace with hash 259139107, now seen corresponding path program 3 times [2021-11-09 09:35:32,450 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:32,450 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1159535820] [2021-11-09 09:35:32,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:32,451 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:32,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:32,463 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:32,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:32,511 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:32,511 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:32,511 INFO L85 PathProgramCache]: Analyzing trace with hash -1372155581, now seen corresponding path program 1 times [2021-11-09 09:35:32,511 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:32,512 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [307595786] [2021-11-09 09:35:32,512 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:32,512 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:32,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:32,517 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:32,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:32,522 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:32,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:32,523 INFO L85 PathProgramCache]: Analyzing trace with hash -202034335, now seen corresponding path program 1 times [2021-11-09 09:35:32,523 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:32,523 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1304937597] [2021-11-09 09:35:32,523 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:32,524 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:32,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:32,559 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:32,559 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:32,559 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1304937597] [2021-11-09 09:35:32,559 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1304937597] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:32,559 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:32,560 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:32,560 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [128295191] [2021-11-09 09:35:32,722 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:32,723 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:35:32,723 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:35:32,723 INFO L87 Difference]: Start difference. First operand 121203 states and 161018 transitions. cyclomatic complexity: 39845 Second operand has 3 states, 3 states have (on average 36.666666666666664) internal successors, (110), 3 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:34,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:34,403 INFO L93 Difference]: Finished difference Result 192773 states and 255376 transitions. [2021-11-09 09:35:34,404 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:35:34,404 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 192773 states and 255376 transitions. [2021-11-09 09:35:35,014 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 191614 [2021-11-09 09:35:35,367 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 192773 states to 192773 states and 255376 transitions. [2021-11-09 09:35:35,367 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 192773 [2021-11-09 09:35:35,436 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 192773 [2021-11-09 09:35:35,436 INFO L73 IsDeterministic]: Start isDeterministic. Operand 192773 states and 255376 transitions. [2021-11-09 09:35:35,495 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 09:35:35,495 INFO L681 BuchiCegarLoop]: Abstraction has 192773 states and 255376 transitions. [2021-11-09 09:35:35,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 192773 states and 255376 transitions. [2021-11-09 09:35:37,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 192773 to 188833. [2021-11-09 09:35:38,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 188833 states, 188833 states have (on average 1.32538274560061) internal successors, (250276), 188832 states have internal predecessors, (250276), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:38,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188833 states to 188833 states and 250276 transitions. [2021-11-09 09:35:38,483 INFO L704 BuchiCegarLoop]: Abstraction has 188833 states and 250276 transitions. [2021-11-09 09:35:38,483 INFO L587 BuchiCegarLoop]: Abstraction has 188833 states and 250276 transitions. [2021-11-09 09:35:38,483 INFO L425 BuchiCegarLoop]: ======== Iteration 29============ [2021-11-09 09:35:38,483 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 188833 states and 250276 transitions. [2021-11-09 09:35:38,944 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 187674 [2021-11-09 09:35:38,944 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 09:35:38,944 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 09:35:38,945 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:38,945 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 09:35:38,945 INFO L791 eck$LassoCheckResult]: Stem: 1726555#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1726556#L-1 havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1726411#L1141 havoc start_simulation_#t~ret26, start_simulation_#t~ret27, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1726354#L529 assume 1 == ~m_i~0;~m_st~0 := 0; 1726355#L536-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1726332#L541-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1726163#L546-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1726164#L551-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1726144#L556-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1726145#L561-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1726718#L566-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1726486#L571-1 assume !(0 == ~M_E~0); 1726483#L769-1 assume !(0 == ~T1_E~0); 1726484#L774-1 assume !(0 == ~T2_E~0); 1726545#L779-1 assume !(0 == ~T3_E~0); 1726698#L784-1 assume !(0 == ~T4_E~0); 1726479#L789-1 assume !(0 == ~T5_E~0); 1726480#L794-1 assume !(0 == ~T6_E~0); 1726616#L799-1 assume !(0 == ~T7_E~0); 1726487#L804-1 assume !(0 == ~E_M~0); 1726488#L809-1 assume !(0 == ~E_1~0); 1726533#L814-1 assume !(0 == ~E_2~0); 1725896#L819-1 assume !(0 == ~E_3~0); 1725897#L824-1 assume !(0 == ~E_4~0); 1726231#L829-1 assume !(0 == ~E_5~0); 1726800#L834-1 assume !(0 == ~E_6~0); 1726013#L839-1 assume !(0 == ~E_7~0); 1726014#L844-1 havoc activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_#t~ret19, activate_threads_#t~ret20, activate_threads_#t~ret21, activate_threads_#t~ret22, activate_threads_#t~ret23, activate_threads_#t~ret24, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1726420#L376 assume !(1 == ~m_pc~0); 1726416#L376-2 is_master_triggered_~__retres1~0 := 0; 1726417#L387 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1726773#L388 activate_threads_#t~ret17 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1725971#L955 assume !(0 != activate_threads_~tmp~1); 1725972#L955-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1726323#L395 assume !(1 == ~t1_pc~0); 1726512#L395-2 is_transmit1_triggered_~__retres1~1 := 0; 1726682#L406 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1725900#L407 activate_threads_#t~ret18 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1725901#L963 assume !(0 != activate_threads_~tmp___0~0); 1726429#L963-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1726430#L414 assume !(1 == ~t2_pc~0); 1726016#L414-2 is_transmit2_triggered_~__retres1~2 := 0; 1726724#L425 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1726218#L426 activate_threads_#t~ret19 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret19;havoc activate_threads_#t~ret19; 1726219#L971 assume !(0 != activate_threads_~tmp___1~0); 1726723#L971-2 havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1726328#L433 assume !(1 == ~t3_pc~0); 1726134#L433-2 is_transmit3_triggered_~__retres1~3 := 0; 1726135#L444 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1726300#L445 activate_threads_#t~ret20 := is_transmit3_triggered_#res;activate_threads_~tmp___2~0 := activate_threads_#t~ret20;havoc activate_threads_#t~ret20; 1726301#L979 assume !(0 != activate_threads_~tmp___2~0); 1725985#L979-2 havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1725986#L452 assume !(1 == ~t4_pc~0); 1726140#L452-2 is_transmit4_triggered_~__retres1~4 := 0; 1726141#L463 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1726465#L464 activate_threads_#t~ret21 := is_transmit4_triggered_#res;activate_threads_~tmp___3~0 := activate_threads_#t~ret21;havoc activate_threads_#t~ret21; 1726544#L987 assume !(0 != activate_threads_~tmp___3~0); 1726174#L987-2 havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1726175#L471 assume !(1 == ~t5_pc~0); 1726596#L471-2 is_transmit5_triggered_~__retres1~5 := 0; 1726831#L482 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1726534#L483 activate_threads_#t~ret22 := is_transmit5_triggered_#res;activate_threads_~tmp___4~0 := activate_threads_#t~ret22;havoc activate_threads_#t~ret22; 1726535#L995 assume !(0 != activate_threads_~tmp___4~0); 1726791#L995-2 havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1726792#L490 assume !(1 == ~t6_pc~0); 1726425#L490-2 is_transmit6_triggered_~__retres1~6 := 0; 1726426#L501 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1726473#L502 activate_threads_#t~ret23 := is_transmit6_triggered_#res;activate_threads_~tmp___5~0 := activate_threads_#t~ret23;havoc activate_threads_#t~ret23; 1726477#L1003 assume !(0 != activate_threads_~tmp___5~0); 1726340#L1003-2 havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1726303#L509 assume !(1 == ~t7_pc~0); 1726304#L509-2 is_transmit7_triggered_~__retres1~7 := 0; 1726119#L520 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1726120#L521 activate_threads_#t~ret24 := is_transmit7_triggered_#res;activate_threads_~tmp___6~0 := activate_threads_#t~ret24;havoc activate_threads_#t~ret24; 1726179#L1011 assume !(0 != activate_threads_~tmp___6~0); 1726180#L1011-2 assume !(1 == ~M_E~0); 1726813#L857-1 assume !(1 == ~T1_E~0); 1726239#L862-1 assume !(1 == ~T2_E~0); 1726240#L867-1 assume !(1 == ~T3_E~0); 1726247#L872-1 assume !(1 == ~T4_E~0); 1726329#L877-1 assume !(1 == ~T5_E~0); 1726569#L882-1 assume !(1 == ~T6_E~0); 1726757#L887-1 assume !(1 == ~T7_E~0); 1726641#L892-1 assume !(1 == ~E_M~0); 1726642#L897-1 assume !(1 == ~E_1~0); 1726260#L902-1 assume !(1 == ~E_2~0); 1726261#L907-1 assume !(1 == ~E_3~0); 1726589#L912-1 assume !(1 == ~E_4~0); 1726577#L917-1 assume !(1 == ~E_5~0); 1726578#L922-1 assume !(1 == ~E_6~0); 1726804#L927-1 assume !(1 == ~E_7~0); 1726879#L1178-1 assume !false; 1766258#L1179 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret8, eval_#t~nondet9, eval_~tmp_ndt_1~0, eval_#t~nondet10, eval_~tmp_ndt_2~0, eval_#t~nondet11, eval_~tmp_ndt_3~0, eval_#t~nondet12, eval_~tmp_ndt_4~0, eval_#t~nondet13, eval_~tmp_ndt_5~0, eval_#t~nondet14, eval_~tmp_ndt_6~0, eval_#t~nondet15, eval_~tmp_ndt_7~0, eval_#t~nondet16, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 1766259#L744 [2021-11-09 09:35:38,945 INFO L793 eck$LassoCheckResult]: Loop: 1766259#L744 assume !false; 1805273#L637 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1805271#L584 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1805270#L626 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1805269#L627 eval_#t~ret8 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret8;havoc eval_#t~ret8; 1805268#L641 assume 0 != eval_~tmp~0; 1805266#L641-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 1805265#L649 assume !(0 != eval_~tmp_ndt_1~0); 1766187#L646 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 1766188#L663 assume !(0 != eval_~tmp_ndt_2~0); 1805298#L660 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet11;havoc eval_#t~nondet11; 1805297#L677 assume !(0 != eval_~tmp_ndt_3~0); 1840760#L674 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet12;havoc eval_#t~nondet12; 1840759#L691 assume !(0 != eval_~tmp_ndt_4~0); 1805288#L688 assume !(0 == ~t4_st~0); 1805287#L702 assume !(0 == ~t5_st~0); 1805280#L716 assume !(0 == ~t6_st~0); 1805277#L730 assume !(0 == ~t7_st~0); 1766259#L744 [2021-11-09 09:35:38,946 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:38,946 INFO L85 PathProgramCache]: Analyzing trace with hash 259139107, now seen corresponding path program 4 times [2021-11-09 09:35:38,946 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:38,946 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [685897389] [2021-11-09 09:35:38,947 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:38,947 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:38,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:38,956 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:38,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:38,992 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:38,992 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:38,993 INFO L85 PathProgramCache]: Analyzing trace with hash -1836711777, now seen corresponding path program 1 times [2021-11-09 09:35:38,993 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:38,993 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1987534932] [2021-11-09 09:35:38,993 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:38,993 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:38,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:38,997 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 09:35:38,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 09:35:39,001 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 09:35:39,001 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 09:35:39,002 INFO L85 PathProgramCache]: Analyzing trace with hash 77308481, now seen corresponding path program 1 times [2021-11-09 09:35:39,002 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 09:35:39,002 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1841499402] [2021-11-09 09:35:39,002 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 09:35:39,002 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 09:35:39,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 09:35:39,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 09:35:39,031 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 09:35:39,031 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1841499402] [2021-11-09 09:35:39,031 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1841499402] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 09:35:39,032 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 09:35:39,032 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 09:35:39,032 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1781171791] [2021-11-09 09:35:39,200 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 09:35:39,200 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 09:35:39,201 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 09:35:39,201 INFO L87 Difference]: Start difference. First operand 188833 states and 250276 transitions. cyclomatic complexity: 61473 Second operand has 3 states, 3 states have (on average 37.0) internal successors, (111), 3 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 09:35:40,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 09:35:40,867 INFO L93 Difference]: Finished difference Result 266147 states and 352372 transitions. [2021-11-09 09:35:40,868 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 09:35:40,868 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 266147 states and 352372 transitions. [2021-11-09 09:35:42,023 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 264758