./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.02.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version f8e1c903 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89494476-70ab-4624-a02f-13ca4a15a593/bin/uautomizer-IVEQpCNsaX/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89494476-70ab-4624-a02f-13ca4a15a593/bin/uautomizer-IVEQpCNsaX/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89494476-70ab-4624-a02f-13ca4a15a593/bin/uautomizer-IVEQpCNsaX/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89494476-70ab-4624-a02f-13ca4a15a593/bin/uautomizer-IVEQpCNsaX/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.02.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89494476-70ab-4624-a02f-13ca4a15a593/bin/uautomizer-IVEQpCNsaX/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89494476-70ab-4624-a02f-13ca4a15a593/bin/uautomizer-IVEQpCNsaX --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c --- Real Ultimate output --- This is Ultimate 0.2.1-dev-f8e1c90 [2021-11-09 08:57:15,723 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-09 08:57:15,725 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-09 08:57:15,771 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-09 08:57:15,772 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-09 08:57:15,773 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-09 08:57:15,775 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-09 08:57:15,778 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-09 08:57:15,780 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-09 08:57:15,781 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-09 08:57:15,782 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-09 08:57:15,784 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-09 08:57:15,785 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-09 08:57:15,786 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-09 08:57:15,788 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-09 08:57:15,789 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-09 08:57:15,791 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-09 08:57:15,792 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-09 08:57:15,794 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-09 08:57:15,797 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-09 08:57:15,799 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-09 08:57:15,801 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-09 08:57:15,803 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-09 08:57:15,804 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-09 08:57:15,808 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-09 08:57:15,808 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-09 08:57:15,809 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-09 08:57:15,810 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-09 08:57:15,811 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-09 08:57:15,812 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-09 08:57:15,813 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-09 08:57:15,814 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-09 08:57:15,815 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-09 08:57:15,816 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-09 08:57:15,817 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-09 08:57:15,818 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-09 08:57:15,819 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-09 08:57:15,819 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-09 08:57:15,819 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-09 08:57:15,821 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-09 08:57:15,822 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-09 08:57:15,823 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89494476-70ab-4624-a02f-13ca4a15a593/bin/uautomizer-IVEQpCNsaX/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-09 08:57:15,856 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-09 08:57:15,859 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-09 08:57:15,860 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-09 08:57:15,861 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-09 08:57:15,863 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-09 08:57:15,863 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-09 08:57:15,864 INFO L138 SettingsManager]: * Use SBE=true [2021-11-09 08:57:15,864 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-09 08:57:15,864 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-09 08:57:15,864 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-09 08:57:15,865 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-09 08:57:15,866 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-09 08:57:15,866 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-09 08:57:15,866 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-09 08:57:15,867 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-09 08:57:15,867 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-09 08:57:15,867 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-09 08:57:15,867 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-09 08:57:15,867 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-09 08:57:15,868 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-09 08:57:15,868 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-09 08:57:15,868 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-09 08:57:15,868 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-09 08:57:15,869 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-09 08:57:15,869 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-09 08:57:15,869 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-09 08:57:15,871 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-09 08:57:15,871 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-09 08:57:15,872 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-09 08:57:15,872 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-09 08:57:15,872 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-09 08:57:15,872 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-09 08:57:15,873 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-09 08:57:15,874 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89494476-70ab-4624-a02f-13ca4a15a593/bin/uautomizer-IVEQpCNsaX/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89494476-70ab-4624-a02f-13ca4a15a593/bin/uautomizer-IVEQpCNsaX Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2cbfaf31aa56f767af01fea9a12ccb47d60ab19076d72b85e8ca46d6ff778e4c [2021-11-09 08:57:16,180 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-09 08:57:16,204 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-09 08:57:16,207 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-09 08:57:16,208 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-09 08:57:16,210 INFO L275 PluginConnector]: CDTParser initialized [2021-11-09 08:57:16,210 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89494476-70ab-4624-a02f-13ca4a15a593/bin/uautomizer-IVEQpCNsaX/../../sv-benchmarks/c/systemc/transmitter.02.cil.c [2021-11-09 08:57:16,292 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89494476-70ab-4624-a02f-13ca4a15a593/bin/uautomizer-IVEQpCNsaX/data/30db27467/fbde4a8a2cbd43b89a96fe030ca6cfdd/FLAGdc8ea38cd [2021-11-09 08:57:16,755 INFO L306 CDTParser]: Found 1 translation units. [2021-11-09 08:57:16,756 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89494476-70ab-4624-a02f-13ca4a15a593/sv-benchmarks/c/systemc/transmitter.02.cil.c [2021-11-09 08:57:16,765 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89494476-70ab-4624-a02f-13ca4a15a593/bin/uautomizer-IVEQpCNsaX/data/30db27467/fbde4a8a2cbd43b89a96fe030ca6cfdd/FLAGdc8ea38cd [2021-11-09 08:57:17,153 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89494476-70ab-4624-a02f-13ca4a15a593/bin/uautomizer-IVEQpCNsaX/data/30db27467/fbde4a8a2cbd43b89a96fe030ca6cfdd [2021-11-09 08:57:17,157 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-09 08:57:17,160 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-09 08:57:17,162 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-09 08:57:17,163 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-09 08:57:17,168 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-09 08:57:17,178 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 08:57:17" (1/1) ... [2021-11-09 08:57:17,179 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@12a7783 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 08:57:17, skipping insertion in model container [2021-11-09 08:57:17,179 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 09.11 08:57:17" (1/1) ... [2021-11-09 08:57:17,192 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-09 08:57:17,226 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-09 08:57:17,379 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89494476-70ab-4624-a02f-13ca4a15a593/sv-benchmarks/c/systemc/transmitter.02.cil.c[706,719] [2021-11-09 08:57:17,427 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-09 08:57:17,437 INFO L203 MainTranslator]: Completed pre-run [2021-11-09 08:57:17,448 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89494476-70ab-4624-a02f-13ca4a15a593/sv-benchmarks/c/systemc/transmitter.02.cil.c[706,719] [2021-11-09 08:57:17,477 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-09 08:57:17,493 INFO L208 MainTranslator]: Completed translation [2021-11-09 08:57:17,493 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 08:57:17 WrapperNode [2021-11-09 08:57:17,494 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-09 08:57:17,495 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-09 08:57:17,495 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-09 08:57:17,495 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-09 08:57:17,504 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 08:57:17" (1/1) ... [2021-11-09 08:57:17,514 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 08:57:17" (1/1) ... [2021-11-09 08:57:17,556 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-09 08:57:17,557 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-09 08:57:17,557 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-09 08:57:17,557 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-09 08:57:17,565 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 08:57:17" (1/1) ... [2021-11-09 08:57:17,580 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 08:57:17" (1/1) ... [2021-11-09 08:57:17,583 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 08:57:17" (1/1) ... [2021-11-09 08:57:17,583 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 08:57:17" (1/1) ... [2021-11-09 08:57:17,594 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 08:57:17" (1/1) ... [2021-11-09 08:57:17,604 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 08:57:17" (1/1) ... [2021-11-09 08:57:17,607 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 08:57:17" (1/1) ... [2021-11-09 08:57:17,612 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-09 08:57:17,613 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-09 08:57:17,614 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-09 08:57:17,614 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-09 08:57:17,615 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 08:57:17" (1/1) ... [2021-11-09 08:57:17,652 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-09 08:57:17,665 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89494476-70ab-4624-a02f-13ca4a15a593/bin/uautomizer-IVEQpCNsaX/z3 [2021-11-09 08:57:17,690 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89494476-70ab-4624-a02f-13ca4a15a593/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-09 08:57:17,714 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89494476-70ab-4624-a02f-13ca4a15a593/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-09 08:57:17,745 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-09 08:57:17,746 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-09 08:57:17,746 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-09 08:57:17,746 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-09 08:57:18,475 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-09 08:57:18,475 INFO L299 CfgBuilder]: Removed 94 assume(true) statements. [2021-11-09 08:57:18,478 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 08:57:18 BoogieIcfgContainer [2021-11-09 08:57:18,482 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-09 08:57:18,483 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-09 08:57:18,484 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-09 08:57:18,488 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-09 08:57:18,490 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-09 08:57:18,490 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 09.11 08:57:17" (1/3) ... [2021-11-09 08:57:18,492 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@35d4d49d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 08:57:18, skipping insertion in model container [2021-11-09 08:57:18,493 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-09 08:57:18,493 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 09.11 08:57:17" (2/3) ... [2021-11-09 08:57:18,494 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@35d4d49d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 09.11 08:57:18, skipping insertion in model container [2021-11-09 08:57:18,494 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-09 08:57:18,494 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 08:57:18" (3/3) ... [2021-11-09 08:57:18,496 INFO L389 chiAutomizerObserver]: Analyzing ICFG transmitter.02.cil.c [2021-11-09 08:57:18,587 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-09 08:57:18,587 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-09 08:57:18,587 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-09 08:57:18,587 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-09 08:57:18,596 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-09 08:57:18,596 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-09 08:57:18,596 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-09 08:57:18,597 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-09 08:57:18,652 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 191 states, 190 states have (on average 1.5789473684210527) internal successors, (300), 190 states have internal predecessors, (300), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:18,690 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 150 [2021-11-09 08:57:18,691 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 08:57:18,691 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 08:57:18,700 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:18,700 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:18,700 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-09 08:57:18,701 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 191 states, 190 states have (on average 1.5789473684210527) internal successors, (300), 190 states have internal predecessors, (300), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:18,711 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 150 [2021-11-09 08:57:18,712 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 08:57:18,712 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 08:57:18,715 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:18,715 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:18,723 INFO L791 eck$LassoCheckResult]: Stem: 172#ULTIMATE.startENTRYtrue #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 63#L-1true havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 5#L491true havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 177#L214true assume !(1 == ~m_i~0);~m_st~0 := 2; 91#L221-1true assume 1 == ~t1_i~0;~t1_st~0 := 0; 67#L226-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 73#L231-1true assume !(0 == ~M_E~0); 60#L334-1true assume !(0 == ~T1_E~0); 169#L339-1true assume !(0 == ~T2_E~0); 159#L344-1true assume !(0 == ~E_1~0); 37#L349-1true assume !(0 == ~E_2~0); 65#L354-1true havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 182#L156true assume !(1 == ~m_pc~0); 61#L156-2true is_master_triggered_~__retres1~0 := 0; 26#L167true is_master_triggered_#res := is_master_triggered_~__retres1~0; 8#L168true activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 121#L405true assume !(0 != activate_threads_~tmp~1); 98#L405-2true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6#L175true assume 1 == ~t1_pc~0; 72#L176true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 99#L186true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 174#L187true activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 178#L413true assume !(0 != activate_threads_~tmp___0~0); 137#L413-2true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 142#L194true assume !(1 == ~t2_pc~0); 181#L194-2true is_transmit2_triggered_~__retres1~2 := 0; 113#L205true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 51#L206true activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 44#L421true assume !(0 != activate_threads_~tmp___1~0); 130#L421-2true assume !(1 == ~M_E~0); 146#L367-1true assume !(1 == ~T1_E~0); 17#L372-1true assume !(1 == ~T2_E~0); 19#L377-1true assume !(1 == ~E_1~0); 35#L382-1true assume !(1 == ~E_2~0); 81#L528-1true [2021-11-09 08:57:18,725 INFO L793 eck$LassoCheckResult]: Loop: 81#L528-1true assume !false; 132#L529true start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 127#L309true assume false; 20#L324true start_simulation_~kernel_st~0 := 2; 122#L214-1true start_simulation_~kernel_st~0 := 3; 88#L334-2true assume 0 == ~M_E~0;~M_E~0 := 1; 100#L334-4true assume 0 == ~T1_E~0;~T1_E~0 := 1; 179#L339-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 131#L344-3true assume 0 == ~E_1~0;~E_1~0 := 1; 119#L349-3true assume !(0 == ~E_2~0); 50#L354-3true havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 148#L156-9true assume 1 == ~m_pc~0; 188#L157-3true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 94#L167-3true is_master_triggered_#res := is_master_triggered_~__retres1~0; 112#L168-3true activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 184#L405-9true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 29#L405-11true havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 158#L175-9true assume !(1 == ~t1_pc~0); 34#L175-11true is_transmit1_triggered_~__retres1~1 := 0; 21#L186-3true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 173#L187-3true activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 59#L413-9true assume !(0 != activate_threads_~tmp___0~0); 43#L413-11true havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 152#L194-9true assume 1 == ~t2_pc~0; 128#L195-3true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 166#L205-3true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 129#L206-3true activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 164#L421-9true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 40#L421-11true assume 1 == ~M_E~0;~M_E~0 := 2; 83#L367-3true assume 1 == ~T1_E~0;~T1_E~0 := 2; 52#L372-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 25#L377-3true assume !(1 == ~E_1~0); 48#L382-3true assume 1 == ~E_2~0;~E_2~0 := 2; 167#L387-3true havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 41#L244-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 117#L261-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 38#L262-1true start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 58#L547true assume !(0 == start_simulation_~tmp~3); 141#L547-1true havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 54#L244-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 80#L261-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 109#L262-2true stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 64#L502true assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 77#L509true stop_simulation_#res := stop_simulation_~__retres2~0; 126#L510true start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 28#L560true assume !(0 != start_simulation_~tmp___0~1); 81#L528-1true [2021-11-09 08:57:18,731 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:18,732 INFO L85 PathProgramCache]: Analyzing trace with hash 1765217540, now seen corresponding path program 1 times [2021-11-09 08:57:18,742 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:18,743 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [490621781] [2021-11-09 08:57:18,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:18,745 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:18,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 08:57:18,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 08:57:18,944 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 08:57:18,945 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [490621781] [2021-11-09 08:57:18,946 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [490621781] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 08:57:18,948 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 08:57:18,949 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 08:57:18,951 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [904299948] [2021-11-09 08:57:18,957 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 08:57:18,964 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:18,965 INFO L85 PathProgramCache]: Analyzing trace with hash 1231104429, now seen corresponding path program 1 times [2021-11-09 08:57:18,966 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:18,966 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1486986303] [2021-11-09 08:57:18,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:18,967 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:18,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 08:57:19,007 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 08:57:19,008 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 08:57:19,009 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1486986303] [2021-11-09 08:57:19,009 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1486986303] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 08:57:19,009 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 08:57:19,010 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-09 08:57:19,010 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1602162831] [2021-11-09 08:57:19,012 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 08:57:19,013 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 08:57:19,028 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 08:57:19,029 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 08:57:19,033 INFO L87 Difference]: Start difference. First operand has 191 states, 190 states have (on average 1.5789473684210527) internal successors, (300), 190 states have internal predecessors, (300), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:19,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 08:57:19,100 INFO L93 Difference]: Finished difference Result 191 states and 286 transitions. [2021-11-09 08:57:19,100 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 08:57:19,102 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 191 states and 286 transitions. [2021-11-09 08:57:19,114 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2021-11-09 08:57:19,124 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 191 states to 186 states and 281 transitions. [2021-11-09 08:57:19,127 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 186 [2021-11-09 08:57:19,130 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 186 [2021-11-09 08:57:19,131 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 281 transitions. [2021-11-09 08:57:19,134 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 08:57:19,134 INFO L681 BuchiCegarLoop]: Abstraction has 186 states and 281 transitions. [2021-11-09 08:57:19,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 281 transitions. [2021-11-09 08:57:19,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 186. [2021-11-09 08:57:19,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 186 states, 186 states have (on average 1.510752688172043) internal successors, (281), 185 states have internal predecessors, (281), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:19,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 281 transitions. [2021-11-09 08:57:19,198 INFO L704 BuchiCegarLoop]: Abstraction has 186 states and 281 transitions. [2021-11-09 08:57:19,198 INFO L587 BuchiCegarLoop]: Abstraction has 186 states and 281 transitions. [2021-11-09 08:57:19,198 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-09 08:57:19,198 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 186 states and 281 transitions. [2021-11-09 08:57:19,200 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2021-11-09 08:57:19,201 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 08:57:19,201 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 08:57:19,203 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:19,204 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:19,204 INFO L791 eck$LassoCheckResult]: Stem: 575#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 502#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 396#L491 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 397#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 533#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 506#L226-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 507#L231-1 assume !(0 == ~M_E~0); 497#L334-1 assume !(0 == ~T1_E~0); 498#L339-1 assume !(0 == ~T2_E~0); 572#L344-1 assume !(0 == ~E_1~0); 461#L349-1 assume !(0 == ~E_2~0); 462#L354-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 503#L156 assume !(1 == ~m_pc~0); 409#L156-2 is_master_triggered_~__retres1~0 := 0; 410#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 401#L168 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 402#L405 assume !(0 != activate_threads_~tmp~1); 540#L405-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 398#L175 assume 1 == ~t1_pc~0; 399#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 515#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 541#L187 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 576#L413 assume !(0 != activate_threads_~tmp___0~0); 564#L413-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 565#L194 assume !(1 == ~t2_pc~0); 566#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 549#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 488#L206 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 472#L421 assume !(0 != activate_threads_~tmp___1~0); 473#L421-2 assume !(1 == ~M_E~0); 557#L367-1 assume !(1 == ~T1_E~0); 423#L372-1 assume !(1 == ~T2_E~0); 424#L377-1 assume !(1 == ~E_1~0); 427#L382-1 assume !(1 == ~E_2~0); 443#L528-1 [2021-11-09 08:57:19,205 INFO L793 eck$LassoCheckResult]: Loop: 443#L528-1 assume !false; 524#L529 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 407#L309 assume !false; 514#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 413#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 414#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 535#L262 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 391#L276 assume !(0 != eval_~tmp~0); 393#L324 start_simulation_~kernel_st~0 := 2; 430#L214-1 start_simulation_~kernel_st~0 := 3; 529#L334-2 assume 0 == ~M_E~0;~M_E~0 := 1; 530#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 538#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 558#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 550#L349-3 assume !(0 == ~E_2~0); 481#L354-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 482#L156-9 assume !(1 == ~m_pc~0); 403#L156-11 is_master_triggered_~__retres1~0 := 0; 404#L167-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 534#L168-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 547#L405-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 444#L405-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 445#L175-9 assume 1 == ~t1_pc~0; 516#L176-3 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 428#L186-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 429#L187-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 496#L413-9 assume !(0 != activate_threads_~tmp___0~0); 470#L413-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 471#L194-9 assume 1 == ~t2_pc~0; 554#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 476#L205-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 555#L206-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 556#L421-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 463#L421-11 assume 1 == ~M_E~0;~M_E~0 := 2; 464#L367-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 483#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 438#L377-3 assume !(1 == ~E_1~0); 439#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 478#L387-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 465#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 466#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 459#L262-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 460#L547 assume !(0 == start_simulation_~tmp~3); 492#L547-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 485#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 486#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 523#L262-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 500#L502 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 501#L509 stop_simulation_#res := stop_simulation_~__retres2~0; 518#L510 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 442#L560 assume !(0 != start_simulation_~tmp___0~1); 443#L528-1 [2021-11-09 08:57:19,205 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:19,206 INFO L85 PathProgramCache]: Analyzing trace with hash 1063617666, now seen corresponding path program 1 times [2021-11-09 08:57:19,206 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:19,206 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [667925689] [2021-11-09 08:57:19,206 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:19,207 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:19,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 08:57:19,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 08:57:19,254 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 08:57:19,254 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [667925689] [2021-11-09 08:57:19,254 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [667925689] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 08:57:19,254 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 08:57:19,255 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 08:57:19,255 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1561316137] [2021-11-09 08:57:19,255 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 08:57:19,256 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:19,256 INFO L85 PathProgramCache]: Analyzing trace with hash -1036257152, now seen corresponding path program 1 times [2021-11-09 08:57:19,257 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:19,257 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1974688424] [2021-11-09 08:57:19,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:19,258 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:19,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 08:57:19,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 08:57:19,322 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 08:57:19,322 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1974688424] [2021-11-09 08:57:19,322 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1974688424] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 08:57:19,323 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 08:57:19,323 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 08:57:19,323 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [160055162] [2021-11-09 08:57:19,324 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 08:57:19,324 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 08:57:19,325 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 08:57:19,325 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 08:57:19,325 INFO L87 Difference]: Start difference. First operand 186 states and 281 transitions. cyclomatic complexity: 96 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:19,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 08:57:19,338 INFO L93 Difference]: Finished difference Result 186 states and 280 transitions. [2021-11-09 08:57:19,338 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 08:57:19,339 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 186 states and 280 transitions. [2021-11-09 08:57:19,341 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2021-11-09 08:57:19,344 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 186 states to 186 states and 280 transitions. [2021-11-09 08:57:19,344 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 186 [2021-11-09 08:57:19,345 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 186 [2021-11-09 08:57:19,345 INFO L73 IsDeterministic]: Start isDeterministic. Operand 186 states and 280 transitions. [2021-11-09 08:57:19,347 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 08:57:19,347 INFO L681 BuchiCegarLoop]: Abstraction has 186 states and 280 transitions. [2021-11-09 08:57:19,347 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states and 280 transitions. [2021-11-09 08:57:19,354 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 186. [2021-11-09 08:57:19,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 186 states, 186 states have (on average 1.5053763440860215) internal successors, (280), 185 states have internal predecessors, (280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:19,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 280 transitions. [2021-11-09 08:57:19,357 INFO L704 BuchiCegarLoop]: Abstraction has 186 states and 280 transitions. [2021-11-09 08:57:19,357 INFO L587 BuchiCegarLoop]: Abstraction has 186 states and 280 transitions. [2021-11-09 08:57:19,357 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-09 08:57:19,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 186 states and 280 transitions. [2021-11-09 08:57:19,359 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 149 [2021-11-09 08:57:19,359 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 08:57:19,359 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 08:57:19,361 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:19,361 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:19,362 INFO L791 eck$LassoCheckResult]: Stem: 954#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 879#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 773#L491 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 774#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 911#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 885#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 886#L231-1 assume !(0 == ~M_E~0); 876#L334-1 assume !(0 == ~T1_E~0); 877#L339-1 assume !(0 == ~T2_E~0); 951#L344-1 assume !(0 == ~E_1~0); 838#L349-1 assume !(0 == ~E_2~0); 839#L354-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 882#L156 assume !(1 == ~m_pc~0); 788#L156-2 is_master_triggered_~__retres1~0 := 0; 789#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 780#L168 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 781#L405 assume !(0 != activate_threads_~tmp~1); 917#L405-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 775#L175 assume 1 == ~t1_pc~0; 776#L176 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 894#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 918#L187 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 955#L413 assume !(0 != activate_threads_~tmp___0~0); 942#L413-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 943#L194 assume !(1 == ~t2_pc~0); 945#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 927#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 862#L206 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 851#L421 assume !(0 != activate_threads_~tmp___1~0); 852#L421-2 assume !(1 == ~M_E~0); 936#L367-1 assume !(1 == ~T1_E~0); 802#L372-1 assume !(1 == ~T2_E~0); 803#L377-1 assume !(1 == ~E_1~0); 806#L382-1 assume !(1 == ~E_2~0); 822#L528-1 [2021-11-09 08:57:19,362 INFO L793 eck$LassoCheckResult]: Loop: 822#L528-1 assume !false; 903#L529 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 784#L309 assume !false; 890#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 790#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 791#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 913#L262 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 770#L276 assume !(0 != eval_~tmp~0); 772#L324 start_simulation_~kernel_st~0 := 2; 807#L214-1 start_simulation_~kernel_st~0 := 3; 908#L334-2 assume 0 == ~M_E~0;~M_E~0 := 1; 909#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 919#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 937#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 929#L349-3 assume !(0 == ~E_2~0); 860#L354-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 861#L156-9 assume !(1 == ~m_pc~0); 785#L156-11 is_master_triggered_~__retres1~0 := 0; 786#L167-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 914#L168-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 926#L405-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 823#L405-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 824#L175-9 assume !(1 == ~t1_pc~0); 836#L175-11 is_transmit1_triggered_~__retres1~1 := 0; 808#L186-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 809#L187-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 875#L413-9 assume !(0 != activate_threads_~tmp___0~0); 849#L413-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 850#L194-9 assume 1 == ~t2_pc~0; 933#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 855#L205-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 934#L206-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 935#L421-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 842#L421-11 assume 1 == ~M_E~0;~M_E~0 := 2; 843#L367-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 863#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 817#L377-3 assume !(1 == ~E_1~0); 818#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 859#L387-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 844#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 845#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 840#L262-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 841#L547 assume !(0 == start_simulation_~tmp~3); 874#L547-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 865#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 866#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 902#L262-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 880#L502 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 881#L509 stop_simulation_#res := stop_simulation_~__retres2~0; 897#L510 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 821#L560 assume !(0 != start_simulation_~tmp___0~1); 822#L528-1 [2021-11-09 08:57:19,362 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:19,363 INFO L85 PathProgramCache]: Analyzing trace with hash -322585728, now seen corresponding path program 1 times [2021-11-09 08:57:19,363 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:19,363 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1285632767] [2021-11-09 08:57:19,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:19,364 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:19,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 08:57:19,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 08:57:19,424 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 08:57:19,424 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1285632767] [2021-11-09 08:57:19,424 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1285632767] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 08:57:19,425 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 08:57:19,425 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 08:57:19,425 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [78274385] [2021-11-09 08:57:19,426 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 08:57:19,426 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:19,426 INFO L85 PathProgramCache]: Analyzing trace with hash -2007931839, now seen corresponding path program 1 times [2021-11-09 08:57:19,426 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:19,427 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1808239041] [2021-11-09 08:57:19,427 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:19,427 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:19,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 08:57:19,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 08:57:19,509 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 08:57:19,509 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1808239041] [2021-11-09 08:57:19,509 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1808239041] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 08:57:19,509 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 08:57:19,509 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 08:57:19,510 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [521380491] [2021-11-09 08:57:19,510 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 08:57:19,510 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 08:57:19,511 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-09 08:57:19,511 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-09 08:57:19,511 INFO L87 Difference]: Start difference. First operand 186 states and 280 transitions. cyclomatic complexity: 95 Second operand has 4 states, 4 states have (on average 8.5) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:19,714 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 08:57:19,715 INFO L93 Difference]: Finished difference Result 441 states and 644 transitions. [2021-11-09 08:57:19,715 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-09 08:57:19,715 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 441 states and 644 transitions. [2021-11-09 08:57:19,722 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 377 [2021-11-09 08:57:19,729 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 441 states to 441 states and 644 transitions. [2021-11-09 08:57:19,729 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 441 [2021-11-09 08:57:19,730 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 441 [2021-11-09 08:57:19,731 INFO L73 IsDeterministic]: Start isDeterministic. Operand 441 states and 644 transitions. [2021-11-09 08:57:19,736 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 08:57:19,737 INFO L681 BuchiCegarLoop]: Abstraction has 441 states and 644 transitions. [2021-11-09 08:57:19,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 441 states and 644 transitions. [2021-11-09 08:57:19,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 441 to 403. [2021-11-09 08:57:19,778 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 403 states, 403 states have (on average 1.478908188585608) internal successors, (596), 402 states have internal predecessors, (596), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:19,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 403 states to 403 states and 596 transitions. [2021-11-09 08:57:19,785 INFO L704 BuchiCegarLoop]: Abstraction has 403 states and 596 transitions. [2021-11-09 08:57:19,785 INFO L587 BuchiCegarLoop]: Abstraction has 403 states and 596 transitions. [2021-11-09 08:57:19,785 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-09 08:57:19,785 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 403 states and 596 transitions. [2021-11-09 08:57:19,788 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 363 [2021-11-09 08:57:19,788 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 08:57:19,789 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 08:57:19,791 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:19,791 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:19,792 INFO L791 eck$LassoCheckResult]: Stem: 1611#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1517#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1412#L491 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 1413#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 1554#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1521#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1522#L231-1 assume !(0 == ~M_E~0); 1510#L334-1 assume !(0 == ~T1_E~0); 1511#L339-1 assume !(0 == ~T2_E~0); 1601#L344-1 assume !(0 == ~E_1~0); 1474#L349-1 assume !(0 == ~E_2~0); 1475#L354-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1518#L156 assume !(1 == ~m_pc~0); 1512#L156-2 is_master_triggered_~__retres1~0 := 0; 1454#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1416#L168 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1417#L405 assume !(0 != activate_threads_~tmp~1); 1563#L405-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1414#L175 assume !(1 == ~t1_pc~0); 1415#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 1564#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1565#L187 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1612#L413 assume !(0 != activate_threads_~tmp___0~0); 1591#L413-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1592#L194 assume !(1 == ~t2_pc~0); 1594#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 1574#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1501#L206 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1485#L421 assume !(0 != activate_threads_~tmp___1~0); 1486#L421-2 assume !(1 == ~M_E~0); 1584#L367-1 assume !(1 == ~T1_E~0); 1434#L372-1 assume !(1 == ~T2_E~0); 1435#L377-1 assume !(1 == ~E_1~0); 1438#L382-1 assume !(1 == ~E_2~0); 1456#L528-1 [2021-11-09 08:57:19,795 INFO L793 eck$LassoCheckResult]: Loop: 1456#L528-1 assume !false; 1542#L529 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 1420#L309 assume !false; 1527#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1423#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1424#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1618#L262 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 1738#L276 assume !(0 != eval_~tmp~0); 1439#L324 start_simulation_~kernel_st~0 := 2; 1440#L214-1 start_simulation_~kernel_st~0 := 3; 1549#L334-2 assume 0 == ~M_E~0;~M_E~0 := 1; 1550#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1561#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1585#L344-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1575#L349-3 assume !(0 == ~E_2~0); 1494#L354-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1495#L156-9 assume !(1 == ~m_pc~0); 1421#L156-11 is_master_triggered_~__retres1~0 := 0; 1422#L167-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1555#L168-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1572#L405-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1457#L405-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1458#L175-9 assume !(1 == ~t1_pc~0); 1467#L175-11 is_transmit1_triggered_~__retres1~1 := 0; 1441#L186-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1442#L187-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1509#L413-9 assume !(0 != activate_threads_~tmp___0~0); 1483#L413-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1484#L194-9 assume !(1 == ~t2_pc~0); 1488#L194-11 is_transmit2_triggered_~__retres1~2 := 0; 1489#L205-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1607#L206-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1789#L421-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1788#L421-11 assume 1 == ~M_E~0;~M_E~0 := 2; 1787#L367-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1496#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1450#L377-3 assume !(1 == ~E_1~0); 1451#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1491#L387-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1754#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1750#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1749#L262-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 1748#L547 assume !(0 == start_simulation_~tmp~3); 1535#L547-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1498#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1499#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1541#L262-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 1515#L502 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 1516#L509 stop_simulation_#res := stop_simulation_~__retres2~0; 1536#L510 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 1455#L560 assume !(0 != start_simulation_~tmp___0~1); 1456#L528-1 [2021-11-09 08:57:19,795 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:19,796 INFO L85 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 1 times [2021-11-09 08:57:19,796 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:19,797 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2117975303] [2021-11-09 08:57:19,797 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:19,797 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:19,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:19,840 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 08:57:19,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:19,912 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 08:57:19,913 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:19,914 INFO L85 PathProgramCache]: Analyzing trace with hash -1227950910, now seen corresponding path program 1 times [2021-11-09 08:57:19,914 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:19,914 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2110479500] [2021-11-09 08:57:19,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:19,915 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:19,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 08:57:19,995 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 08:57:19,996 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 08:57:19,996 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2110479500] [2021-11-09 08:57:19,996 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2110479500] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 08:57:19,996 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 08:57:19,997 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 08:57:19,997 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [517040672] [2021-11-09 08:57:19,997 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 08:57:19,997 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 08:57:19,998 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 08:57:19,998 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 08:57:19,998 INFO L87 Difference]: Start difference. First operand 403 states and 596 transitions. cyclomatic complexity: 195 Second operand has 3 states, 3 states have (on average 17.0) internal successors, (51), 3 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:20,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 08:57:20,041 INFO L93 Difference]: Finished difference Result 570 states and 836 transitions. [2021-11-09 08:57:20,041 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 08:57:20,042 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 570 states and 836 transitions. [2021-11-09 08:57:20,047 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 506 [2021-11-09 08:57:20,053 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 570 states to 570 states and 836 transitions. [2021-11-09 08:57:20,053 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 570 [2021-11-09 08:57:20,054 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 570 [2021-11-09 08:57:20,054 INFO L73 IsDeterministic]: Start isDeterministic. Operand 570 states and 836 transitions. [2021-11-09 08:57:20,055 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 08:57:20,055 INFO L681 BuchiCegarLoop]: Abstraction has 570 states and 836 transitions. [2021-11-09 08:57:20,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 570 states and 836 transitions. [2021-11-09 08:57:20,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 570 to 568. [2021-11-09 08:57:20,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 568 states, 568 states have (on average 1.4683098591549295) internal successors, (834), 567 states have internal predecessors, (834), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:20,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 568 states to 568 states and 834 transitions. [2021-11-09 08:57:20,071 INFO L704 BuchiCegarLoop]: Abstraction has 568 states and 834 transitions. [2021-11-09 08:57:20,071 INFO L587 BuchiCegarLoop]: Abstraction has 568 states and 834 transitions. [2021-11-09 08:57:20,071 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-09 08:57:20,071 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 568 states and 834 transitions. [2021-11-09 08:57:20,075 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 504 [2021-11-09 08:57:20,075 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 08:57:20,075 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 08:57:20,076 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:20,076 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:20,077 INFO L791 eck$LassoCheckResult]: Stem: 2588#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 2496#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2391#L491 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 2392#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 2531#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2500#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2501#L231-1 assume !(0 == ~M_E~0); 2489#L334-1 assume !(0 == ~T1_E~0); 2490#L339-1 assume !(0 == ~T2_E~0); 2576#L344-1 assume 0 == ~E_1~0;~E_1~0 := 1; 2452#L349-1 assume !(0 == ~E_2~0); 2453#L354-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2497#L156 assume !(1 == ~m_pc~0); 2491#L156-2 is_master_triggered_~__retres1~0 := 0; 2430#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2395#L168 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2396#L405 assume !(0 != activate_threads_~tmp~1); 2538#L405-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2393#L175 assume !(1 == ~t1_pc~0); 2394#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 2539#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2540#L187 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2589#L413 assume !(0 != activate_threads_~tmp___0~0); 2590#L413-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2717#L194 assume !(1 == ~t2_pc~0); 2709#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 2705#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2635#L206 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2463#L421 assume !(0 != activate_threads_~tmp___1~0); 2464#L421-2 assume !(1 == ~M_E~0); 2556#L367-1 assume !(1 == ~T1_E~0); 2413#L372-1 assume !(1 == ~T2_E~0); 2414#L377-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2417#L382-1 assume !(1 == ~E_2~0); 2447#L528-1 [2021-11-09 08:57:20,077 INFO L793 eck$LassoCheckResult]: Loop: 2447#L528-1 assume !false; 2789#L529 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 2787#L309 assume !false; 2785#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2714#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2708#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2704#L262 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 2702#L276 assume !(0 != eval_~tmp~0); 2703#L324 start_simulation_~kernel_st~0 := 2; 2786#L214-1 start_simulation_~kernel_st~0 := 3; 2784#L334-2 assume 0 == ~M_E~0;~M_E~0 := 1; 2783#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2782#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2780#L344-3 assume !(0 == ~E_1~0); 2779#L349-3 assume !(0 == ~E_2~0); 2778#L354-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2777#L156-9 assume !(1 == ~m_pc~0); 2776#L156-11 is_master_triggered_~__retres1~0 := 0; 2775#L167-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2773#L168-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2771#L405-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2769#L405-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2767#L175-9 assume !(1 == ~t1_pc~0); 2765#L175-11 is_transmit1_triggered_~__retres1~1 := 0; 2763#L186-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2761#L187-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2759#L413-9 assume !(0 != activate_threads_~tmp___0~0); 2757#L413-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2755#L194-9 assume 1 == ~t2_pc~0; 2752#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2750#L205-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2749#L206-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2748#L421-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2747#L421-11 assume 1 == ~M_E~0;~M_E~0 := 2; 2746#L367-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2745#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2742#L377-3 assume !(1 == ~E_1~0); 2740#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2738#L387-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2454#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2455#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2450#L262-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 2451#L547 assume !(0 == start_simulation_~tmp~3); 2484#L547-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2812#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2809#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2807#L262-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 2805#L502 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 2803#L509 stop_simulation_#res := stop_simulation_~__retres2~0; 2796#L510 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 2795#L560 assume !(0 != start_simulation_~tmp___0~1); 2447#L528-1 [2021-11-09 08:57:20,077 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:20,077 INFO L85 PathProgramCache]: Analyzing trace with hash 713469919, now seen corresponding path program 1 times [2021-11-09 08:57:20,077 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:20,078 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [500309742] [2021-11-09 08:57:20,078 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:20,078 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:20,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 08:57:20,106 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 08:57:20,106 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 08:57:20,107 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [500309742] [2021-11-09 08:57:20,107 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [500309742] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 08:57:20,107 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 08:57:20,107 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-09 08:57:20,107 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1250608579] [2021-11-09 08:57:20,108 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 08:57:20,108 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:20,108 INFO L85 PathProgramCache]: Analyzing trace with hash 1257676159, now seen corresponding path program 1 times [2021-11-09 08:57:20,108 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:20,109 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1201005367] [2021-11-09 08:57:20,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:20,109 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:20,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 08:57:20,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 08:57:20,147 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 08:57:20,147 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1201005367] [2021-11-09 08:57:20,147 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1201005367] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 08:57:20,147 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 08:57:20,148 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-09 08:57:20,148 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1104694044] [2021-11-09 08:57:20,148 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 08:57:20,148 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 08:57:20,149 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 08:57:20,149 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 08:57:20,149 INFO L87 Difference]: Start difference. First operand 568 states and 834 transitions. cyclomatic complexity: 268 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 2 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:20,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 08:57:20,176 INFO L93 Difference]: Finished difference Result 402 states and 580 transitions. [2021-11-09 08:57:20,176 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 08:57:20,176 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 402 states and 580 transitions. [2021-11-09 08:57:20,180 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 362 [2021-11-09 08:57:20,184 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 402 states to 402 states and 580 transitions. [2021-11-09 08:57:20,185 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 402 [2021-11-09 08:57:20,185 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 402 [2021-11-09 08:57:20,185 INFO L73 IsDeterministic]: Start isDeterministic. Operand 402 states and 580 transitions. [2021-11-09 08:57:20,186 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 08:57:20,186 INFO L681 BuchiCegarLoop]: Abstraction has 402 states and 580 transitions. [2021-11-09 08:57:20,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 402 states and 580 transitions. [2021-11-09 08:57:20,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 402 to 402. [2021-11-09 08:57:20,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 402 states, 402 states have (on average 1.4427860696517414) internal successors, (580), 401 states have internal predecessors, (580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:20,197 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 402 states to 402 states and 580 transitions. [2021-11-09 08:57:20,197 INFO L704 BuchiCegarLoop]: Abstraction has 402 states and 580 transitions. [2021-11-09 08:57:20,197 INFO L587 BuchiCegarLoop]: Abstraction has 402 states and 580 transitions. [2021-11-09 08:57:20,197 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-09 08:57:20,197 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 402 states and 580 transitions. [2021-11-09 08:57:20,200 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 362 [2021-11-09 08:57:20,200 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 08:57:20,200 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 08:57:20,201 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:20,201 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:20,201 INFO L791 eck$LassoCheckResult]: Stem: 3554#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 3471#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 3370#L491 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 3371#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 3504#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3475#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3476#L231-1 assume !(0 == ~M_E~0); 3465#L334-1 assume !(0 == ~T1_E~0); 3466#L339-1 assume !(0 == ~T2_E~0); 3544#L344-1 assume !(0 == ~E_1~0); 3429#L349-1 assume !(0 == ~E_2~0); 3430#L354-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3472#L156 assume !(1 == ~m_pc~0); 3467#L156-2 is_master_triggered_~__retres1~0 := 0; 3411#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3374#L168 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3375#L405 assume !(0 != activate_threads_~tmp~1); 3511#L405-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3372#L175 assume !(1 == ~t1_pc~0); 3373#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 3512#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3513#L187 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3555#L413 assume !(0 != activate_threads_~tmp___0~0); 3536#L413-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3537#L194 assume !(1 == ~t2_pc~0); 3538#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 3521#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3456#L206 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3440#L421 assume !(0 != activate_threads_~tmp___1~0); 3441#L421-2 assume !(1 == ~M_E~0); 3529#L367-1 assume !(1 == ~T1_E~0); 3392#L372-1 assume !(1 == ~T2_E~0); 3393#L377-1 assume !(1 == ~E_1~0); 3396#L382-1 assume !(1 == ~E_2~0); 3413#L528-1 [2021-11-09 08:57:20,202 INFO L793 eck$LassoCheckResult]: Loop: 3413#L528-1 assume !false; 3493#L529 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 3380#L309 assume !false; 3483#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3383#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3384#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3506#L262 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 3365#L276 assume !(0 != eval_~tmp~0); 3367#L324 start_simulation_~kernel_st~0 := 2; 3399#L214-1 start_simulation_~kernel_st~0 := 3; 3499#L334-2 assume 0 == ~M_E~0;~M_E~0 := 1; 3500#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3509#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3530#L344-3 assume !(0 == ~E_1~0); 3522#L349-3 assume !(0 == ~E_2~0); 3449#L354-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3450#L156-9 assume !(1 == ~m_pc~0); 3376#L156-11 is_master_triggered_~__retres1~0 := 0; 3377#L167-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3505#L168-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3520#L405-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3414#L405-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3415#L175-9 assume !(1 == ~t1_pc~0); 3423#L175-11 is_transmit1_triggered_~__retres1~1 := 0; 3397#L186-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3398#L187-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3464#L413-9 assume !(0 != activate_threads_~tmp___0~0); 3438#L413-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3439#L194-9 assume !(1 == ~t2_pc~0); 3443#L194-11 is_transmit2_triggered_~__retres1~2 := 0; 3444#L205-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3527#L206-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3528#L421-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3431#L421-11 assume 1 == ~M_E~0;~M_E~0 := 2; 3432#L367-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3451#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3407#L377-3 assume !(1 == ~E_1~0); 3408#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3446#L387-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3433#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3434#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3427#L262-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 3428#L547 assume !(0 == start_simulation_~tmp~3); 3460#L547-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3453#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3454#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3492#L262-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 3469#L502 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 3470#L509 stop_simulation_#res := stop_simulation_~__retres2~0; 3487#L510 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 3412#L560 assume !(0 != start_simulation_~tmp___0~1); 3413#L528-1 [2021-11-09 08:57:20,202 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:20,202 INFO L85 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 2 times [2021-11-09 08:57:20,202 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:20,203 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2084121154] [2021-11-09 08:57:20,203 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:20,203 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:20,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:20,233 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 08:57:20,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:20,250 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 08:57:20,250 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:20,251 INFO L85 PathProgramCache]: Analyzing trace with hash 2037657088, now seen corresponding path program 1 times [2021-11-09 08:57:20,251 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:20,251 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [836863315] [2021-11-09 08:57:20,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:20,251 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:20,258 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 08:57:20,284 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 08:57:20,284 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 08:57:20,285 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [836863315] [2021-11-09 08:57:20,285 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [836863315] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 08:57:20,285 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 08:57:20,285 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-09 08:57:20,286 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2039068819] [2021-11-09 08:57:20,286 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 08:57:20,286 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 08:57:20,287 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-09 08:57:20,287 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-09 08:57:20,287 INFO L87 Difference]: Start difference. First operand 402 states and 580 transitions. cyclomatic complexity: 180 Second operand has 5 states, 5 states have (on average 10.2) internal successors, (51), 5 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:20,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 08:57:20,367 INFO L93 Difference]: Finished difference Result 670 states and 947 transitions. [2021-11-09 08:57:20,367 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-11-09 08:57:20,367 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 670 states and 947 transitions. [2021-11-09 08:57:20,373 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 625 [2021-11-09 08:57:20,380 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 670 states to 670 states and 947 transitions. [2021-11-09 08:57:20,380 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 670 [2021-11-09 08:57:20,382 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 670 [2021-11-09 08:57:20,383 INFO L73 IsDeterministic]: Start isDeterministic. Operand 670 states and 947 transitions. [2021-11-09 08:57:20,384 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 08:57:20,384 INFO L681 BuchiCegarLoop]: Abstraction has 670 states and 947 transitions. [2021-11-09 08:57:20,385 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 670 states and 947 transitions. [2021-11-09 08:57:20,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 670 to 411. [2021-11-09 08:57:20,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 411 states, 411 states have (on average 1.4330900243309002) internal successors, (589), 410 states have internal predecessors, (589), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:20,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 411 states to 411 states and 589 transitions. [2021-11-09 08:57:20,398 INFO L704 BuchiCegarLoop]: Abstraction has 411 states and 589 transitions. [2021-11-09 08:57:20,400 INFO L587 BuchiCegarLoop]: Abstraction has 411 states and 589 transitions. [2021-11-09 08:57:20,401 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-09 08:57:20,401 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 411 states and 589 transitions. [2021-11-09 08:57:20,403 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 371 [2021-11-09 08:57:20,404 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 08:57:20,404 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 08:57:20,407 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:20,407 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:20,408 INFO L791 eck$LassoCheckResult]: Stem: 4668#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 4567#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4455#L491 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 4456#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 4604#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4571#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4572#L231-1 assume !(0 == ~M_E~0); 4561#L334-1 assume !(0 == ~T1_E~0); 4562#L339-1 assume !(0 == ~T2_E~0); 4659#L344-1 assume !(0 == ~E_1~0); 4521#L349-1 assume !(0 == ~E_2~0); 4522#L354-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4568#L156 assume !(1 == ~m_pc~0); 4563#L156-2 is_master_triggered_~__retres1~0 := 0; 4498#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4461#L168 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4462#L405 assume !(0 != activate_threads_~tmp~1); 4614#L405-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4457#L175 assume !(1 == ~t1_pc~0); 4458#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 4615#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4616#L187 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4670#L413 assume !(0 != activate_threads_~tmp___0~0); 4643#L413-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4644#L194 assume !(1 == ~t2_pc~0); 4649#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 4626#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4551#L206 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4532#L421 assume !(0 != activate_threads_~tmp___1~0); 4533#L421-2 assume !(1 == ~M_E~0); 4637#L367-1 assume !(1 == ~T1_E~0); 4479#L372-1 assume !(1 == ~T2_E~0); 4480#L377-1 assume !(1 == ~E_1~0); 4484#L382-1 assume !(1 == ~E_2~0); 4516#L528-1 [2021-11-09 08:57:20,408 INFO L793 eck$LassoCheckResult]: Loop: 4516#L528-1 assume !false; 4788#L529 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 4787#L309 assume !false; 4579#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4468#L244 assume !(0 == ~m_st~0); 4470#L248 assume !(0 == ~t1_st~0); 4595#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 4596#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4699#L262 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 4700#L276 assume !(0 != eval_~tmp~0); 4487#L324 start_simulation_~kernel_st~0 := 2; 4488#L214-1 start_simulation_~kernel_st~0 := 3; 4715#L334-2 assume 0 == ~M_E~0;~M_E~0 := 1; 4612#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4613#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4711#L344-3 assume !(0 == ~E_1~0); 4706#L349-3 assume !(0 == ~E_2~0); 4543#L354-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4544#L156-9 assume !(1 == ~m_pc~0); 4463#L156-11 is_master_triggered_~__retres1~0 := 0; 4464#L167-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4622#L168-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4623#L405-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4503#L405-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4504#L175-9 assume !(1 == ~t1_pc~0); 4512#L175-11 is_transmit1_triggered_~__retres1~1 := 0; 4513#L186-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4669#L187-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4559#L413-9 assume !(0 != activate_threads_~tmp___0~0); 4560#L413-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4653#L194-9 assume !(1 == ~t2_pc~0); 4537#L194-11 is_transmit2_triggered_~__retres1~2 := 0; 4538#L205-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4635#L206-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4636#L421-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4662#L421-11 assume 1 == ~M_E~0;~M_E~0 := 2; 4593#L367-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4594#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4496#L377-3 assume !(1 == ~E_1~0); 4497#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4663#L387-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4664#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4771#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4769#L262-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 4765#L547 assume !(0 == start_simulation_~tmp~3); 4766#L547-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4815#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4812#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4811#L262-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 4809#L502 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 4798#L509 stop_simulation_#res := stop_simulation_~__retres2~0; 4797#L510 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 4796#L560 assume !(0 != start_simulation_~tmp___0~1); 4516#L528-1 [2021-11-09 08:57:20,409 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:20,410 INFO L85 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 3 times [2021-11-09 08:57:20,410 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:20,410 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1851320280] [2021-11-09 08:57:20,410 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:20,410 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:20,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:20,434 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 08:57:20,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:20,463 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 08:57:20,470 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:20,470 INFO L85 PathProgramCache]: Analyzing trace with hash 1585704135, now seen corresponding path program 1 times [2021-11-09 08:57:20,470 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:20,470 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1612566044] [2021-11-09 08:57:20,470 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:20,471 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:20,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 08:57:20,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 08:57:20,539 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 08:57:20,539 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1612566044] [2021-11-09 08:57:20,540 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1612566044] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 08:57:20,540 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 08:57:20,540 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-09 08:57:20,540 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1485026024] [2021-11-09 08:57:20,541 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 08:57:20,541 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 08:57:20,541 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-09 08:57:20,542 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-09 08:57:20,542 INFO L87 Difference]: Start difference. First operand 411 states and 589 transitions. cyclomatic complexity: 180 Second operand has 5 states, 5 states have (on average 10.6) internal successors, (53), 5 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:20,646 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 08:57:20,646 INFO L93 Difference]: Finished difference Result 1194 states and 1698 transitions. [2021-11-09 08:57:20,647 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2021-11-09 08:57:20,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1194 states and 1698 transitions. [2021-11-09 08:57:20,658 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1139 [2021-11-09 08:57:20,670 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1194 states to 1194 states and 1698 transitions. [2021-11-09 08:57:20,670 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1194 [2021-11-09 08:57:20,672 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1194 [2021-11-09 08:57:20,672 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1194 states and 1698 transitions. [2021-11-09 08:57:20,674 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 08:57:20,674 INFO L681 BuchiCegarLoop]: Abstraction has 1194 states and 1698 transitions. [2021-11-09 08:57:20,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1194 states and 1698 transitions. [2021-11-09 08:57:20,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1194 to 420. [2021-11-09 08:57:20,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 420 states, 420 states have (on average 1.4238095238095239) internal successors, (598), 419 states have internal predecessors, (598), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:20,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 420 states to 420 states and 598 transitions. [2021-11-09 08:57:20,693 INFO L704 BuchiCegarLoop]: Abstraction has 420 states and 598 transitions. [2021-11-09 08:57:20,693 INFO L587 BuchiCegarLoop]: Abstraction has 420 states and 598 transitions. [2021-11-09 08:57:20,693 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-09 08:57:20,694 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 420 states and 598 transitions. [2021-11-09 08:57:20,696 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 380 [2021-11-09 08:57:20,696 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 08:57:20,696 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 08:57:20,697 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:20,697 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:20,698 INFO L791 eck$LassoCheckResult]: Stem: 6286#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 6186#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6077#L491 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 6078#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 6224#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6192#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6193#L231-1 assume !(0 == ~M_E~0); 6181#L334-1 assume !(0 == ~T1_E~0); 6182#L339-1 assume !(0 == ~T2_E~0); 6276#L344-1 assume !(0 == ~E_1~0); 6140#L349-1 assume !(0 == ~E_2~0); 6141#L354-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6189#L156 assume !(1 == ~m_pc~0); 6183#L156-2 is_master_triggered_~__retres1~0 := 0; 6120#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6083#L168 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6084#L405 assume !(0 != activate_threads_~tmp~1); 6232#L405-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6079#L175 assume !(1 == ~t1_pc~0); 6080#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 6233#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6234#L187 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6289#L413 assume !(0 != activate_threads_~tmp___0~0); 6261#L413-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6262#L194 assume !(1 == ~t2_pc~0); 6266#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 6244#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6165#L206 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6153#L421 assume !(0 != activate_threads_~tmp___1~0); 6154#L421-2 assume !(1 == ~M_E~0); 6255#L367-1 assume !(1 == ~T1_E~0); 6101#L372-1 assume !(1 == ~T2_E~0); 6102#L377-1 assume !(1 == ~E_1~0); 6106#L382-1 assume !(1 == ~E_2~0); 6138#L528-1 [2021-11-09 08:57:20,698 INFO L793 eck$LassoCheckResult]: Loop: 6138#L528-1 assume !false; 6212#L529 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 6087#L309 assume !false; 6251#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6394#L244 assume !(0 == ~m_st~0); 6341#L248 assume !(0 == ~t1_st~0); 6340#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 6339#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6327#L262 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 6328#L276 assume !(0 != eval_~tmp~0); 6107#L324 start_simulation_~kernel_st~0 := 2; 6108#L214-1 start_simulation_~kernel_st~0 := 3; 6247#L334-2 assume 0 == ~M_E~0;~M_E~0 := 1; 6337#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6290#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6256#L344-3 assume !(0 == ~E_1~0); 6246#L349-3 assume !(0 == ~E_2~0); 6163#L354-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6164#L156-9 assume !(1 == ~m_pc~0); 6088#L156-11 is_master_triggered_~__retres1~0 := 0; 6089#L167-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6460#L168-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6291#L405-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6292#L405-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6274#L175-9 assume !(1 == ~t1_pc~0); 6275#L175-11 is_transmit1_triggered_~__retres1~1 := 0; 6109#L186-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6110#L187-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6179#L413-9 assume !(0 != activate_threads_~tmp___0~0); 6180#L413-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6272#L194-9 assume 1 == ~t2_pc~0; 6252#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6157#L205-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6253#L206-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6254#L421-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6144#L421-11 assume 1 == ~M_E~0;~M_E~0 := 2; 6145#L367-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6455#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6118#L377-3 assume !(1 == ~E_1~0); 6119#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6282#L387-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6146#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6147#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6142#L262-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 6143#L547 assume !(0 == start_simulation_~tmp~3); 6178#L547-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6265#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6420#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6241#L262-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 6187#L502 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6188#L509 stop_simulation_#res := stop_simulation_~__retres2~0; 6418#L510 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 6417#L560 assume !(0 != start_simulation_~tmp___0~1); 6138#L528-1 [2021-11-09 08:57:20,698 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:20,698 INFO L85 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 4 times [2021-11-09 08:57:20,699 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:20,699 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2002541774] [2021-11-09 08:57:20,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:20,708 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:20,720 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:20,720 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 08:57:20,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:20,746 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 08:57:20,747 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:20,748 INFO L85 PathProgramCache]: Analyzing trace with hash 805663624, now seen corresponding path program 1 times [2021-11-09 08:57:20,748 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:20,748 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [757802479] [2021-11-09 08:57:20,748 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:20,748 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:20,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 08:57:20,839 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 08:57:20,840 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 08:57:20,840 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [757802479] [2021-11-09 08:57:20,840 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [757802479] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 08:57:20,840 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 08:57:20,840 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-09 08:57:20,843 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1832001648] [2021-11-09 08:57:20,843 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 08:57:20,843 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 08:57:20,844 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-09 08:57:20,844 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-09 08:57:20,844 INFO L87 Difference]: Start difference. First operand 420 states and 598 transitions. cyclomatic complexity: 180 Second operand has 5 states, 5 states have (on average 10.6) internal successors, (53), 5 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:20,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 08:57:20,962 INFO L93 Difference]: Finished difference Result 921 states and 1298 transitions. [2021-11-09 08:57:20,963 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-09 08:57:20,963 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 921 states and 1298 transitions. [2021-11-09 08:57:20,972 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 881 [2021-11-09 08:57:20,980 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 921 states to 921 states and 1298 transitions. [2021-11-09 08:57:20,980 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 921 [2021-11-09 08:57:20,981 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 921 [2021-11-09 08:57:20,981 INFO L73 IsDeterministic]: Start isDeterministic. Operand 921 states and 1298 transitions. [2021-11-09 08:57:20,983 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 08:57:20,983 INFO L681 BuchiCegarLoop]: Abstraction has 921 states and 1298 transitions. [2021-11-09 08:57:20,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 921 states and 1298 transitions. [2021-11-09 08:57:20,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 921 to 441. [2021-11-09 08:57:20,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 441 states, 441 states have (on average 1.3968253968253967) internal successors, (616), 440 states have internal predecessors, (616), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:20,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 441 states to 441 states and 616 transitions. [2021-11-09 08:57:20,997 INFO L704 BuchiCegarLoop]: Abstraction has 441 states and 616 transitions. [2021-11-09 08:57:20,997 INFO L587 BuchiCegarLoop]: Abstraction has 441 states and 616 transitions. [2021-11-09 08:57:20,997 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-09 08:57:20,997 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 441 states and 616 transitions. [2021-11-09 08:57:21,000 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 401 [2021-11-09 08:57:21,000 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 08:57:21,000 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 08:57:21,001 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:21,001 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:21,003 INFO L791 eck$LassoCheckResult]: Stem: 7634#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 7539#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 7431#L491 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 7432#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 7575#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7545#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7546#L231-1 assume !(0 == ~M_E~0); 7535#L334-1 assume !(0 == ~T1_E~0); 7536#L339-1 assume !(0 == ~T2_E~0); 7625#L344-1 assume !(0 == ~E_1~0); 7495#L349-1 assume !(0 == ~E_2~0); 7496#L354-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7542#L156 assume !(1 == ~m_pc~0); 7537#L156-2 is_master_triggered_~__retres1~0 := 0; 7474#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7437#L168 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7438#L405 assume !(0 != activate_threads_~tmp~1); 7581#L405-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7433#L175 assume !(1 == ~t1_pc~0); 7434#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 7582#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7583#L187 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7635#L413 assume !(0 != activate_threads_~tmp___0~0); 7610#L413-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7611#L194 assume !(1 == ~t2_pc~0); 7613#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 7593#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7520#L206 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7509#L421 assume !(0 != activate_threads_~tmp___1~0); 7510#L421-2 assume !(1 == ~M_E~0); 7603#L367-1 assume !(1 == ~T1_E~0); 7455#L372-1 assume !(1 == ~T2_E~0); 7456#L377-1 assume !(1 == ~E_1~0); 7460#L382-1 assume !(1 == ~E_2~0); 7492#L528-1 [2021-11-09 08:57:21,004 INFO L793 eck$LassoCheckResult]: Loop: 7492#L528-1 assume !false; 7680#L529 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 7679#L309 assume !false; 7678#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7675#L244 assume !(0 == ~m_st~0); 7676#L248 assume !(0 == ~t1_st~0); 7677#L252 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 7674#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7672#L262 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 7670#L276 assume !(0 != eval_~tmp~0); 7669#L324 start_simulation_~kernel_st~0 := 2; 7668#L214-1 start_simulation_~kernel_st~0 := 3; 7667#L334-2 assume 0 == ~M_E~0;~M_E~0 := 1; 7666#L334-4 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7664#L339-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7662#L344-3 assume !(0 == ~E_1~0); 7659#L349-3 assume !(0 == ~E_2~0); 7656#L354-3 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7616#L156-9 assume !(1 == ~m_pc~0); 7617#L156-11 is_master_triggered_~__retres1~0 := 0; 7749#L167-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7748#L168-3 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7747#L405-9 assume !(0 != activate_threads_~tmp~1); 7746#L405-11 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7745#L175-9 assume !(1 == ~t1_pc~0); 7744#L175-11 is_transmit1_triggered_~__retres1~1 := 0; 7742#L186-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7740#L187-3 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7738#L413-9 assume !(0 != activate_threads_~tmp___0~0); 7736#L413-11 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7734#L194-9 assume 1 == ~t2_pc~0; 7731#L195-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7729#L205-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7727#L206-3 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7725#L421-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7723#L421-11 assume 1 == ~M_E~0;~M_E~0 := 2; 7721#L367-3 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7718#L372-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7716#L377-3 assume !(1 == ~E_1~0); 7714#L382-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7712#L387-3 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7710#L244-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 7706#L261-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7704#L262-1 start_simulation_#t~ret15 := exists_runnable_thread_#res;start_simulation_~tmp~3 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 7702#L547 assume !(0 == start_simulation_~tmp~3); 7700#L547-1 havoc stop_simulation_#res;havoc stop_simulation_#t~ret14, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7699#L244-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 7696#L261-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7694#L262-2 stop_simulation_#t~ret14 := exists_runnable_thread_#res;stop_simulation_~tmp~2 := stop_simulation_#t~ret14;havoc stop_simulation_#t~ret14; 7692#L502 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7690#L509 stop_simulation_#res := stop_simulation_~__retres2~0; 7689#L510 start_simulation_#t~ret16 := stop_simulation_#res;start_simulation_~tmp___0~1 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 7687#L560 assume !(0 != start_simulation_~tmp___0~1); 7492#L528-1 [2021-11-09 08:57:21,004 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:21,004 INFO L85 PathProgramCache]: Analyzing trace with hash 854018591, now seen corresponding path program 5 times [2021-11-09 08:57:21,004 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:21,005 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387066109] [2021-11-09 08:57:21,005 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:21,005 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:21,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:21,015 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 08:57:21,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:21,032 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 08:57:21,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:21,033 INFO L85 PathProgramCache]: Analyzing trace with hash 1507263498, now seen corresponding path program 1 times [2021-11-09 08:57:21,033 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:21,033 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1999909339] [2021-11-09 08:57:21,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:21,033 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:21,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 08:57:21,069 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 08:57:21,069 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 08:57:21,070 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1999909339] [2021-11-09 08:57:21,070 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1999909339] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 08:57:21,070 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 08:57:21,070 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 08:57:21,070 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [393707933] [2021-11-09 08:57:21,071 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-09 08:57:21,071 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 08:57:21,071 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 08:57:21,073 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 08:57:21,073 INFO L87 Difference]: Start difference. First operand 441 states and 616 transitions. cyclomatic complexity: 177 Second operand has 3 states, 3 states have (on average 17.666666666666668) internal successors, (53), 3 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:21,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 08:57:21,114 INFO L93 Difference]: Finished difference Result 675 states and 925 transitions. [2021-11-09 08:57:21,114 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 08:57:21,114 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 675 states and 925 transitions. [2021-11-09 08:57:21,120 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 633 [2021-11-09 08:57:21,125 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 675 states to 675 states and 925 transitions. [2021-11-09 08:57:21,126 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 675 [2021-11-09 08:57:21,126 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 675 [2021-11-09 08:57:21,127 INFO L73 IsDeterministic]: Start isDeterministic. Operand 675 states and 925 transitions. [2021-11-09 08:57:21,128 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 08:57:21,128 INFO L681 BuchiCegarLoop]: Abstraction has 675 states and 925 transitions. [2021-11-09 08:57:21,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 675 states and 925 transitions. [2021-11-09 08:57:21,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 675 to 643. [2021-11-09 08:57:21,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 643 states, 643 states have (on average 1.374805598755832) internal successors, (884), 642 states have internal predecessors, (884), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:21,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 643 states to 643 states and 884 transitions. [2021-11-09 08:57:21,143 INFO L704 BuchiCegarLoop]: Abstraction has 643 states and 884 transitions. [2021-11-09 08:57:21,143 INFO L587 BuchiCegarLoop]: Abstraction has 643 states and 884 transitions. [2021-11-09 08:57:21,143 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-09 08:57:21,143 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 643 states and 884 transitions. [2021-11-09 08:57:21,147 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 601 [2021-11-09 08:57:21,147 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 08:57:21,147 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 08:57:21,148 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:21,148 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:21,148 INFO L791 eck$LassoCheckResult]: Stem: 8761#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 8661#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 8553#L491 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 8554#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 8699#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8665#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8666#L231-1 assume !(0 == ~M_E~0); 8655#L334-1 assume !(0 == ~T1_E~0); 8656#L339-1 assume !(0 == ~T2_E~0); 8751#L344-1 assume !(0 == ~E_1~0); 8616#L349-1 assume !(0 == ~E_2~0); 8617#L354-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8662#L156 assume !(1 == ~m_pc~0); 8657#L156-2 is_master_triggered_~__retres1~0 := 0; 8596#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8559#L168 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8560#L405 assume !(0 != activate_threads_~tmp~1); 8711#L405-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8555#L175 assume !(1 == ~t1_pc~0); 8556#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 8712#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8713#L187 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8762#L413 assume !(0 != activate_threads_~tmp___0~0); 8741#L413-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8742#L194 assume !(1 == ~t2_pc~0); 8743#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 8723#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8644#L206 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8626#L421 assume !(0 != activate_threads_~tmp___1~0); 8627#L421-2 assume !(1 == ~M_E~0); 8732#L367-1 assume !(1 == ~T1_E~0); 8576#L372-1 assume !(1 == ~T2_E~0); 8577#L377-1 assume !(1 == ~E_1~0); 8580#L382-1 assume !(1 == ~E_2~0); 8611#L528-1 assume !false; 9144#L529 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 9143#L309 [2021-11-09 08:57:21,148 INFO L793 eck$LassoCheckResult]: Loop: 9143#L309 assume !false; 9142#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 9141#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 9140#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 9138#L262 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 8551#L276 assume 0 != eval_~tmp~0; 8552#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 8705#L284 assume !(0 != eval_~tmp_ndt_1~0); 8706#L281 assume !(0 == ~t1_st~0); 8629#L295 assume !(0 == ~t2_st~0); 9143#L309 [2021-11-09 08:57:21,149 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:21,149 INFO L85 PathProgramCache]: Analyzing trace with hash 373117697, now seen corresponding path program 1 times [2021-11-09 08:57:21,149 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:21,153 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [292581594] [2021-11-09 08:57:21,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:21,153 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:21,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:21,162 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 08:57:21,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:21,189 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 08:57:21,190 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:21,190 INFO L85 PathProgramCache]: Analyzing trace with hash -1206180399, now seen corresponding path program 1 times [2021-11-09 08:57:21,190 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:21,191 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [213596646] [2021-11-09 08:57:21,191 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:21,191 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:21,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:21,196 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 08:57:21,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:21,203 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 08:57:21,203 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:21,203 INFO L85 PathProgramCache]: Analyzing trace with hash 202160337, now seen corresponding path program 1 times [2021-11-09 08:57:21,204 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:21,204 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [853368996] [2021-11-09 08:57:21,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:21,204 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:21,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 08:57:21,247 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 08:57:21,247 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 08:57:21,247 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [853368996] [2021-11-09 08:57:21,248 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [853368996] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 08:57:21,248 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 08:57:21,248 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 08:57:21,248 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [80040826] [2021-11-09 08:57:21,360 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 08:57:21,361 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 08:57:21,361 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 08:57:21,361 INFO L87 Difference]: Start difference. First operand 643 states and 884 transitions. cyclomatic complexity: 244 Second operand has 3 states, 3 states have (on average 15.333333333333334) internal successors, (46), 3 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:21,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 08:57:21,428 INFO L93 Difference]: Finished difference Result 1127 states and 1531 transitions. [2021-11-09 08:57:21,428 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 08:57:21,428 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1127 states and 1531 transitions. [2021-11-09 08:57:21,449 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 995 [2021-11-09 08:57:21,458 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1127 states to 1127 states and 1531 transitions. [2021-11-09 08:57:21,472 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1127 [2021-11-09 08:57:21,473 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1127 [2021-11-09 08:57:21,473 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1127 states and 1531 transitions. [2021-11-09 08:57:21,475 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 08:57:21,476 INFO L681 BuchiCegarLoop]: Abstraction has 1127 states and 1531 transitions. [2021-11-09 08:57:21,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1127 states and 1531 transitions. [2021-11-09 08:57:21,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1127 to 1058. [2021-11-09 08:57:21,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1058 states, 1058 states have (on average 1.3648393194706994) internal successors, (1444), 1057 states have internal predecessors, (1444), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:21,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1058 states to 1058 states and 1444 transitions. [2021-11-09 08:57:21,535 INFO L704 BuchiCegarLoop]: Abstraction has 1058 states and 1444 transitions. [2021-11-09 08:57:21,535 INFO L587 BuchiCegarLoop]: Abstraction has 1058 states and 1444 transitions. [2021-11-09 08:57:21,536 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-09 08:57:21,536 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1058 states and 1444 transitions. [2021-11-09 08:57:21,557 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 959 [2021-11-09 08:57:21,557 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 08:57:21,557 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 08:57:21,557 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:21,558 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:21,558 INFO L791 eck$LassoCheckResult]: Stem: 10538#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 10440#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 10331#L491 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 10332#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 10480#L221-1 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 10481#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11071#L231-1 assume !(0 == ~M_E~0); 11067#L334-1 assume !(0 == ~T1_E~0); 11065#L339-1 assume !(0 == ~T2_E~0); 11062#L344-1 assume !(0 == ~E_1~0); 11060#L349-1 assume !(0 == ~E_2~0); 11058#L354-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11056#L156 assume !(1 == ~m_pc~0); 11054#L156-2 is_master_triggered_~__retres1~0 := 0; 11052#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11050#L168 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11048#L405 assume !(0 != activate_threads_~tmp~1); 11047#L405-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11046#L175 assume !(1 == ~t1_pc~0); 11045#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 11044#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11043#L187 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11042#L413 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10520#L413-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10521#L194 assume !(1 == ~t2_pc~0); 10522#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 10501#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10418#L206 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10404#L421 assume !(0 != activate_threads_~tmp___1~0); 10405#L421-2 assume !(1 == ~M_E~0); 10513#L367-1 assume !(1 == ~T1_E~0); 10354#L372-1 assume !(1 == ~T2_E~0); 10355#L377-1 assume !(1 == ~E_1~0); 10358#L382-1 assume !(1 == ~E_2~0); 10389#L528-1 assume !false; 11381#L529 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 11380#L309 [2021-11-09 08:57:21,558 INFO L793 eck$LassoCheckResult]: Loop: 11380#L309 assume !false; 11379#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 11378#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 10550#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 10551#L262 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 11277#L276 assume 0 != eval_~tmp~0; 11250#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 10485#L284 assume !(0 != eval_~tmp_ndt_1~0); 10486#L281 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 10406#L298 assume !(0 != eval_~tmp_ndt_2~0); 10407#L295 assume !(0 == ~t2_st~0); 11380#L309 [2021-11-09 08:57:21,558 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:21,559 INFO L85 PathProgramCache]: Analyzing trace with hash 1658994561, now seen corresponding path program 1 times [2021-11-09 08:57:21,559 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:21,559 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1220459602] [2021-11-09 08:57:21,559 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:21,559 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:21,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 08:57:21,603 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 08:57:21,603 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 08:57:21,603 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1220459602] [2021-11-09 08:57:21,603 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1220459602] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 08:57:21,604 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 08:57:21,604 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-09 08:57:21,604 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1845645848] [2021-11-09 08:57:21,604 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-09 08:57:21,605 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:21,605 INFO L85 PathProgramCache]: Analyzing trace with hash 1263010541, now seen corresponding path program 1 times [2021-11-09 08:57:21,605 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:21,605 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2138768289] [2021-11-09 08:57:21,605 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:21,606 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:21,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:21,609 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 08:57:21,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:21,613 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 08:57:21,734 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 08:57:21,735 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 08:57:21,735 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 08:57:21,735 INFO L87 Difference]: Start difference. First operand 1058 states and 1444 transitions. cyclomatic complexity: 390 Second operand has 3 states, 3 states have (on average 12.0) internal successors, (36), 3 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:21,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 08:57:21,745 INFO L93 Difference]: Finished difference Result 890 states and 1214 transitions. [2021-11-09 08:57:21,746 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 08:57:21,746 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 890 states and 1214 transitions. [2021-11-09 08:57:21,752 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 848 [2021-11-09 08:57:21,759 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 890 states to 890 states and 1214 transitions. [2021-11-09 08:57:21,760 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 890 [2021-11-09 08:57:21,761 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 890 [2021-11-09 08:57:21,761 INFO L73 IsDeterministic]: Start isDeterministic. Operand 890 states and 1214 transitions. [2021-11-09 08:57:21,762 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 08:57:21,762 INFO L681 BuchiCegarLoop]: Abstraction has 890 states and 1214 transitions. [2021-11-09 08:57:21,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 890 states and 1214 transitions. [2021-11-09 08:57:21,777 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 890 to 890. [2021-11-09 08:57:21,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 890 states, 890 states have (on average 1.3640449438202247) internal successors, (1214), 889 states have internal predecessors, (1214), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:21,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 890 states to 890 states and 1214 transitions. [2021-11-09 08:57:21,783 INFO L704 BuchiCegarLoop]: Abstraction has 890 states and 1214 transitions. [2021-11-09 08:57:21,783 INFO L587 BuchiCegarLoop]: Abstraction has 890 states and 1214 transitions. [2021-11-09 08:57:21,783 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-09 08:57:21,783 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 890 states and 1214 transitions. [2021-11-09 08:57:21,788 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 848 [2021-11-09 08:57:21,789 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 08:57:21,789 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 08:57:21,789 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:21,790 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:21,790 INFO L791 eck$LassoCheckResult]: Stem: 12503#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 12393#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 12285#L491 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 12286#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 12432#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12399#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12400#L231-1 assume !(0 == ~M_E~0); 12389#L334-1 assume !(0 == ~T1_E~0); 12390#L339-1 assume !(0 == ~T2_E~0); 12491#L344-1 assume !(0 == ~E_1~0); 12346#L349-1 assume !(0 == ~E_2~0); 12347#L354-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12396#L156 assume !(1 == ~m_pc~0); 12391#L156-2 is_master_triggered_~__retres1~0 := 0; 12326#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12291#L168 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12292#L405 assume !(0 != activate_threads_~tmp~1); 12442#L405-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12287#L175 assume !(1 == ~t1_pc~0); 12288#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 12443#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12444#L187 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12504#L413 assume !(0 != activate_threads_~tmp___0~0); 12476#L413-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12477#L194 assume !(1 == ~t2_pc~0); 12481#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 12454#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12371#L206 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12359#L421 assume !(0 != activate_threads_~tmp___1~0); 12360#L421-2 assume !(1 == ~M_E~0); 12468#L367-1 assume !(1 == ~T1_E~0); 12308#L372-1 assume !(1 == ~T2_E~0); 12309#L377-1 assume !(1 == ~E_1~0); 12312#L382-1 assume !(1 == ~E_2~0); 12343#L528-1 assume !false; 13137#L529 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 13135#L309 [2021-11-09 08:57:21,790 INFO L793 eck$LassoCheckResult]: Loop: 13135#L309 assume !false; 13134#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 13132#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 13131#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 13130#L262 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 13129#L276 assume 0 != eval_~tmp~0; 13128#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 12438#L284 assume !(0 != eval_~tmp_ndt_1~0); 12439#L281 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 12859#L298 assume !(0 != eval_~tmp_ndt_2~0); 12920#L295 assume !(0 == ~t2_st~0); 13135#L309 [2021-11-09 08:57:21,791 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:21,791 INFO L85 PathProgramCache]: Analyzing trace with hash 373117697, now seen corresponding path program 2 times [2021-11-09 08:57:21,791 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:21,791 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1174837133] [2021-11-09 08:57:21,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:21,792 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:21,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:21,799 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 08:57:21,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:21,811 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 08:57:21,812 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:21,812 INFO L85 PathProgramCache]: Analyzing trace with hash 1263010541, now seen corresponding path program 2 times [2021-11-09 08:57:21,812 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:21,812 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [358057681] [2021-11-09 08:57:21,812 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:21,813 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:21,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:21,816 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 08:57:21,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:21,820 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 08:57:21,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:21,821 INFO L85 PathProgramCache]: Analyzing trace with hash 1971900397, now seen corresponding path program 1 times [2021-11-09 08:57:21,821 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:21,821 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1318436566] [2021-11-09 08:57:21,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:21,821 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:21,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-09 08:57:21,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-09 08:57:21,849 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-09 08:57:21,849 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1318436566] [2021-11-09 08:57:21,849 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1318436566] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-09 08:57:21,849 INFO L186 FreeRefinementEngine]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2021-11-09 08:57:21,849 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-09 08:57:21,850 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [184481711] [2021-11-09 08:57:21,937 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-09 08:57:21,938 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-09 08:57:21,938 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-09 08:57:21,939 INFO L87 Difference]: Start difference. First operand 890 states and 1214 transitions. cyclomatic complexity: 326 Second operand has 3 states, 2 states have (on average 23.5) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:22,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-09 08:57:22,001 INFO L93 Difference]: Finished difference Result 1558 states and 2113 transitions. [2021-11-09 08:57:22,001 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-09 08:57:22,001 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1558 states and 2113 transitions. [2021-11-09 08:57:22,012 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1511 [2021-11-09 08:57:22,025 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1558 states to 1558 states and 2113 transitions. [2021-11-09 08:57:22,025 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1558 [2021-11-09 08:57:22,027 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1558 [2021-11-09 08:57:22,027 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1558 states and 2113 transitions. [2021-11-09 08:57:22,029 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-09 08:57:22,029 INFO L681 BuchiCegarLoop]: Abstraction has 1558 states and 2113 transitions. [2021-11-09 08:57:22,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1558 states and 2113 transitions. [2021-11-09 08:57:22,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1558 to 1558. [2021-11-09 08:57:22,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1558 states, 1558 states have (on average 1.3562259306803595) internal successors, (2113), 1557 states have internal predecessors, (2113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-09 08:57:22,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1558 states to 1558 states and 2113 transitions. [2021-11-09 08:57:22,062 INFO L704 BuchiCegarLoop]: Abstraction has 1558 states and 2113 transitions. [2021-11-09 08:57:22,062 INFO L587 BuchiCegarLoop]: Abstraction has 1558 states and 2113 transitions. [2021-11-09 08:57:22,062 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-09 08:57:22,062 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1558 states and 2113 transitions. [2021-11-09 08:57:22,071 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1511 [2021-11-09 08:57:22,071 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-09 08:57:22,071 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-09 08:57:22,072 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:22,072 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-09 08:57:22,072 INFO L791 eck$LassoCheckResult]: Stem: 14945#ULTIMATE.startENTRY #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(21);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 14846#L-1 havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 14741#L491 havoc start_simulation_#t~ret15, start_simulation_#t~ret16, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0; 14742#L214 assume 1 == ~m_i~0;~m_st~0 := 0; 14882#L221-1 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14852#L226-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14853#L231-1 assume !(0 == ~M_E~0); 14842#L334-1 assume !(0 == ~T1_E~0); 14843#L339-1 assume !(0 == ~T2_E~0); 14935#L344-1 assume !(0 == ~E_1~0); 14801#L349-1 assume !(0 == ~E_2~0); 14802#L354-1 havoc activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14849#L156 assume !(1 == ~m_pc~0); 14844#L156-2 is_master_triggered_~__retres1~0 := 0; 14781#L167 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14747#L168 activate_threads_#t~ret11 := is_master_triggered_#res;activate_threads_~tmp~1 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 14748#L405 assume !(0 != activate_threads_~tmp~1); 14890#L405-2 havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14743#L175 assume !(1 == ~t1_pc~0); 14744#L175-2 is_transmit1_triggered_~__retres1~1 := 0; 14891#L186 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14892#L187 activate_threads_#t~ret12 := is_transmit1_triggered_#res;activate_threads_~tmp___0~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 14946#L413 assume !(0 != activate_threads_~tmp___0~0); 14923#L413-2 havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14924#L194 assume !(1 == ~t2_pc~0); 14926#L194-2 is_transmit2_triggered_~__retres1~2 := 0; 14902#L205 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14826#L206 activate_threads_#t~ret13 := is_transmit2_triggered_#res;activate_threads_~tmp___1~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14814#L421 assume !(0 != activate_threads_~tmp___1~0); 14815#L421-2 assume !(1 == ~M_E~0); 14915#L367-1 assume !(1 == ~T1_E~0); 14763#L372-1 assume !(1 == ~T2_E~0); 14764#L377-1 assume !(1 == ~E_1~0); 14767#L382-1 assume !(1 == ~E_2~0); 14798#L528-1 assume !false; 16170#L529 start_simulation_~kernel_st~0 := 1;havoc eval_#t~ret7, eval_#t~nondet8, eval_~tmp_ndt_1~0, eval_#t~nondet9, eval_~tmp_ndt_2~0, eval_#t~nondet10, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 16168#L309 [2021-11-09 08:57:22,073 INFO L793 eck$LassoCheckResult]: Loop: 16168#L309 assume !false; 16164#L272 havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 16160#L244 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 16156#L261 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 16153#L262 eval_#t~ret7 := exists_runnable_thread_#res;eval_~tmp~0 := eval_#t~ret7;havoc eval_#t~ret7; 16149#L276 assume 0 != eval_~tmp~0; 16145#L276-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 14886#L284 assume !(0 != eval_~tmp_ndt_1~0); 14887#L281 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 16175#L298 assume !(0 != eval_~tmp_ndt_2~0); 16173#L295 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet10;havoc eval_#t~nondet10; 15819#L312 assume !(0 != eval_~tmp_ndt_3~0); 16168#L309 [2021-11-09 08:57:22,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:22,073 INFO L85 PathProgramCache]: Analyzing trace with hash 373117697, now seen corresponding path program 3 times [2021-11-09 08:57:22,073 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:22,074 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [984191302] [2021-11-09 08:57:22,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:22,074 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:22,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:22,081 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 08:57:22,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:22,093 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 08:57:22,093 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:22,094 INFO L85 PathProgramCache]: Analyzing trace with hash 498620433, now seen corresponding path program 1 times [2021-11-09 08:57:22,094 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:22,094 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [205924096] [2021-11-09 08:57:22,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:22,094 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:22,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:22,097 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 08:57:22,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:22,101 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 08:57:22,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-09 08:57:22,102 INFO L85 PathProgramCache]: Analyzing trace with hash 999369489, now seen corresponding path program 1 times [2021-11-09 08:57:22,102 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-09 08:57:22,102 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1198598240] [2021-11-09 08:57:22,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-09 08:57:22,103 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-09 08:57:22,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:22,110 INFO L355 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2021-11-09 08:57:22,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2021-11-09 08:57:22,123 INFO L133 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2021-11-09 08:57:23,343 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 09.11 08:57:23 BoogieIcfgContainer [2021-11-09 08:57:23,343 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2021-11-09 08:57:23,344 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2021-11-09 08:57:23,344 INFO L271 PluginConnector]: Initializing Witness Printer... [2021-11-09 08:57:23,344 INFO L275 PluginConnector]: Witness Printer initialized [2021-11-09 08:57:23,345 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 09.11 08:57:18" (3/4) ... [2021-11-09 08:57:23,348 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2021-11-09 08:57:23,394 INFO L141 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89494476-70ab-4624-a02f-13ca4a15a593/bin/uautomizer-IVEQpCNsaX/witness.graphml [2021-11-09 08:57:23,395 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2021-11-09 08:57:23,396 INFO L168 Benchmark]: Toolchain (without parser) took 6236.02 ms. Allocated memory was 86.0 MB in the beginning and 138.4 MB in the end (delta: 52.4 MB). Free memory was 45.5 MB in the beginning and 78.3 MB in the end (delta: -32.9 MB). Peak memory consumption was 20.2 MB. Max. memory is 16.1 GB. [2021-11-09 08:57:23,397 INFO L168 Benchmark]: CDTParser took 0.27 ms. Allocated memory is still 86.0 MB. Free memory is still 62.2 MB. There was no memory consumed. Max. memory is 16.1 GB. [2021-11-09 08:57:23,397 INFO L168 Benchmark]: CACSL2BoogieTranslator took 331.70 ms. Allocated memory is still 86.0 MB. Free memory was 45.2 MB in the beginning and 59.8 MB in the end (delta: -14.5 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-11-09 08:57:23,398 INFO L168 Benchmark]: Boogie Procedure Inliner took 61.33 ms. Allocated memory is still 86.0 MB. Free memory was 59.8 MB in the beginning and 56.9 MB in the end (delta: 2.9 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. [2021-11-09 08:57:23,398 INFO L168 Benchmark]: Boogie Preprocessor took 55.95 ms. Allocated memory is still 86.0 MB. Free memory was 56.9 MB in the beginning and 54.6 MB in the end (delta: 2.3 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-11-09 08:57:23,399 INFO L168 Benchmark]: RCFGBuilder took 868.73 ms. Allocated memory is still 86.0 MB. Free memory was 54.6 MB in the beginning and 32.6 MB in the end (delta: 22.0 MB). Peak memory consumption was 21.0 MB. Max. memory is 16.1 GB. [2021-11-09 08:57:23,399 INFO L168 Benchmark]: BuchiAutomizer took 4860.03 ms. Allocated memory was 86.0 MB in the beginning and 138.4 MB in the end (delta: 52.4 MB). Free memory was 32.4 MB in the beginning and 80.4 MB in the end (delta: -48.0 MB). Peak memory consumption was 55.7 MB. Max. memory is 16.1 GB. [2021-11-09 08:57:23,400 INFO L168 Benchmark]: Witness Printer took 50.95 ms. Allocated memory is still 138.4 MB. Free memory was 80.4 MB in the beginning and 78.3 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. [2021-11-09 08:57:23,402 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.27 ms. Allocated memory is still 86.0 MB. Free memory is still 62.2 MB. There was no memory consumed. Max. memory is 16.1 GB. * CACSL2BoogieTranslator took 331.70 ms. Allocated memory is still 86.0 MB. Free memory was 45.2 MB in the beginning and 59.8 MB in the end (delta: -14.5 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Boogie Procedure Inliner took 61.33 ms. Allocated memory is still 86.0 MB. Free memory was 59.8 MB in the beginning and 56.9 MB in the end (delta: 2.9 MB). Peak memory consumption was 4.2 MB. Max. memory is 16.1 GB. * Boogie Preprocessor took 55.95 ms. Allocated memory is still 86.0 MB. Free memory was 56.9 MB in the beginning and 54.6 MB in the end (delta: 2.3 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * RCFGBuilder took 868.73 ms. Allocated memory is still 86.0 MB. Free memory was 54.6 MB in the beginning and 32.6 MB in the end (delta: 22.0 MB). Peak memory consumption was 21.0 MB. Max. memory is 16.1 GB. * BuchiAutomizer took 4860.03 ms. Allocated memory was 86.0 MB in the beginning and 138.4 MB in the end (delta: 52.4 MB). Free memory was 32.4 MB in the beginning and 80.4 MB in the end (delta: -48.0 MB). Peak memory consumption was 55.7 MB. Max. memory is 16.1 GB. * Witness Printer took 50.95 ms. Allocated memory is still 138.4 MB. Free memory was 80.4 MB in the beginning and 78.3 MB in the end (delta: 2.1 MB). Peak memory consumption was 2.1 MB. Max. memory is 16.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 12 terminating modules (12 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.12 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1558 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.7s and 13 iterations. TraceHistogramMax:1. Analysis of lassos took 3.0s. Construction of modules took 0.3s. Büchi inclusion checks took 0.4s. Highest rank in rank-based complementation 0. Minimization of det autom 12. Minimization of nondet autom 0. Automata minimization 0.3s AutomataMinimizationTime, 12 MinimizatonAttempts, 1654 StatesRemovedByMinimization, 7 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had 1558 states and ocurred in iteration 12. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 3637 SDtfs, 4123 SDslu, 4299 SDs, 0 SdLazy, 293 SolverSat, 119 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.3s Time LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc2 concLT0 SILN1 SILU0 SILI4 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 271]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {NULL=21208} State at position 1 is {NULL=0, NULL=21208, tmp=1, __retres1=0, kernel_st=1, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4686f59d=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@682133ab=0, E_1=2, NULL=0, NULL=0, tmp_ndt_2=0, \result=0, m_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5dad310d=0, NULL=0, tmp___0=0, tmp=0, __retres1=0, m_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6d401db9=0, NULL=21209, \result=0, __retres1=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, __retres1=1, T1_E=2, NULL=21210, tmp_ndt_1=0, NULL=0, M_E=2, tmp=0, tmp_ndt_3=0, __retres1=0, NULL=21211, t2_i=1, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1764c829=0, t1_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@18623949=0, t2_pc=0, tmp___1=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@480665f=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@cbeb796=0, \result=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@b02c971=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 271]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int m_st ; [L29] int t1_st ; [L30] int t2_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int M_E = 2; [L35] int T1_E = 2; [L36] int T2_E = 2; [L37] int E_1 = 2; [L38] int E_2 = 2; [L573] int __retres1 ; [L487] m_i = 1 [L488] t1_i = 1 [L489] t2_i = 1 [L514] int kernel_st ; [L515] int tmp ; [L516] int tmp___0 ; [L520] kernel_st = 0 [L221] COND TRUE m_i == 1 [L222] m_st = 0 [L226] COND TRUE t1_i == 1 [L227] t1_st = 0 [L231] COND TRUE t2_i == 1 [L232] t2_st = 0 [L334] COND FALSE !(M_E == 0) [L339] COND FALSE !(T1_E == 0) [L344] COND FALSE !(T2_E == 0) [L349] COND FALSE !(E_1 == 0) [L354] COND FALSE !(E_2 == 0) [L397] int tmp ; [L398] int tmp___0 ; [L399] int tmp___1 ; [L153] int __retres1 ; [L156] COND FALSE !(m_pc == 1) [L166] __retres1 = 0 [L168] return (__retres1); [L403] tmp = is_master_triggered() [L405] COND FALSE !(\read(tmp)) [L172] int __retres1 ; [L175] COND FALSE !(t1_pc == 1) [L185] __retres1 = 0 [L187] return (__retres1); [L411] tmp___0 = is_transmit1_triggered() [L413] COND FALSE !(\read(tmp___0)) [L191] int __retres1 ; [L194] COND FALSE !(t2_pc == 1) [L204] __retres1 = 0 [L206] return (__retres1); [L419] tmp___1 = is_transmit2_triggered() [L421] COND FALSE !(\read(tmp___1)) [L367] COND FALSE !(M_E == 1) [L372] COND FALSE !(T1_E == 1) [L377] COND FALSE !(T2_E == 1) [L382] COND FALSE !(E_1 == 1) [L387] COND FALSE !(E_2 == 1) [L528] COND TRUE 1 [L531] kernel_st = 1 [L267] int tmp ; Loop: [L271] COND TRUE 1 [L241] int __retres1 ; [L244] COND TRUE m_st == 0 [L245] __retres1 = 1 [L262] return (__retres1); [L274] tmp = exists_runnable_thread() [L276] COND TRUE \read(tmp) [L281] COND TRUE m_st == 0 [L282] int tmp_ndt_1; [L283] tmp_ndt_1 = __VERIFIER_nondet_int() [L284] COND FALSE !(\read(tmp_ndt_1)) [L295] COND TRUE t1_st == 0 [L296] int tmp_ndt_2; [L297] tmp_ndt_2 = __VERIFIER_nondet_int() [L298] COND FALSE !(\read(tmp_ndt_2)) [L309] COND TRUE t2_st == 0 [L310] int tmp_ndt_3; [L311] tmp_ndt_3 = __VERIFIER_nondet_int() [L312] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2021-11-09 08:57:23,468 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89494476-70ab-4624-a02f-13ca4a15a593/bin/uautomizer-IVEQpCNsaX/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)