./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.11.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 63182f13 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26bada49-22f8-41df-8acc-9361bb13732a/bin/uautomizer-YU5uOKAj3y/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26bada49-22f8-41df-8acc-9361bb13732a/bin/uautomizer-YU5uOKAj3y/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26bada49-22f8-41df-8acc-9361bb13732a/bin/uautomizer-YU5uOKAj3y/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26bada49-22f8-41df-8acc-9361bb13732a/bin/uautomizer-YU5uOKAj3y/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.11.cil-1.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26bada49-22f8-41df-8acc-9361bb13732a/bin/uautomizer-YU5uOKAj3y/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26bada49-22f8-41df-8acc-9361bb13732a/bin/uautomizer-YU5uOKAj3y --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 79f20a4b12634e812af836a5fe92e9d987e7766e2c28337c49504608346f2347 --- Real Ultimate output --- This is Ultimate 0.2.1-dev-63182f1 [2021-11-13 18:20:33,612 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-13 18:20:33,614 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-13 18:20:33,646 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-13 18:20:33,646 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-13 18:20:33,648 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-13 18:20:33,650 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-13 18:20:33,652 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-13 18:20:33,654 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-13 18:20:33,655 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-13 18:20:33,657 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-13 18:20:33,658 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-13 18:20:33,659 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-13 18:20:33,660 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-13 18:20:33,662 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-13 18:20:33,663 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-13 18:20:33,664 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-13 18:20:33,666 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-13 18:20:33,668 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-13 18:20:33,670 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-13 18:20:33,673 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-13 18:20:33,674 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-13 18:20:33,676 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-13 18:20:33,677 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-13 18:20:33,681 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-13 18:20:33,681 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-13 18:20:33,681 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-13 18:20:33,683 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-13 18:20:33,683 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-13 18:20:33,684 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-13 18:20:33,685 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-13 18:20:33,686 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-13 18:20:33,687 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-13 18:20:33,688 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-13 18:20:33,689 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-13 18:20:33,689 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-13 18:20:33,690 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-13 18:20:33,690 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-13 18:20:33,690 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-13 18:20:33,691 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-13 18:20:33,692 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-13 18:20:33,693 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26bada49-22f8-41df-8acc-9361bb13732a/bin/uautomizer-YU5uOKAj3y/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-13 18:20:33,717 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-13 18:20:33,717 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-13 18:20:33,717 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-13 18:20:33,718 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-13 18:20:33,719 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-13 18:20:33,719 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-13 18:20:33,719 INFO L138 SettingsManager]: * Use SBE=true [2021-11-13 18:20:33,720 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-13 18:20:33,720 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-13 18:20:33,720 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-13 18:20:33,720 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-13 18:20:33,720 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-13 18:20:33,721 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-13 18:20:33,721 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-13 18:20:33,721 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-13 18:20:33,721 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-13 18:20:33,721 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-13 18:20:33,722 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-13 18:20:33,722 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-13 18:20:33,722 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-13 18:20:33,722 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-13 18:20:33,722 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-13 18:20:33,723 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-13 18:20:33,723 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-13 18:20:33,723 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-13 18:20:33,723 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-13 18:20:33,723 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-13 18:20:33,724 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-13 18:20:33,724 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-13 18:20:33,724 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-13 18:20:33,724 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-13 18:20:33,724 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-13 18:20:33,725 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-13 18:20:33,726 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26bada49-22f8-41df-8acc-9361bb13732a/bin/uautomizer-YU5uOKAj3y/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26bada49-22f8-41df-8acc-9361bb13732a/bin/uautomizer-YU5uOKAj3y Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 79f20a4b12634e812af836a5fe92e9d987e7766e2c28337c49504608346f2347 [2021-11-13 18:20:34,000 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-13 18:20:34,025 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-13 18:20:34,027 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-13 18:20:34,028 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-13 18:20:34,029 INFO L275 PluginConnector]: CDTParser initialized [2021-11-13 18:20:34,030 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26bada49-22f8-41df-8acc-9361bb13732a/bin/uautomizer-YU5uOKAj3y/../../sv-benchmarks/c/systemc/token_ring.11.cil-1.c [2021-11-13 18:20:34,099 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26bada49-22f8-41df-8acc-9361bb13732a/bin/uautomizer-YU5uOKAj3y/data/07f95a028/66a9dd05c36543ac9ab3c9480e28f5db/FLAGc0a59fbbf [2021-11-13 18:20:34,697 INFO L306 CDTParser]: Found 1 translation units. [2021-11-13 18:20:34,698 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26bada49-22f8-41df-8acc-9361bb13732a/sv-benchmarks/c/systemc/token_ring.11.cil-1.c [2021-11-13 18:20:34,727 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26bada49-22f8-41df-8acc-9361bb13732a/bin/uautomizer-YU5uOKAj3y/data/07f95a028/66a9dd05c36543ac9ab3c9480e28f5db/FLAGc0a59fbbf [2021-11-13 18:20:35,006 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26bada49-22f8-41df-8acc-9361bb13732a/bin/uautomizer-YU5uOKAj3y/data/07f95a028/66a9dd05c36543ac9ab3c9480e28f5db [2021-11-13 18:20:35,008 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-13 18:20:35,010 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-13 18:20:35,011 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-13 18:20:35,012 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-13 18:20:35,015 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-13 18:20:35,015 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 06:20:35" (1/1) ... [2021-11-13 18:20:35,016 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@67249f6c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:20:35, skipping insertion in model container [2021-11-13 18:20:35,016 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 06:20:35" (1/1) ... [2021-11-13 18:20:35,023 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-13 18:20:35,084 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-13 18:20:35,249 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26bada49-22f8-41df-8acc-9361bb13732a/sv-benchmarks/c/systemc/token_ring.11.cil-1.c[671,684] [2021-11-13 18:20:35,365 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-13 18:20:35,376 INFO L203 MainTranslator]: Completed pre-run [2021-11-13 18:20:35,391 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26bada49-22f8-41df-8acc-9361bb13732a/sv-benchmarks/c/systemc/token_ring.11.cil-1.c[671,684] [2021-11-13 18:20:35,473 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-13 18:20:35,510 INFO L208 MainTranslator]: Completed translation [2021-11-13 18:20:35,511 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:20:35 WrapperNode [2021-11-13 18:20:35,511 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-13 18:20:35,512 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-13 18:20:35,512 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-13 18:20:35,513 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-13 18:20:35,519 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:20:35" (1/1) ... [2021-11-13 18:20:35,531 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:20:35" (1/1) ... [2021-11-13 18:20:35,661 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-13 18:20:35,661 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-13 18:20:35,661 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-13 18:20:35,662 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-13 18:20:35,670 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:20:35" (1/1) ... [2021-11-13 18:20:35,670 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:20:35" (1/1) ... [2021-11-13 18:20:35,682 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:20:35" (1/1) ... [2021-11-13 18:20:35,682 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:20:35" (1/1) ... [2021-11-13 18:20:35,737 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:20:35" (1/1) ... [2021-11-13 18:20:35,777 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:20:35" (1/1) ... [2021-11-13 18:20:35,784 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:20:35" (1/1) ... [2021-11-13 18:20:35,797 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-13 18:20:35,798 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-13 18:20:35,798 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-13 18:20:35,798 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-13 18:20:35,799 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:20:35" (1/1) ... [2021-11-13 18:20:35,852 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-13 18:20:35,863 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26bada49-22f8-41df-8acc-9361bb13732a/bin/uautomizer-YU5uOKAj3y/z3 [2021-11-13 18:20:35,880 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26bada49-22f8-41df-8acc-9361bb13732a/bin/uautomizer-YU5uOKAj3y/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-13 18:20:35,899 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_26bada49-22f8-41df-8acc-9361bb13732a/bin/uautomizer-YU5uOKAj3y/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-13 18:20:35,950 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-13 18:20:35,950 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-13 18:20:35,950 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-13 18:20:35,950 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-13 18:20:38,077 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-13 18:20:38,078 INFO L299 CfgBuilder]: Removed 14 assume(true) statements. [2021-11-13 18:20:38,082 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 06:20:38 BoogieIcfgContainer [2021-11-13 18:20:38,083 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-13 18:20:38,086 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-13 18:20:38,086 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-13 18:20:38,090 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-13 18:20:38,091 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-13 18:20:38,092 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 06:20:35" (1/3) ... [2021-11-13 18:20:38,093 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@21c0b213 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 06:20:38, skipping insertion in model container [2021-11-13 18:20:38,093 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-13 18:20:38,094 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 06:20:35" (2/3) ... [2021-11-13 18:20:38,094 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@21c0b213 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 06:20:38, skipping insertion in model container [2021-11-13 18:20:38,095 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-13 18:20:38,095 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 06:20:38" (3/3) ... [2021-11-13 18:20:38,096 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.11.cil-1.c [2021-11-13 18:20:38,161 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-13 18:20:38,162 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-13 18:20:38,162 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-13 18:20:38,162 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-13 18:20:38,162 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-13 18:20:38,162 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-13 18:20:38,163 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-13 18:20:38,163 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-13 18:20:38,222 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1579 states, 1578 states have (on average 1.503168567807351) internal successors, (2372), 1578 states have internal predecessors, (2372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:38,337 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1424 [2021-11-13 18:20:38,337 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:20:38,337 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:20:38,357 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:38,358 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:38,358 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-13 18:20:38,362 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1579 states, 1578 states have (on average 1.503168567807351) internal successors, (2372), 1578 states have internal predecessors, (2372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:38,383 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1424 [2021-11-13 18:20:38,383 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:20:38,384 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:20:38,390 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:38,394 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:38,411 INFO L791 eck$LassoCheckResult]: Stem: 348#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 1498#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 780#L1653true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 968#L785true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 652#L792true assume !(1 == ~m_i~0);~m_st~0 := 2; 1000#L792-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 48#L797-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1412#L802-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1303#L807-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 629#L812-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1135#L817-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 929#L822-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1064#L827-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1356#L832-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1217#L837-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1224#L842-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 1002#L847-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 795#L1121true assume !(0 == ~M_E~0); 575#L1121-2true assume !(0 == ~T1_E~0); 178#L1126-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 272#L1131-1true assume !(0 == ~T3_E~0); 327#L1136-1true assume !(0 == ~T4_E~0); 474#L1141-1true assume !(0 == ~T5_E~0); 1261#L1146-1true assume !(0 == ~T6_E~0); 728#L1151-1true assume !(0 == ~T7_E~0); 360#L1156-1true assume !(0 == ~T8_E~0); 41#L1161-1true assume !(0 == ~T9_E~0); 860#L1166-1true assume 0 == ~T10_E~0;~T10_E~0 := 1; 145#L1171-1true assume !(0 == ~T11_E~0); 742#L1176-1true assume !(0 == ~E_M~0); 886#L1181-1true assume !(0 == ~E_1~0); 1330#L1186-1true assume !(0 == ~E_2~0); 946#L1191-1true assume !(0 == ~E_3~0); 159#L1196-1true assume !(0 == ~E_4~0); 1340#L1201-1true assume !(0 == ~E_5~0); 1420#L1206-1true assume 0 == ~E_6~0;~E_6~0 := 1; 1003#L1211-1true assume !(0 == ~E_7~0); 1157#L1216-1true assume !(0 == ~E_8~0); 233#L1221-1true assume !(0 == ~E_9~0); 1086#L1226-1true assume !(0 == ~E_10~0); 87#L1231-1true assume !(0 == ~E_11~0); 1234#L1236-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 743#L556true assume 1 == ~m_pc~0; 757#L557true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28#L567true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 538#L568true activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1136#L1391true assume !(0 != activate_threads_~tmp~1#1); 919#L1391-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1082#L575true assume !(1 == ~t1_pc~0); 6#L575-2true is_transmit1_triggered_~__retres1~1#1 := 0; 69#L586true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1075#L587true activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 240#L1399true assume !(0 != activate_threads_~tmp___0~0#1); 218#L1399-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 717#L594true assume 1 == ~t2_pc~0; 181#L595true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1521#L605true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 459#L606true activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36#L1407true assume !(0 != activate_threads_~tmp___1~0#1); 64#L1407-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1209#L613true assume !(1 == ~t3_pc~0); 1543#L613-2true is_transmit3_triggered_~__retres1~3#1 := 0; 307#L624true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 85#L625true activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 473#L1415true assume !(0 != activate_threads_~tmp___2~0#1); 1078#L1415-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 294#L632true assume 1 == ~t4_pc~0; 638#L633true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 796#L643true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1342#L644true activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1496#L1423true assume !(0 != activate_threads_~tmp___3~0#1); 749#L1423-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 525#L651true assume 1 == ~t5_pc~0; 970#L652true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 124#L662true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 367#L663true activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 449#L1431true assume !(0 != activate_threads_~tmp___4~0#1); 132#L1431-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1111#L670true assume !(1 == ~t6_pc~0); 977#L670-2true is_transmit6_triggered_~__retres1~6#1 := 0; 321#L681true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1133#L682true activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1305#L1439true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 503#L1439-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1323#L689true assume 1 == ~t7_pc~0; 1516#L690true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 585#L700true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1573#L701true activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 999#L1447true assume !(0 != activate_threads_~tmp___6~0#1); 431#L1447-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1190#L708true assume !(1 == ~t8_pc~0); 176#L708-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1131#L719true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1387#L720true activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1108#L1455true assume !(0 != activate_threads_~tmp___7~0#1); 209#L1455-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 280#L727true assume 1 == ~t9_pc~0; 1226#L728true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1409#L738true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1361#L739true activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1434#L1463true assume !(0 != activate_threads_~tmp___8~0#1); 1306#L1463-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 238#L746true assume !(1 == ~t10_pc~0); 706#L746-2true is_transmit10_triggered_~__retres1~10#1 := 0; 817#L757true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1435#L758true activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1123#L1471true assume !(0 != activate_threads_~tmp___9~0#1); 924#L1471-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 332#L765true assume 1 == ~t11_pc~0; 1364#L766true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1388#L776true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12#L777true activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 975#L1479true assume !(0 != activate_threads_~tmp___10~0#1); 1166#L1479-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1105#L1249true assume !(1 == ~M_E~0); 642#L1249-2true assume !(1 == ~T1_E~0); 382#L1254-1true assume !(1 == ~T2_E~0); 34#L1259-1true assume !(1 == ~T3_E~0); 25#L1264-1true assume !(1 == ~T4_E~0); 1574#L1269-1true assume !(1 == ~T5_E~0); 1503#L1274-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1245#L1279-1true assume !(1 == ~T7_E~0); 119#L1284-1true assume !(1 == ~T8_E~0); 1365#L1289-1true assume !(1 == ~T9_E~0); 414#L1294-1true assume !(1 == ~T10_E~0); 421#L1299-1true assume !(1 == ~T11_E~0); 1430#L1304-1true assume !(1 == ~E_M~0); 1461#L1309-1true assume !(1 == ~E_1~0); 1440#L1314-1true assume 1 == ~E_2~0;~E_2~0 := 2; 96#L1319-1true assume !(1 == ~E_3~0); 839#L1324-1true assume !(1 == ~E_4~0); 157#L1329-1true assume !(1 == ~E_5~0); 1043#L1334-1true assume !(1 == ~E_6~0); 1394#L1339-1true assume !(1 == ~E_7~0); 1170#L1344-1true assume !(1 == ~E_8~0); 1520#L1349-1true assume !(1 == ~E_9~0); 514#L1354-1true assume 1 == ~E_10~0;~E_10~0 := 2; 843#L1359-1true assume !(1 == ~E_11~0); 1369#L1364-1true assume { :end_inline_reset_delta_events } true; 202#L1690-2true [2021-11-13 18:20:38,424 INFO L793 eck$LassoCheckResult]: Loop: 202#L1690-2true assume !false; 871#L1691true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 857#L1096true assume !true; 680#L1111true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1378#L785-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 319#L1121-3true assume 0 == ~M_E~0;~M_E~0 := 1; 1515#L1121-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1313#L1126-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 447#L1131-3true assume !(0 == ~T3_E~0); 1526#L1136-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1508#L1141-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 751#L1146-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 175#L1151-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1162#L1156-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1380#L1161-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 576#L1166-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 1255#L1171-3true assume !(0 == ~T11_E~0); 609#L1176-3true assume 0 == ~E_M~0;~E_M~0 := 1; 200#L1181-3true assume 0 == ~E_1~0;~E_1~0 := 1; 1225#L1186-3true assume 0 == ~E_2~0;~E_2~0 := 1; 682#L1191-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1213#L1196-3true assume 0 == ~E_4~0;~E_4~0 := 1; 898#L1201-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1423#L1206-3true assume 0 == ~E_6~0;~E_6~0 := 1; 588#L1211-3true assume !(0 == ~E_7~0); 155#L1216-3true assume 0 == ~E_8~0;~E_8~0 := 1; 389#L1221-3true assume 0 == ~E_9~0;~E_9~0 := 1; 869#L1226-3true assume 0 == ~E_10~0;~E_10~0 := 1; 184#L1231-3true assume 0 == ~E_11~0;~E_11~0 := 1; 311#L1236-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1451#L556-39true assume 1 == ~m_pc~0; 691#L557-13true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 657#L567-13true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 237#L568-13true activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 336#L1391-39true assume !(0 != activate_threads_~tmp~1#1); 1296#L1391-41true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 621#L575-39true assume 1 == ~t1_pc~0; 1039#L576-13true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 904#L586-13true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 746#L587-13true activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1477#L1399-39true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 600#L1399-41true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 799#L594-39true assume !(1 == ~t2_pc~0); 1194#L594-41true is_transmit2_triggered_~__retres1~2#1 := 0; 602#L605-13true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1531#L606-13true activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1112#L1407-39true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 273#L1407-41true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1073#L613-39true assume 1 == ~t3_pc~0; 1468#L614-13true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15#L624-13true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 418#L625-13true activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 807#L1415-39true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 61#L1415-41true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1493#L632-39true assume !(1 == ~t4_pc~0); 845#L632-41true is_transmit4_triggered_~__retres1~4#1 := 0; 368#L643-13true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 832#L644-13true activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1081#L1423-39true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1017#L1423-41true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 190#L651-39true assume 1 == ~t5_pc~0; 1557#L652-13true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 996#L662-13true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1180#L663-13true activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1271#L1431-39true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1500#L1431-41true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1367#L670-39true assume !(1 == ~t6_pc~0); 694#L670-41true is_transmit6_triggered_~__retres1~6#1 := 0; 37#L681-13true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 70#L682-13true activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 472#L1439-39true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 387#L1439-41true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 548#L689-39true assume 1 == ~t7_pc~0; 983#L690-13true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 488#L700-13true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 191#L701-13true activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1467#L1447-39true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 126#L1447-41true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 731#L708-39true assume !(1 == ~t8_pc~0); 486#L708-41true is_transmit8_triggered_~__retres1~8#1 := 0; 423#L719-13true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 147#L720-13true activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1177#L1455-39true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 758#L1455-41true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 353#L727-39true assume !(1 == ~t9_pc~0); 362#L727-41true is_transmit9_triggered_~__retres1~9#1 := 0; 225#L738-13true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1046#L739-13true activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1148#L1463-39true assume !(0 != activate_threads_~tmp___8~0#1); 801#L1463-41true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 960#L746-39true assume 1 == ~t10_pc~0; 775#L747-13true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1282#L757-13true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1151#L758-13true activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 534#L1471-39true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 965#L1471-41true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1455#L765-39true assume !(1 == ~t11_pc~0); 283#L765-41true is_transmit11_triggered_~__retres1~11#1 := 0; 1197#L776-13true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 825#L777-13true activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 201#L1479-39true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 712#L1479-41true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 571#L1249-3true assume 1 == ~M_E~0;~M_E~0 := 2; 107#L1249-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1343#L1254-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1160#L1259-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 674#L1264-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 89#L1269-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1413#L1274-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1241#L1279-3true assume !(1 == ~T7_E~0); 339#L1284-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1284#L1289-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 335#L1294-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1456#L1299-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 511#L1304-3true assume 1 == ~E_M~0;~E_M~0 := 2; 863#L1309-3true assume 1 == ~E_1~0;~E_1~0 := 2; 292#L1314-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1530#L1319-3true assume !(1 == ~E_3~0); 912#L1324-3true assume 1 == ~E_4~0;~E_4~0 := 2; 138#L1329-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1408#L1334-3true assume 1 == ~E_6~0;~E_6~0 := 2; 458#L1339-3true assume 1 == ~E_7~0;~E_7~0 := 2; 666#L1344-3true assume 1 == ~E_8~0;~E_8~0 := 2; 626#L1349-3true assume 1 == ~E_9~0;~E_9~0 := 2; 277#L1354-3true assume 1 == ~E_10~0;~E_10~0 := 2; 637#L1359-3true assume !(1 == ~E_11~0); 1429#L1364-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 71#L860-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 595#L922-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 408#L923-1true start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 837#L1709true assume !(0 == start_simulation_~tmp~3#1); 1294#L1709-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 938#L860-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1524#L922-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 400#L923-2true stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 105#L1664true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 610#L1671true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1239#L1672true start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1058#L1722true assume !(0 != start_simulation_~tmp___0~1#1); 202#L1690-2true [2021-11-13 18:20:38,430 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:38,430 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 1 times [2021-11-13 18:20:38,450 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:38,450 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [470433302] [2021-11-13 18:20:38,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:38,452 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:38,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:38,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:38,774 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:38,774 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [470433302] [2021-11-13 18:20:38,775 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [470433302] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:38,775 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:38,776 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:38,778 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [600418319] [2021-11-13 18:20:38,778 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:38,783 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:20:38,784 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:38,784 INFO L85 PathProgramCache]: Analyzing trace with hash -840324833, now seen corresponding path program 1 times [2021-11-13 18:20:38,784 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:38,784 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [816279372] [2021-11-13 18:20:38,785 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:38,785 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:38,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:38,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:38,863 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:38,863 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [816279372] [2021-11-13 18:20:38,863 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [816279372] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:38,864 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:38,864 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:20:38,864 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [28433912] [2021-11-13 18:20:38,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:38,866 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:20:38,867 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:20:38,934 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-11-13 18:20:38,936 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-11-13 18:20:38,941 INFO L87 Difference]: Start difference. First operand has 1579 states, 1578 states have (on average 1.503168567807351) internal successors, (2372), 1578 states have internal predecessors, (2372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 69.5) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:39,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:20:39,024 INFO L93 Difference]: Finished difference Result 1577 states and 2340 transitions. [2021-11-13 18:20:39,025 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-11-13 18:20:39,033 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1577 states and 2340 transitions. [2021-11-13 18:20:39,052 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:39,072 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1577 states to 1571 states and 2334 transitions. [2021-11-13 18:20:39,073 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-11-13 18:20:39,076 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-11-13 18:20:39,077 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2334 transitions. [2021-11-13 18:20:39,085 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:20:39,085 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2334 transitions. [2021-11-13 18:20:39,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2334 transitions. [2021-11-13 18:20:39,174 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-11-13 18:20:39,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4856779121578612) internal successors, (2334), 1570 states have internal predecessors, (2334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:39,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2334 transitions. [2021-11-13 18:20:39,192 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2334 transitions. [2021-11-13 18:20:39,192 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2334 transitions. [2021-11-13 18:20:39,192 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-13 18:20:39,193 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2334 transitions. [2021-11-13 18:20:39,204 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:39,205 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:20:39,205 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:20:39,209 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:39,210 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:39,210 INFO L791 eck$LassoCheckResult]: Stem: 3841#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 3842#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4382#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4383#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4252#L792 assume !(1 == ~m_i~0);~m_st~0 := 2; 4253#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3260#L797-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3261#L802-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4699#L807-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4226#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4227#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4504#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4505#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4588#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4670#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 4671#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 4552#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4400#L1121 assume !(0 == ~M_E~0); 4155#L1121-2 assume !(0 == ~T1_E~0); 3536#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3537#L1131-1 assume !(0 == ~T3_E~0); 3707#L1136-1 assume !(0 == ~T4_E~0); 3803#L1141-1 assume !(0 == ~T5_E~0); 4023#L1146-1 assume !(0 == ~T6_E~0); 4323#L1151-1 assume !(0 == ~T7_E~0); 3863#L1156-1 assume !(0 == ~T8_E~0); 3246#L1161-1 assume !(0 == ~T9_E~0); 3247#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3472#L1171-1 assume !(0 == ~T11_E~0); 3473#L1176-1 assume !(0 == ~E_M~0); 4337#L1181-1 assume !(0 == ~E_1~0); 4465#L1186-1 assume !(0 == ~E_2~0); 4515#L1191-1 assume !(0 == ~E_3~0); 3499#L1196-1 assume !(0 == ~E_4~0); 3500#L1201-1 assume !(0 == ~E_5~0); 4708#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 4553#L1211-1 assume !(0 == ~E_7~0); 4554#L1216-1 assume !(0 == ~E_8~0); 3642#L1221-1 assume !(0 == ~E_9~0); 3643#L1226-1 assume !(0 == ~E_10~0); 3342#L1231-1 assume !(0 == ~E_11~0); 3343#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4338#L556 assume 1 == ~m_pc~0; 4339#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3220#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3221#L568 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4116#L1391 assume !(0 != activate_threads_~tmp~1#1); 4493#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4494#L575 assume !(1 == ~t1_pc~0); 3171#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3172#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3305#L587 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3655#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 3612#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3613#L594 assume 1 == ~t2_pc~0; 3541#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3542#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4008#L606 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3235#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 3236#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3294#L613 assume !(1 == ~t3_pc~0); 3413#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3412#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3338#L625 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3339#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 4022#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3740#L632 assume 1 == ~t4_pc~0; 3741#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4241#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4401#L644 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4709#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 4347#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4098#L651 assume 1 == ~t5_pc~0; 4099#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3426#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3427#L663 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3875#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 3443#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3444#L670 assume !(1 == ~t6_pc~0); 4535#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3789#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3790#L682 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4631#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4063#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4064#L689 assume 1 == ~t7_pc~0; 4705#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4174#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4175#L701 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4550#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 3966#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3967#L708 assume !(1 == ~t8_pc~0); 3532#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3533#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4630#L720 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4615#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 3597#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3598#L727 assume 1 == ~t9_pc~0; 3720#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3296#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4712#L739 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4713#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 4700#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3651#L746 assume !(1 == ~t10_pc~0); 3652#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4300#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4416#L758 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4624#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 4497#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3812#L765 assume 1 == ~t11_pc~0; 3813#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4018#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3185#L777 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 3186#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 4534#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4612#L1249 assume !(1 == ~M_E~0); 4245#L1249-2 assume !(1 == ~T1_E~0); 3895#L1254-1 assume !(1 == ~T2_E~0); 3231#L1259-1 assume !(1 == ~T3_E~0); 3213#L1264-1 assume !(1 == ~T4_E~0); 3214#L1269-1 assume !(1 == ~T5_E~0); 4731#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4679#L1279-1 assume !(1 == ~T7_E~0); 3414#L1284-1 assume !(1 == ~T8_E~0); 3415#L1289-1 assume !(1 == ~T9_E~0); 3945#L1294-1 assume !(1 == ~T10_E~0); 3946#L1299-1 assume !(1 == ~T11_E~0); 3955#L1304-1 assume !(1 == ~E_M~0); 4725#L1309-1 assume !(1 == ~E_1~0); 4728#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3361#L1319-1 assume !(1 == ~E_3~0); 3362#L1324-1 assume !(1 == ~E_4~0); 3494#L1329-1 assume !(1 == ~E_5~0); 3495#L1334-1 assume !(1 == ~E_6~0); 4573#L1339-1 assume !(1 == ~E_7~0); 4650#L1344-1 assume !(1 == ~E_8~0); 4651#L1349-1 assume !(1 == ~E_9~0); 4078#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 4079#L1359-1 assume !(1 == ~E_11~0); 4438#L1364-1 assume { :end_inline_reset_delta_events } true; 3583#L1690-2 [2021-11-13 18:20:39,211 INFO L793 eck$LassoCheckResult]: Loop: 3583#L1690-2 assume !false; 3584#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3469#L1096 assume !false; 4447#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3315#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3316#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4341#L923 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 3810#L937 assume !(0 != eval_~tmp~0#1); 3811#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4281#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3785#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3786#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4701#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3993#L1131-3 assume !(0 == ~T3_E~0); 3994#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4732#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4348#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3530#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3531#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4645#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4156#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4157#L1171-3 assume !(0 == ~T11_E~0); 4202#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3579#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3580#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4283#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4284#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4474#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4475#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4180#L1211-3 assume !(0 == ~E_7~0); 3492#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3493#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3906#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3549#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3550#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3770#L556-39 assume 1 == ~m_pc~0; 4291#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4258#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3649#L568-13 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3650#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 3822#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4216#L575-39 assume 1 == ~t1_pc~0; 4217#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4482#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4343#L587-13 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4344#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4191#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4192#L594-39 assume !(1 == ~t2_pc~0); 4403#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 4194#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4195#L606-13 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4617#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3708#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3709#L613-39 assume 1 == ~t3_pc~0; 4594#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3191#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3192#L625-13 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3950#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3290#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3291#L632-39 assume 1 == ~t4_pc~0; 4562#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3876#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3877#L644-13 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4430#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4561#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3560#L651-39 assume 1 == ~t5_pc~0; 3561#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3323#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4549#L663-13 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4656#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4694#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4714#L670-39 assume !(1 == ~t6_pc~0); 4293#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 3237#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3238#L682-13 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3306#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3903#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3904#L689-39 assume !(1 == ~t7_pc~0); 4027#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 4028#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3562#L701-13 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3563#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3430#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3431#L708-39 assume 1 == ~t8_pc~0; 3367#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3368#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3476#L720-13 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3477#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4357#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3849#L727-39 assume !(1 == ~t9_pc~0); 3850#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 3627#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3628#L739-13 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4577#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 4406#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4407#L746-39 assume 1 == ~t10_pc~0; 4376#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4377#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4642#L758-13 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4112#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4113#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4525#L765-39 assume 1 == ~t11_pc~0; 3241#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 3243#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4425#L777-13 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 3581#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3582#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4149#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3387#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3388#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4644#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4272#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3346#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3347#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4677#L1279-3 assume !(1 == ~T7_E~0); 3825#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3826#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3820#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3821#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4072#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4073#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3737#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3738#L1319-3 assume !(1 == ~E_3~0); 4491#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3456#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3457#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4006#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4007#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4225#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3716#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3717#L1359-3 assume !(1 == ~E_11~0); 4240#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 3307#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3308#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3934#L923-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 3935#L1709 assume !(0 == start_simulation_~tmp~3#1); 3745#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4511#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3421#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3923#L923-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 3384#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3385#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4203#L1672 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 4584#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 3583#L1690-2 [2021-11-13 18:20:39,213 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:39,213 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 2 times [2021-11-13 18:20:39,213 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:39,214 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981019385] [2021-11-13 18:20:39,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:39,214 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:39,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:39,299 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:39,299 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:39,300 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1981019385] [2021-11-13 18:20:39,300 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1981019385] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:39,302 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:39,303 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:39,303 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [160890448] [2021-11-13 18:20:39,303 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:39,304 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:20:39,305 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:39,314 INFO L85 PathProgramCache]: Analyzing trace with hash -1946660288, now seen corresponding path program 1 times [2021-11-13 18:20:39,315 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:39,315 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [25783373] [2021-11-13 18:20:39,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:39,315 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:39,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:39,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:39,542 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:39,543 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [25783373] [2021-11-13 18:20:39,543 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [25783373] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:39,543 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:39,544 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:39,544 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2127033552] [2021-11-13 18:20:39,544 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:39,545 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:20:39,545 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:20:39,546 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:20:39,546 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:20:39,547 INFO L87 Difference]: Start difference. First operand 1571 states and 2334 transitions. cyclomatic complexity: 764 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:39,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:20:39,611 INFO L93 Difference]: Finished difference Result 1571 states and 2333 transitions. [2021-11-13 18:20:39,612 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:20:39,613 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2333 transitions. [2021-11-13 18:20:39,628 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:39,644 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2333 transitions. [2021-11-13 18:20:39,644 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-11-13 18:20:39,647 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-11-13 18:20:39,647 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2333 transitions. [2021-11-13 18:20:39,650 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:20:39,650 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2333 transitions. [2021-11-13 18:20:39,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2333 transitions. [2021-11-13 18:20:39,680 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-11-13 18:20:39,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4850413749204328) internal successors, (2333), 1570 states have internal predecessors, (2333), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:39,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2333 transitions. [2021-11-13 18:20:39,693 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2333 transitions. [2021-11-13 18:20:39,694 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2333 transitions. [2021-11-13 18:20:39,694 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-13 18:20:39,694 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2333 transitions. [2021-11-13 18:20:39,705 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:39,706 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:20:39,706 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:20:39,711 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:39,712 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:39,712 INFO L791 eck$LassoCheckResult]: Stem: 6990#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 6991#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 7531#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7532#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7401#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 7402#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6409#L797-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 6410#L802-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7848#L807-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7375#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7376#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7653#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7654#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7737#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7819#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 7820#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 7701#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7549#L1121 assume !(0 == ~M_E~0); 7304#L1121-2 assume !(0 == ~T1_E~0); 6685#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6686#L1131-1 assume !(0 == ~T3_E~0); 6856#L1136-1 assume !(0 == ~T4_E~0); 6952#L1141-1 assume !(0 == ~T5_E~0); 7172#L1146-1 assume !(0 == ~T6_E~0); 7472#L1151-1 assume !(0 == ~T7_E~0); 7012#L1156-1 assume !(0 == ~T8_E~0); 6395#L1161-1 assume !(0 == ~T9_E~0); 6396#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6621#L1171-1 assume !(0 == ~T11_E~0); 6622#L1176-1 assume !(0 == ~E_M~0); 7486#L1181-1 assume !(0 == ~E_1~0); 7614#L1186-1 assume !(0 == ~E_2~0); 7664#L1191-1 assume !(0 == ~E_3~0); 6648#L1196-1 assume !(0 == ~E_4~0); 6649#L1201-1 assume !(0 == ~E_5~0); 7857#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 7702#L1211-1 assume !(0 == ~E_7~0); 7703#L1216-1 assume !(0 == ~E_8~0); 6791#L1221-1 assume !(0 == ~E_9~0); 6792#L1226-1 assume !(0 == ~E_10~0); 6491#L1231-1 assume !(0 == ~E_11~0); 6492#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7487#L556 assume 1 == ~m_pc~0; 7488#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 6369#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6370#L568 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7265#L1391 assume !(0 != activate_threads_~tmp~1#1); 7642#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7643#L575 assume !(1 == ~t1_pc~0); 6320#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6321#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6454#L587 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6804#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 6761#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6762#L594 assume 1 == ~t2_pc~0; 6690#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6691#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7157#L606 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6384#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 6385#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6443#L613 assume !(1 == ~t3_pc~0); 6562#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6561#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6487#L625 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6488#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 7171#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6889#L632 assume 1 == ~t4_pc~0; 6890#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7390#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7550#L644 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7858#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 7496#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7247#L651 assume 1 == ~t5_pc~0; 7248#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6575#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6576#L663 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7024#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 6592#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6593#L670 assume !(1 == ~t6_pc~0); 7684#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6938#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6939#L682 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7780#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7212#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7213#L689 assume 1 == ~t7_pc~0; 7854#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7323#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7324#L701 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7699#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 7115#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7116#L708 assume !(1 == ~t8_pc~0); 6681#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6682#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7779#L720 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7764#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 6746#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6747#L727 assume 1 == ~t9_pc~0; 6869#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6445#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7861#L739 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7862#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 7849#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6800#L746 assume !(1 == ~t10_pc~0); 6801#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 7449#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7565#L758 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7773#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 7646#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6961#L765 assume 1 == ~t11_pc~0; 6962#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7167#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6334#L777 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 6335#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 7683#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7761#L1249 assume !(1 == ~M_E~0); 7394#L1249-2 assume !(1 == ~T1_E~0); 7044#L1254-1 assume !(1 == ~T2_E~0); 6380#L1259-1 assume !(1 == ~T3_E~0); 6362#L1264-1 assume !(1 == ~T4_E~0); 6363#L1269-1 assume !(1 == ~T5_E~0); 7880#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7828#L1279-1 assume !(1 == ~T7_E~0); 6563#L1284-1 assume !(1 == ~T8_E~0); 6564#L1289-1 assume !(1 == ~T9_E~0); 7094#L1294-1 assume !(1 == ~T10_E~0); 7095#L1299-1 assume !(1 == ~T11_E~0); 7104#L1304-1 assume !(1 == ~E_M~0); 7874#L1309-1 assume !(1 == ~E_1~0); 7877#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6510#L1319-1 assume !(1 == ~E_3~0); 6511#L1324-1 assume !(1 == ~E_4~0); 6643#L1329-1 assume !(1 == ~E_5~0); 6644#L1334-1 assume !(1 == ~E_6~0); 7722#L1339-1 assume !(1 == ~E_7~0); 7799#L1344-1 assume !(1 == ~E_8~0); 7800#L1349-1 assume !(1 == ~E_9~0); 7227#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 7228#L1359-1 assume !(1 == ~E_11~0); 7587#L1364-1 assume { :end_inline_reset_delta_events } true; 6732#L1690-2 [2021-11-13 18:20:39,713 INFO L793 eck$LassoCheckResult]: Loop: 6732#L1690-2 assume !false; 6733#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6618#L1096 assume !false; 7596#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6464#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6465#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7490#L923 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 6959#L937 assume !(0 != eval_~tmp~0#1); 6960#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7430#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6934#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6935#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7850#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7142#L1131-3 assume !(0 == ~T3_E~0); 7143#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7881#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7497#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6679#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6680#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7794#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7305#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7306#L1171-3 assume !(0 == ~T11_E~0); 7351#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6728#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6729#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7432#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7433#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7623#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7624#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7329#L1211-3 assume !(0 == ~E_7~0); 6641#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6642#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 7055#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6698#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 6699#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6919#L556-39 assume 1 == ~m_pc~0; 7440#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7407#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6798#L568-13 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6799#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 6971#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7365#L575-39 assume 1 == ~t1_pc~0; 7366#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7631#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7492#L587-13 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7493#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7340#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7341#L594-39 assume !(1 == ~t2_pc~0); 7552#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 7343#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7344#L606-13 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7766#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6857#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6858#L613-39 assume !(1 == ~t3_pc~0); 7744#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 6340#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6341#L625-13 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7099#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6439#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6440#L632-39 assume !(1 == ~t4_pc~0); 7588#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 7025#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7026#L644-13 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7579#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7710#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6709#L651-39 assume 1 == ~t5_pc~0; 6710#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6472#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7698#L663-13 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7805#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7843#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7863#L670-39 assume !(1 == ~t6_pc~0); 7442#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 6386#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6387#L682-13 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6455#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7052#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7053#L689-39 assume !(1 == ~t7_pc~0); 7176#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 7177#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6711#L701-13 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 6712#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6579#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6580#L708-39 assume 1 == ~t8_pc~0; 6516#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6517#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6625#L720-13 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 6626#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7506#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6998#L727-39 assume !(1 == ~t9_pc~0); 6999#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 6776#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6777#L739-13 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7726#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 7555#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7556#L746-39 assume 1 == ~t10_pc~0; 7525#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7526#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7791#L758-13 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7261#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 7262#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7674#L765-39 assume 1 == ~t11_pc~0; 6390#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 6392#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7574#L777-13 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 6730#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 6731#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7298#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6536#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6537#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7793#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7421#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6495#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6496#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7826#L1279-3 assume !(1 == ~T7_E~0); 6974#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6975#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6969#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6970#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 7221#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7222#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6886#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6887#L1319-3 assume !(1 == ~E_3~0); 7640#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6605#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6606#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7155#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7156#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7374#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6865#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6866#L1359-3 assume !(1 == ~E_11~0); 7389#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 6456#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6457#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7083#L923-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 7084#L1709 assume !(0 == start_simulation_~tmp~3#1); 6894#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7660#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6570#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7072#L923-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 6533#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6534#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7352#L1672 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 7733#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 6732#L1690-2 [2021-11-13 18:20:39,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:39,717 INFO L85 PathProgramCache]: Analyzing trace with hash -968871490, now seen corresponding path program 1 times [2021-11-13 18:20:39,717 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:39,718 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [909445972] [2021-11-13 18:20:39,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:39,719 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:39,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:39,816 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:39,817 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:39,817 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [909445972] [2021-11-13 18:20:39,817 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [909445972] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:39,818 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:39,818 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:39,819 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [838480207] [2021-11-13 18:20:39,819 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:39,820 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:20:39,821 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:39,821 INFO L85 PathProgramCache]: Analyzing trace with hash -29726974, now seen corresponding path program 1 times [2021-11-13 18:20:39,822 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:39,823 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [239878109] [2021-11-13 18:20:39,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:39,824 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:39,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:39,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:39,919 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:39,919 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [239878109] [2021-11-13 18:20:39,920 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [239878109] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:39,920 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:39,921 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:39,921 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2088826439] [2021-11-13 18:20:39,921 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:39,922 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:20:39,922 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:20:39,922 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:20:39,923 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:20:39,923 INFO L87 Difference]: Start difference. First operand 1571 states and 2333 transitions. cyclomatic complexity: 763 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:40,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:20:40,007 INFO L93 Difference]: Finished difference Result 1571 states and 2332 transitions. [2021-11-13 18:20:40,007 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:20:40,009 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2332 transitions. [2021-11-13 18:20:40,023 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:40,037 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2332 transitions. [2021-11-13 18:20:40,037 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-11-13 18:20:40,039 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-11-13 18:20:40,039 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2332 transitions. [2021-11-13 18:20:40,042 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:20:40,042 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2332 transitions. [2021-11-13 18:20:40,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2332 transitions. [2021-11-13 18:20:40,067 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-11-13 18:20:40,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4844048376830044) internal successors, (2332), 1570 states have internal predecessors, (2332), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:40,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2332 transitions. [2021-11-13 18:20:40,078 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2332 transitions. [2021-11-13 18:20:40,078 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2332 transitions. [2021-11-13 18:20:40,078 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-13 18:20:40,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2332 transitions. [2021-11-13 18:20:40,088 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:40,089 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:20:40,089 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:20:40,098 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:40,099 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:40,099 INFO L791 eck$LassoCheckResult]: Stem: 10143#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 10144#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 10680#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10681#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10550#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 10551#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9558#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9559#L802-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10997#L807-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10524#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10525#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10802#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10803#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10886#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 10968#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10969#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 10850#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10698#L1121 assume !(0 == ~M_E~0); 10453#L1121-2 assume !(0 == ~T1_E~0); 9835#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9836#L1131-1 assume !(0 == ~T3_E~0); 10005#L1136-1 assume !(0 == ~T4_E~0); 10101#L1141-1 assume !(0 == ~T5_E~0); 10326#L1146-1 assume !(0 == ~T6_E~0); 10621#L1151-1 assume !(0 == ~T7_E~0); 10161#L1156-1 assume !(0 == ~T8_E~0); 9544#L1161-1 assume !(0 == ~T9_E~0); 9545#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9770#L1171-1 assume !(0 == ~T11_E~0); 9771#L1176-1 assume !(0 == ~E_M~0); 10635#L1181-1 assume !(0 == ~E_1~0); 10763#L1186-1 assume !(0 == ~E_2~0); 10813#L1191-1 assume !(0 == ~E_3~0); 9797#L1196-1 assume !(0 == ~E_4~0); 9798#L1201-1 assume !(0 == ~E_5~0); 11006#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 10851#L1211-1 assume !(0 == ~E_7~0); 10852#L1216-1 assume !(0 == ~E_8~0); 9943#L1221-1 assume !(0 == ~E_9~0); 9944#L1226-1 assume !(0 == ~E_10~0); 9640#L1231-1 assume !(0 == ~E_11~0); 9641#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10637#L556 assume 1 == ~m_pc~0; 10638#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9518#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9519#L568 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10415#L1391 assume !(0 != activate_threads_~tmp~1#1); 10791#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10792#L575 assume !(1 == ~t1_pc~0); 9469#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9470#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9603#L587 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9953#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 9910#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9911#L594 assume 1 == ~t2_pc~0; 9839#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9840#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10306#L606 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9535#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 9536#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9592#L613 assume !(1 == ~t3_pc~0); 9711#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9710#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9636#L625 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9637#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 10320#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10038#L632 assume 1 == ~t4_pc~0; 10039#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10539#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10699#L644 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11007#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 10645#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10396#L651 assume 1 == ~t5_pc~0; 10397#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9724#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9725#L663 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10173#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 9741#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9742#L670 assume !(1 == ~t6_pc~0); 10834#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10092#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10093#L682 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10930#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10363#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10364#L689 assume 1 == ~t7_pc~0; 11003#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10472#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10473#L701 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10848#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 10264#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10265#L708 assume !(1 == ~t8_pc~0); 9830#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 9831#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10928#L720 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 10913#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 9895#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9896#L727 assume 1 == ~t9_pc~0; 10018#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9594#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11010#L739 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11011#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 10998#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9950#L746 assume !(1 == ~t10_pc~0); 9951#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 10598#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10714#L758 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 10922#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 10795#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10113#L765 assume 1 == ~t11_pc~0; 10114#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10316#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9483#L777 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9484#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 10832#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10910#L1249 assume !(1 == ~M_E~0); 10544#L1249-2 assume !(1 == ~T1_E~0); 10193#L1254-1 assume !(1 == ~T2_E~0); 9529#L1259-1 assume !(1 == ~T3_E~0); 9511#L1264-1 assume !(1 == ~T4_E~0); 9512#L1269-1 assume !(1 == ~T5_E~0); 11029#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10977#L1279-1 assume !(1 == ~T7_E~0); 9712#L1284-1 assume !(1 == ~T8_E~0); 9713#L1289-1 assume !(1 == ~T9_E~0); 10243#L1294-1 assume !(1 == ~T10_E~0); 10244#L1299-1 assume !(1 == ~T11_E~0); 10253#L1304-1 assume !(1 == ~E_M~0); 11023#L1309-1 assume !(1 == ~E_1~0); 11026#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 9659#L1319-1 assume !(1 == ~E_3~0); 9660#L1324-1 assume !(1 == ~E_4~0); 9792#L1329-1 assume !(1 == ~E_5~0); 9793#L1334-1 assume !(1 == ~E_6~0); 10871#L1339-1 assume !(1 == ~E_7~0); 10948#L1344-1 assume !(1 == ~E_8~0); 10949#L1349-1 assume !(1 == ~E_9~0); 10376#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 10377#L1359-1 assume !(1 == ~E_11~0); 10736#L1364-1 assume { :end_inline_reset_delta_events } true; 9881#L1690-2 [2021-11-13 18:20:40,100 INFO L793 eck$LassoCheckResult]: Loop: 9881#L1690-2 assume !false; 9882#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9767#L1096 assume !false; 10745#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9613#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9614#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10640#L923 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 10108#L937 assume !(0 != eval_~tmp~0#1); 10109#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10579#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10085#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10086#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10999#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10291#L1131-3 assume !(0 == ~T3_E~0); 10292#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11030#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10646#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9828#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9829#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10943#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10454#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10455#L1171-3 assume !(0 == ~T11_E~0); 10500#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9877#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9878#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10581#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10582#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10772#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10773#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10478#L1211-3 assume !(0 == ~E_7~0); 9790#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9791#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 10204#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9847#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 9848#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10068#L556-39 assume 1 == ~m_pc~0; 10589#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10556#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9947#L568-13 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9948#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 10120#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10514#L575-39 assume 1 == ~t1_pc~0; 10515#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10780#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10641#L587-13 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10642#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10489#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10490#L594-39 assume !(1 == ~t2_pc~0); 10701#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 10492#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10493#L606-13 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10915#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10006#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10007#L613-39 assume 1 == ~t3_pc~0; 10892#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9489#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9490#L625-13 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10248#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9588#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9589#L632-39 assume !(1 == ~t4_pc~0); 10737#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 10174#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10175#L644-13 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10728#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10859#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9858#L651-39 assume 1 == ~t5_pc~0; 9859#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9621#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10847#L663-13 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10954#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 10992#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11012#L670-39 assume 1 == ~t6_pc~0; 11013#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9533#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9534#L682-13 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9604#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10201#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10202#L689-39 assume !(1 == ~t7_pc~0); 10324#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 10325#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9860#L701-13 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9861#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9728#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9729#L708-39 assume 1 == ~t8_pc~0; 9665#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9666#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9772#L720-13 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9773#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10655#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10147#L727-39 assume !(1 == ~t9_pc~0); 10148#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 9925#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9926#L739-13 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 10875#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 10704#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10705#L746-39 assume 1 == ~t10_pc~0; 10674#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10675#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10940#L758-13 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 10410#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 10411#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10823#L765-39 assume 1 == ~t11_pc~0; 9539#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 9541#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10723#L777-13 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9879#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 9880#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10447#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9685#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9686#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10942#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10570#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9644#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9645#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10975#L1279-3 assume !(1 == ~T7_E~0); 10123#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10124#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10118#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 10119#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 10370#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10371#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10032#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10033#L1319-3 assume !(1 == ~E_3~0); 10789#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9751#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9752#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10304#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10305#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10523#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10014#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10015#L1359-3 assume !(1 == ~E_11~0); 10538#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 9605#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9606#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10232#L923-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 10233#L1709 assume !(0 == start_simulation_~tmp~3#1); 10043#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10809#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9719#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10221#L923-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 9682#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9683#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10501#L1672 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 10882#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 9881#L1690-2 [2021-11-13 18:20:40,100 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:40,101 INFO L85 PathProgramCache]: Analyzing trace with hash -1332337988, now seen corresponding path program 1 times [2021-11-13 18:20:40,102 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:40,102 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1157468383] [2021-11-13 18:20:40,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:40,103 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:40,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:40,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:40,162 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:40,163 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1157468383] [2021-11-13 18:20:40,163 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1157468383] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:40,164 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:40,164 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:40,164 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [353564839] [2021-11-13 18:20:40,165 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:40,165 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:20:40,165 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:40,168 INFO L85 PathProgramCache]: Analyzing trace with hash -1000867648, now seen corresponding path program 1 times [2021-11-13 18:20:40,168 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:40,172 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [817882509] [2021-11-13 18:20:40,173 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:40,174 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:40,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:40,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:40,246 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:40,247 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [817882509] [2021-11-13 18:20:40,254 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [817882509] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:40,254 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:40,255 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:40,255 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1423207296] [2021-11-13 18:20:40,255 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:40,256 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:20:40,256 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:20:40,257 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:20:40,257 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:20:40,258 INFO L87 Difference]: Start difference. First operand 1571 states and 2332 transitions. cyclomatic complexity: 762 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:40,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:20:40,296 INFO L93 Difference]: Finished difference Result 1571 states and 2331 transitions. [2021-11-13 18:20:40,297 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:20:40,298 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2331 transitions. [2021-11-13 18:20:40,311 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:40,325 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2331 transitions. [2021-11-13 18:20:40,325 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-11-13 18:20:40,327 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-11-13 18:20:40,327 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2331 transitions. [2021-11-13 18:20:40,331 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:20:40,331 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2331 transitions. [2021-11-13 18:20:40,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2331 transitions. [2021-11-13 18:20:40,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-11-13 18:20:40,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4837683004455762) internal successors, (2331), 1570 states have internal predecessors, (2331), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:40,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2331 transitions. [2021-11-13 18:20:40,367 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2331 transitions. [2021-11-13 18:20:40,367 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2331 transitions. [2021-11-13 18:20:40,367 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-13 18:20:40,367 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2331 transitions. [2021-11-13 18:20:40,377 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:40,378 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:20:40,378 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:20:40,380 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:40,381 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:40,381 INFO L791 eck$LassoCheckResult]: Stem: 13290#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 13291#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 13829#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13830#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13699#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 13700#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12707#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12708#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14146#L807-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13673#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13674#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13951#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13952#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14035#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14117#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 14118#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13999#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13847#L1121 assume !(0 == ~M_E~0); 13602#L1121-2 assume !(0 == ~T1_E~0); 12984#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12985#L1131-1 assume !(0 == ~T3_E~0); 13154#L1136-1 assume !(0 == ~T4_E~0); 13250#L1141-1 assume !(0 == ~T5_E~0); 13470#L1146-1 assume !(0 == ~T6_E~0); 13770#L1151-1 assume !(0 == ~T7_E~0); 13310#L1156-1 assume !(0 == ~T8_E~0); 12693#L1161-1 assume !(0 == ~T9_E~0); 12694#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12919#L1171-1 assume !(0 == ~T11_E~0); 12920#L1176-1 assume !(0 == ~E_M~0); 13784#L1181-1 assume !(0 == ~E_1~0); 13912#L1186-1 assume !(0 == ~E_2~0); 13962#L1191-1 assume !(0 == ~E_3~0); 12946#L1196-1 assume !(0 == ~E_4~0); 12947#L1201-1 assume !(0 == ~E_5~0); 14155#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 14000#L1211-1 assume !(0 == ~E_7~0); 14001#L1216-1 assume !(0 == ~E_8~0); 13089#L1221-1 assume !(0 == ~E_9~0); 13090#L1226-1 assume !(0 == ~E_10~0); 12789#L1231-1 assume !(0 == ~E_11~0); 12790#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13785#L556 assume 1 == ~m_pc~0; 13786#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12667#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12668#L568 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13564#L1391 assume !(0 != activate_threads_~tmp~1#1); 13940#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13941#L575 assume !(1 == ~t1_pc~0); 12618#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12619#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12752#L587 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13102#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 13059#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13060#L594 assume 1 == ~t2_pc~0; 12988#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12989#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13455#L606 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12682#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 12683#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12741#L613 assume !(1 == ~t3_pc~0); 12860#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12859#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12785#L625 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12786#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 13469#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13187#L632 assume 1 == ~t4_pc~0; 13188#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13688#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13848#L644 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 14156#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 13794#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13545#L651 assume 1 == ~t5_pc~0; 13546#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12873#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12874#L663 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13322#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 12890#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12891#L670 assume !(1 == ~t6_pc~0); 13982#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 13236#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13237#L682 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14079#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13510#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13511#L689 assume 1 == ~t7_pc~0; 14152#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13621#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13622#L701 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13997#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 13413#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13414#L708 assume !(1 == ~t8_pc~0); 12979#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12980#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14077#L720 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14062#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 13044#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13045#L727 assume 1 == ~t9_pc~0; 13167#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12743#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 14159#L739 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14160#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 14147#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13098#L746 assume !(1 == ~t10_pc~0); 13099#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 13747#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13863#L758 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 14071#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 13944#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13259#L765 assume 1 == ~t11_pc~0; 13260#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13465#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12632#L777 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12633#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 13981#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14059#L1249 assume !(1 == ~M_E~0); 13692#L1249-2 assume !(1 == ~T1_E~0); 13342#L1254-1 assume !(1 == ~T2_E~0); 12678#L1259-1 assume !(1 == ~T3_E~0); 12660#L1264-1 assume !(1 == ~T4_E~0); 12661#L1269-1 assume !(1 == ~T5_E~0); 14178#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14126#L1279-1 assume !(1 == ~T7_E~0); 12861#L1284-1 assume !(1 == ~T8_E~0); 12862#L1289-1 assume !(1 == ~T9_E~0); 13392#L1294-1 assume !(1 == ~T10_E~0); 13393#L1299-1 assume !(1 == ~T11_E~0); 13402#L1304-1 assume !(1 == ~E_M~0); 14172#L1309-1 assume !(1 == ~E_1~0); 14175#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 12808#L1319-1 assume !(1 == ~E_3~0); 12809#L1324-1 assume !(1 == ~E_4~0); 12941#L1329-1 assume !(1 == ~E_5~0); 12942#L1334-1 assume !(1 == ~E_6~0); 14020#L1339-1 assume !(1 == ~E_7~0); 14097#L1344-1 assume !(1 == ~E_8~0); 14098#L1349-1 assume !(1 == ~E_9~0); 13525#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 13526#L1359-1 assume !(1 == ~E_11~0); 13885#L1364-1 assume { :end_inline_reset_delta_events } true; 13030#L1690-2 [2021-11-13 18:20:40,382 INFO L793 eck$LassoCheckResult]: Loop: 13030#L1690-2 assume !false; 13031#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12916#L1096 assume !false; 13894#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12762#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12763#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13788#L923 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 13257#L937 assume !(0 != eval_~tmp~0#1); 13258#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13728#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13234#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13235#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14148#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13440#L1131-3 assume !(0 == ~T3_E~0); 13441#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14179#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13795#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12977#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12978#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14092#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13603#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13604#L1171-3 assume !(0 == ~T11_E~0); 13650#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13026#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13027#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13730#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13731#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13921#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13922#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13627#L1211-3 assume !(0 == ~E_7~0); 12939#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12940#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 13353#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12996#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 12997#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13217#L556-39 assume 1 == ~m_pc~0; 13738#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13705#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13096#L568-13 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13097#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 13269#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13663#L575-39 assume 1 == ~t1_pc~0; 13664#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13929#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13790#L587-13 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13791#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13638#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13639#L594-39 assume !(1 == ~t2_pc~0); 13850#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 13641#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13642#L606-13 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14064#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13155#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13156#L613-39 assume 1 == ~t3_pc~0; 14041#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12638#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12639#L625-13 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13398#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12737#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12738#L632-39 assume 1 == ~t4_pc~0; 14009#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13323#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13324#L644-13 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13877#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14008#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13007#L651-39 assume 1 == ~t5_pc~0; 13008#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12770#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13996#L663-13 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14104#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14141#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14161#L670-39 assume 1 == ~t6_pc~0; 14162#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12684#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12685#L682-13 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12756#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13350#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13351#L689-39 assume !(1 == ~t7_pc~0); 13474#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 13475#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13009#L701-13 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13010#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12875#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12876#L708-39 assume !(1 == ~t8_pc~0); 12816#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 12815#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12921#L720-13 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12922#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13804#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13295#L727-39 assume !(1 == ~t9_pc~0); 13296#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 13074#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13075#L739-13 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 14024#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 13852#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13853#L746-39 assume !(1 == ~t10_pc~0); 13825#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 13824#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14089#L758-13 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13559#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13560#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13972#L765-39 assume 1 == ~t11_pc~0; 12688#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 12690#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13872#L777-13 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13028#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13029#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13596#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12833#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12834#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14091#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13719#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12793#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12794#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14124#L1279-3 assume !(1 == ~T7_E~0); 13272#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13273#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13265#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13266#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13519#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13520#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13180#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13181#L1319-3 assume !(1 == ~E_3~0); 13938#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12897#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12898#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13453#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13454#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13672#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13163#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13164#L1359-3 assume !(1 == ~E_11~0); 13686#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 12753#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12754#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13381#L923-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 13382#L1709 assume !(0 == start_simulation_~tmp~3#1); 13192#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13958#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12868#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13370#L923-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 12831#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12832#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13649#L1672 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 14031#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 13030#L1690-2 [2021-11-13 18:20:40,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:40,383 INFO L85 PathProgramCache]: Analyzing trace with hash -1621157378, now seen corresponding path program 1 times [2021-11-13 18:20:40,383 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:40,383 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1559364670] [2021-11-13 18:20:40,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:40,383 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:40,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:40,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:40,423 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:40,423 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1559364670] [2021-11-13 18:20:40,424 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1559364670] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:40,424 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:40,424 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:40,424 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1587766329] [2021-11-13 18:20:40,424 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:40,425 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:20:40,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:40,425 INFO L85 PathProgramCache]: Analyzing trace with hash -1581912831, now seen corresponding path program 1 times [2021-11-13 18:20:40,426 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:40,426 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [698599312] [2021-11-13 18:20:40,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:40,426 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:40,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:40,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:40,482 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:40,482 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [698599312] [2021-11-13 18:20:40,482 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [698599312] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:40,482 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:40,482 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:40,483 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [190868345] [2021-11-13 18:20:40,483 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:40,483 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:20:40,484 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:20:40,484 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:20:40,484 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:20:40,485 INFO L87 Difference]: Start difference. First operand 1571 states and 2331 transitions. cyclomatic complexity: 761 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:40,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:20:40,527 INFO L93 Difference]: Finished difference Result 1571 states and 2330 transitions. [2021-11-13 18:20:40,527 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:20:40,530 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2330 transitions. [2021-11-13 18:20:40,544 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:40,557 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2330 transitions. [2021-11-13 18:20:40,558 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-11-13 18:20:40,559 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-11-13 18:20:40,560 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2330 transitions. [2021-11-13 18:20:40,562 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:20:40,562 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2330 transitions. [2021-11-13 18:20:40,566 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2330 transitions. [2021-11-13 18:20:40,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-11-13 18:20:40,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4831317632081478) internal successors, (2330), 1570 states have internal predecessors, (2330), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:40,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2330 transitions. [2021-11-13 18:20:40,598 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2330 transitions. [2021-11-13 18:20:40,599 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2330 transitions. [2021-11-13 18:20:40,599 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-13 18:20:40,599 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2330 transitions. [2021-11-13 18:20:40,636 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:40,636 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:20:40,636 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:20:40,639 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:40,639 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:40,639 INFO L791 eck$LassoCheckResult]: Stem: 16437#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 16438#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 16978#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16979#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16848#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 16849#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15856#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15857#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17295#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16822#L812-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16823#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17100#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17101#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17184#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17266#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17267#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17148#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16996#L1121 assume !(0 == ~M_E~0); 16751#L1121-2 assume !(0 == ~T1_E~0); 16132#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16133#L1131-1 assume !(0 == ~T3_E~0); 16303#L1136-1 assume !(0 == ~T4_E~0); 16399#L1141-1 assume !(0 == ~T5_E~0); 16619#L1146-1 assume !(0 == ~T6_E~0); 16919#L1151-1 assume !(0 == ~T7_E~0); 16459#L1156-1 assume !(0 == ~T8_E~0); 15842#L1161-1 assume !(0 == ~T9_E~0); 15843#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16068#L1171-1 assume !(0 == ~T11_E~0); 16069#L1176-1 assume !(0 == ~E_M~0); 16933#L1181-1 assume !(0 == ~E_1~0); 17061#L1186-1 assume !(0 == ~E_2~0); 17111#L1191-1 assume !(0 == ~E_3~0); 16095#L1196-1 assume !(0 == ~E_4~0); 16096#L1201-1 assume !(0 == ~E_5~0); 17304#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 17149#L1211-1 assume !(0 == ~E_7~0); 17150#L1216-1 assume !(0 == ~E_8~0); 16238#L1221-1 assume !(0 == ~E_9~0); 16239#L1226-1 assume !(0 == ~E_10~0); 15938#L1231-1 assume !(0 == ~E_11~0); 15939#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16934#L556 assume 1 == ~m_pc~0; 16935#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 15816#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15817#L568 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16712#L1391 assume !(0 != activate_threads_~tmp~1#1); 17089#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17090#L575 assume !(1 == ~t1_pc~0); 15767#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15768#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15901#L587 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16251#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 16208#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16209#L594 assume 1 == ~t2_pc~0; 16137#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16138#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16604#L606 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15831#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 15832#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15890#L613 assume !(1 == ~t3_pc~0); 16009#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16008#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15934#L625 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 15935#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 16618#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16336#L632 assume 1 == ~t4_pc~0; 16337#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16837#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16997#L644 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17305#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 16943#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16694#L651 assume 1 == ~t5_pc~0; 16695#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16022#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16023#L663 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16471#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 16039#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16040#L670 assume !(1 == ~t6_pc~0); 17131#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16385#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16386#L682 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17227#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16659#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16660#L689 assume 1 == ~t7_pc~0; 17301#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16770#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16771#L701 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17146#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 16562#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16563#L708 assume !(1 == ~t8_pc~0); 16128#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16129#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17226#L720 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17211#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 16193#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16194#L727 assume 1 == ~t9_pc~0; 16316#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15892#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17308#L739 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17309#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 17296#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16247#L746 assume !(1 == ~t10_pc~0); 16248#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16896#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17012#L758 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17220#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 17093#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16408#L765 assume 1 == ~t11_pc~0; 16409#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16614#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 15781#L777 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 15782#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 17130#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17208#L1249 assume !(1 == ~M_E~0); 16841#L1249-2 assume !(1 == ~T1_E~0); 16491#L1254-1 assume !(1 == ~T2_E~0); 15827#L1259-1 assume !(1 == ~T3_E~0); 15809#L1264-1 assume !(1 == ~T4_E~0); 15810#L1269-1 assume !(1 == ~T5_E~0); 17327#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17275#L1279-1 assume !(1 == ~T7_E~0); 16010#L1284-1 assume !(1 == ~T8_E~0); 16011#L1289-1 assume !(1 == ~T9_E~0); 16541#L1294-1 assume !(1 == ~T10_E~0); 16542#L1299-1 assume !(1 == ~T11_E~0); 16551#L1304-1 assume !(1 == ~E_M~0); 17321#L1309-1 assume !(1 == ~E_1~0); 17324#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 15957#L1319-1 assume !(1 == ~E_3~0); 15958#L1324-1 assume !(1 == ~E_4~0); 16090#L1329-1 assume !(1 == ~E_5~0); 16091#L1334-1 assume !(1 == ~E_6~0); 17169#L1339-1 assume !(1 == ~E_7~0); 17246#L1344-1 assume !(1 == ~E_8~0); 17247#L1349-1 assume !(1 == ~E_9~0); 16674#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 16675#L1359-1 assume !(1 == ~E_11~0); 17034#L1364-1 assume { :end_inline_reset_delta_events } true; 16179#L1690-2 [2021-11-13 18:20:40,640 INFO L793 eck$LassoCheckResult]: Loop: 16179#L1690-2 assume !false; 16180#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16065#L1096 assume !false; 17043#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15911#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15912#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16937#L923 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 16406#L937 assume !(0 != eval_~tmp~0#1); 16407#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16877#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16381#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16382#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17297#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16589#L1131-3 assume !(0 == ~T3_E~0); 16590#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17328#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16944#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16126#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16127#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17241#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16752#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16753#L1171-3 assume !(0 == ~T11_E~0); 16798#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16175#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16176#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16879#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16880#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17070#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17071#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16776#L1211-3 assume !(0 == ~E_7~0); 16088#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16089#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16502#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16145#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16146#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16366#L556-39 assume 1 == ~m_pc~0; 16887#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 16854#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16245#L568-13 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16246#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 16418#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16812#L575-39 assume 1 == ~t1_pc~0; 16813#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17078#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16939#L587-13 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16940#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16787#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16788#L594-39 assume !(1 == ~t2_pc~0); 16999#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 16790#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16791#L606-13 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17213#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16304#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16305#L613-39 assume 1 == ~t3_pc~0; 17190#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15787#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15788#L625-13 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16546#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15886#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15887#L632-39 assume 1 == ~t4_pc~0; 17158#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16472#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16473#L644-13 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17026#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17157#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16156#L651-39 assume 1 == ~t5_pc~0; 16157#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15919#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17145#L663-13 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17252#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17290#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17310#L670-39 assume !(1 == ~t6_pc~0); 16889#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 15833#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15834#L682-13 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 15902#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16499#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16500#L689-39 assume 1 == ~t7_pc~0; 16722#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16624#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16158#L701-13 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16159#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16026#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16027#L708-39 assume 1 == ~t8_pc~0; 15963#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15964#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16072#L720-13 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16073#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16953#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16445#L727-39 assume !(1 == ~t9_pc~0); 16446#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 16223#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16224#L739-13 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17173#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 17002#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17003#L746-39 assume 1 == ~t10_pc~0; 16972#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16973#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17238#L758-13 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16708#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16709#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17121#L765-39 assume 1 == ~t11_pc~0; 15837#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 15839#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17021#L777-13 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 16177#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16178#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16745#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15983#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15984#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17240#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16868#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15942#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15943#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17273#L1279-3 assume !(1 == ~T7_E~0); 16421#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16422#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16416#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16417#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16668#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16669#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16333#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16334#L1319-3 assume !(1 == ~E_3~0); 17087#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16052#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16053#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16602#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16603#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16821#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 16312#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16313#L1359-3 assume !(1 == ~E_11~0); 16836#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 15903#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15904#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16530#L923-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 16531#L1709 assume !(0 == start_simulation_~tmp~3#1); 16341#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 17107#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 16017#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16519#L923-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 15980#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15981#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16799#L1672 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 17180#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 16179#L1690-2 [2021-11-13 18:20:40,646 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:40,646 INFO L85 PathProgramCache]: Analyzing trace with hash -1076284804, now seen corresponding path program 1 times [2021-11-13 18:20:40,647 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:40,647 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1317608208] [2021-11-13 18:20:40,647 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:40,647 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:40,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:40,691 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:40,691 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:40,691 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1317608208] [2021-11-13 18:20:40,692 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1317608208] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:40,692 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:40,692 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:40,692 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1933001135] [2021-11-13 18:20:40,692 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:40,693 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:20:40,693 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:40,693 INFO L85 PathProgramCache]: Analyzing trace with hash 210812735, now seen corresponding path program 1 times [2021-11-13 18:20:40,695 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:40,700 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [36403215] [2021-11-13 18:20:40,703 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:40,704 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:40,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:40,747 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:40,747 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:40,747 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [36403215] [2021-11-13 18:20:40,747 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [36403215] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:40,747 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:40,748 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:40,749 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [95620037] [2021-11-13 18:20:40,750 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:40,750 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:20:40,751 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:20:40,751 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:20:40,752 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:20:40,752 INFO L87 Difference]: Start difference. First operand 1571 states and 2330 transitions. cyclomatic complexity: 760 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:40,788 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:20:40,789 INFO L93 Difference]: Finished difference Result 1571 states and 2329 transitions. [2021-11-13 18:20:40,789 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:20:40,791 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2329 transitions. [2021-11-13 18:20:40,802 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:40,817 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2329 transitions. [2021-11-13 18:20:40,817 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-11-13 18:20:40,819 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-11-13 18:20:40,819 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2329 transitions. [2021-11-13 18:20:40,821 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:20:40,822 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2329 transitions. [2021-11-13 18:20:40,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2329 transitions. [2021-11-13 18:20:40,848 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-11-13 18:20:40,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4824952259707194) internal successors, (2329), 1570 states have internal predecessors, (2329), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:40,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2329 transitions. [2021-11-13 18:20:40,859 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2329 transitions. [2021-11-13 18:20:40,860 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2329 transitions. [2021-11-13 18:20:40,860 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-13 18:20:40,860 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2329 transitions. [2021-11-13 18:20:40,870 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:40,870 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:20:40,870 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:20:40,873 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:40,873 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:40,873 INFO L791 eck$LassoCheckResult]: Stem: 19586#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 19587#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 20127#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20128#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19997#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 19998#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19005#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19006#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20444#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19971#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19972#L817-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 20249#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20250#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 20333#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 20415#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 20416#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 20297#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20145#L1121 assume !(0 == ~M_E~0); 19900#L1121-2 assume !(0 == ~T1_E~0); 19281#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19282#L1131-1 assume !(0 == ~T3_E~0); 19452#L1136-1 assume !(0 == ~T4_E~0); 19548#L1141-1 assume !(0 == ~T5_E~0); 19768#L1146-1 assume !(0 == ~T6_E~0); 20068#L1151-1 assume !(0 == ~T7_E~0); 19608#L1156-1 assume !(0 == ~T8_E~0); 18991#L1161-1 assume !(0 == ~T9_E~0); 18992#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19217#L1171-1 assume !(0 == ~T11_E~0); 19218#L1176-1 assume !(0 == ~E_M~0); 20082#L1181-1 assume !(0 == ~E_1~0); 20210#L1186-1 assume !(0 == ~E_2~0); 20260#L1191-1 assume !(0 == ~E_3~0); 19244#L1196-1 assume !(0 == ~E_4~0); 19245#L1201-1 assume !(0 == ~E_5~0); 20453#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 20298#L1211-1 assume !(0 == ~E_7~0); 20299#L1216-1 assume !(0 == ~E_8~0); 19387#L1221-1 assume !(0 == ~E_9~0); 19388#L1226-1 assume !(0 == ~E_10~0); 19087#L1231-1 assume !(0 == ~E_11~0); 19088#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20083#L556 assume 1 == ~m_pc~0; 20084#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 18965#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18966#L568 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19861#L1391 assume !(0 != activate_threads_~tmp~1#1); 20238#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20239#L575 assume !(1 == ~t1_pc~0); 18916#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18917#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19050#L587 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19400#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 19357#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19358#L594 assume 1 == ~t2_pc~0; 19286#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19287#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19753#L606 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18980#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 18981#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19039#L613 assume !(1 == ~t3_pc~0); 19158#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19157#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19083#L625 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19084#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 19767#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19485#L632 assume 1 == ~t4_pc~0; 19486#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19986#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20146#L644 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20454#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 20092#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19843#L651 assume 1 == ~t5_pc~0; 19844#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19171#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19172#L663 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 19620#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 19188#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19189#L670 assume !(1 == ~t6_pc~0); 20280#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19534#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19535#L682 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20376#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19808#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19809#L689 assume 1 == ~t7_pc~0; 20450#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19919#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19920#L701 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20295#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 19711#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19712#L708 assume !(1 == ~t8_pc~0); 19277#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19278#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20375#L720 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20360#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 19342#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19343#L727 assume 1 == ~t9_pc~0; 19465#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19041#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20457#L739 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20458#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 20445#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19396#L746 assume !(1 == ~t10_pc~0); 19397#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20045#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20161#L758 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20369#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 20242#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19557#L765 assume 1 == ~t11_pc~0; 19558#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 19763#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18930#L777 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 18931#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 20279#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20357#L1249 assume !(1 == ~M_E~0); 19990#L1249-2 assume !(1 == ~T1_E~0); 19640#L1254-1 assume !(1 == ~T2_E~0); 18976#L1259-1 assume !(1 == ~T3_E~0); 18958#L1264-1 assume !(1 == ~T4_E~0); 18959#L1269-1 assume !(1 == ~T5_E~0); 20476#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20424#L1279-1 assume !(1 == ~T7_E~0); 19159#L1284-1 assume !(1 == ~T8_E~0); 19160#L1289-1 assume !(1 == ~T9_E~0); 19690#L1294-1 assume !(1 == ~T10_E~0); 19691#L1299-1 assume !(1 == ~T11_E~0); 19700#L1304-1 assume !(1 == ~E_M~0); 20470#L1309-1 assume !(1 == ~E_1~0); 20473#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 19106#L1319-1 assume !(1 == ~E_3~0); 19107#L1324-1 assume !(1 == ~E_4~0); 19239#L1329-1 assume !(1 == ~E_5~0); 19240#L1334-1 assume !(1 == ~E_6~0); 20318#L1339-1 assume !(1 == ~E_7~0); 20395#L1344-1 assume !(1 == ~E_8~0); 20396#L1349-1 assume !(1 == ~E_9~0); 19823#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 19824#L1359-1 assume !(1 == ~E_11~0); 20183#L1364-1 assume { :end_inline_reset_delta_events } true; 19328#L1690-2 [2021-11-13 18:20:40,874 INFO L793 eck$LassoCheckResult]: Loop: 19328#L1690-2 assume !false; 19329#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19214#L1096 assume !false; 20192#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19060#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19061#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 20086#L923 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 19555#L937 assume !(0 != eval_~tmp~0#1); 19556#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20026#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19530#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19531#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20446#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19738#L1131-3 assume !(0 == ~T3_E~0); 19739#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20477#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20093#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19275#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19276#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20390#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19901#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19902#L1171-3 assume !(0 == ~T11_E~0); 19947#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19324#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19325#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 20028#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 20029#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20219#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20220#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19925#L1211-3 assume !(0 == ~E_7~0); 19237#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19238#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19651#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19294#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 19295#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19515#L556-39 assume 1 == ~m_pc~0; 20036#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20003#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19394#L568-13 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19395#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 19567#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19961#L575-39 assume 1 == ~t1_pc~0; 19962#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20227#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20088#L587-13 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20089#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19936#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19937#L594-39 assume !(1 == ~t2_pc~0); 20148#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 19939#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19940#L606-13 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20362#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19453#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19454#L613-39 assume 1 == ~t3_pc~0; 20339#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18936#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18937#L625-13 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19695#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19035#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19036#L632-39 assume 1 == ~t4_pc~0; 20307#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 19621#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19622#L644-13 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20175#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20306#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19305#L651-39 assume 1 == ~t5_pc~0; 19306#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19068#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20294#L663-13 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20401#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 20439#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20459#L670-39 assume !(1 == ~t6_pc~0); 20038#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 18982#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18983#L682-13 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19051#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19648#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19649#L689-39 assume !(1 == ~t7_pc~0); 19772#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 19773#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19307#L701-13 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19308#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19175#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19176#L708-39 assume 1 == ~t8_pc~0; 19112#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19113#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19221#L720-13 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19222#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20102#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19594#L727-39 assume !(1 == ~t9_pc~0); 19595#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 19372#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19373#L739-13 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20322#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 20151#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20152#L746-39 assume 1 == ~t10_pc~0; 20121#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20122#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 20387#L758-13 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19857#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19858#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20270#L765-39 assume 1 == ~t11_pc~0; 18986#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 18988#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20170#L777-13 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 19326#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19327#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19894#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19132#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19133#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20389#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20017#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19091#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19092#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20422#L1279-3 assume !(1 == ~T7_E~0); 19570#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19571#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19565#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19566#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 19817#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19818#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19482#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19483#L1319-3 assume !(1 == ~E_3~0); 20236#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19201#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 19202#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19751#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19752#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19970#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19461#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19462#L1359-3 assume !(1 == ~E_11~0); 19985#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19052#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19053#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19679#L923-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 19680#L1709 assume !(0 == start_simulation_~tmp~3#1); 19490#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 20256#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19166#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19668#L923-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 19129#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19130#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19948#L1672 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 20329#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 19328#L1690-2 [2021-11-13 18:20:40,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:40,875 INFO L85 PathProgramCache]: Analyzing trace with hash -1751444930, now seen corresponding path program 1 times [2021-11-13 18:20:40,875 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:40,876 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1266779982] [2021-11-13 18:20:40,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:40,876 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:40,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:40,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:40,910 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:40,911 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1266779982] [2021-11-13 18:20:40,911 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1266779982] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:40,911 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:40,911 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:40,912 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1193222543] [2021-11-13 18:20:40,912 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:40,913 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:20:40,913 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:40,913 INFO L85 PathProgramCache]: Analyzing trace with hash -1946660288, now seen corresponding path program 2 times [2021-11-13 18:20:40,913 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:40,914 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1759977183] [2021-11-13 18:20:40,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:40,914 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:40,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:40,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:40,972 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:40,972 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1759977183] [2021-11-13 18:20:40,972 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1759977183] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:40,972 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:40,974 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:40,974 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1008050780] [2021-11-13 18:20:40,975 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:40,975 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:20:40,975 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:20:40,976 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:20:40,977 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:20:40,978 INFO L87 Difference]: Start difference. First operand 1571 states and 2329 transitions. cyclomatic complexity: 759 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:41,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:20:41,027 INFO L93 Difference]: Finished difference Result 1571 states and 2328 transitions. [2021-11-13 18:20:41,027 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:20:41,029 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2328 transitions. [2021-11-13 18:20:41,040 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:41,054 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2328 transitions. [2021-11-13 18:20:41,054 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-11-13 18:20:41,056 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-11-13 18:20:41,056 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2328 transitions. [2021-11-13 18:20:41,059 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:20:41,059 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2328 transitions. [2021-11-13 18:20:41,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2328 transitions. [2021-11-13 18:20:41,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-11-13 18:20:41,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.481858688733291) internal successors, (2328), 1570 states have internal predecessors, (2328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:41,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2328 transitions. [2021-11-13 18:20:41,096 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2328 transitions. [2021-11-13 18:20:41,096 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2328 transitions. [2021-11-13 18:20:41,096 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-13 18:20:41,096 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2328 transitions. [2021-11-13 18:20:41,104 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:41,104 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:20:41,104 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:20:41,107 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:41,107 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:41,108 INFO L791 eck$LassoCheckResult]: Stem: 22735#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 22736#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 23276#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23277#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 23146#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 23147#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22154#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22155#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23593#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23120#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 23121#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 23398#L822-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23399#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 23482#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 23564#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 23565#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 23446#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23294#L1121 assume !(0 == ~M_E~0); 23049#L1121-2 assume !(0 == ~T1_E~0); 22430#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22431#L1131-1 assume !(0 == ~T3_E~0); 22601#L1136-1 assume !(0 == ~T4_E~0); 22697#L1141-1 assume !(0 == ~T5_E~0); 22917#L1146-1 assume !(0 == ~T6_E~0); 23217#L1151-1 assume !(0 == ~T7_E~0); 22757#L1156-1 assume !(0 == ~T8_E~0); 22140#L1161-1 assume !(0 == ~T9_E~0); 22141#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22366#L1171-1 assume !(0 == ~T11_E~0); 22367#L1176-1 assume !(0 == ~E_M~0); 23231#L1181-1 assume !(0 == ~E_1~0); 23359#L1186-1 assume !(0 == ~E_2~0); 23409#L1191-1 assume !(0 == ~E_3~0); 22393#L1196-1 assume !(0 == ~E_4~0); 22394#L1201-1 assume !(0 == ~E_5~0); 23602#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 23447#L1211-1 assume !(0 == ~E_7~0); 23448#L1216-1 assume !(0 == ~E_8~0); 22536#L1221-1 assume !(0 == ~E_9~0); 22537#L1226-1 assume !(0 == ~E_10~0); 22236#L1231-1 assume !(0 == ~E_11~0); 22237#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23232#L556 assume 1 == ~m_pc~0; 23233#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 22114#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22115#L568 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23010#L1391 assume !(0 != activate_threads_~tmp~1#1); 23387#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23388#L575 assume !(1 == ~t1_pc~0); 22065#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22066#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22199#L587 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22549#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 22506#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22507#L594 assume 1 == ~t2_pc~0; 22435#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22436#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22902#L606 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22129#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 22130#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22188#L613 assume !(1 == ~t3_pc~0); 22307#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22306#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22232#L625 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22233#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 22916#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22634#L632 assume 1 == ~t4_pc~0; 22635#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23135#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23295#L644 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23603#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 23241#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22992#L651 assume 1 == ~t5_pc~0; 22993#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22320#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22321#L663 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22769#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 22337#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22338#L670 assume !(1 == ~t6_pc~0); 23429#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22683#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22684#L682 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23525#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22957#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22958#L689 assume 1 == ~t7_pc~0; 23599#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23068#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23069#L701 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23444#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 22860#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22861#L708 assume !(1 == ~t8_pc~0); 22426#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22427#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23524#L720 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23509#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 22491#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22492#L727 assume 1 == ~t9_pc~0; 22614#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22190#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23606#L739 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23607#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 23594#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 22545#L746 assume !(1 == ~t10_pc~0); 22546#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 23194#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23310#L758 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23518#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 23391#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22706#L765 assume 1 == ~t11_pc~0; 22707#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22912#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22079#L777 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22080#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 23428#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23506#L1249 assume !(1 == ~M_E~0); 23139#L1249-2 assume !(1 == ~T1_E~0); 22789#L1254-1 assume !(1 == ~T2_E~0); 22125#L1259-1 assume !(1 == ~T3_E~0); 22107#L1264-1 assume !(1 == ~T4_E~0); 22108#L1269-1 assume !(1 == ~T5_E~0); 23625#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23573#L1279-1 assume !(1 == ~T7_E~0); 22308#L1284-1 assume !(1 == ~T8_E~0); 22309#L1289-1 assume !(1 == ~T9_E~0); 22839#L1294-1 assume !(1 == ~T10_E~0); 22840#L1299-1 assume !(1 == ~T11_E~0); 22849#L1304-1 assume !(1 == ~E_M~0); 23619#L1309-1 assume !(1 == ~E_1~0); 23622#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22255#L1319-1 assume !(1 == ~E_3~0); 22256#L1324-1 assume !(1 == ~E_4~0); 22388#L1329-1 assume !(1 == ~E_5~0); 22389#L1334-1 assume !(1 == ~E_6~0); 23467#L1339-1 assume !(1 == ~E_7~0); 23544#L1344-1 assume !(1 == ~E_8~0); 23545#L1349-1 assume !(1 == ~E_9~0); 22972#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 22973#L1359-1 assume !(1 == ~E_11~0); 23332#L1364-1 assume { :end_inline_reset_delta_events } true; 22477#L1690-2 [2021-11-13 18:20:41,108 INFO L793 eck$LassoCheckResult]: Loop: 22477#L1690-2 assume !false; 22478#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22363#L1096 assume !false; 23341#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22209#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22210#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 23235#L923 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 22704#L937 assume !(0 != eval_~tmp~0#1); 22705#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 23175#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22679#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22680#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23595#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22887#L1131-3 assume !(0 == ~T3_E~0); 22888#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23626#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23242#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 22424#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22425#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23539#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23050#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 23051#L1171-3 assume !(0 == ~T11_E~0); 23096#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 22473#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22474#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23177#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23178#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23368#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23369#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23074#L1211-3 assume !(0 == ~E_7~0); 22386#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22387#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22800#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22443#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22444#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22664#L556-39 assume 1 == ~m_pc~0; 23185#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23152#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22543#L568-13 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22544#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 22716#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23110#L575-39 assume 1 == ~t1_pc~0; 23111#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 23376#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23237#L587-13 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23238#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23085#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23086#L594-39 assume !(1 == ~t2_pc~0); 23297#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 23088#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23089#L606-13 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23511#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22602#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22603#L613-39 assume 1 == ~t3_pc~0; 23488#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22085#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22086#L625-13 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22844#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22184#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22185#L632-39 assume 1 == ~t4_pc~0; 23456#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22770#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22771#L644-13 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 23324#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23455#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22454#L651-39 assume 1 == ~t5_pc~0; 22455#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22217#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23443#L663-13 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23550#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 23588#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 23608#L670-39 assume !(1 == ~t6_pc~0); 23187#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 22131#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22132#L682-13 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22200#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22797#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22798#L689-39 assume !(1 == ~t7_pc~0); 22921#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 22922#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22456#L701-13 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22457#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22324#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22325#L708-39 assume 1 == ~t8_pc~0; 22261#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22262#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22370#L720-13 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22371#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 23251#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22743#L727-39 assume !(1 == ~t9_pc~0); 22744#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 22521#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22522#L739-13 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 23471#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 23300#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23301#L746-39 assume 1 == ~t10_pc~0; 23270#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23271#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 23536#L758-13 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 23006#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 23007#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23419#L765-39 assume 1 == ~t11_pc~0; 22135#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 22137#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23319#L777-13 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22475#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 22476#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23043#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22281#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22282#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23538#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23166#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22240#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22241#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23571#L1279-3 assume !(1 == ~T7_E~0); 22719#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22720#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22714#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22715#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22966#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22967#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22631#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22632#L1319-3 assume !(1 == ~E_3~0); 23385#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22350#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 22351#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 22900#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22901#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 23119#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22610#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22611#L1359-3 assume !(1 == ~E_11~0); 23134#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22201#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22202#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22828#L923-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 22829#L1709 assume !(0 == start_simulation_~tmp~3#1); 22639#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 23405#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22315#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22817#L923-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 22278#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22279#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 23097#L1672 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 23478#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 22477#L1690-2 [2021-11-13 18:20:41,109 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:41,109 INFO L85 PathProgramCache]: Analyzing trace with hash -803392964, now seen corresponding path program 1 times [2021-11-13 18:20:41,109 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:41,110 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1725672063] [2021-11-13 18:20:41,110 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:41,110 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:41,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:41,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:41,148 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:41,148 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1725672063] [2021-11-13 18:20:41,148 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1725672063] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:41,149 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:41,150 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:41,150 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1255245351] [2021-11-13 18:20:41,150 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:41,151 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:20:41,151 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:41,151 INFO L85 PathProgramCache]: Analyzing trace with hash -1946660288, now seen corresponding path program 3 times [2021-11-13 18:20:41,151 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:41,152 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [202775653] [2021-11-13 18:20:41,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:41,152 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:41,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:41,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:41,200 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:41,202 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [202775653] [2021-11-13 18:20:41,204 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [202775653] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:41,204 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:41,205 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:41,205 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1840116617] [2021-11-13 18:20:41,205 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:41,205 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:20:41,206 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:20:41,206 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:20:41,206 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:20:41,207 INFO L87 Difference]: Start difference. First operand 1571 states and 2328 transitions. cyclomatic complexity: 758 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:41,241 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:20:41,242 INFO L93 Difference]: Finished difference Result 1571 states and 2327 transitions. [2021-11-13 18:20:41,242 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:20:41,245 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2327 transitions. [2021-11-13 18:20:41,256 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:41,270 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2327 transitions. [2021-11-13 18:20:41,270 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-11-13 18:20:41,274 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-11-13 18:20:41,274 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2327 transitions. [2021-11-13 18:20:41,277 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:20:41,277 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2327 transitions. [2021-11-13 18:20:41,280 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2327 transitions. [2021-11-13 18:20:41,312 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-11-13 18:20:41,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4812221514958626) internal successors, (2327), 1570 states have internal predecessors, (2327), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:41,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2327 transitions. [2021-11-13 18:20:41,323 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2327 transitions. [2021-11-13 18:20:41,323 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2327 transitions. [2021-11-13 18:20:41,324 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-13 18:20:41,324 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2327 transitions. [2021-11-13 18:20:41,331 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:41,331 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:20:41,331 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:20:41,334 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:41,334 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:41,335 INFO L791 eck$LassoCheckResult]: Stem: 25886#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 25887#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 26425#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26426#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26295#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 26296#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25303#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25304#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26742#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26269#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26270#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26547#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26548#L827-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 26631#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 26713#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 26714#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 26595#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26443#L1121 assume !(0 == ~M_E~0); 26198#L1121-2 assume !(0 == ~T1_E~0); 25580#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25581#L1131-1 assume !(0 == ~T3_E~0); 25750#L1136-1 assume !(0 == ~T4_E~0); 25846#L1141-1 assume !(0 == ~T5_E~0); 26071#L1146-1 assume !(0 == ~T6_E~0); 26366#L1151-1 assume !(0 == ~T7_E~0); 25906#L1156-1 assume !(0 == ~T8_E~0); 25289#L1161-1 assume !(0 == ~T9_E~0); 25290#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25515#L1171-1 assume !(0 == ~T11_E~0); 25516#L1176-1 assume !(0 == ~E_M~0); 26380#L1181-1 assume !(0 == ~E_1~0); 26508#L1186-1 assume !(0 == ~E_2~0); 26558#L1191-1 assume !(0 == ~E_3~0); 25542#L1196-1 assume !(0 == ~E_4~0); 25543#L1201-1 assume !(0 == ~E_5~0); 26751#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 26596#L1211-1 assume !(0 == ~E_7~0); 26597#L1216-1 assume !(0 == ~E_8~0); 25685#L1221-1 assume !(0 == ~E_9~0); 25686#L1226-1 assume !(0 == ~E_10~0); 25385#L1231-1 assume !(0 == ~E_11~0); 25386#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26381#L556 assume 1 == ~m_pc~0; 26382#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25263#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25264#L568 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26160#L1391 assume !(0 != activate_threads_~tmp~1#1); 26536#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26537#L575 assume !(1 == ~t1_pc~0); 25214#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25215#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25348#L587 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25698#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 25655#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25656#L594 assume 1 == ~t2_pc~0; 25584#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25585#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26051#L606 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 25280#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 25281#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25337#L613 assume !(1 == ~t3_pc~0); 25456#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25455#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25381#L625 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25382#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 26065#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25783#L632 assume 1 == ~t4_pc~0; 25784#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 26284#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26444#L644 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26752#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 26390#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26141#L651 assume 1 == ~t5_pc~0; 26142#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25469#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25470#L663 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25918#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 25486#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25487#L670 assume !(1 == ~t6_pc~0); 26578#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25834#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25835#L682 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26675#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26106#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26107#L689 assume 1 == ~t7_pc~0; 26748#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 26217#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26218#L701 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26593#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 26009#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26010#L708 assume !(1 == ~t8_pc~0); 25575#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25576#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26673#L720 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26658#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 25640#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25641#L727 assume 1 == ~t9_pc~0; 25763#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25339#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26755#L739 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26756#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 26743#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25694#L746 assume !(1 == ~t10_pc~0); 25695#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 26343#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26459#L758 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26667#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 26540#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25855#L765 assume 1 == ~t11_pc~0; 25856#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26061#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25228#L777 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 25229#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 26577#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26655#L1249 assume !(1 == ~M_E~0); 26288#L1249-2 assume !(1 == ~T1_E~0); 25938#L1254-1 assume !(1 == ~T2_E~0); 25274#L1259-1 assume !(1 == ~T3_E~0); 25256#L1264-1 assume !(1 == ~T4_E~0); 25257#L1269-1 assume !(1 == ~T5_E~0); 26774#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26722#L1279-1 assume !(1 == ~T7_E~0); 25457#L1284-1 assume !(1 == ~T8_E~0); 25458#L1289-1 assume !(1 == ~T9_E~0); 25988#L1294-1 assume !(1 == ~T10_E~0); 25989#L1299-1 assume !(1 == ~T11_E~0); 25998#L1304-1 assume !(1 == ~E_M~0); 26768#L1309-1 assume !(1 == ~E_1~0); 26771#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25404#L1319-1 assume !(1 == ~E_3~0); 25405#L1324-1 assume !(1 == ~E_4~0); 25537#L1329-1 assume !(1 == ~E_5~0); 25538#L1334-1 assume !(1 == ~E_6~0); 26616#L1339-1 assume !(1 == ~E_7~0); 26693#L1344-1 assume !(1 == ~E_8~0); 26694#L1349-1 assume !(1 == ~E_9~0); 26121#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 26122#L1359-1 assume !(1 == ~E_11~0); 26481#L1364-1 assume { :end_inline_reset_delta_events } true; 25626#L1690-2 [2021-11-13 18:20:41,335 INFO L793 eck$LassoCheckResult]: Loop: 25626#L1690-2 assume !false; 25627#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25512#L1096 assume !false; 26490#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 25358#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25359#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 26384#L923 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 25853#L937 assume !(0 != eval_~tmp~0#1); 25854#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26324#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25830#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25831#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26744#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26036#L1131-3 assume !(0 == ~T3_E~0); 26037#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26775#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26391#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25573#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25574#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 26688#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26199#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 26200#L1171-3 assume !(0 == ~T11_E~0); 26246#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25622#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25623#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26326#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26327#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26517#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26518#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 26223#L1211-3 assume !(0 == ~E_7~0); 25535#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25536#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25949#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25592#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25593#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25813#L556-39 assume 1 == ~m_pc~0; 26334#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26301#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25692#L568-13 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25693#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 25865#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26259#L575-39 assume 1 == ~t1_pc~0; 26260#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 26525#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26386#L587-13 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26387#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26234#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26235#L594-39 assume !(1 == ~t2_pc~0); 26446#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 26237#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26238#L606-13 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26660#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25751#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25752#L613-39 assume 1 == ~t3_pc~0; 26637#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25234#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25235#L625-13 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25997#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25333#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25334#L632-39 assume !(1 == ~t4_pc~0); 26482#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 25919#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25920#L644-13 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26473#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26604#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25600#L651-39 assume 1 == ~t5_pc~0; 25601#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25364#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26592#L663-13 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26699#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 26737#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26757#L670-39 assume !(1 == ~t6_pc~0); 26336#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 25278#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25279#L682-13 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25349#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25946#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25947#L689-39 assume !(1 == ~t7_pc~0); 26069#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 26070#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25605#L701-13 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25606#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 25473#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25474#L708-39 assume 1 == ~t8_pc~0; 25410#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25411#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25517#L720-13 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25518#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26400#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25892#L727-39 assume !(1 == ~t9_pc~0); 25893#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 25670#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25671#L739-13 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 26620#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 26448#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26449#L746-39 assume 1 == ~t10_pc~0; 26419#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 26420#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 26685#L758-13 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26155#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 26156#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26568#L765-39 assume 1 == ~t11_pc~0; 25284#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25286#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26468#L777-13 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 25624#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25625#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26192#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25430#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25431#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26687#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26315#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25389#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25390#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26720#L1279-3 assume !(1 == ~T7_E~0); 25868#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 25869#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25861#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 25862#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 26115#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 26116#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25776#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25777#L1319-3 assume !(1 == ~E_3~0); 26534#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25493#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25494#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 26049#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 26050#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 26268#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25759#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 25760#L1359-3 assume !(1 == ~E_11~0); 26282#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 25350#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25351#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25977#L923-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 25978#L1709 assume !(0 == start_simulation_~tmp~3#1); 25788#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26554#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25464#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25966#L923-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 25427#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25428#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26245#L1672 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 26627#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 25626#L1690-2 [2021-11-13 18:20:41,336 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:41,336 INFO L85 PathProgramCache]: Analyzing trace with hash -218621314, now seen corresponding path program 1 times [2021-11-13 18:20:41,336 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:41,337 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [217623654] [2021-11-13 18:20:41,337 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:41,337 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:41,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:41,394 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:41,394 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:41,395 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [217623654] [2021-11-13 18:20:41,395 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [217623654] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:41,395 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:41,395 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:41,396 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [402268907] [2021-11-13 18:20:41,396 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:41,397 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:20:41,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:41,397 INFO L85 PathProgramCache]: Analyzing trace with hash 1131120385, now seen corresponding path program 1 times [2021-11-13 18:20:41,397 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:41,398 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [654590714] [2021-11-13 18:20:41,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:41,398 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:41,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:41,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:41,442 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:41,442 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [654590714] [2021-11-13 18:20:41,442 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [654590714] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:41,443 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:41,443 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:41,443 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [738178667] [2021-11-13 18:20:41,443 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:41,444 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:20:41,444 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:20:41,444 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:20:41,445 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:20:41,445 INFO L87 Difference]: Start difference. First operand 1571 states and 2327 transitions. cyclomatic complexity: 757 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:41,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:20:41,488 INFO L93 Difference]: Finished difference Result 1571 states and 2326 transitions. [2021-11-13 18:20:41,488 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:20:41,489 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2326 transitions. [2021-11-13 18:20:41,500 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:41,514 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2326 transitions. [2021-11-13 18:20:41,515 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-11-13 18:20:41,516 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-11-13 18:20:41,517 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2326 transitions. [2021-11-13 18:20:41,519 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:20:41,520 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2326 transitions. [2021-11-13 18:20:41,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2326 transitions. [2021-11-13 18:20:41,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-11-13 18:20:41,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4805856142584342) internal successors, (2326), 1570 states have internal predecessors, (2326), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:41,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2326 transitions. [2021-11-13 18:20:41,555 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2326 transitions. [2021-11-13 18:20:41,556 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2326 transitions. [2021-11-13 18:20:41,556 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-13 18:20:41,556 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2326 transitions. [2021-11-13 18:20:41,563 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:41,564 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:20:41,564 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:20:41,566 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:41,566 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:41,567 INFO L791 eck$LassoCheckResult]: Stem: 29033#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 29034#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 29574#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29575#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 29444#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 29445#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28452#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28453#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29891#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29418#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29419#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29696#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29697#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 29780#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29862#L837-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29863#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29744#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29592#L1121 assume !(0 == ~M_E~0); 29347#L1121-2 assume !(0 == ~T1_E~0); 28728#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28729#L1131-1 assume !(0 == ~T3_E~0); 28899#L1136-1 assume !(0 == ~T4_E~0); 28995#L1141-1 assume !(0 == ~T5_E~0); 29215#L1146-1 assume !(0 == ~T6_E~0); 29515#L1151-1 assume !(0 == ~T7_E~0); 29055#L1156-1 assume !(0 == ~T8_E~0); 28438#L1161-1 assume !(0 == ~T9_E~0); 28439#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28664#L1171-1 assume !(0 == ~T11_E~0); 28665#L1176-1 assume !(0 == ~E_M~0); 29529#L1181-1 assume !(0 == ~E_1~0); 29657#L1186-1 assume !(0 == ~E_2~0); 29707#L1191-1 assume !(0 == ~E_3~0); 28691#L1196-1 assume !(0 == ~E_4~0); 28692#L1201-1 assume !(0 == ~E_5~0); 29900#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 29745#L1211-1 assume !(0 == ~E_7~0); 29746#L1216-1 assume !(0 == ~E_8~0); 28834#L1221-1 assume !(0 == ~E_9~0); 28835#L1226-1 assume !(0 == ~E_10~0); 28534#L1231-1 assume !(0 == ~E_11~0); 28535#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29530#L556 assume 1 == ~m_pc~0; 29531#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 28412#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28413#L568 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29308#L1391 assume !(0 != activate_threads_~tmp~1#1); 29685#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29686#L575 assume !(1 == ~t1_pc~0); 28363#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28364#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28497#L587 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28847#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 28804#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28805#L594 assume 1 == ~t2_pc~0; 28733#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28734#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29200#L606 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28427#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 28428#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28486#L613 assume !(1 == ~t3_pc~0); 28605#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 28604#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28530#L625 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28531#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 29214#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28932#L632 assume 1 == ~t4_pc~0; 28933#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29433#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29593#L644 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29901#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 29539#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29290#L651 assume 1 == ~t5_pc~0; 29291#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28618#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28619#L663 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29067#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 28635#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28636#L670 assume !(1 == ~t6_pc~0); 29727#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 28981#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28982#L682 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29823#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29255#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29256#L689 assume 1 == ~t7_pc~0; 29897#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29366#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29367#L701 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29742#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 29158#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29159#L708 assume !(1 == ~t8_pc~0); 28724#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 28725#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29822#L720 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29807#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 28789#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28790#L727 assume 1 == ~t9_pc~0; 28912#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28488#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29904#L739 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29905#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 29892#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28843#L746 assume !(1 == ~t10_pc~0); 28844#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 29492#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29608#L758 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29816#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 29689#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29004#L765 assume 1 == ~t11_pc~0; 29005#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29210#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28377#L777 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 28378#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 29726#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29804#L1249 assume !(1 == ~M_E~0); 29437#L1249-2 assume !(1 == ~T1_E~0); 29087#L1254-1 assume !(1 == ~T2_E~0); 28423#L1259-1 assume !(1 == ~T3_E~0); 28405#L1264-1 assume !(1 == ~T4_E~0); 28406#L1269-1 assume !(1 == ~T5_E~0); 29923#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29871#L1279-1 assume !(1 == ~T7_E~0); 28606#L1284-1 assume !(1 == ~T8_E~0); 28607#L1289-1 assume !(1 == ~T9_E~0); 29137#L1294-1 assume !(1 == ~T10_E~0); 29138#L1299-1 assume !(1 == ~T11_E~0); 29147#L1304-1 assume !(1 == ~E_M~0); 29917#L1309-1 assume !(1 == ~E_1~0); 29920#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 28553#L1319-1 assume !(1 == ~E_3~0); 28554#L1324-1 assume !(1 == ~E_4~0); 28686#L1329-1 assume !(1 == ~E_5~0); 28687#L1334-1 assume !(1 == ~E_6~0); 29765#L1339-1 assume !(1 == ~E_7~0); 29842#L1344-1 assume !(1 == ~E_8~0); 29843#L1349-1 assume !(1 == ~E_9~0); 29270#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 29271#L1359-1 assume !(1 == ~E_11~0); 29630#L1364-1 assume { :end_inline_reset_delta_events } true; 28775#L1690-2 [2021-11-13 18:20:41,567 INFO L793 eck$LassoCheckResult]: Loop: 28775#L1690-2 assume !false; 28776#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28661#L1096 assume !false; 29639#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 28507#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28508#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29533#L923 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 29002#L937 assume !(0 != eval_~tmp~0#1); 29003#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29473#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28977#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28978#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29893#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29185#L1131-3 assume !(0 == ~T3_E~0); 29186#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29924#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29540#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28722#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28723#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29837#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 29348#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29349#L1171-3 assume !(0 == ~T11_E~0); 29394#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 28771#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28772#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29475#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29476#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29666#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29667#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29372#L1211-3 assume !(0 == ~E_7~0); 28684#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28685#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29098#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28741#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28742#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28962#L556-39 assume 1 == ~m_pc~0; 29483#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29450#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28841#L568-13 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28842#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 29014#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29408#L575-39 assume 1 == ~t1_pc~0; 29409#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29674#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29535#L587-13 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29536#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29383#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29384#L594-39 assume !(1 == ~t2_pc~0); 29595#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 29386#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29387#L606-13 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29809#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28900#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28901#L613-39 assume 1 == ~t3_pc~0; 29786#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28383#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 28384#L625-13 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29142#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 28482#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 28483#L632-39 assume 1 == ~t4_pc~0; 29754#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29068#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29069#L644-13 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29622#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29753#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 28752#L651-39 assume 1 == ~t5_pc~0; 28753#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28515#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29741#L663-13 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29848#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29886#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29906#L670-39 assume 1 == ~t6_pc~0; 29907#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 28429#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28430#L682-13 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28498#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29095#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29096#L689-39 assume !(1 == ~t7_pc~0); 29219#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 29220#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28754#L701-13 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 28755#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28622#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28623#L708-39 assume !(1 == ~t8_pc~0); 28561#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 28560#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28668#L720-13 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28669#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29549#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29041#L727-39 assume !(1 == ~t9_pc~0); 29042#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 28819#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28820#L739-13 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29769#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 29598#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29599#L746-39 assume 1 == ~t10_pc~0; 29568#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 29569#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29834#L758-13 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29304#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29305#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29717#L765-39 assume 1 == ~t11_pc~0; 28433#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 28435#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29617#L777-13 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 28773#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28774#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29341#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28579#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28580#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29836#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29464#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28538#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28539#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29869#L1279-3 assume !(1 == ~T7_E~0); 29017#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29018#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 29012#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 29013#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 29264#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29265#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28929#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28930#L1319-3 assume !(1 == ~E_3~0); 29683#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28648#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28649#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 29198#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 29199#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 29417#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28908#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 28909#L1359-3 assume !(1 == ~E_11~0); 29432#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 28499#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28500#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29126#L923-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 29127#L1709 assume !(0 == start_simulation_~tmp~3#1); 28937#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29703#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28613#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29115#L923-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 28576#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28577#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29395#L1672 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 29776#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 28775#L1690-2 [2021-11-13 18:20:41,568 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:41,569 INFO L85 PathProgramCache]: Analyzing trace with hash 215884284, now seen corresponding path program 1 times [2021-11-13 18:20:41,569 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:41,569 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1381463166] [2021-11-13 18:20:41,569 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:41,570 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:41,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:41,602 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:41,603 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:41,603 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1381463166] [2021-11-13 18:20:41,603 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1381463166] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:41,603 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:41,604 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:41,604 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1237521365] [2021-11-13 18:20:41,604 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:41,605 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:20:41,606 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:41,606 INFO L85 PathProgramCache]: Analyzing trace with hash 1244851136, now seen corresponding path program 1 times [2021-11-13 18:20:41,606 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:41,607 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [82043855] [2021-11-13 18:20:41,607 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:41,607 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:41,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:41,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:41,658 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:41,658 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [82043855] [2021-11-13 18:20:41,658 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [82043855] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:41,658 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:41,658 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:41,659 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1399079088] [2021-11-13 18:20:41,659 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:41,659 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:20:41,660 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:20:41,660 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:20:41,660 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:20:41,660 INFO L87 Difference]: Start difference. First operand 1571 states and 2326 transitions. cyclomatic complexity: 756 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:41,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:20:41,703 INFO L93 Difference]: Finished difference Result 1571 states and 2325 transitions. [2021-11-13 18:20:41,703 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:20:41,704 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2325 transitions. [2021-11-13 18:20:41,714 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:41,726 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2325 transitions. [2021-11-13 18:20:41,727 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-11-13 18:20:41,728 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-11-13 18:20:41,729 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2325 transitions. [2021-11-13 18:20:41,731 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:20:41,731 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2325 transitions. [2021-11-13 18:20:41,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2325 transitions. [2021-11-13 18:20:41,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-11-13 18:20:41,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4799490770210058) internal successors, (2325), 1570 states have internal predecessors, (2325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:41,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2325 transitions. [2021-11-13 18:20:41,767 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2325 transitions. [2021-11-13 18:20:41,767 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2325 transitions. [2021-11-13 18:20:41,768 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-13 18:20:41,768 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2325 transitions. [2021-11-13 18:20:41,775 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:41,776 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:20:41,776 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:20:41,778 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:41,778 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:41,779 INFO L791 eck$LassoCheckResult]: Stem: 32182#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 32183#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 32723#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32724#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32593#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 32594#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 31601#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 31602#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33040#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32567#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 32568#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32845#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32846#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 32929#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33011#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 33012#L842-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 32893#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32741#L1121 assume !(0 == ~M_E~0); 32496#L1121-2 assume !(0 == ~T1_E~0); 31877#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31878#L1131-1 assume !(0 == ~T3_E~0); 32048#L1136-1 assume !(0 == ~T4_E~0); 32144#L1141-1 assume !(0 == ~T5_E~0); 32364#L1146-1 assume !(0 == ~T6_E~0); 32664#L1151-1 assume !(0 == ~T7_E~0); 32204#L1156-1 assume !(0 == ~T8_E~0); 31587#L1161-1 assume !(0 == ~T9_E~0); 31588#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31813#L1171-1 assume !(0 == ~T11_E~0); 31814#L1176-1 assume !(0 == ~E_M~0); 32678#L1181-1 assume !(0 == ~E_1~0); 32806#L1186-1 assume !(0 == ~E_2~0); 32856#L1191-1 assume !(0 == ~E_3~0); 31840#L1196-1 assume !(0 == ~E_4~0); 31841#L1201-1 assume !(0 == ~E_5~0); 33049#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 32894#L1211-1 assume !(0 == ~E_7~0); 32895#L1216-1 assume !(0 == ~E_8~0); 31983#L1221-1 assume !(0 == ~E_9~0); 31984#L1226-1 assume !(0 == ~E_10~0); 31683#L1231-1 assume !(0 == ~E_11~0); 31684#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32679#L556 assume 1 == ~m_pc~0; 32680#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 31561#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31562#L568 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32457#L1391 assume !(0 != activate_threads_~tmp~1#1); 32834#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32835#L575 assume !(1 == ~t1_pc~0); 31512#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31513#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31646#L587 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 31996#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 31953#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31954#L594 assume 1 == ~t2_pc~0; 31882#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31883#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32349#L606 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 31576#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 31577#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31635#L613 assume !(1 == ~t3_pc~0); 31754#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 31753#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31679#L625 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 31680#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 32363#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32081#L632 assume 1 == ~t4_pc~0; 32082#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32582#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32742#L644 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33050#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 32688#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32439#L651 assume 1 == ~t5_pc~0; 32440#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31767#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31768#L663 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32216#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 31784#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 31785#L670 assume !(1 == ~t6_pc~0); 32876#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 32130#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32131#L682 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32972#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32404#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32405#L689 assume 1 == ~t7_pc~0; 33046#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 32515#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32516#L701 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32891#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 32307#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32308#L708 assume !(1 == ~t8_pc~0); 31873#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 31874#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32971#L720 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32956#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 31938#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 31939#L727 assume 1 == ~t9_pc~0; 32061#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31637#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 33053#L739 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33054#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 33041#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 31992#L746 assume !(1 == ~t10_pc~0); 31993#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32641#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32757#L758 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32965#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 32838#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32153#L765 assume 1 == ~t11_pc~0; 32154#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32359#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 31526#L777 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 31527#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 32875#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32953#L1249 assume !(1 == ~M_E~0); 32586#L1249-2 assume !(1 == ~T1_E~0); 32236#L1254-1 assume !(1 == ~T2_E~0); 31572#L1259-1 assume !(1 == ~T3_E~0); 31554#L1264-1 assume !(1 == ~T4_E~0); 31555#L1269-1 assume !(1 == ~T5_E~0); 33072#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33020#L1279-1 assume !(1 == ~T7_E~0); 31755#L1284-1 assume !(1 == ~T8_E~0); 31756#L1289-1 assume !(1 == ~T9_E~0); 32286#L1294-1 assume !(1 == ~T10_E~0); 32287#L1299-1 assume !(1 == ~T11_E~0); 32296#L1304-1 assume !(1 == ~E_M~0); 33066#L1309-1 assume !(1 == ~E_1~0); 33069#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 31702#L1319-1 assume !(1 == ~E_3~0); 31703#L1324-1 assume !(1 == ~E_4~0); 31835#L1329-1 assume !(1 == ~E_5~0); 31836#L1334-1 assume !(1 == ~E_6~0); 32914#L1339-1 assume !(1 == ~E_7~0); 32991#L1344-1 assume !(1 == ~E_8~0); 32992#L1349-1 assume !(1 == ~E_9~0); 32419#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 32420#L1359-1 assume !(1 == ~E_11~0); 32779#L1364-1 assume { :end_inline_reset_delta_events } true; 31924#L1690-2 [2021-11-13 18:20:41,779 INFO L793 eck$LassoCheckResult]: Loop: 31924#L1690-2 assume !false; 31925#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31810#L1096 assume !false; 32788#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 31656#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31657#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32682#L923 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 32151#L937 assume !(0 != eval_~tmp~0#1); 32152#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32622#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 32126#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32127#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33042#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32334#L1131-3 assume !(0 == ~T3_E~0); 32335#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33073#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32689#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 31871#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 31872#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32986#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 32497#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32498#L1171-3 assume !(0 == ~T11_E~0); 32543#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 31920#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31921#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32624#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32625#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32815#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32816#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 32521#L1211-3 assume !(0 == ~E_7~0); 31833#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 31834#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 32247#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31890#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 31891#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32111#L556-39 assume 1 == ~m_pc~0; 32632#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32599#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31990#L568-13 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 31991#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 32163#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32557#L575-39 assume 1 == ~t1_pc~0; 32558#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 32823#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32684#L587-13 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32685#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32532#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32533#L594-39 assume !(1 == ~t2_pc~0); 32744#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 32535#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32536#L606-13 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32958#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32049#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32050#L613-39 assume 1 == ~t3_pc~0; 32935#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31532#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 31533#L625-13 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32291#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 31631#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 31632#L632-39 assume 1 == ~t4_pc~0; 32903#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 32217#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32218#L644-13 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32771#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32902#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 31901#L651-39 assume 1 == ~t5_pc~0; 31902#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31664#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32890#L663-13 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32997#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33035#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33055#L670-39 assume 1 == ~t6_pc~0; 33056#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 31578#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31579#L682-13 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31647#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32244#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32245#L689-39 assume !(1 == ~t7_pc~0); 32368#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 32369#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31903#L701-13 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 31904#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 31771#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 31772#L708-39 assume 1 == ~t8_pc~0; 31708#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 31709#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 31817#L720-13 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 31818#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32698#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32190#L727-39 assume 1 == ~t9_pc~0; 32192#L728-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31968#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 31969#L739-13 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32918#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 32747#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32748#L746-39 assume 1 == ~t10_pc~0; 32717#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 32718#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32983#L758-13 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32453#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 32454#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32866#L765-39 assume 1 == ~t11_pc~0; 31582#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 31584#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32766#L777-13 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 31922#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 31923#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32490#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 31728#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 31729#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32985#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32613#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31687#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31688#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33018#L1279-3 assume !(1 == ~T7_E~0); 32166#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32167#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 32161#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 32162#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32413#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 32414#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32078#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32079#L1319-3 assume !(1 == ~E_3~0); 32832#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31797#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31798#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32347#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32348#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32566#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 32057#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32058#L1359-3 assume !(1 == ~E_11~0); 32581#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 31648#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31649#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32275#L923-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 32276#L1709 assume !(0 == start_simulation_~tmp~3#1); 32086#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32852#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31762#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32264#L923-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 31725#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31726#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 32544#L1672 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 32925#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 31924#L1690-2 [2021-11-13 18:20:41,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:41,780 INFO L85 PathProgramCache]: Analyzing trace with hash 922480890, now seen corresponding path program 1 times [2021-11-13 18:20:41,781 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:41,781 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1332000991] [2021-11-13 18:20:41,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:41,781 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:41,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:41,824 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:41,825 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:41,825 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1332000991] [2021-11-13 18:20:41,825 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1332000991] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:41,825 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:41,825 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:41,826 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1388187920] [2021-11-13 18:20:41,826 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:41,826 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:20:41,827 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:41,827 INFO L85 PathProgramCache]: Analyzing trace with hash 1324447614, now seen corresponding path program 1 times [2021-11-13 18:20:41,827 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:41,827 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1027639216] [2021-11-13 18:20:41,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:41,828 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:41,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:41,872 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:41,873 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:41,873 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1027639216] [2021-11-13 18:20:41,873 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1027639216] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:41,873 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:41,873 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:41,873 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1047640482] [2021-11-13 18:20:41,874 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:41,874 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:20:41,874 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:20:41,875 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:20:41,875 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:20:41,875 INFO L87 Difference]: Start difference. First operand 1571 states and 2325 transitions. cyclomatic complexity: 755 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:41,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:20:41,910 INFO L93 Difference]: Finished difference Result 1571 states and 2324 transitions. [2021-11-13 18:20:41,910 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:20:41,911 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2324 transitions. [2021-11-13 18:20:41,921 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:41,933 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2324 transitions. [2021-11-13 18:20:41,933 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-11-13 18:20:41,935 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-11-13 18:20:41,935 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2324 transitions. [2021-11-13 18:20:41,938 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:20:41,938 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2324 transitions. [2021-11-13 18:20:41,941 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2324 transitions. [2021-11-13 18:20:41,973 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-11-13 18:20:41,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4793125397835774) internal successors, (2324), 1570 states have internal predecessors, (2324), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:41,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2324 transitions. [2021-11-13 18:20:41,983 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2324 transitions. [2021-11-13 18:20:41,983 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2324 transitions. [2021-11-13 18:20:41,983 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-13 18:20:41,983 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2324 transitions. [2021-11-13 18:20:41,991 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:41,991 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:20:41,991 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:20:41,994 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:41,994 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:41,994 INFO L791 eck$LassoCheckResult]: Stem: 35331#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 35332#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 35872#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35873#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35742#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 35743#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 34750#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34751#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 36189#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35716#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35717#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35994#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35995#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 36078#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 36160#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 36161#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 36042#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35890#L1121 assume !(0 == ~M_E~0); 35645#L1121-2 assume !(0 == ~T1_E~0); 35026#L1126-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35027#L1131-1 assume !(0 == ~T3_E~0); 35197#L1136-1 assume !(0 == ~T4_E~0); 35293#L1141-1 assume !(0 == ~T5_E~0); 35513#L1146-1 assume !(0 == ~T6_E~0); 35813#L1151-1 assume !(0 == ~T7_E~0); 35353#L1156-1 assume !(0 == ~T8_E~0); 34736#L1161-1 assume !(0 == ~T9_E~0); 34737#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34962#L1171-1 assume !(0 == ~T11_E~0); 34963#L1176-1 assume !(0 == ~E_M~0); 35827#L1181-1 assume !(0 == ~E_1~0); 35955#L1186-1 assume !(0 == ~E_2~0); 36005#L1191-1 assume !(0 == ~E_3~0); 34989#L1196-1 assume !(0 == ~E_4~0); 34990#L1201-1 assume !(0 == ~E_5~0); 36198#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 36043#L1211-1 assume !(0 == ~E_7~0); 36044#L1216-1 assume !(0 == ~E_8~0); 35132#L1221-1 assume !(0 == ~E_9~0); 35133#L1226-1 assume !(0 == ~E_10~0); 34832#L1231-1 assume !(0 == ~E_11~0); 34833#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35828#L556 assume 1 == ~m_pc~0; 35829#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 34710#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34711#L568 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35606#L1391 assume !(0 != activate_threads_~tmp~1#1); 35983#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35984#L575 assume !(1 == ~t1_pc~0); 34661#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34662#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34795#L587 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35145#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 35102#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35103#L594 assume 1 == ~t2_pc~0; 35031#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35032#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35498#L606 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34725#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 34726#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34784#L613 assume !(1 == ~t3_pc~0); 34903#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34902#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34828#L625 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34829#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 35512#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35230#L632 assume 1 == ~t4_pc~0; 35231#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35731#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35891#L644 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36199#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 35837#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35588#L651 assume 1 == ~t5_pc~0; 35589#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34916#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34917#L663 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 35365#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 34933#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34934#L670 assume !(1 == ~t6_pc~0); 36025#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 35279#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35280#L682 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 36121#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35553#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35554#L689 assume 1 == ~t7_pc~0; 36195#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35664#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35665#L701 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36040#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 35456#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35457#L708 assume !(1 == ~t8_pc~0); 35022#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35023#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36120#L720 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36105#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 35087#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35088#L727 assume 1 == ~t9_pc~0; 35210#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34786#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36202#L739 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36203#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 36190#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35141#L746 assume !(1 == ~t10_pc~0); 35142#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35790#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35906#L758 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36114#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 35987#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35302#L765 assume 1 == ~t11_pc~0; 35303#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 35508#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34675#L777 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34676#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 36024#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36102#L1249 assume !(1 == ~M_E~0); 35735#L1249-2 assume !(1 == ~T1_E~0); 35385#L1254-1 assume !(1 == ~T2_E~0); 34721#L1259-1 assume !(1 == ~T3_E~0); 34703#L1264-1 assume !(1 == ~T4_E~0); 34704#L1269-1 assume !(1 == ~T5_E~0); 36221#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36169#L1279-1 assume !(1 == ~T7_E~0); 34904#L1284-1 assume !(1 == ~T8_E~0); 34905#L1289-1 assume !(1 == ~T9_E~0); 35435#L1294-1 assume !(1 == ~T10_E~0); 35436#L1299-1 assume !(1 == ~T11_E~0); 35445#L1304-1 assume !(1 == ~E_M~0); 36215#L1309-1 assume !(1 == ~E_1~0); 36218#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 34851#L1319-1 assume !(1 == ~E_3~0); 34852#L1324-1 assume !(1 == ~E_4~0); 34984#L1329-1 assume !(1 == ~E_5~0); 34985#L1334-1 assume !(1 == ~E_6~0); 36063#L1339-1 assume !(1 == ~E_7~0); 36140#L1344-1 assume !(1 == ~E_8~0); 36141#L1349-1 assume !(1 == ~E_9~0); 35568#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 35569#L1359-1 assume !(1 == ~E_11~0); 35928#L1364-1 assume { :end_inline_reset_delta_events } true; 35073#L1690-2 [2021-11-13 18:20:41,995 INFO L793 eck$LassoCheckResult]: Loop: 35073#L1690-2 assume !false; 35074#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 34959#L1096 assume !false; 35937#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 34805#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34806#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35831#L923 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 35300#L937 assume !(0 != eval_~tmp~0#1); 35301#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35771#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35275#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 35276#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 36191#L1126-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35483#L1131-3 assume !(0 == ~T3_E~0); 35484#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36222#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35838#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35020#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35021#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36135#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35646#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 35647#L1171-3 assume !(0 == ~T11_E~0); 35692#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35069#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35070#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35773#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35774#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35964#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35965#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 35670#L1211-3 assume !(0 == ~E_7~0); 34982#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 34983#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 35396#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 35039#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35040#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35260#L556-39 assume 1 == ~m_pc~0; 35781#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35748#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35139#L568-13 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35140#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 35312#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35706#L575-39 assume 1 == ~t1_pc~0; 35707#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35972#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35833#L587-13 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35834#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 35681#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35682#L594-39 assume !(1 == ~t2_pc~0); 35893#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 35684#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35685#L606-13 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36107#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 35198#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35199#L613-39 assume 1 == ~t3_pc~0; 36084#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34681#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34682#L625-13 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35440#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34780#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34781#L632-39 assume 1 == ~t4_pc~0; 36052#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 35366#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35367#L644-13 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35920#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36051#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35050#L651-39 assume 1 == ~t5_pc~0; 35051#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34813#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36039#L663-13 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36146#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 36184#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36204#L670-39 assume !(1 == ~t6_pc~0); 35783#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 34727#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34728#L682-13 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34796#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35393#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35394#L689-39 assume 1 == ~t7_pc~0; 35616#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 35518#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35052#L701-13 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35053#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 34920#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34921#L708-39 assume 1 == ~t8_pc~0; 34857#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34858#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34966#L720-13 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34967#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35847#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35339#L727-39 assume !(1 == ~t9_pc~0); 35340#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 35117#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35118#L739-13 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 36067#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 35896#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35897#L746-39 assume 1 == ~t10_pc~0; 35866#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35867#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 36132#L758-13 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 35602#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35603#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 36015#L765-39 assume 1 == ~t11_pc~0; 34731#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 34733#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35915#L777-13 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 35071#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35072#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35639#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 34877#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34878#L1254-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36134#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35762#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 34836#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 34837#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36167#L1279-3 assume !(1 == ~T7_E~0); 35315#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 35316#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35310#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 35311#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 35562#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 35563#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35227#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35228#L1319-3 assume !(1 == ~E_3~0); 35981#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 34946#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 34947#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35496#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35497#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35715#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 35206#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35207#L1359-3 assume !(1 == ~E_11~0); 35730#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 34797#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34798#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35424#L923-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 35425#L1709 assume !(0 == start_simulation_~tmp~3#1); 35235#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 36001#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34911#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35413#L923-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 34874#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34875#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35693#L1672 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 36074#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 35073#L1690-2 [2021-11-13 18:20:41,996 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:41,996 INFO L85 PathProgramCache]: Analyzing trace with hash -24556996, now seen corresponding path program 1 times [2021-11-13 18:20:41,996 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:41,996 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [164536124] [2021-11-13 18:20:41,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:41,997 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:42,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:42,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:42,039 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:42,039 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [164536124] [2021-11-13 18:20:42,039 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [164536124] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:42,041 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:42,041 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:20:42,043 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1826774981] [2021-11-13 18:20:42,043 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:42,067 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:20:42,068 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:42,068 INFO L85 PathProgramCache]: Analyzing trace with hash 210812735, now seen corresponding path program 2 times [2021-11-13 18:20:42,068 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:42,069 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1922402758] [2021-11-13 18:20:42,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:42,069 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:42,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:42,116 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:42,116 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:42,117 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1922402758] [2021-11-13 18:20:42,117 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1922402758] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:42,117 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:42,117 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:42,117 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [771680768] [2021-11-13 18:20:42,118 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:42,118 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:20:42,118 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:20:42,119 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:20:42,119 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:20:42,119 INFO L87 Difference]: Start difference. First operand 1571 states and 2324 transitions. cyclomatic complexity: 754 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:42,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:20:42,164 INFO L93 Difference]: Finished difference Result 1571 states and 2319 transitions. [2021-11-13 18:20:42,165 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:20:42,166 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2319 transitions. [2021-11-13 18:20:42,177 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:42,198 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2319 transitions. [2021-11-13 18:20:42,198 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-11-13 18:20:42,200 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-11-13 18:20:42,201 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2319 transitions. [2021-11-13 18:20:42,203 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:20:42,204 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2319 transitions. [2021-11-13 18:20:42,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2319 transitions. [2021-11-13 18:20:42,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-11-13 18:20:42,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4761298535964353) internal successors, (2319), 1570 states have internal predecessors, (2319), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:42,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2319 transitions. [2021-11-13 18:20:42,245 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2319 transitions. [2021-11-13 18:20:42,245 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2319 transitions. [2021-11-13 18:20:42,245 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-13 18:20:42,245 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2319 transitions. [2021-11-13 18:20:42,253 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:42,253 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:20:42,253 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:20:42,256 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:42,256 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:42,257 INFO L791 eck$LassoCheckResult]: Stem: 38484#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 38485#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 39021#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39022#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38891#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 38892#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37899#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37900#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39338#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38865#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38866#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39143#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 39144#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 39227#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 39309#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 39310#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 39191#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39039#L1121 assume !(0 == ~M_E~0); 38794#L1121-2 assume !(0 == ~T1_E~0); 38176#L1126-1 assume !(0 == ~T2_E~0); 38177#L1131-1 assume !(0 == ~T3_E~0); 38346#L1136-1 assume !(0 == ~T4_E~0); 38442#L1141-1 assume !(0 == ~T5_E~0); 38667#L1146-1 assume !(0 == ~T6_E~0); 38962#L1151-1 assume !(0 == ~T7_E~0); 38502#L1156-1 assume !(0 == ~T8_E~0); 37885#L1161-1 assume !(0 == ~T9_E~0); 37886#L1166-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 38111#L1171-1 assume !(0 == ~T11_E~0); 38112#L1176-1 assume !(0 == ~E_M~0); 38976#L1181-1 assume !(0 == ~E_1~0); 39104#L1186-1 assume !(0 == ~E_2~0); 39154#L1191-1 assume !(0 == ~E_3~0); 38138#L1196-1 assume !(0 == ~E_4~0); 38139#L1201-1 assume !(0 == ~E_5~0); 39347#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 39192#L1211-1 assume !(0 == ~E_7~0); 39193#L1216-1 assume !(0 == ~E_8~0); 38281#L1221-1 assume !(0 == ~E_9~0); 38282#L1226-1 assume !(0 == ~E_10~0); 37981#L1231-1 assume !(0 == ~E_11~0); 37982#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38977#L556 assume 1 == ~m_pc~0; 38978#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37859#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37860#L568 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38756#L1391 assume !(0 != activate_threads_~tmp~1#1); 39132#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39133#L575 assume !(1 == ~t1_pc~0); 37810#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 37811#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37944#L587 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38294#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 38251#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38252#L594 assume 1 == ~t2_pc~0; 38180#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38181#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38647#L606 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 37876#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 37877#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37933#L613 assume !(1 == ~t3_pc~0); 38052#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 38051#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37977#L625 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37978#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 38661#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38379#L632 assume 1 == ~t4_pc~0; 38380#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38880#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39040#L644 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39348#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 38986#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38737#L651 assume 1 == ~t5_pc~0; 38738#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38065#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38066#L663 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 38514#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 38082#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38083#L670 assume !(1 == ~t6_pc~0); 39175#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 38433#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38434#L682 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39271#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38702#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38703#L689 assume 1 == ~t7_pc~0; 39344#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 38813#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38814#L701 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39189#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 38605#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38606#L708 assume !(1 == ~t8_pc~0); 38171#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 38172#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39269#L720 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39254#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 38236#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38237#L727 assume 1 == ~t9_pc~0; 38359#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37935#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 39351#L739 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39352#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 39339#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38291#L746 assume !(1 == ~t10_pc~0); 38292#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 38939#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39055#L758 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 39263#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 39136#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38451#L765 assume 1 == ~t11_pc~0; 38452#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38657#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37824#L777 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 37825#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 39173#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39251#L1249 assume !(1 == ~M_E~0); 38885#L1249-2 assume !(1 == ~T1_E~0); 38534#L1254-1 assume !(1 == ~T2_E~0); 37870#L1259-1 assume !(1 == ~T3_E~0); 37852#L1264-1 assume !(1 == ~T4_E~0); 37853#L1269-1 assume !(1 == ~T5_E~0); 39370#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 39318#L1279-1 assume !(1 == ~T7_E~0); 38053#L1284-1 assume !(1 == ~T8_E~0); 38054#L1289-1 assume !(1 == ~T9_E~0); 38584#L1294-1 assume !(1 == ~T10_E~0); 38585#L1299-1 assume !(1 == ~T11_E~0); 38594#L1304-1 assume !(1 == ~E_M~0); 39364#L1309-1 assume !(1 == ~E_1~0); 39367#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 38000#L1319-1 assume !(1 == ~E_3~0); 38001#L1324-1 assume !(1 == ~E_4~0); 38133#L1329-1 assume !(1 == ~E_5~0); 38134#L1334-1 assume !(1 == ~E_6~0); 39212#L1339-1 assume !(1 == ~E_7~0); 39289#L1344-1 assume !(1 == ~E_8~0); 39290#L1349-1 assume !(1 == ~E_9~0); 38717#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 38718#L1359-1 assume !(1 == ~E_11~0); 39077#L1364-1 assume { :end_inline_reset_delta_events } true; 38222#L1690-2 [2021-11-13 18:20:42,258 INFO L793 eck$LassoCheckResult]: Loop: 38222#L1690-2 assume !false; 38223#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38108#L1096 assume !false; 39086#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 37954#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 37955#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 38980#L923 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 38449#L937 assume !(0 != eval_~tmp~0#1); 38450#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38920#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38426#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38427#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 39340#L1126-3 assume !(0 == ~T2_E~0); 38632#L1131-3 assume !(0 == ~T3_E~0); 38633#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 39371#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 38987#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 38169#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 38170#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 39284#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38795#L1166-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 38796#L1171-3 assume !(0 == ~T11_E~0); 38842#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 38218#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38219#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38922#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38923#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 39113#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 39114#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38819#L1211-3 assume !(0 == ~E_7~0); 38131#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38132#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 38545#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 38188#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38189#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38409#L556-39 assume 1 == ~m_pc~0; 38930#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 38899#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38288#L568-13 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38289#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 38461#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38854#L575-39 assume 1 == ~t1_pc~0; 38855#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 39121#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38982#L587-13 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38983#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 38830#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38831#L594-39 assume !(1 == ~t2_pc~0); 39042#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 38833#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38834#L606-13 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39256#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38347#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38348#L613-39 assume 1 == ~t3_pc~0; 39233#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37830#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37831#L625-13 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38589#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37929#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37930#L632-39 assume 1 == ~t4_pc~0; 39201#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38515#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38516#L644-13 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 39069#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 39200#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38198#L651-39 assume 1 == ~t5_pc~0; 38199#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 37962#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39188#L663-13 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39295#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 39333#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39353#L670-39 assume !(1 == ~t6_pc~0); 38932#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 37874#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37875#L682-13 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37945#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38542#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38543#L689-39 assume !(1 == ~t7_pc~0); 38665#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 38666#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38201#L701-13 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38202#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38069#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38070#L708-39 assume 1 == ~t8_pc~0; 38006#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38007#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38113#L720-13 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38114#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 38996#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38488#L727-39 assume !(1 == ~t9_pc~0); 38489#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 38266#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38267#L739-13 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 39216#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 39045#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 39046#L746-39 assume 1 == ~t10_pc~0; 39015#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 39016#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 39281#L758-13 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38751#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38752#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39164#L765-39 assume 1 == ~t11_pc~0; 37880#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37882#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39064#L777-13 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38220#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38221#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38788#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 38026#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38027#L1254-3 assume !(1 == ~T2_E~0); 39283#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38911#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37985#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 37986#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 39316#L1279-3 assume !(1 == ~T7_E~0); 38464#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38465#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38457#L1294-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38458#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 38711#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 38712#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38372#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38373#L1319-3 assume !(1 == ~E_3~0); 39130#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 38089#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38090#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38645#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 38646#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 38864#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 38355#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 38356#L1359-3 assume !(1 == ~E_11~0); 38878#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 37946#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 37947#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 38573#L923-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 38574#L1709 assume !(0 == start_simulation_~tmp~3#1); 38384#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 39150#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 38060#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 38562#L923-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 38023#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38024#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38841#L1672 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 39223#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 38222#L1690-2 [2021-11-13 18:20:42,258 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:42,259 INFO L85 PathProgramCache]: Analyzing trace with hash -1117192198, now seen corresponding path program 1 times [2021-11-13 18:20:42,259 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:42,259 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1850030778] [2021-11-13 18:20:42,259 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:42,260 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:42,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:42,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:42,303 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:42,303 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1850030778] [2021-11-13 18:20:42,304 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1850030778] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:42,304 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:42,304 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:20:42,304 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [996456396] [2021-11-13 18:20:42,304 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:42,306 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:20:42,306 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:42,306 INFO L85 PathProgramCache]: Analyzing trace with hash 1793120896, now seen corresponding path program 1 times [2021-11-13 18:20:42,307 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:42,307 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [600361761] [2021-11-13 18:20:42,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:42,307 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:42,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:42,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:42,377 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:42,377 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [600361761] [2021-11-13 18:20:42,378 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [600361761] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:42,378 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:42,378 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:42,378 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1440023031] [2021-11-13 18:20:42,379 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:42,379 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:20:42,379 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:20:42,380 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:20:42,380 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:20:42,380 INFO L87 Difference]: Start difference. First operand 1571 states and 2319 transitions. cyclomatic complexity: 749 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:42,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:20:42,424 INFO L93 Difference]: Finished difference Result 1571 states and 2314 transitions. [2021-11-13 18:20:42,425 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:20:42,426 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2314 transitions. [2021-11-13 18:20:42,438 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:42,448 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1571 states and 2314 transitions. [2021-11-13 18:20:42,448 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1571 [2021-11-13 18:20:42,450 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1571 [2021-11-13 18:20:42,450 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1571 states and 2314 transitions. [2021-11-13 18:20:42,453 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:20:42,453 INFO L681 BuchiCegarLoop]: Abstraction has 1571 states and 2314 transitions. [2021-11-13 18:20:42,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1571 states and 2314 transitions. [2021-11-13 18:20:42,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1571 to 1571. [2021-11-13 18:20:42,496 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1571 states, 1571 states have (on average 1.4729471674092935) internal successors, (2314), 1570 states have internal predecessors, (2314), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:42,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1571 states to 1571 states and 2314 transitions. [2021-11-13 18:20:42,509 INFO L704 BuchiCegarLoop]: Abstraction has 1571 states and 2314 transitions. [2021-11-13 18:20:42,509 INFO L587 BuchiCegarLoop]: Abstraction has 1571 states and 2314 transitions. [2021-11-13 18:20:42,509 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-13 18:20:42,509 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1571 states and 2314 transitions. [2021-11-13 18:20:42,517 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1420 [2021-11-13 18:20:42,518 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:20:42,518 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:20:42,521 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:42,521 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:42,522 INFO L791 eck$LassoCheckResult]: Stem: 41629#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 41630#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 42170#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42171#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42040#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 42041#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41048#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41049#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42487#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42014#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42015#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 42292#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42293#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 42376#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 42458#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 42459#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 42340#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42188#L1121 assume !(0 == ~M_E~0); 41943#L1121-2 assume !(0 == ~T1_E~0); 41324#L1126-1 assume !(0 == ~T2_E~0); 41325#L1131-1 assume !(0 == ~T3_E~0); 41495#L1136-1 assume !(0 == ~T4_E~0); 41591#L1141-1 assume !(0 == ~T5_E~0); 41811#L1146-1 assume !(0 == ~T6_E~0); 42111#L1151-1 assume !(0 == ~T7_E~0); 41651#L1156-1 assume !(0 == ~T8_E~0); 41034#L1161-1 assume !(0 == ~T9_E~0); 41035#L1166-1 assume !(0 == ~T10_E~0); 41260#L1171-1 assume !(0 == ~T11_E~0); 41261#L1176-1 assume !(0 == ~E_M~0); 42125#L1181-1 assume !(0 == ~E_1~0); 42253#L1186-1 assume !(0 == ~E_2~0); 42303#L1191-1 assume !(0 == ~E_3~0); 41287#L1196-1 assume !(0 == ~E_4~0); 41288#L1201-1 assume !(0 == ~E_5~0); 42496#L1206-1 assume 0 == ~E_6~0;~E_6~0 := 1; 42341#L1211-1 assume !(0 == ~E_7~0); 42342#L1216-1 assume !(0 == ~E_8~0); 41430#L1221-1 assume !(0 == ~E_9~0); 41431#L1226-1 assume !(0 == ~E_10~0); 41130#L1231-1 assume !(0 == ~E_11~0); 41131#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42126#L556 assume 1 == ~m_pc~0; 42127#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 41008#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41009#L568 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41904#L1391 assume !(0 != activate_threads_~tmp~1#1); 42281#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42282#L575 assume !(1 == ~t1_pc~0); 40959#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40960#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41093#L587 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41443#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 41400#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41401#L594 assume 1 == ~t2_pc~0; 41329#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41330#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41796#L606 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41023#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 41024#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41082#L613 assume !(1 == ~t3_pc~0); 41201#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41200#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 41126#L625 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41127#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 41810#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41528#L632 assume 1 == ~t4_pc~0; 41529#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 42029#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42189#L644 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42497#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 42135#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41886#L651 assume 1 == ~t5_pc~0; 41887#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41214#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41215#L663 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41663#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 41231#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41232#L670 assume !(1 == ~t6_pc~0); 42323#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41577#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41578#L682 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42419#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41851#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41852#L689 assume 1 == ~t7_pc~0; 42493#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41962#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41963#L701 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 42338#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 41754#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41755#L708 assume !(1 == ~t8_pc~0); 41320#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 41321#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42418#L720 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42403#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 41385#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41386#L727 assume 1 == ~t9_pc~0; 41508#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41084#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42500#L739 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42501#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 42488#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41439#L746 assume !(1 == ~t10_pc~0); 41440#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 42088#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42204#L758 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42412#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 42285#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41600#L765 assume 1 == ~t11_pc~0; 41601#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41806#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 40973#L777 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 40974#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 42322#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42400#L1249 assume !(1 == ~M_E~0); 42033#L1249-2 assume !(1 == ~T1_E~0); 41683#L1254-1 assume !(1 == ~T2_E~0); 41019#L1259-1 assume !(1 == ~T3_E~0); 41001#L1264-1 assume !(1 == ~T4_E~0); 41002#L1269-1 assume !(1 == ~T5_E~0); 42519#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42467#L1279-1 assume !(1 == ~T7_E~0); 41202#L1284-1 assume !(1 == ~T8_E~0); 41203#L1289-1 assume !(1 == ~T9_E~0); 41733#L1294-1 assume !(1 == ~T10_E~0); 41734#L1299-1 assume !(1 == ~T11_E~0); 41743#L1304-1 assume !(1 == ~E_M~0); 42513#L1309-1 assume !(1 == ~E_1~0); 42516#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 41149#L1319-1 assume !(1 == ~E_3~0); 41150#L1324-1 assume !(1 == ~E_4~0); 41282#L1329-1 assume !(1 == ~E_5~0); 41283#L1334-1 assume !(1 == ~E_6~0); 42361#L1339-1 assume !(1 == ~E_7~0); 42438#L1344-1 assume !(1 == ~E_8~0); 42439#L1349-1 assume !(1 == ~E_9~0); 41866#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 41867#L1359-1 assume !(1 == ~E_11~0); 42226#L1364-1 assume { :end_inline_reset_delta_events } true; 41371#L1690-2 [2021-11-13 18:20:42,523 INFO L793 eck$LassoCheckResult]: Loop: 41371#L1690-2 assume !false; 41372#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41257#L1096 assume !false; 42235#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41103#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 41104#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 42129#L923 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 41598#L937 assume !(0 != eval_~tmp~0#1); 41599#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 42069#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41573#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41574#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 42489#L1126-3 assume !(0 == ~T2_E~0); 41781#L1131-3 assume !(0 == ~T3_E~0); 41782#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 42520#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 42136#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41318#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41319#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 42433#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41944#L1166-3 assume !(0 == ~T10_E~0); 41945#L1171-3 assume !(0 == ~T11_E~0); 41990#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41367#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41368#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 42071#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42072#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42262#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42263#L1206-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41968#L1211-3 assume !(0 == ~E_7~0); 41280#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41281#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 41694#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41337#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41338#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41558#L556-39 assume !(1 == ~m_pc~0); 42080#L556-41 is_master_triggered_~__retres1~0#1 := 0; 42046#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41437#L568-13 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41438#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 41610#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42004#L575-39 assume 1 == ~t1_pc~0; 42005#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 42270#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42131#L587-13 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42132#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41979#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41980#L594-39 assume 1 == ~t2_pc~0; 42192#L595-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41982#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41983#L606-13 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42405#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41496#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 41497#L613-39 assume 1 == ~t3_pc~0; 42382#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40979#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40980#L625-13 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41738#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 41078#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41079#L632-39 assume !(1 == ~t4_pc~0); 42227#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 41664#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41665#L644-13 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 42218#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42349#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41348#L651-39 assume 1 == ~t5_pc~0; 41349#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41111#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42337#L663-13 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42444#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42482#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42502#L670-39 assume !(1 == ~t6_pc~0); 42081#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 41025#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41026#L682-13 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41094#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41691#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41692#L689-39 assume !(1 == ~t7_pc~0); 41815#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 41816#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41350#L701-13 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41351#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41218#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41219#L708-39 assume 1 == ~t8_pc~0; 41155#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41156#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41264#L720-13 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41265#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 42145#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41637#L727-39 assume !(1 == ~t9_pc~0); 41638#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 41415#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41416#L739-13 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42365#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 42194#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42195#L746-39 assume 1 == ~t10_pc~0; 42164#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 42165#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42430#L758-13 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41900#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41901#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42313#L765-39 assume 1 == ~t11_pc~0; 41029#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41031#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42213#L777-13 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 41369#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41370#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41937#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 41175#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41176#L1254-3 assume !(1 == ~T2_E~0); 42432#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42060#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41134#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41135#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42465#L1279-3 assume !(1 == ~T7_E~0); 41613#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 41614#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41608#L1294-3 assume !(1 == ~T10_E~0); 41609#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41860#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41861#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41525#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 41526#L1319-3 assume !(1 == ~E_3~0); 42279#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41244#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41245#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 41794#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41795#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 42013#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 41504#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 41505#L1359-3 assume !(1 == ~E_11~0); 42028#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41095#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 41096#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 41722#L923-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 41723#L1709 assume !(0 == start_simulation_~tmp~3#1); 41533#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 42299#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 41209#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 41711#L923-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 41172#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41173#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41991#L1672 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 42372#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 41371#L1690-2 [2021-11-13 18:20:42,523 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:42,524 INFO L85 PathProgramCache]: Analyzing trace with hash -645835848, now seen corresponding path program 1 times [2021-11-13 18:20:42,524 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:42,524 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1485536061] [2021-11-13 18:20:42,524 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:42,525 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:42,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:42,572 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:42,572 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:42,572 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1485536061] [2021-11-13 18:20:42,573 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1485536061] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:42,573 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:42,573 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:42,573 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [705118570] [2021-11-13 18:20:42,573 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:42,574 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:20:42,574 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:42,575 INFO L85 PathProgramCache]: Analyzing trace with hash 48037377, now seen corresponding path program 1 times [2021-11-13 18:20:42,575 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:42,575 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [617157865] [2021-11-13 18:20:42,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:42,576 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:42,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:42,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:42,616 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:42,617 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [617157865] [2021-11-13 18:20:42,617 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [617157865] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:42,617 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:42,617 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:42,617 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [752032142] [2021-11-13 18:20:42,618 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:42,618 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:20:42,618 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:20:42,619 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:20:42,619 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:20:42,620 INFO L87 Difference]: Start difference. First operand 1571 states and 2314 transitions. cyclomatic complexity: 744 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:42,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:20:42,825 INFO L93 Difference]: Finished difference Result 2922 states and 4299 transitions. [2021-11-13 18:20:42,825 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:20:42,826 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2922 states and 4299 transitions. [2021-11-13 18:20:42,842 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2754 [2021-11-13 18:20:42,857 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2922 states to 2922 states and 4299 transitions. [2021-11-13 18:20:42,857 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2922 [2021-11-13 18:20:42,860 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2922 [2021-11-13 18:20:42,861 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2922 states and 4299 transitions. [2021-11-13 18:20:42,865 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:20:42,865 INFO L681 BuchiCegarLoop]: Abstraction has 2922 states and 4299 transitions. [2021-11-13 18:20:42,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2922 states and 4299 transitions. [2021-11-13 18:20:42,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2922 to 2921. [2021-11-13 18:20:42,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2921 states, 2921 states have (on average 1.4714138993495378) internal successors, (4298), 2920 states have internal predecessors, (4298), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:42,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2921 states to 2921 states and 4298 transitions. [2021-11-13 18:20:42,938 INFO L704 BuchiCegarLoop]: Abstraction has 2921 states and 4298 transitions. [2021-11-13 18:20:42,939 INFO L587 BuchiCegarLoop]: Abstraction has 2921 states and 4298 transitions. [2021-11-13 18:20:42,939 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-13 18:20:42,939 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2921 states and 4298 transitions. [2021-11-13 18:20:42,951 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2754 [2021-11-13 18:20:42,951 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:20:42,952 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:20:42,954 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:42,954 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:42,955 INFO L791 eck$LassoCheckResult]: Stem: 46139#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 46140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 46707#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46708#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46565#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 46566#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45551#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45552#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47078#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46534#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46535#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46844#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46845#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 46935#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 47035#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47036#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 46898#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46728#L1121 assume !(0 == ~M_E~0); 46460#L1121-2 assume !(0 == ~T1_E~0); 45828#L1126-1 assume !(0 == ~T2_E~0); 45829#L1131-1 assume !(0 == ~T3_E~0); 45999#L1136-1 assume !(0 == ~T4_E~0); 46098#L1141-1 assume !(0 == ~T5_E~0); 46322#L1146-1 assume !(0 == ~T6_E~0); 46643#L1151-1 assume !(0 == ~T7_E~0); 46161#L1156-1 assume !(0 == ~T8_E~0); 45537#L1161-1 assume !(0 == ~T9_E~0); 45538#L1166-1 assume !(0 == ~T10_E~0); 45764#L1171-1 assume !(0 == ~T11_E~0); 45765#L1176-1 assume !(0 == ~E_M~0); 46657#L1181-1 assume !(0 == ~E_1~0); 46802#L1186-1 assume !(0 == ~E_2~0); 46856#L1191-1 assume !(0 == ~E_3~0); 45791#L1196-1 assume !(0 == ~E_4~0); 45792#L1201-1 assume !(0 == ~E_5~0); 47089#L1206-1 assume !(0 == ~E_6~0); 46899#L1211-1 assume !(0 == ~E_7~0); 46900#L1216-1 assume !(0 == ~E_8~0); 45934#L1221-1 assume !(0 == ~E_9~0); 45935#L1226-1 assume !(0 == ~E_10~0); 45633#L1231-1 assume !(0 == ~E_11~0); 45634#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46658#L556 assume 1 == ~m_pc~0; 46659#L557 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 45511#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45512#L568 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46418#L1391 assume !(0 != activate_threads_~tmp~1#1); 46833#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46834#L575 assume !(1 == ~t1_pc~0); 45462#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 45463#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45596#L587 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 45947#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 45904#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45905#L594 assume 1 == ~t2_pc~0; 45833#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 45834#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46307#L606 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 45526#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 45527#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45585#L613 assume !(1 == ~t3_pc~0); 45704#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 45703#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 45629#L625 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45630#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 46321#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46034#L632 assume 1 == ~t4_pc~0; 46035#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46550#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46729#L644 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47090#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 46667#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46400#L651 assume 1 == ~t5_pc~0; 46401#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 45718#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45719#L663 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46173#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 45735#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45736#L670 assume !(1 == ~t6_pc~0); 46881#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 46084#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46085#L682 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46986#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46365#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46366#L689 assume 1 == ~t7_pc~0; 47085#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 46479#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46480#L701 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46896#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 46264#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46265#L708 assume !(1 == ~t8_pc~0); 45824#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 45825#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46984#L720 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46967#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 45889#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45890#L727 assume 1 == ~t9_pc~0; 46012#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45587#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47096#L739 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47097#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 47079#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45943#L746 assume !(1 == ~t10_pc~0); 45944#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 46618#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46746#L758 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46978#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 46837#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46108#L765 assume 1 == ~t11_pc~0; 46109#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46317#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45476#L777 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 45477#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 46880#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46964#L1249 assume !(1 == ~M_E~0); 46556#L1249-2 assume !(1 == ~T1_E~0); 46193#L1254-1 assume !(1 == ~T2_E~0); 45522#L1259-1 assume !(1 == ~T3_E~0); 45504#L1264-1 assume !(1 == ~T4_E~0); 45505#L1269-1 assume !(1 == ~T5_E~0); 47139#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 47051#L1279-1 assume !(1 == ~T7_E~0); 45705#L1284-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 45706#L1289-1 assume !(1 == ~T9_E~0); 46243#L1294-1 assume !(1 == ~T10_E~0); 46244#L1299-1 assume !(1 == ~T11_E~0); 46253#L1304-1 assume !(1 == ~E_M~0); 47124#L1309-1 assume !(1 == ~E_1~0); 47127#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 45652#L1319-1 assume !(1 == ~E_3~0); 45653#L1324-1 assume !(1 == ~E_4~0); 45786#L1329-1 assume !(1 == ~E_5~0); 45787#L1334-1 assume !(1 == ~E_6~0); 46920#L1339-1 assume !(1 == ~E_7~0); 47007#L1344-1 assume !(1 == ~E_8~0); 47008#L1349-1 assume !(1 == ~E_9~0); 46380#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 46381#L1359-1 assume !(1 == ~E_11~0); 46769#L1364-1 assume { :end_inline_reset_delta_events } true; 45875#L1690-2 [2021-11-13 18:20:42,955 INFO L793 eck$LassoCheckResult]: Loop: 45875#L1690-2 assume !false; 45876#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45761#L1096 assume !false; 46781#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 47134#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 47165#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 47164#L923 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 47163#L937 assume !(0 != eval_~tmp~0#1); 46596#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 46597#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47106#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47161#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47080#L1126-3 assume !(0 == ~T2_E~0); 47081#L1131-3 assume !(0 == ~T3_E~0); 47147#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47148#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47160#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 45822#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45823#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 47159#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 47451#L1166-3 assume !(0 == ~T10_E~0); 47450#L1171-3 assume !(0 == ~T11_E~0); 47449#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 47448#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47447#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47446#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47445#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47444#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47443#L1206-3 assume !(0 == ~E_6~0); 47442#L1211-3 assume !(0 == ~E_7~0); 47441#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 47440#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 47439#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 47438#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 47437#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47436#L556-39 assume 1 == ~m_pc~0; 47434#L557-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 47433#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47432#L568-13 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47431#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 47430#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47429#L575-39 assume 1 == ~t1_pc~0; 47427#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47426#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47425#L587-13 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47424#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47423#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47422#L594-39 assume 1 == ~t2_pc~0; 47420#L595-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 47419#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47418#L606-13 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47417#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47416#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47415#L613-39 assume 1 == ~t3_pc~0; 47413#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47412#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47411#L625-13 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47410#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47409#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47408#L632-39 assume !(1 == ~t4_pc~0); 47406#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 47405#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47404#L644-13 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47403#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47402#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47401#L651-39 assume 1 == ~t5_pc~0; 47399#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47398#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47397#L663-13 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47396#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 47395#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47394#L670-39 assume !(1 == ~t6_pc~0); 47392#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 47391#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47390#L682-13 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47389#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47388#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47387#L689-39 assume 1 == ~t7_pc~0; 47385#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47384#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47383#L701-13 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47382#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 47381#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47380#L708-39 assume !(1 == ~t8_pc~0); 47378#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 47377#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47376#L720-13 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47375#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47374#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47373#L727-39 assume 1 == ~t9_pc~0; 47371#L728-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47370#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47369#L739-13 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47368#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 47367#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47366#L746-39 assume 1 == ~t10_pc~0; 47364#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 47363#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47362#L758-13 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 47361#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47360#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47359#L765-39 assume !(1 == ~t11_pc~0); 47357#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 47356#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47355#L777-13 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 47354#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 47353#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47352#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 47351#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 47350#L1254-3 assume !(1 == ~T2_E~0); 47349#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47348#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47347#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47346#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 47345#L1279-3 assume !(1 == ~T7_E~0); 47344#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46122#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47343#L1294-3 assume !(1 == ~T10_E~0); 47342#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47341#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 47340#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47339#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 47338#L1319-3 assume !(1 == ~E_3~0); 47337#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47336#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47335#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47117#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47334#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 47333#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47332#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 46547#L1359-3 assume !(1 == ~E_11~0); 46548#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 47123#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 46492#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 46493#L923-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 46764#L1709 assume !(0 == start_simulation_~tmp~3#1); 46039#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 46851#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 45713#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 46221#L923-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 45675#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 45676#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46509#L1672 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 46931#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 45875#L1690-2 [2021-11-13 18:20:42,956 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:42,956 INFO L85 PathProgramCache]: Analyzing trace with hash -1963161228, now seen corresponding path program 1 times [2021-11-13 18:20:42,957 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:42,957 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1487701105] [2021-11-13 18:20:42,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:42,957 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:42,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:43,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:43,021 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:43,021 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1487701105] [2021-11-13 18:20:43,021 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1487701105] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:43,021 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:43,021 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:20:43,022 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [832630638] [2021-11-13 18:20:43,022 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:43,022 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:20:43,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:43,023 INFO L85 PathProgramCache]: Analyzing trace with hash -1717268674, now seen corresponding path program 1 times [2021-11-13 18:20:43,023 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:43,023 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1363347338] [2021-11-13 18:20:43,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:43,024 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:43,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:43,061 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:43,061 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:43,061 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1363347338] [2021-11-13 18:20:43,061 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1363347338] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:43,061 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:43,062 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:43,062 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2113805257] [2021-11-13 18:20:43,062 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:43,062 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:20:43,063 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:20:43,063 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:20:43,063 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:20:43,063 INFO L87 Difference]: Start difference. First operand 2921 states and 4298 transitions. cyclomatic complexity: 1379 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:43,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:20:43,184 INFO L93 Difference]: Finished difference Result 5631 states and 8223 transitions. [2021-11-13 18:20:43,185 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:20:43,185 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5631 states and 8223 transitions. [2021-11-13 18:20:43,215 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5463 [2021-11-13 18:20:43,242 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5631 states to 5631 states and 8223 transitions. [2021-11-13 18:20:43,242 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5631 [2021-11-13 18:20:43,248 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5631 [2021-11-13 18:20:43,248 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5631 states and 8223 transitions. [2021-11-13 18:20:43,256 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:20:43,256 INFO L681 BuchiCegarLoop]: Abstraction has 5631 states and 8223 transitions. [2021-11-13 18:20:43,263 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5631 states and 8223 transitions. [2021-11-13 18:20:43,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5631 to 5465. [2021-11-13 18:20:43,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5465 states, 5465 states have (on average 1.4618481244281794) internal successors, (7989), 5464 states have internal predecessors, (7989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:43,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5465 states to 5465 states and 7989 transitions. [2021-11-13 18:20:43,370 INFO L704 BuchiCegarLoop]: Abstraction has 5465 states and 7989 transitions. [2021-11-13 18:20:43,370 INFO L587 BuchiCegarLoop]: Abstraction has 5465 states and 7989 transitions. [2021-11-13 18:20:43,370 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-13 18:20:43,370 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5465 states and 7989 transitions. [2021-11-13 18:20:43,393 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5297 [2021-11-13 18:20:43,393 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:20:43,393 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:20:43,395 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:43,396 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:43,396 INFO L791 eck$LassoCheckResult]: Stem: 54695#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 54696#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 55286#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55287#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55128#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 55129#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 54109#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 54110#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55700#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55099#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 55100#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 55422#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55423#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 55540#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 55650#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 55651#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 55486#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55304#L1121 assume !(0 == ~M_E~0); 55018#L1121-2 assume !(0 == ~T1_E~0); 54384#L1126-1 assume !(0 == ~T2_E~0); 54385#L1131-1 assume !(0 == ~T3_E~0); 54556#L1136-1 assume !(0 == ~T4_E~0); 54653#L1141-1 assume !(0 == ~T5_E~0); 54882#L1146-1 assume !(0 == ~T6_E~0); 55220#L1151-1 assume !(0 == ~T7_E~0); 54713#L1156-1 assume !(0 == ~T8_E~0); 54095#L1161-1 assume !(0 == ~T9_E~0); 54096#L1166-1 assume !(0 == ~T10_E~0); 54319#L1171-1 assume !(0 == ~T11_E~0); 54320#L1176-1 assume !(0 == ~E_M~0); 55238#L1181-1 assume !(0 == ~E_1~0); 55382#L1186-1 assume !(0 == ~E_2~0); 55436#L1191-1 assume !(0 == ~E_3~0); 54346#L1196-1 assume !(0 == ~E_4~0); 54347#L1201-1 assume !(0 == ~E_5~0); 55714#L1206-1 assume !(0 == ~E_6~0); 55487#L1211-1 assume !(0 == ~E_7~0); 55488#L1216-1 assume !(0 == ~E_8~0); 54493#L1221-1 assume !(0 == ~E_9~0); 54494#L1226-1 assume !(0 == ~E_10~0); 54191#L1231-1 assume !(0 == ~E_11~0); 54192#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55242#L556 assume !(1 == ~m_pc~0); 55243#L556-2 is_master_triggered_~__retres1~0#1 := 0; 54069#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54070#L568 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54975#L1391 assume !(0 != activate_threads_~tmp~1#1); 55412#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55413#L575 assume !(1 == ~t1_pc~0); 54021#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 54022#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54154#L587 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54503#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 54460#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54461#L594 assume 1 == ~t2_pc~0; 54388#L595 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54389#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54862#L606 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54086#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 54087#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54143#L613 assume !(1 == ~t3_pc~0); 54262#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54261#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54187#L625 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54188#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 54876#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54589#L632 assume 1 == ~t4_pc~0; 54590#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 55114#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 55305#L644 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55715#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 55248#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54956#L651 assume 1 == ~t5_pc~0; 54957#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54275#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54276#L663 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54726#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 54291#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54292#L670 assume !(1 == ~t6_pc~0); 55464#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 54644#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54645#L682 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55600#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54923#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54924#L689 assume 1 == ~t7_pc~0; 55711#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 55037#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55038#L701 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 55484#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 54819#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54820#L708 assume !(1 == ~t8_pc~0); 54379#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 54380#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55598#L720 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 55581#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 54445#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54446#L727 assume 1 == ~t9_pc~0; 54569#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54145#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 55726#L739 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 55727#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 55705#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54500#L746 assume !(1 == ~t10_pc~0); 54501#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 55195#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 55323#L758 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 55590#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 55415#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54665#L765 assume 1 == ~t11_pc~0; 54666#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54872#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54034#L777 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54035#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 55462#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55578#L1249 assume !(1 == ~M_E~0); 55120#L1249-2 assume !(1 == ~T1_E~0); 54746#L1254-1 assume !(1 == ~T2_E~0); 54080#L1259-1 assume !(1 == ~T3_E~0); 54062#L1264-1 assume !(1 == ~T4_E~0); 54063#L1269-1 assume !(1 == ~T5_E~0); 55780#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 55668#L1279-1 assume !(1 == ~T7_E~0); 54263#L1284-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54264#L1289-1 assume !(1 == ~T9_E~0); 54798#L1294-1 assume !(1 == ~T10_E~0); 54799#L1299-1 assume !(1 == ~T11_E~0); 54808#L1304-1 assume !(1 == ~E_M~0); 55759#L1309-1 assume !(1 == ~E_1~0); 55764#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 54210#L1319-1 assume !(1 == ~E_3~0); 54211#L1324-1 assume !(1 == ~E_4~0); 54341#L1329-1 assume !(1 == ~E_5~0); 54342#L1334-1 assume !(1 == ~E_6~0); 55518#L1339-1 assume !(1 == ~E_7~0); 55625#L1344-1 assume !(1 == ~E_8~0); 55626#L1349-1 assume !(1 == ~E_9~0); 54936#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 54937#L1359-1 assume !(1 == ~E_11~0); 55348#L1364-1 assume { :end_inline_reset_delta_events } true; 54431#L1690-2 [2021-11-13 18:20:43,397 INFO L793 eck$LassoCheckResult]: Loop: 54431#L1690-2 assume !false; 54432#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 54316#L1096 assume !false; 55362#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 54164#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 54165#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 58034#L923 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 54660#L937 assume !(0 != eval_~tmp~0#1); 54661#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 55740#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 55741#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 58026#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 55706#L1126-3 assume !(0 == ~T2_E~0); 54847#L1131-3 assume !(0 == ~T3_E~0); 54848#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 55782#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55783#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 54377#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 54378#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 55742#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 55019#L1166-3 assume !(0 == ~T10_E~0); 55020#L1171-3 assume !(0 == ~T11_E~0); 55071#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 54427#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 54428#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 55168#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 55169#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 55392#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 55393#L1206-3 assume !(0 == ~E_6~0); 55044#L1211-3 assume !(0 == ~E_7~0); 54339#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 54340#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 54757#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 54396#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 54397#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54620#L556-39 assume !(1 == ~m_pc~0); 55574#L556-41 is_master_triggered_~__retres1~0#1 := 0; 55134#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54497#L568-13 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54498#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 54672#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 55697#L575-39 assume 1 == ~t1_pc~0; 55513#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 55400#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 55244#L587-13 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 55245#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 55057#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 55058#L594-39 assume 1 == ~t2_pc~0; 55424#L595-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 55061#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 55062#L606-13 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 55583#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54557#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54558#L613-39 assume !(1 == ~t3_pc~0); 55767#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 54040#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54041#L625-13 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54803#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54139#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54140#L632-39 assume !(1 == ~t4_pc~0); 55349#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 54727#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54728#L644-13 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 55339#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 55498#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54406#L651-39 assume 1 == ~t5_pc~0; 54407#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 59420#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59419#L663-13 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 59418#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 59417#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59416#L670-39 assume !(1 == ~t6_pc~0); 59414#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 59413#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59412#L682-13 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 59411#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 59410#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54984#L689-39 assume 1 == ~t7_pc~0; 54985#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 59409#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59408#L701-13 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59407#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 59406#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 55221#L708-39 assume 1 == ~t8_pc~0; 55222#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 59405#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59404#L720-13 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59403#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 59402#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54699#L727-39 assume !(1 == ~t9_pc~0); 54700#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 59401#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59400#L739-13 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59399#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 59398#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 59397#L746-39 assume !(1 == ~t10_pc~0); 55281#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 55280#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 55611#L758-13 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54970#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 54971#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 55453#L765-39 assume 1 == ~t11_pc~0; 54090#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54092#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 55333#L777-13 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54429#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 54430#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55012#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 54236#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54237#L1254-3 assume !(1 == ~T2_E~0); 55616#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 55154#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54195#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 54196#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 55663#L1279-3 assume !(1 == ~T7_E~0); 54675#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54676#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54670#L1294-3 assume !(1 == ~T10_E~0); 54671#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54930#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 54931#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 54586#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 54587#L1319-3 assume !(1 == ~E_3~0); 55409#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 54303#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 54304#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 54860#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 54861#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 55098#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 54565#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 54566#L1359-3 assume !(1 == ~E_11~0); 55113#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 54156#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 54157#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 55051#L923-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 55343#L1709 assume !(0 == start_simulation_~tmp~3#1); 54594#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 55431#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 54271#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 54774#L923-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 54233#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54234#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 55072#L1672 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 55533#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 54431#L1690-2 [2021-11-13 18:20:43,397 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:43,397 INFO L85 PathProgramCache]: Analyzing trace with hash 470394037, now seen corresponding path program 1 times [2021-11-13 18:20:43,398 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:43,398 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [195356458] [2021-11-13 18:20:43,398 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:43,398 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:43,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:43,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:43,436 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:43,436 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [195356458] [2021-11-13 18:20:43,436 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [195356458] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:43,437 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:43,437 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:43,437 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [32569369] [2021-11-13 18:20:43,437 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:43,438 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:20:43,438 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:43,438 INFO L85 PathProgramCache]: Analyzing trace with hash -2114744064, now seen corresponding path program 1 times [2021-11-13 18:20:43,438 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:43,439 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1250426943] [2021-11-13 18:20:43,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:43,439 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:43,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:43,478 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:43,479 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:43,479 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1250426943] [2021-11-13 18:20:43,479 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1250426943] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:43,479 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:43,479 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:43,479 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [398332813] [2021-11-13 18:20:43,480 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:43,480 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:20:43,480 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:20:43,481 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:20:43,481 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:20:43,481 INFO L87 Difference]: Start difference. First operand 5465 states and 7989 transitions. cyclomatic complexity: 2528 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:43,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:20:43,802 INFO L93 Difference]: Finished difference Result 13159 states and 19082 transitions. [2021-11-13 18:20:43,802 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:20:43,803 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13159 states and 19082 transitions. [2021-11-13 18:20:43,869 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 12810 [2021-11-13 18:20:43,996 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13159 states to 13159 states and 19082 transitions. [2021-11-13 18:20:43,997 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13159 [2021-11-13 18:20:44,010 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13159 [2021-11-13 18:20:44,010 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13159 states and 19082 transitions. [2021-11-13 18:20:44,022 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:20:44,022 INFO L681 BuchiCegarLoop]: Abstraction has 13159 states and 19082 transitions. [2021-11-13 18:20:44,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13159 states and 19082 transitions. [2021-11-13 18:20:44,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13159 to 10361. [2021-11-13 18:20:44,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10361 states, 10361 states have (on average 1.454975388476016) internal successors, (15075), 10360 states have internal predecessors, (15075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:44,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10361 states to 10361 states and 15075 transitions. [2021-11-13 18:20:44,283 INFO L704 BuchiCegarLoop]: Abstraction has 10361 states and 15075 transitions. [2021-11-13 18:20:44,283 INFO L587 BuchiCegarLoop]: Abstraction has 10361 states and 15075 transitions. [2021-11-13 18:20:44,284 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-13 18:20:44,284 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10361 states and 15075 transitions. [2021-11-13 18:20:44,317 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10192 [2021-11-13 18:20:44,317 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:20:44,317 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:20:44,320 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:44,321 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:44,321 INFO L791 eck$LassoCheckResult]: Stem: 73325#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 73326#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 73891#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 73892#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 73747#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 73748#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 72743#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 72744#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 74253#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 73720#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 73721#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 74026#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 74027#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 74120#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 74213#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 74214#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 74080#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 73909#L1121 assume !(0 == ~M_E~0); 73644#L1121-2 assume !(0 == ~T1_E~0); 73016#L1126-1 assume !(0 == ~T2_E~0); 73017#L1131-1 assume !(0 == ~T3_E~0); 73184#L1136-1 assume !(0 == ~T4_E~0); 73282#L1141-1 assume !(0 == ~T5_E~0); 73516#L1146-1 assume !(0 == ~T6_E~0); 73833#L1151-1 assume !(0 == ~T7_E~0); 73343#L1156-1 assume !(0 == ~T8_E~0); 72729#L1161-1 assume !(0 == ~T9_E~0); 72730#L1166-1 assume !(0 == ~T10_E~0); 72950#L1171-1 assume !(0 == ~T11_E~0); 72951#L1176-1 assume !(0 == ~E_M~0); 73846#L1181-1 assume !(0 == ~E_1~0); 73984#L1186-1 assume !(0 == ~E_2~0); 74043#L1191-1 assume !(0 == ~E_3~0); 72978#L1196-1 assume !(0 == ~E_4~0); 72979#L1201-1 assume !(0 == ~E_5~0); 74268#L1206-1 assume !(0 == ~E_6~0); 74081#L1211-1 assume !(0 == ~E_7~0); 74082#L1216-1 assume !(0 == ~E_8~0); 73122#L1221-1 assume !(0 == ~E_9~0); 73123#L1226-1 assume !(0 == ~E_10~0); 72825#L1231-1 assume !(0 == ~E_11~0); 72826#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 73849#L556 assume !(1 == ~m_pc~0); 73850#L556-2 is_master_triggered_~__retres1~0#1 := 0; 72703#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 72704#L568 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 73604#L1391 assume !(0 != activate_threads_~tmp~1#1); 74016#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 74017#L575 assume !(1 == ~t1_pc~0); 72655#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 72656#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 72788#L587 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 73132#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 73088#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73089#L594 assume !(1 == ~t2_pc~0); 73819#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 73923#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 73495#L606 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 72720#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 72721#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 72777#L613 assume !(1 == ~t3_pc~0); 72894#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 72893#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 72821#L625 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 72822#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 73510#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 73218#L632 assume 1 == ~t4_pc~0; 73219#L633 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 73736#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 73910#L644 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 74269#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 73856#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 73586#L651 assume 1 == ~t5_pc~0; 73587#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 72907#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 72908#L663 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 73355#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 72923#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 72924#L670 assume !(1 == ~t6_pc~0); 74064#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 73273#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 73274#L682 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 74171#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 73551#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 73552#L689 assume 1 == ~t7_pc~0; 74264#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 73664#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 73665#L701 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 74078#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 73451#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 73452#L708 assume !(1 == ~t8_pc~0); 73011#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 73012#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 74169#L720 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 74153#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 73073#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 73074#L727 assume 1 == ~t9_pc~0; 73198#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 72779#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 74277#L739 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 74278#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 74258#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 73129#L746 assume !(1 == ~t10_pc~0); 73130#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 73804#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 73928#L758 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 74163#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 74019#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 73294#L765 assume 1 == ~t11_pc~0; 73295#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 73506#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 72668#L777 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 72669#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 74062#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 74150#L1249 assume !(1 == ~M_E~0); 73741#L1249-2 assume !(1 == ~T1_E~0); 73376#L1254-1 assume !(1 == ~T2_E~0); 72714#L1259-1 assume !(1 == ~T3_E~0); 72696#L1264-1 assume !(1 == ~T4_E~0); 72697#L1269-1 assume !(1 == ~T5_E~0); 74316#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 74223#L1279-1 assume !(1 == ~T7_E~0); 72895#L1284-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 72896#L1289-1 assume !(1 == ~T9_E~0); 74279#L1294-1 assume !(1 == ~T10_E~0); 73439#L1299-1 assume !(1 == ~T11_E~0); 73440#L1304-1 assume !(1 == ~E_M~0); 74312#L1309-1 assume !(1 == ~E_1~0); 74313#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 72844#L1319-1 assume !(1 == ~E_3~0); 72845#L1324-1 assume !(1 == ~E_4~0); 72973#L1329-1 assume !(1 == ~E_5~0); 72974#L1334-1 assume !(1 == ~E_6~0); 74103#L1339-1 assume !(1 == ~E_7~0); 74289#L1344-1 assume !(1 == ~E_8~0); 74321#L1349-1 assume !(1 == ~E_9~0); 74322#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 73955#L1359-1 assume !(1 == ~E_11~0); 73956#L1364-1 assume { :end_inline_reset_delta_events } true; 81852#L1690-2 [2021-11-13 18:20:44,322 INFO L793 eck$LassoCheckResult]: Loop: 81852#L1690-2 assume !false; 81839#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 81835#L1096 assume !false; 81833#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 81820#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 81816#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 81814#L923 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 81811#L937 assume !(0 != eval_~tmp~0#1); 81812#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 82531#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 82528#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 82526#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 82524#L1126-3 assume !(0 == ~T2_E~0); 82522#L1131-3 assume !(0 == ~T3_E~0); 82520#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 82518#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 82515#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 82513#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 82511#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 82509#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 82507#L1166-3 assume !(0 == ~T10_E~0); 82505#L1171-3 assume !(0 == ~T11_E~0); 82502#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 82500#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 82498#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 82496#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 82494#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 82492#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 82489#L1206-3 assume !(0 == ~E_6~0); 82487#L1211-3 assume !(0 == ~E_7~0); 82485#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 82483#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 82481#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 82479#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 82478#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82477#L556-39 assume !(1 == ~m_pc~0); 82476#L556-41 is_master_triggered_~__retres1~0#1 := 0; 82475#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82474#L568-13 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 82473#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 82472#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82471#L575-39 assume 1 == ~t1_pc~0; 82469#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 82468#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82467#L587-13 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 82466#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 82465#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82464#L594-39 assume !(1 == ~t2_pc~0); 81639#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 82463#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82462#L606-13 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82461#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 82460#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82459#L613-39 assume 1 == ~t3_pc~0; 82457#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 82456#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82455#L625-13 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 82454#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 82452#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82450#L632-39 assume 1 == ~t4_pc~0; 82448#L633-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 82445#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82443#L644-13 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 82441#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 82439#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82436#L651-39 assume 1 == ~t5_pc~0; 82433#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 82431#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82429#L663-13 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 82427#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 82425#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 82424#L670-39 assume !(1 == ~t6_pc~0); 82421#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 82419#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 82417#L682-13 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 82415#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 82413#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 82410#L689-39 assume 1 == ~t7_pc~0; 82407#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 82405#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 82403#L701-13 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 82401#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 82399#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 82396#L708-39 assume !(1 == ~t8_pc~0); 82393#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 82391#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 82389#L720-13 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 82387#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 82385#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 82382#L727-39 assume 1 == ~t9_pc~0; 82379#L728-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 82377#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 82375#L739-13 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 82373#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 82371#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 82368#L746-39 assume 1 == ~t10_pc~0; 82365#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 82363#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 82361#L758-13 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 82359#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 82357#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 82354#L765-39 assume 1 == ~t11_pc~0; 82352#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 82349#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 82347#L777-13 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 82345#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 82343#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82340#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 82338#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 82336#L1254-3 assume !(1 == ~T2_E~0); 82334#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 82332#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 82330#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 82327#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 82325#L1279-3 assume !(1 == ~T7_E~0); 82323#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 73305#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 82320#L1294-3 assume !(1 == ~T10_E~0); 82318#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 82315#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 82313#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 82311#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 82309#L1319-3 assume !(1 == ~E_3~0); 82307#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 82305#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 82302#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 74295#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 82299#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 82297#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 82295#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 82294#L1359-3 assume !(1 == ~E_11~0); 82293#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 82254#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 82248#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 82244#L923-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 82224#L1709 assume !(0 == start_simulation_~tmp~3#1); 82215#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 81895#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 81884#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 81882#L923-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 81880#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 81878#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 81875#L1672 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 81860#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 81852#L1690-2 [2021-11-13 18:20:44,322 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:44,322 INFO L85 PathProgramCache]: Analyzing trace with hash -746792586, now seen corresponding path program 1 times [2021-11-13 18:20:44,323 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:44,323 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [597254415] [2021-11-13 18:20:44,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:44,323 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:44,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:44,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:44,365 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:44,365 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [597254415] [2021-11-13 18:20:44,365 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [597254415] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:44,365 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:44,366 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:20:44,366 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1401894329] [2021-11-13 18:20:44,366 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:44,367 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:20:44,367 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:44,367 INFO L85 PathProgramCache]: Analyzing trace with hash -929664642, now seen corresponding path program 1 times [2021-11-13 18:20:44,367 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:44,368 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1458314288] [2021-11-13 18:20:44,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:44,368 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:44,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:44,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:44,409 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:44,410 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1458314288] [2021-11-13 18:20:44,410 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1458314288] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:44,410 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:44,410 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:44,410 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1912806958] [2021-11-13 18:20:44,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:44,411 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:20:44,411 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:20:44,412 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:20:44,412 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:20:44,412 INFO L87 Difference]: Start difference. First operand 10361 states and 15075 transitions. cyclomatic complexity: 4718 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:44,618 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:20:44,618 INFO L93 Difference]: Finished difference Result 19776 states and 28648 transitions. [2021-11-13 18:20:44,619 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:20:44,619 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19776 states and 28648 transitions. [2021-11-13 18:20:44,815 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19588 [2021-11-13 18:20:44,895 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19776 states to 19776 states and 28648 transitions. [2021-11-13 18:20:44,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19776 [2021-11-13 18:20:44,923 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19776 [2021-11-13 18:20:44,924 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19776 states and 28648 transitions. [2021-11-13 18:20:44,941 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:20:44,941 INFO L681 BuchiCegarLoop]: Abstraction has 19776 states and 28648 transitions. [2021-11-13 18:20:44,957 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19776 states and 28648 transitions. [2021-11-13 18:20:45,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19776 to 19760. [2021-11-13 18:20:45,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19760 states, 19760 states have (on average 1.4489878542510122) internal successors, (28632), 19759 states have internal predecessors, (28632), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:45,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19760 states to 19760 states and 28632 transitions. [2021-11-13 18:20:45,532 INFO L704 BuchiCegarLoop]: Abstraction has 19760 states and 28632 transitions. [2021-11-13 18:20:45,533 INFO L587 BuchiCegarLoop]: Abstraction has 19760 states and 28632 transitions. [2021-11-13 18:20:45,533 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-13 18:20:45,533 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19760 states and 28632 transitions. [2021-11-13 18:20:45,592 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19572 [2021-11-13 18:20:45,593 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:20:45,593 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:20:45,596 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:45,596 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:45,596 INFO L791 eck$LassoCheckResult]: Stem: 103470#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 103471#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 104066#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 104067#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 103915#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 103916#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 102887#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 102888#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 104468#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 103889#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 103890#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 104213#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 104214#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 104316#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 104419#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 104420#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 104276#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 104085#L1121 assume !(0 == ~M_E~0); 103801#L1121-2 assume !(0 == ~T1_E~0); 103161#L1126-1 assume !(0 == ~T2_E~0); 103162#L1131-1 assume !(0 == ~T3_E~0); 103332#L1136-1 assume !(0 == ~T4_E~0); 103428#L1141-1 assume !(0 == ~T5_E~0); 103665#L1146-1 assume !(0 == ~T6_E~0); 104000#L1151-1 assume !(0 == ~T7_E~0); 103490#L1156-1 assume !(0 == ~T8_E~0); 102873#L1161-1 assume !(0 == ~T9_E~0); 102874#L1166-1 assume !(0 == ~T10_E~0); 103095#L1171-1 assume !(0 == ~T11_E~0); 103096#L1176-1 assume !(0 == ~E_M~0); 104020#L1181-1 assume !(0 == ~E_1~0); 104171#L1186-1 assume !(0 == ~E_2~0); 104230#L1191-1 assume !(0 == ~E_3~0); 103123#L1196-1 assume !(0 == ~E_4~0); 103124#L1201-1 assume !(0 == ~E_5~0); 104485#L1206-1 assume !(0 == ~E_6~0); 104277#L1211-1 assume !(0 == ~E_7~0); 104278#L1216-1 assume !(0 == ~E_8~0); 103264#L1221-1 assume !(0 == ~E_9~0); 103265#L1226-1 assume !(0 == ~E_10~0); 102968#L1231-1 assume !(0 == ~E_11~0); 102969#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 104021#L556 assume !(1 == ~m_pc~0); 104022#L556-2 is_master_triggered_~__retres1~0#1 := 0; 102847#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 102848#L568 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 103758#L1391 assume !(0 != activate_threads_~tmp~1#1); 104202#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 104203#L575 assume !(1 == ~t1_pc~0); 102799#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 102800#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 102931#L587 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 103278#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 103234#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 103235#L594 assume !(1 == ~t2_pc~0); 103987#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 104100#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 103646#L606 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 102864#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 102865#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102921#L613 assume !(1 == ~t3_pc~0); 103037#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 103036#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 102964#L625 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 102965#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 103662#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 103366#L632 assume !(1 == ~t4_pc~0); 103367#L632-2 is_transmit4_triggered_~__retres1~4#1 := 0; 104086#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 104087#L644 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 104486#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 104029#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 103740#L651 assume 1 == ~t5_pc~0; 103741#L652 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 103050#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 103051#L663 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 103502#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 103067#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 103068#L670 assume !(1 == ~t6_pc~0); 104257#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 103417#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 103418#L682 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 104369#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 103704#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 103705#L689 assume 1 == ~t7_pc~0; 104480#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 103823#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 103824#L701 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 104274#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 103602#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 103603#L708 assume !(1 == ~t8_pc~0); 103156#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 103157#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 104367#L720 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 104348#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 103219#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 103220#L727 assume 1 == ~t9_pc~0; 103346#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 102923#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 104493#L739 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 104494#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 104469#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 103274#L746 assume !(1 == ~t10_pc~0); 103275#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 103974#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 104108#L758 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 104359#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 104206#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 103437#L765 assume 1 == ~t11_pc~0; 103438#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 103656#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 102812#L777 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 102813#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 104256#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 104345#L1249 assume !(1 == ~M_E~0); 103908#L1249-2 assume !(1 == ~T1_E~0); 103523#L1254-1 assume !(1 == ~T2_E~0); 102858#L1259-1 assume !(1 == ~T3_E~0); 102840#L1264-1 assume !(1 == ~T4_E~0); 102841#L1269-1 assume !(1 == ~T5_E~0); 104539#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 104432#L1279-1 assume !(1 == ~T7_E~0); 103038#L1284-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 103039#L1289-1 assume !(1 == ~T9_E~0); 111877#L1294-1 assume !(1 == ~T10_E~0); 111876#L1299-1 assume !(1 == ~T11_E~0); 111875#L1304-1 assume !(1 == ~E_M~0); 111874#L1309-1 assume !(1 == ~E_1~0); 111873#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 111872#L1319-1 assume !(1 == ~E_3~0); 111871#L1324-1 assume !(1 == ~E_4~0); 111870#L1329-1 assume !(1 == ~E_5~0); 111869#L1334-1 assume !(1 == ~E_6~0); 104298#L1339-1 assume !(1 == ~E_7~0); 111868#L1344-1 assume !(1 == ~E_8~0); 111867#L1349-1 assume !(1 == ~E_9~0); 111866#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 111865#L1359-1 assume !(1 == ~E_11~0); 111864#L1364-1 assume { :end_inline_reset_delta_events } true; 111862#L1690-2 [2021-11-13 18:20:45,597 INFO L793 eck$LassoCheckResult]: Loop: 111862#L1690-2 assume !false; 111774#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 111772#L1096 assume !false; 111771#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 109056#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 109054#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 109044#L923 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 109045#L937 assume !(0 != eval_~tmp~0#1); 111756#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 112653#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 112651#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 112649#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 112647#L1126-3 assume !(0 == ~T2_E~0); 112644#L1131-3 assume !(0 == ~T3_E~0); 112642#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 112640#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 112638#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 112636#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 112634#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 112632#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 112630#L1166-3 assume !(0 == ~T10_E~0); 112628#L1171-3 assume !(0 == ~T11_E~0); 112626#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 112624#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 112622#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 112619#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 112617#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 112615#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 112613#L1206-3 assume !(0 == ~E_6~0); 112611#L1211-3 assume !(0 == ~E_7~0); 112609#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 112608#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 112607#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 112606#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 112605#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 112604#L556-39 assume !(1 == ~m_pc~0); 112603#L556-41 is_master_triggered_~__retres1~0#1 := 0; 112602#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112601#L568-13 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 112600#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 112599#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 112598#L575-39 assume !(1 == ~t1_pc~0); 112597#L575-41 is_transmit1_triggered_~__retres1~1#1 := 0; 112595#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 112594#L587-13 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 112593#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 112592#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 112591#L594-39 assume !(1 == ~t2_pc~0); 110997#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 112590#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 112589#L606-13 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 112588#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 112587#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 112586#L613-39 assume !(1 == ~t3_pc~0); 112585#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 112583#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 112582#L625-13 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 112581#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 112580#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 112579#L632-39 assume !(1 == ~t4_pc~0); 112578#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 112577#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 112576#L644-13 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 112575#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 112574#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 112573#L651-39 assume 1 == ~t5_pc~0; 112571#L652-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 112570#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 112569#L663-13 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 112568#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 112567#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 112566#L670-39 assume 1 == ~t6_pc~0; 112565#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 112563#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 112562#L682-13 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 112561#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 112560#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 112559#L689-39 assume 1 == ~t7_pc~0; 112557#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 112556#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 112555#L701-13 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 112554#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 112553#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 112552#L708-39 assume 1 == ~t8_pc~0; 112551#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 112549#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 112548#L720-13 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 112547#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 112546#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 112545#L727-39 assume !(1 == ~t9_pc~0); 112544#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 112542#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 112541#L739-13 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 112540#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 112539#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 112538#L746-39 assume !(1 == ~t10_pc~0); 112537#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 112535#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 112534#L758-13 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 112533#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 112532#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 112531#L765-39 assume !(1 == ~t11_pc~0); 112529#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 112528#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 112527#L777-13 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 112526#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 112525#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112524#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 112523#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 112522#L1254-3 assume !(1 == ~T2_E~0); 112521#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 112520#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 112519#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 112518#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 112517#L1279-3 assume !(1 == ~T7_E~0); 112516#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 109393#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 112515#L1294-3 assume !(1 == ~T10_E~0); 112514#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 112513#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 112512#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 112511#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 112510#L1319-3 assume !(1 == ~E_3~0); 112509#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 112508#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 112507#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 109371#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 112506#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 112505#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 112504#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 112503#L1359-3 assume !(1 == ~E_11~0); 112502#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 109334#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 109332#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 109325#L923-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 109326#L1709 assume !(0 == start_simulation_~tmp~3#1); 111895#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 111892#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 111882#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 111881#L923-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 111880#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 111879#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 111878#L1672 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 111863#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 111862#L1690-2 [2021-11-13 18:20:45,598 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:45,598 INFO L85 PathProgramCache]: Analyzing trace with hash 1385195447, now seen corresponding path program 1 times [2021-11-13 18:20:45,598 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:45,598 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2117995099] [2021-11-13 18:20:45,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:45,599 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:45,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:45,722 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:45,723 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:45,723 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2117995099] [2021-11-13 18:20:45,723 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2117995099] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:45,723 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:45,723 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:45,723 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1855431747] [2021-11-13 18:20:45,724 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:45,724 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:20:45,724 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:45,725 INFO L85 PathProgramCache]: Analyzing trace with hash -1894233470, now seen corresponding path program 1 times [2021-11-13 18:20:45,725 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:45,725 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [562363288] [2021-11-13 18:20:45,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:45,725 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:45,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:45,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:45,766 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:45,766 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [562363288] [2021-11-13 18:20:45,766 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [562363288] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:45,766 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:45,767 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:45,767 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [38937986] [2021-11-13 18:20:45,767 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:45,768 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:20:45,768 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:20:45,768 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:20:45,768 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:20:45,769 INFO L87 Difference]: Start difference. First operand 19760 states and 28632 transitions. cyclomatic complexity: 8880 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:46,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:20:46,319 INFO L93 Difference]: Finished difference Result 48451 states and 69677 transitions. [2021-11-13 18:20:46,320 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:20:46,320 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48451 states and 69677 transitions. [2021-11-13 18:20:46,701 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 47520 [2021-11-13 18:20:46,908 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48451 states to 48451 states and 69677 transitions. [2021-11-13 18:20:46,908 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48451 [2021-11-13 18:20:46,933 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48451 [2021-11-13 18:20:46,933 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48451 states and 69677 transitions. [2021-11-13 18:20:46,983 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:20:46,984 INFO L681 BuchiCegarLoop]: Abstraction has 48451 states and 69677 transitions. [2021-11-13 18:20:47,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48451 states and 69677 transitions. [2021-11-13 18:20:47,555 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48451 to 38447. [2021-11-13 18:20:47,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38447 states, 38447 states have (on average 1.4423231981689077) internal successors, (55453), 38446 states have internal predecessors, (55453), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:47,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38447 states to 38447 states and 55453 transitions. [2021-11-13 18:20:47,724 INFO L704 BuchiCegarLoop]: Abstraction has 38447 states and 55453 transitions. [2021-11-13 18:20:47,724 INFO L587 BuchiCegarLoop]: Abstraction has 38447 states and 55453 transitions. [2021-11-13 18:20:47,724 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-13 18:20:47,724 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38447 states and 55453 transitions. [2021-11-13 18:20:47,982 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 38236 [2021-11-13 18:20:47,982 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:20:47,982 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:20:47,985 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:47,985 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:47,986 INFO L791 eck$LassoCheckResult]: Stem: 171684#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 171685#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 172268#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 172269#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 172105#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 172106#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 171108#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 171109#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 172648#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 172080#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 172081#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 172405#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 172406#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 172504#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 172608#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 172609#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 172462#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 172286#L1121 assume !(0 == ~M_E~0); 172005#L1121-2 assume !(0 == ~T1_E~0); 171379#L1126-1 assume !(0 == ~T2_E~0); 171380#L1131-1 assume !(0 == ~T3_E~0); 171545#L1136-1 assume !(0 == ~T4_E~0); 171642#L1141-1 assume !(0 == ~T5_E~0); 171878#L1146-1 assume !(0 == ~T6_E~0); 172201#L1151-1 assume !(0 == ~T7_E~0); 171701#L1156-1 assume !(0 == ~T8_E~0); 171094#L1161-1 assume !(0 == ~T9_E~0); 171095#L1166-1 assume !(0 == ~T10_E~0); 171313#L1171-1 assume !(0 == ~T11_E~0); 171314#L1176-1 assume !(0 == ~E_M~0); 172218#L1181-1 assume !(0 == ~E_1~0); 172361#L1186-1 assume !(0 == ~E_2~0); 172420#L1191-1 assume !(0 == ~E_3~0); 171341#L1196-1 assume !(0 == ~E_4~0); 171342#L1201-1 assume !(0 == ~E_5~0); 172667#L1206-1 assume !(0 == ~E_6~0); 172463#L1211-1 assume !(0 == ~E_7~0); 172464#L1216-1 assume !(0 == ~E_8~0); 171483#L1221-1 assume !(0 == ~E_9~0); 171484#L1226-1 assume !(0 == ~E_10~0); 171189#L1231-1 assume !(0 == ~E_11~0); 171190#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 172221#L556 assume !(1 == ~m_pc~0); 172222#L556-2 is_master_triggered_~__retres1~0#1 := 0; 171068#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 171069#L568 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 171965#L1391 assume !(0 != activate_threads_~tmp~1#1); 172395#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 172396#L575 assume !(1 == ~t1_pc~0); 171020#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 171021#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 171152#L587 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 171493#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 171450#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 171451#L594 assume !(1 == ~t2_pc~0); 172186#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 172302#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 171859#L606 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 171085#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 171086#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 171142#L613 assume !(1 == ~t3_pc~0); 171257#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 171256#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 171185#L625 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 171186#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 171872#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 171580#L632 assume !(1 == ~t4_pc~0); 171581#L632-2 is_transmit4_triggered_~__retres1~4#1 := 0; 172287#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 172288#L644 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 172668#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 172227#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 171948#L651 assume !(1 == ~t5_pc~0); 171949#L651-2 is_transmit5_triggered_~__retres1~5#1 := 0; 171270#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 171271#L663 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 171713#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 171286#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 171287#L670 assume !(1 == ~t6_pc~0); 172444#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 171633#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 171634#L682 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 172558#L1439 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 171915#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 171916#L689 assume 1 == ~t7_pc~0; 172661#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 172023#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 172024#L701 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 172460#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 171811#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 171812#L708 assume !(1 == ~t8_pc~0); 171374#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 171375#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 172556#L720 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 172540#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 171435#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 171436#L727 assume 1 == ~t9_pc~0; 171559#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 171144#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 172678#L739 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 172679#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 172653#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 171490#L746 assume !(1 == ~t10_pc~0); 171491#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 172169#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 172307#L758 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 172550#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 172399#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 171654#L765 assume 1 == ~t11_pc~0; 171655#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 171869#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 171033#L777 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 171034#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 172442#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 172537#L1249 assume !(1 == ~M_E~0); 172099#L1249-2 assume !(1 == ~T1_E~0); 171734#L1254-1 assume !(1 == ~T2_E~0); 171079#L1259-1 assume !(1 == ~T3_E~0); 171061#L1264-1 assume !(1 == ~T4_E~0); 171062#L1269-1 assume !(1 == ~T5_E~0); 172710#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 172617#L1279-1 assume !(1 == ~T7_E~0); 171258#L1284-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 171259#L1289-1 assume !(1 == ~T9_E~0); 171790#L1294-1 assume !(1 == ~T10_E~0); 171791#L1299-1 assume !(1 == ~T11_E~0); 171800#L1304-1 assume !(1 == ~E_M~0); 172693#L1309-1 assume !(1 == ~E_1~0); 172697#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 171208#L1319-1 assume !(1 == ~E_3~0); 171209#L1324-1 assume !(1 == ~E_4~0); 171336#L1329-1 assume !(1 == ~E_5~0); 171337#L1334-1 assume !(1 == ~E_6~0); 172487#L1339-1 assume !(1 == ~E_7~0); 172580#L1344-1 assume !(1 == ~E_8~0); 172581#L1349-1 assume !(1 == ~E_9~0); 171928#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 171929#L1359-1 assume !(1 == ~E_11~0); 172332#L1364-1 assume { :end_inline_reset_delta_events } true; 171421#L1690-2 [2021-11-13 18:20:47,987 INFO L793 eck$LassoCheckResult]: Loop: 171421#L1690-2 assume !false; 171422#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 171310#L1096 assume !false; 172343#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 171162#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 171163#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 172220#L923 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 171649#L937 assume !(0 != eval_~tmp~0#1); 171650#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 209062#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 209061#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 209060#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 209059#L1126-3 assume !(0 == ~T2_E~0); 209058#L1131-3 assume !(0 == ~T3_E~0); 209057#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 209056#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 209055#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 209054#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 209052#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 209050#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 209048#L1166-3 assume !(0 == ~T10_E~0); 209046#L1171-3 assume !(0 == ~T11_E~0); 209044#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 209042#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 209040#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 209037#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 209035#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 209033#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 209031#L1206-3 assume !(0 == ~E_6~0); 209029#L1211-3 assume !(0 == ~E_7~0); 208849#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 208846#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 208845#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 208844#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 208843#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 208842#L556-39 assume !(1 == ~m_pc~0); 208841#L556-41 is_master_triggered_~__retres1~0#1 := 0; 208840#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 208839#L568-13 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 208837#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 208835#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 208833#L575-39 assume !(1 == ~t1_pc~0); 208831#L575-41 is_transmit1_triggered_~__retres1~1#1 := 0; 208828#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 208826#L587-13 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 208824#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 208821#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 172290#L594-39 assume !(1 == ~t2_pc~0); 172291#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 172044#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 172045#L606-13 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 172542#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 171546#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 171547#L613-39 assume 1 == ~t3_pc~0; 172510#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 171039#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 171040#L625-13 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 171795#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 171138#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 171139#L632-39 assume !(1 == ~t4_pc~0); 172333#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 171714#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 171715#L644-13 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 172324#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 172472#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 171395#L651-39 assume !(1 == ~t5_pc~0); 171165#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 171166#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 172459#L663-13 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 172588#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 172639#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 172681#L670-39 assume !(1 == ~t6_pc~0); 172160#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 171083#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 171084#L682-13 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 171153#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 171743#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 171744#L689-39 assume 1 == ~t7_pc~0; 171975#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 171877#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 171400#L701-13 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 171401#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 171274#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 171275#L708-39 assume !(1 == ~t8_pc~0); 171216#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 171215#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 171315#L720-13 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 171316#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 172237#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 171688#L727-39 assume 1 == ~t9_pc~0; 171690#L728-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 171465#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 171466#L739-13 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 172491#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 172296#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 172297#L746-39 assume !(1 == ~t10_pc~0); 172263#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 172262#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 172569#L758-13 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 171960#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 171961#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 172433#L765-39 assume !(1 == ~t11_pc~0); 171090#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 171091#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 172317#L777-13 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 171419#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 171420#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 171999#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 171232#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 171233#L1254-3 assume !(1 == ~T2_E~0); 172574#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 172132#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 171193#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 171194#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 172615#L1279-3 assume !(1 == ~T7_E~0); 171664#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 171665#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 171657#L1294-3 assume !(1 == ~T10_E~0); 171658#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 171922#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 171923#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 171576#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 171577#L1319-3 assume !(1 == ~E_3~0); 172391#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 171298#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 171299#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 171857#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 171858#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 172079#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 171554#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 171555#L1359-3 assume !(1 == ~E_11~0); 172094#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 171154#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 171155#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 171779#L923-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 171780#L1709 assume !(0 == start_simulation_~tmp~3#1); 171584#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 172415#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 171266#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 171766#L923-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 171229#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 171230#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 172055#L1672 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 172500#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 171421#L1690-2 [2021-11-13 18:20:47,988 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:47,988 INFO L85 PathProgramCache]: Analyzing trace with hash -772277576, now seen corresponding path program 1 times [2021-11-13 18:20:47,988 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:47,989 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [238641165] [2021-11-13 18:20:47,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:47,989 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:48,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:48,043 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:48,044 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:48,044 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [238641165] [2021-11-13 18:20:48,044 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [238641165] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:48,044 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:48,045 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-13 18:20:48,045 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2040671318] [2021-11-13 18:20:48,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:48,046 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:20:48,048 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:48,049 INFO L85 PathProgramCache]: Analyzing trace with hash -1696731773, now seen corresponding path program 1 times [2021-11-13 18:20:48,049 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:48,049 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2081090840] [2021-11-13 18:20:48,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:48,049 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:48,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:48,087 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:48,087 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:48,087 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2081090840] [2021-11-13 18:20:48,088 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2081090840] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:48,088 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:48,088 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:48,088 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [669543232] [2021-11-13 18:20:48,088 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:48,090 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:20:48,090 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:20:48,091 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-13 18:20:48,091 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-13 18:20:48,091 INFO L87 Difference]: Start difference. First operand 38447 states and 55453 transitions. cyclomatic complexity: 17014 Second operand has 5 states, 5 states have (on average 27.8) internal successors, (139), 5 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:48,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:20:48,936 INFO L93 Difference]: Finished difference Result 96704 states and 140076 transitions. [2021-11-13 18:20:48,936 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-13 18:20:48,936 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 96704 states and 140076 transitions. [2021-11-13 18:20:49,645 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 96240 [2021-11-13 18:20:49,967 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 96704 states to 96704 states and 140076 transitions. [2021-11-13 18:20:49,967 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 96704 [2021-11-13 18:20:50,026 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 96704 [2021-11-13 18:20:50,026 INFO L73 IsDeterministic]: Start isDeterministic. Operand 96704 states and 140076 transitions. [2021-11-13 18:20:50,157 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:20:50,157 INFO L681 BuchiCegarLoop]: Abstraction has 96704 states and 140076 transitions. [2021-11-13 18:20:50,224 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96704 states and 140076 transitions. [2021-11-13 18:20:51,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96704 to 39578. [2021-11-13 18:20:51,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39578 states, 39578 states have (on average 1.4296831573096165) internal successors, (56584), 39577 states have internal predecessors, (56584), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:51,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39578 states to 39578 states and 56584 transitions. [2021-11-13 18:20:51,206 INFO L704 BuchiCegarLoop]: Abstraction has 39578 states and 56584 transitions. [2021-11-13 18:20:51,207 INFO L587 BuchiCegarLoop]: Abstraction has 39578 states and 56584 transitions. [2021-11-13 18:20:51,207 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-13 18:20:51,207 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39578 states and 56584 transitions. [2021-11-13 18:20:51,338 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 39364 [2021-11-13 18:20:51,338 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:20:51,338 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:20:51,340 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:51,341 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:51,341 INFO L791 eck$LassoCheckResult]: Stem: 306853#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 306854#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 307444#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 307445#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 307282#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 307283#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 306273#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 306274#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 307878#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 307255#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 307256#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 307592#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 307593#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 307717#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 307836#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 307837#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 307660#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 307462#L1121 assume !(0 == ~M_E~0); 307182#L1121-2 assume !(0 == ~T1_E~0); 306545#L1126-1 assume !(0 == ~T2_E~0); 306546#L1131-1 assume !(0 == ~T3_E~0); 306712#L1136-1 assume !(0 == ~T4_E~0); 306810#L1141-1 assume !(0 == ~T5_E~0); 307045#L1146-1 assume !(0 == ~T6_E~0); 307376#L1151-1 assume !(0 == ~T7_E~0); 306870#L1156-1 assume !(0 == ~T8_E~0); 306259#L1161-1 assume !(0 == ~T9_E~0); 306260#L1166-1 assume !(0 == ~T10_E~0); 306479#L1171-1 assume !(0 == ~T11_E~0); 306480#L1176-1 assume !(0 == ~E_M~0); 307393#L1181-1 assume !(0 == ~E_1~0); 307543#L1186-1 assume !(0 == ~E_2~0); 307610#L1191-1 assume !(0 == ~E_3~0); 306507#L1196-1 assume !(0 == ~E_4~0); 306508#L1201-1 assume !(0 == ~E_5~0); 307902#L1206-1 assume !(0 == ~E_6~0); 307661#L1211-1 assume !(0 == ~E_7~0); 307662#L1216-1 assume !(0 == ~E_8~0); 306646#L1221-1 assume !(0 == ~E_9~0); 306647#L1226-1 assume !(0 == ~E_10~0); 306354#L1231-1 assume !(0 == ~E_11~0); 306355#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 307394#L556 assume !(1 == ~m_pc~0); 307395#L556-2 is_master_triggered_~__retres1~0#1 := 0; 306233#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 306234#L568 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 307138#L1391 assume !(0 != activate_threads_~tmp~1#1); 307578#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 307579#L575 assume !(1 == ~t1_pc~0); 306184#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 306185#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 306318#L587 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 306659#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 306616#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 306617#L594 assume !(1 == ~t2_pc~0); 307362#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 307477#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 307023#L606 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 306250#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 306251#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 306308#L613 assume !(1 == ~t3_pc~0); 306422#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 306421#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 306350#L625 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 306351#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 307039#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 306748#L632 assume !(1 == ~t4_pc~0); 306749#L632-2 is_transmit4_triggered_~__retres1~4#1 := 0; 307463#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 307464#L644 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 307904#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 307401#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 307119#L651 assume !(1 == ~t5_pc~0); 307120#L651-2 is_transmit5_triggered_~__retres1~5#1 := 0; 306435#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 306436#L663 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 306882#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 306452#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 306453#L670 assume !(1 == ~t6_pc~0); 307638#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 306801#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 306802#L682 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 307879#L1439 assume !(0 != activate_threads_~tmp___5~0#1); 307083#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 307084#L689 assume 1 == ~t7_pc~0; 307893#L690 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 307200#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 307201#L701 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 307657#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 306979#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 306980#L708 assume !(1 == ~t8_pc~0); 306540#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 306541#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 307774#L720 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 307752#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 306601#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 306602#L727 assume 1 == ~t9_pc~0; 306726#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 306310#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 307914#L739 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 307915#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 307883#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 306656#L746 assume !(1 == ~t10_pc~0); 306657#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 307344#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 307483#L758 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 307766#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 307583#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 306822#L765 assume 1 == ~t11_pc~0; 306823#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 307034#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 306198#L777 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 306199#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 307636#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 307749#L1249 assume !(1 == ~M_E~0); 307274#L1249-2 assume !(1 == ~T1_E~0); 306903#L1254-1 assume !(1 == ~T2_E~0); 306244#L1259-1 assume !(1 == ~T3_E~0); 306226#L1264-1 assume !(1 == ~T4_E~0); 306227#L1269-1 assume !(1 == ~T5_E~0); 307964#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 307846#L1279-1 assume !(1 == ~T7_E~0); 306423#L1284-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 306424#L1289-1 assume !(1 == ~T9_E~0); 326524#L1294-1 assume !(1 == ~T10_E~0); 326522#L1299-1 assume !(1 == ~T11_E~0); 326520#L1304-1 assume !(1 == ~E_M~0); 326517#L1309-1 assume !(1 == ~E_1~0); 326515#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 326513#L1319-1 assume !(1 == ~E_3~0); 326511#L1324-1 assume !(1 == ~E_4~0); 326509#L1329-1 assume !(1 == ~E_5~0); 326507#L1334-1 assume !(1 == ~E_6~0); 307698#L1339-1 assume !(1 == ~E_7~0); 326503#L1344-1 assume !(1 == ~E_8~0); 326501#L1349-1 assume !(1 == ~E_9~0); 326499#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 326497#L1359-1 assume !(1 == ~E_11~0); 326495#L1364-1 assume { :end_inline_reset_delta_events } true; 326491#L1690-2 [2021-11-13 18:20:51,342 INFO L793 eck$LassoCheckResult]: Loop: 326491#L1690-2 assume !false; 326415#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 326411#L1096 assume !false; 326409#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 326385#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 326380#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 326378#L923 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 326375#L937 assume !(0 != eval_~tmp~0#1); 326376#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 345004#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 345003#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 345002#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 345001#L1126-3 assume !(0 == ~T2_E~0); 345000#L1131-3 assume !(0 == ~T3_E~0); 344998#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 344996#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 344994#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 344992#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 344990#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 344988#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 344986#L1166-3 assume !(0 == ~T10_E~0); 344983#L1171-3 assume !(0 == ~T11_E~0); 344981#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 344979#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 344977#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 344975#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 344973#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 344972#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 344969#L1206-3 assume !(0 == ~E_6~0); 344967#L1211-3 assume !(0 == ~E_7~0); 344965#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 344963#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 344961#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 344959#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 344956#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 344954#L556-39 assume !(1 == ~m_pc~0); 344952#L556-41 is_master_triggered_~__retres1~0#1 := 0; 344950#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 344948#L568-13 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 344946#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 344944#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 344942#L575-39 assume !(1 == ~t1_pc~0); 344940#L575-41 is_transmit1_triggered_~__retres1~1#1 := 0; 344936#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 344935#L587-13 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 344934#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 344933#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 307468#L594-39 assume !(1 == ~t2_pc~0); 307469#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 342837#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 342835#L606-13 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 342833#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 342832#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 342798#L613-39 assume 1 == ~t3_pc~0; 342793#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 342789#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 342784#L625-13 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 342780#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 342775#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 342771#L632-39 assume !(1 == ~t4_pc~0); 342767#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 342763#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 342760#L644-13 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 342758#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 342754#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 326894#L651-39 assume !(1 == ~t5_pc~0); 326893#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 326892#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 326891#L663-13 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 326890#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 326889#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 326888#L670-39 assume 1 == ~t6_pc~0; 326886#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 326884#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 326882#L682-13 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 326880#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 326878#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 326876#L689-39 assume 1 == ~t7_pc~0; 326872#L690-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 326870#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 326868#L701-13 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 326866#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 326864#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 326862#L708-39 assume !(1 == ~t8_pc~0); 326858#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 326856#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 326854#L720-13 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 326852#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 326850#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 326848#L727-39 assume 1 == ~t9_pc~0; 326844#L728-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 326842#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 326840#L739-13 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 326838#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 326836#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 326834#L746-39 assume 1 == ~t10_pc~0; 326830#L747-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 326828#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 326826#L758-13 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 326824#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 326822#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 326820#L765-39 assume !(1 == ~t11_pc~0); 326816#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 326814#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 326812#L777-13 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 326810#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 326808#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 326806#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 326804#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 326802#L1254-3 assume !(1 == ~T2_E~0); 326800#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 326798#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 326796#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 326794#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 326792#L1279-3 assume !(1 == ~T7_E~0); 326791#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 326788#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 326786#L1294-3 assume !(1 == ~T10_E~0); 326784#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 326782#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 326780#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 326778#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 326776#L1319-3 assume !(1 == ~E_3~0); 326774#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 326772#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 326771#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 326768#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 326767#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 326766#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 326765#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 326764#L1359-3 assume !(1 == ~E_11~0); 326763#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 326626#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 326622#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 326620#L923-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 326616#L1709 assume !(0 == start_simulation_~tmp~3#1); 326615#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 326612#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 326599#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 326597#L923-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 326595#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 326590#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 326589#L1672 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 326494#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 326491#L1690-2 [2021-11-13 18:20:51,342 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:51,343 INFO L85 PathProgramCache]: Analyzing trace with hash 488639674, now seen corresponding path program 1 times [2021-11-13 18:20:51,343 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:51,343 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1479984692] [2021-11-13 18:20:51,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:51,343 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:51,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:51,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:51,399 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:51,399 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1479984692] [2021-11-13 18:20:51,399 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1479984692] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:51,400 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:51,400 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:51,400 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [192568951] [2021-11-13 18:20:51,403 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:51,403 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:20:51,403 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:51,404 INFO L85 PathProgramCache]: Analyzing trace with hash -1001955839, now seen corresponding path program 1 times [2021-11-13 18:20:51,404 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:51,404 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [466406026] [2021-11-13 18:20:51,404 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:51,404 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:51,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:51,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:51,440 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:51,440 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [466406026] [2021-11-13 18:20:51,440 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [466406026] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:51,440 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:51,440 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:51,441 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [785408489] [2021-11-13 18:20:51,441 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:51,441 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:20:51,441 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:20:51,442 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:20:51,442 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:20:51,442 INFO L87 Difference]: Start difference. First operand 39578 states and 56584 transitions. cyclomatic complexity: 17014 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:52,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:20:52,259 INFO L93 Difference]: Finished difference Result 95557 states and 135745 transitions. [2021-11-13 18:20:52,260 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:20:52,260 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 95557 states and 135745 transitions. [2021-11-13 18:20:52,609 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 93816 [2021-11-13 18:20:53,157 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 95557 states to 95557 states and 135745 transitions. [2021-11-13 18:20:53,158 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 95557 [2021-11-13 18:20:53,202 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 95557 [2021-11-13 18:20:53,203 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95557 states and 135745 transitions. [2021-11-13 18:20:53,251 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:20:53,251 INFO L681 BuchiCegarLoop]: Abstraction has 95557 states and 135745 transitions. [2021-11-13 18:20:53,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95557 states and 135745 transitions. [2021-11-13 18:20:54,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95557 to 75765. [2021-11-13 18:20:54,332 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75765 states, 75765 states have (on average 1.424734376031149) internal successors, (107945), 75764 states have internal predecessors, (107945), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:54,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75765 states to 75765 states and 107945 transitions. [2021-11-13 18:20:54,543 INFO L704 BuchiCegarLoop]: Abstraction has 75765 states and 107945 transitions. [2021-11-13 18:20:54,543 INFO L587 BuchiCegarLoop]: Abstraction has 75765 states and 107945 transitions. [2021-11-13 18:20:54,543 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-13 18:20:54,543 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75765 states and 107945 transitions. [2021-11-13 18:20:54,761 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 75504 [2021-11-13 18:20:54,761 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:20:54,761 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:20:54,765 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:54,766 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:20:54,766 INFO L791 eck$LassoCheckResult]: Stem: 441998#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 441999#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 442605#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 442606#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 442435#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 442436#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 441416#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 441417#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 443038#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 442405#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 442406#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 442756#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 442757#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 442874#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 442985#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 442986#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 442823#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 442624#L1121 assume !(0 == ~M_E~0); 442328#L1121-2 assume !(0 == ~T1_E~0); 441689#L1126-1 assume !(0 == ~T2_E~0); 441690#L1131-1 assume !(0 == ~T3_E~0); 441858#L1136-1 assume !(0 == ~T4_E~0); 441955#L1141-1 assume !(0 == ~T5_E~0); 442195#L1146-1 assume !(0 == ~T6_E~0); 442535#L1151-1 assume !(0 == ~T7_E~0); 442016#L1156-1 assume !(0 == ~T8_E~0); 441403#L1161-1 assume !(0 == ~T9_E~0); 441404#L1166-1 assume !(0 == ~T10_E~0); 441622#L1171-1 assume !(0 == ~T11_E~0); 441623#L1176-1 assume !(0 == ~E_M~0); 442552#L1181-1 assume !(0 == ~E_1~0); 442709#L1186-1 assume !(0 == ~E_2~0); 442770#L1191-1 assume !(0 == ~E_3~0); 441650#L1196-1 assume !(0 == ~E_4~0); 441651#L1201-1 assume !(0 == ~E_5~0); 443057#L1206-1 assume !(0 == ~E_6~0); 442824#L1211-1 assume !(0 == ~E_7~0); 442825#L1216-1 assume !(0 == ~E_8~0); 441794#L1221-1 assume !(0 == ~E_9~0); 441795#L1226-1 assume !(0 == ~E_10~0); 441497#L1231-1 assume !(0 == ~E_11~0); 441498#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 442554#L556 assume !(1 == ~m_pc~0); 442555#L556-2 is_master_triggered_~__retres1~0#1 := 0; 441377#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 441378#L568 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 442282#L1391 assume !(0 != activate_threads_~tmp~1#1); 442746#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 442747#L575 assume !(1 == ~t1_pc~0); 441329#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 441330#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 441461#L587 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 441805#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 441761#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 441762#L594 assume !(1 == ~t2_pc~0); 442522#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 442639#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 442172#L606 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 441394#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 441395#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 441451#L613 assume !(1 == ~t3_pc~0); 441565#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 441564#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 441493#L625 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 441494#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 442189#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 441894#L632 assume !(1 == ~t4_pc~0); 441895#L632-2 is_transmit4_triggered_~__retres1~4#1 := 0; 442625#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 442626#L644 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 443058#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 442561#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 442264#L651 assume !(1 == ~t5_pc~0); 442265#L651-2 is_transmit5_triggered_~__retres1~5#1 := 0; 441578#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 441579#L663 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 442028#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 441594#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 441595#L670 assume !(1 == ~t6_pc~0); 442799#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 441946#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 441947#L682 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 443039#L1439 assume !(0 != activate_threads_~tmp___5~0#1); 442230#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 442231#L689 assume !(1 == ~t7_pc~0); 442478#L689-2 is_transmit7_triggered_~__retres1~7#1 := 0; 442347#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 442348#L701 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 442820#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 442127#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 442128#L708 assume !(1 == ~t8_pc~0); 441684#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 441685#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 442930#L720 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 442911#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 441744#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 441745#L727 assume 1 == ~t9_pc~0; 441873#L728 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 441453#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 443068#L739 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 443069#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 443046#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 441802#L746 assume !(1 == ~t10_pc~0); 441803#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 442503#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 442646#L758 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 442922#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 442749#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 441967#L765 assume 1 == ~t11_pc~0; 441968#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 442183#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 441342#L777 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 441343#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 442797#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 442908#L1249 assume !(1 == ~M_E~0); 442427#L1249-2 assume !(1 == ~T1_E~0); 442049#L1254-1 assume !(1 == ~T2_E~0); 441388#L1259-1 assume !(1 == ~T3_E~0); 441370#L1264-1 assume !(1 == ~T4_E~0); 441371#L1269-1 assume !(1 == ~T5_E~0); 443132#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 443002#L1279-1 assume !(1 == ~T7_E~0); 441566#L1284-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 441567#L1289-1 assume !(1 == ~T9_E~0); 442105#L1294-1 assume !(1 == ~T10_E~0); 442106#L1299-1 assume !(1 == ~T11_E~0); 443103#L1304-1 assume !(1 == ~E_M~0); 443104#L1309-1 assume !(1 == ~E_1~0); 443108#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 443109#L1319-1 assume !(1 == ~E_3~0); 442671#L1324-1 assume !(1 == ~E_4~0); 442672#L1329-1 assume !(1 == ~E_5~0); 442853#L1334-1 assume !(1 == ~E_6~0); 442854#L1339-1 assume !(1 == ~E_7~0); 442951#L1344-1 assume !(1 == ~E_8~0); 442952#L1349-1 assume !(1 == ~E_9~0); 442244#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 442245#L1359-1 assume !(1 == ~E_11~0); 443075#L1364-1 assume { :end_inline_reset_delta_events } true; 443076#L1690-2 [2021-11-13 18:20:54,767 INFO L793 eck$LassoCheckResult]: Loop: 443076#L1690-2 assume !false; 502024#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 502020#L1096 assume !false; 502018#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 501923#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 501912#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 501742#L923 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 501732#L937 assume !(0 != eval_~tmp~0#1); 501733#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 514909#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 514907#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 514904#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 514902#L1126-3 assume !(0 == ~T2_E~0); 514900#L1131-3 assume !(0 == ~T3_E~0); 514898#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 514896#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 514894#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 514891#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 514889#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 514887#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 514885#L1166-3 assume !(0 == ~T10_E~0); 514883#L1171-3 assume !(0 == ~T11_E~0); 514881#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 514878#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 514876#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 514874#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 514872#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 514870#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 514868#L1206-3 assume !(0 == ~E_6~0); 514865#L1211-3 assume !(0 == ~E_7~0); 514863#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 514861#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 514859#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 514857#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 514854#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 514852#L556-39 assume !(1 == ~m_pc~0); 514850#L556-41 is_master_triggered_~__retres1~0#1 := 0; 514848#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 514846#L568-13 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 514843#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 514841#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 514839#L575-39 assume !(1 == ~t1_pc~0); 514837#L575-41 is_transmit1_triggered_~__retres1~1#1 := 0; 514834#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 514832#L587-13 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 514829#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 514828#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 442630#L594-39 assume !(1 == ~t2_pc~0); 442631#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 514946#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 514944#L606-13 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 514942#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 514939#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 514937#L613-39 assume !(1 == ~t3_pc~0); 514935#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 514932#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 514930#L625-13 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 514928#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 514926#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 514924#L632-39 assume !(1 == ~t4_pc~0); 514922#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 514920#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 514918#L644-13 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 514917#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 442834#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 441707#L651-39 assume !(1 == ~t5_pc~0); 441478#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 441479#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 442818#L663-13 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 442961#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 443024#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 443072#L670-39 assume 1 == ~t6_pc~0; 443073#L671-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 441392#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 441393#L682-13 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 441465#L1439-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 442058#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 442059#L689-39 assume !(1 == ~t7_pc~0); 503244#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 503242#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 503240#L701-13 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 503238#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 503236#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 503234#L708-39 assume 1 == ~t8_pc~0; 503232#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 503229#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 503227#L720-13 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 503224#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 503222#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 503220#L727-39 assume !(1 == ~t9_pc~0); 503218#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 503215#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 503213#L739-13 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 503212#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 503209#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 503207#L746-39 assume !(1 == ~t10_pc~0); 503205#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 503202#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 503200#L758-13 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 503198#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 503195#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 503193#L765-39 assume 1 == ~t11_pc~0; 503191#L766-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 503188#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 503186#L777-13 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 503184#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 503182#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 503180#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 503178#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 503176#L1254-3 assume !(1 == ~T2_E~0); 503174#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 503172#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 503171#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 503169#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 503167#L1279-3 assume !(1 == ~T7_E~0); 503165#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 501934#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 503163#L1294-3 assume !(1 == ~T10_E~0); 503159#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 503157#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 503155#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 503153#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 503150#L1319-3 assume !(1 == ~E_3~0); 503148#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 503146#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 503145#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 501435#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 503142#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 503140#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 503138#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 503136#L1359-3 assume !(1 == ~E_11~0); 503133#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 502928#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 502917#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 502910#L923-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 502901#L1709 assume !(0 == start_simulation_~tmp~3#1); 502893#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 502444#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 502434#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 502432#L923-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 502430#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 502428#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 502426#L1672 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 502382#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 443076#L1690-2 [2021-11-13 18:20:54,768 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:54,768 INFO L85 PathProgramCache]: Analyzing trace with hash -619488965, now seen corresponding path program 1 times [2021-11-13 18:20:54,768 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:54,768 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [126814971] [2021-11-13 18:20:54,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:54,769 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:54,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:54,817 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:54,817 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:54,817 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [126814971] [2021-11-13 18:20:54,818 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [126814971] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:54,818 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:54,818 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:54,818 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1393864001] [2021-11-13 18:20:54,818 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:54,819 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:20:54,819 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:20:54,819 INFO L85 PathProgramCache]: Analyzing trace with hash 1702670595, now seen corresponding path program 1 times [2021-11-13 18:20:54,820 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:20:54,820 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2047764956] [2021-11-13 18:20:54,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:20:54,820 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:20:54,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:20:54,860 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:20:54,860 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:20:54,860 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2047764956] [2021-11-13 18:20:54,860 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2047764956] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:20:54,861 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:20:54,861 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:20:54,861 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [371328155] [2021-11-13 18:20:54,861 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:20:54,862 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:20:54,862 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:20:54,862 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:20:54,863 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:20:54,863 INFO L87 Difference]: Start difference. First operand 75765 states and 107945 transitions. cyclomatic complexity: 32188 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:20:56,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:20:56,485 INFO L93 Difference]: Finished difference Result 182088 states and 257826 transitions. [2021-11-13 18:20:56,485 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:20:56,486 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 182088 states and 257826 transitions. [2021-11-13 18:20:57,081 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 178788 [2021-11-13 18:20:58,072 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 182088 states to 182088 states and 257826 transitions. [2021-11-13 18:20:58,072 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 182088 [2021-11-13 18:20:58,128 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 182088 [2021-11-13 18:20:58,128 INFO L73 IsDeterministic]: Start isDeterministic. Operand 182088 states and 257826 transitions. [2021-11-13 18:20:58,227 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:20:58,227 INFO L681 BuchiCegarLoop]: Abstraction has 182088 states and 257826 transitions. [2021-11-13 18:20:58,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182088 states and 257826 transitions. [2021-11-13 18:20:59,673 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182088 to 144980. [2021-11-13 18:20:59,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 144980 states, 144980 states have (on average 1.420154504069527) internal successors, (205894), 144979 states have internal predecessors, (205894), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:21:00,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144980 states to 144980 states and 205894 transitions. [2021-11-13 18:21:00,049 INFO L704 BuchiCegarLoop]: Abstraction has 144980 states and 205894 transitions. [2021-11-13 18:21:00,049 INFO L587 BuchiCegarLoop]: Abstraction has 144980 states and 205894 transitions. [2021-11-13 18:21:00,049 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-13 18:21:00,049 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 144980 states and 205894 transitions. [2021-11-13 18:21:01,196 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 144624 [2021-11-13 18:21:01,198 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:21:01,198 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:21:01,204 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:21:01,204 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:21:01,205 INFO L791 eck$LassoCheckResult]: Stem: 699855#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 699856#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 700451#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 700452#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 700287#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 700288#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 699280#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 699281#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 700892#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 700258#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 700259#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 700606#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 700607#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 700732#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 700846#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 700847#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 700678#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 700469#L1121 assume !(0 == ~M_E~0); 700185#L1121-2 assume !(0 == ~T1_E~0); 699550#L1126-1 assume !(0 == ~T2_E~0); 699551#L1131-1 assume !(0 == ~T3_E~0); 699719#L1136-1 assume !(0 == ~T4_E~0); 699813#L1141-1 assume !(0 == ~T5_E~0); 700049#L1146-1 assume !(0 == ~T6_E~0); 700386#L1151-1 assume !(0 == ~T7_E~0); 699872#L1156-1 assume !(0 == ~T8_E~0); 699266#L1161-1 assume !(0 == ~T9_E~0); 699267#L1166-1 assume !(0 == ~T10_E~0); 699484#L1171-1 assume !(0 == ~T11_E~0); 699485#L1176-1 assume !(0 == ~E_M~0); 700403#L1181-1 assume !(0 == ~E_1~0); 700560#L1186-1 assume !(0 == ~E_2~0); 700620#L1191-1 assume !(0 == ~E_3~0); 699512#L1196-1 assume !(0 == ~E_4~0); 699513#L1201-1 assume !(0 == ~E_5~0); 700916#L1206-1 assume !(0 == ~E_6~0); 700679#L1211-1 assume !(0 == ~E_7~0); 700680#L1216-1 assume !(0 == ~E_8~0); 699656#L1221-1 assume !(0 == ~E_9~0); 699657#L1226-1 assume !(0 == ~E_10~0); 699361#L1231-1 assume !(0 == ~E_11~0); 699362#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 700405#L556 assume !(1 == ~m_pc~0); 700406#L556-2 is_master_triggered_~__retres1~0#1 := 0; 699240#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 699241#L568 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 700135#L1391 assume !(0 != activate_threads_~tmp~1#1); 700593#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 700594#L575 assume !(1 == ~t1_pc~0); 699192#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 699193#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 699324#L587 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 699666#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 699623#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 699624#L594 assume !(1 == ~t2_pc~0); 700372#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 700484#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 700029#L606 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 699257#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 699258#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 699314#L613 assume !(1 == ~t3_pc~0); 699428#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 699427#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 699357#L625 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 699358#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 700043#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 699754#L632 assume !(1 == ~t4_pc~0); 699755#L632-2 is_transmit4_triggered_~__retres1~4#1 := 0; 700470#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 700471#L644 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 700917#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 700411#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 700117#L651 assume !(1 == ~t5_pc~0); 700118#L651-2 is_transmit5_triggered_~__retres1~5#1 := 0; 699441#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 699442#L663 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 699884#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 699457#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 699458#L670 assume !(1 == ~t6_pc~0); 700652#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 699804#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 699805#L682 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 700893#L1439 assume !(0 != activate_threads_~tmp___5~0#1); 700086#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 700087#L689 assume !(1 == ~t7_pc~0); 700332#L689-2 is_transmit7_triggered_~__retres1~7#1 := 0; 700204#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 700205#L701 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 700675#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 699980#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 699981#L708 assume !(1 == ~t8_pc~0); 699545#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 699546#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 700789#L720 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 700773#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 699607#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 699608#L727 assume !(1 == ~t9_pc~0); 699315#L727-2 is_transmit9_triggered_~__retres1~9#1 := 0; 699316#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 700928#L739 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 700929#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 700898#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 699663#L746 assume !(1 == ~t10_pc~0); 699664#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 700354#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 700491#L758 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 700782#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 700596#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 699825#L765 assume 1 == ~t11_pc~0; 699826#L766 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 700039#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 699205#L777 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 699206#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 700650#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 700770#L1249 assume !(1 == ~M_E~0); 700280#L1249-2 assume !(1 == ~T1_E~0); 699904#L1254-1 assume !(1 == ~T2_E~0); 699251#L1259-1 assume !(1 == ~T3_E~0); 699233#L1264-1 assume !(1 == ~T4_E~0); 699234#L1269-1 assume !(1 == ~T5_E~0); 701000#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 700860#L1279-1 assume !(1 == ~T7_E~0); 699429#L1284-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 699430#L1289-1 assume !(1 == ~T9_E~0); 699958#L1294-1 assume !(1 == ~T10_E~0); 699959#L1299-1 assume !(1 == ~T11_E~0); 700968#L1304-1 assume !(1 == ~E_M~0); 700969#L1309-1 assume !(1 == ~E_1~0); 700973#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 700974#L1319-1 assume !(1 == ~E_3~0); 700519#L1324-1 assume !(1 == ~E_4~0); 700520#L1329-1 assume !(1 == ~E_5~0); 700712#L1334-1 assume !(1 == ~E_6~0); 700713#L1339-1 assume !(1 == ~E_7~0); 700814#L1344-1 assume !(1 == ~E_8~0); 700815#L1349-1 assume !(1 == ~E_9~0); 700099#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 700100#L1359-1 assume !(1 == ~E_11~0); 700935#L1364-1 assume { :end_inline_reset_delta_events } true; 699593#L1690-2 [2021-11-13 18:21:01,206 INFO L793 eck$LassoCheckResult]: Loop: 699593#L1690-2 assume !false; 699594#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 699481#L1096 assume !false; 700537#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 699334#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 699335#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 700404#L923 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 699820#L937 assume !(0 != eval_~tmp~0#1); 699821#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 843380#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 843378#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 843376#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 843374#L1126-3 assume !(0 == ~T2_E~0); 843372#L1131-3 assume !(0 == ~T3_E~0); 843370#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 843368#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 843366#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 843364#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 843362#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 843360#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 843358#L1166-3 assume !(0 == ~T10_E~0); 843355#L1171-3 assume !(0 == ~T11_E~0); 843353#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 843351#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 843349#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 843347#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 843345#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 843344#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 843342#L1206-3 assume !(0 == ~E_6~0); 843340#L1211-3 assume !(0 == ~E_7~0); 843338#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 843336#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 843334#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 843331#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 843329#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 843327#L556-39 assume !(1 == ~m_pc~0); 843325#L556-41 is_master_triggered_~__retres1~0#1 := 0; 843323#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 843321#L568-13 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 843319#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 843317#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 843315#L575-39 assume 1 == ~t1_pc~0; 843312#L576-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 843310#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 843309#L587-13 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 843308#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 843307#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 843306#L594-39 assume !(1 == ~t2_pc~0); 842252#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 843305#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 843304#L606-13 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 843303#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 843302#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 843301#L613-39 assume !(1 == ~t3_pc~0); 843300#L613-41 is_transmit3_triggered_~__retres1~3#1 := 0; 843298#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 843297#L625-13 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 843296#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 843295#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 843294#L632-39 assume !(1 == ~t4_pc~0); 843293#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 843292#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 843291#L644-13 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 843290#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 843289#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 841453#L651-39 assume !(1 == ~t5_pc~0); 841452#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 841451#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 841449#L663-13 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 841448#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 841235#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 841234#L670-39 assume !(1 == ~t6_pc~0); 841232#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 841230#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 841228#L682-13 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 841227#L1439-39 assume !(0 != activate_threads_~tmp___5~0#1); 841225#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 700144#L689-39 assume !(1 == ~t7_pc~0); 700044#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 700045#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 699571#L701-13 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 699572#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 699445#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 699446#L708-39 assume !(1 == ~t8_pc~0); 699387#L708-41 is_transmit8_triggered_~__retres1~8#1 := 0; 699386#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 699488#L720-13 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 699489#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 700423#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 699858#L727-39 assume !(1 == ~t9_pc~0); 699859#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 699638#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 699639#L739-13 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 700717#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 700478#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 700479#L746-39 assume !(1 == ~t10_pc~0); 700447#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 700446#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 700806#L758-13 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 700129#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 700130#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 700640#L765-39 assume !(1 == ~t11_pc~0); 699262#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 699263#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 700501#L777-13 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 699591#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 699592#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 700178#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 699403#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 699404#L1254-3 assume !(1 == ~T2_E~0); 700809#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 700315#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 699365#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 699366#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 700854#L1279-3 assume !(1 == ~T7_E~0); 699835#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 699836#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 699830#L1294-3 assume !(1 == ~T10_E~0); 699831#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 700093#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 700094#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 699751#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 699752#L1319-3 assume !(1 == ~E_3~0); 700589#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 699469#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 699470#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 700027#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 700028#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 700257#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 699729#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 699730#L1359-3 assume !(1 == ~E_11~0); 700273#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 699326#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 699327#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 699948#L923-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 699949#L1709 assume !(0 == start_simulation_~tmp~3#1); 699758#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 700615#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 699437#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 699934#L923-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 699400#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 699401#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 700235#L1672 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 700727#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 699593#L1690-2 [2021-11-13 18:21:01,206 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:21:01,206 INFO L85 PathProgramCache]: Analyzing trace with hash 1279041340, now seen corresponding path program 1 times [2021-11-13 18:21:01,207 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:21:01,207 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1094004528] [2021-11-13 18:21:01,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:21:01,208 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:21:01,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:21:01,264 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:21:01,264 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:21:01,265 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1094004528] [2021-11-13 18:21:01,266 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1094004528] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:21:01,266 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:21:01,266 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:21:01,266 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [879763103] [2021-11-13 18:21:01,268 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:21:01,268 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:21:01,269 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:21:01,269 INFO L85 PathProgramCache]: Analyzing trace with hash -341252729, now seen corresponding path program 1 times [2021-11-13 18:21:01,269 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:21:01,269 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1208001801] [2021-11-13 18:21:01,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:21:01,270 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:21:01,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:21:01,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:21:01,321 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:21:01,321 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1208001801] [2021-11-13 18:21:01,322 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1208001801] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:21:01,322 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:21:01,322 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:21:01,322 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1505612620] [2021-11-13 18:21:01,322 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:21:01,323 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:21:01,323 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:21:01,323 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 18:21:01,323 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 18:21:01,324 INFO L87 Difference]: Start difference. First operand 144980 states and 205894 transitions. cyclomatic complexity: 60922 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:21:02,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:21:02,661 INFO L93 Difference]: Finished difference Result 346451 states and 489059 transitions. [2021-11-13 18:21:02,661 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 18:21:02,661 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 346451 states and 489059 transitions. [2021-11-13 18:21:04,691 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 340048 [2021-11-13 18:21:06,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 346451 states to 346451 states and 489059 transitions. [2021-11-13 18:21:06,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 346451 [2021-11-13 18:21:06,200 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 346451 [2021-11-13 18:21:06,200 INFO L73 IsDeterministic]: Start isDeterministic. Operand 346451 states and 489059 transitions. [2021-11-13 18:21:06,312 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:21:06,313 INFO L681 BuchiCegarLoop]: Abstraction has 346451 states and 489059 transitions. [2021-11-13 18:21:06,455 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 346451 states and 489059 transitions. [2021-11-13 18:21:09,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 346451 to 277155. [2021-11-13 18:21:09,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 277155 states, 277155 states have (on average 1.415940538687738) internal successors, (392435), 277154 states have internal predecessors, (392435), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:21:10,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 277155 states to 277155 states and 392435 transitions. [2021-11-13 18:21:10,160 INFO L704 BuchiCegarLoop]: Abstraction has 277155 states and 392435 transitions. [2021-11-13 18:21:10,160 INFO L587 BuchiCegarLoop]: Abstraction has 277155 states and 392435 transitions. [2021-11-13 18:21:10,161 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-11-13 18:21:10,161 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 277155 states and 392435 transitions. [2021-11-13 18:21:11,970 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 276608 [2021-11-13 18:21:11,971 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 18:21:11,971 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 18:21:11,985 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:21:11,986 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 18:21:11,987 INFO L791 eck$LassoCheckResult]: Stem: 1191304#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 1191305#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1191914#L1653 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1191915#L785 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1191746#L792 assume 1 == ~m_i~0;~m_st~0 := 0; 1191747#L792-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1190720#L797-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1190721#L802-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1192359#L807-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1191715#L812-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1191716#L817-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1192071#L822-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1192072#L827-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1192191#L832-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1192300#L837-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1192301#L842-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1192142#L847-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1191932#L1121 assume !(0 == ~M_E~0); 1191643#L1121-2 assume !(0 == ~T1_E~0); 1190989#L1126-1 assume !(0 == ~T2_E~0); 1190990#L1131-1 assume !(0 == ~T3_E~0); 1191160#L1136-1 assume !(0 == ~T4_E~0); 1191262#L1141-1 assume !(0 == ~T5_E~0); 1191504#L1146-1 assume !(0 == ~T6_E~0); 1191843#L1151-1 assume !(0 == ~T7_E~0); 1191321#L1156-1 assume !(0 == ~T8_E~0); 1190707#L1161-1 assume !(0 == ~T9_E~0); 1190708#L1166-1 assume !(0 == ~T10_E~0); 1190924#L1171-1 assume !(0 == ~T11_E~0); 1190925#L1176-1 assume !(0 == ~E_M~0); 1191862#L1181-1 assume !(0 == ~E_1~0); 1192025#L1186-1 assume !(0 == ~E_2~0); 1192089#L1191-1 assume !(0 == ~E_3~0); 1190952#L1196-1 assume !(0 == ~E_4~0); 1190953#L1201-1 assume !(0 == ~E_5~0); 1192383#L1206-1 assume !(0 == ~E_6~0); 1192143#L1211-1 assume !(0 == ~E_7~0); 1192144#L1216-1 assume !(0 == ~E_8~0); 1191092#L1221-1 assume !(0 == ~E_9~0); 1191093#L1226-1 assume !(0 == ~E_10~0); 1190800#L1231-1 assume !(0 == ~E_11~0); 1190801#L1236-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1191864#L556 assume !(1 == ~m_pc~0); 1191865#L556-2 is_master_triggered_~__retres1~0#1 := 0; 1190681#L567 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1190682#L568 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1191588#L1391 assume !(0 != activate_threads_~tmp~1#1); 1192060#L1391-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1192061#L575 assume !(1 == ~t1_pc~0); 1190633#L575-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1190634#L586 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1190763#L587 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1191106#L1399 assume !(0 != activate_threads_~tmp___0~0#1); 1191062#L1399-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1191063#L594 assume !(1 == ~t2_pc~0); 1191833#L594-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1191947#L605 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1191483#L606 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1190698#L1407 assume !(0 != activate_threads_~tmp___1~0#1); 1190699#L1407-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1190753#L613 assume !(1 == ~t3_pc~0); 1190867#L613-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1190866#L624 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1190796#L625 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1190797#L1415 assume !(0 != activate_threads_~tmp___2~0#1); 1191498#L1415-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1191201#L632 assume !(1 == ~t4_pc~0); 1191202#L632-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1191933#L643 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1191934#L644 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1192384#L1423 assume !(0 != activate_threads_~tmp___3~0#1); 1191871#L1423-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1191570#L651 assume !(1 == ~t5_pc~0); 1191571#L651-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1190880#L662 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1190881#L663 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1191334#L1431 assume !(0 != activate_threads_~tmp___4~0#1); 1190897#L1431-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1190898#L670 assume !(1 == ~t6_pc~0); 1192120#L670-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1191253#L681 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1191254#L682 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1192360#L1439 assume !(0 != activate_threads_~tmp___5~0#1); 1191537#L1439-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1191538#L689 assume !(1 == ~t7_pc~0); 1191793#L689-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1191661#L700 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1191662#L701 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1192140#L1447 assume !(0 != activate_threads_~tmp___6~0#1); 1191437#L1447-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1191438#L708 assume !(1 == ~t8_pc~0); 1190984#L708-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1190985#L719 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1192243#L720 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1192226#L1455 assume !(0 != activate_threads_~tmp___7~0#1); 1191046#L1455-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1191047#L727 assume !(1 == ~t9_pc~0); 1190754#L727-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1190755#L738 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1192395#L739 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1192396#L1463 assume !(0 != activate_threads_~tmp___8~0#1); 1192361#L1463-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1191103#L746 assume !(1 == ~t10_pc~0); 1191104#L746-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1191810#L757 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1191954#L758 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1192236#L1471 assume !(0 != activate_threads_~tmp___9~0#1); 1192064#L1471-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1191274#L765 assume !(1 == ~t11_pc~0); 1191275#L765-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1191493#L776 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1190646#L777 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1190647#L1479 assume !(0 != activate_threads_~tmp___10~0#1); 1192118#L1479-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1192223#L1249 assume !(1 == ~M_E~0); 1191736#L1249-2 assume !(1 == ~T1_E~0); 1191356#L1254-1 assume !(1 == ~T2_E~0); 1190692#L1259-1 assume !(1 == ~T3_E~0); 1190674#L1264-1 assume !(1 == ~T4_E~0); 1190675#L1269-1 assume !(1 == ~T5_E~0); 1192469#L1274-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1192324#L1279-1 assume !(1 == ~T7_E~0); 1190868#L1284-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1190869#L1289-1 assume !(1 == ~T9_E~0); 1192397#L1294-1 assume !(1 == ~T10_E~0); 1191423#L1299-1 assume !(1 == ~T11_E~0); 1191424#L1304-1 assume !(1 == ~E_M~0); 1192456#L1309-1 assume !(1 == ~E_1~0); 1192457#L1314-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1190818#L1319-1 assume !(1 == ~E_3~0); 1190819#L1324-1 assume !(1 == ~E_4~0); 1190947#L1329-1 assume !(1 == ~E_5~0); 1190948#L1334-1 assume !(1 == ~E_6~0); 1192173#L1339-1 assume !(1 == ~E_7~0); 1192418#L1344-1 assume !(1 == ~E_8~0); 1192480#L1349-1 assume !(1 == ~E_9~0); 1192481#L1354-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1191988#L1359-1 assume !(1 == ~E_11~0); 1191989#L1364-1 assume { :end_inline_reset_delta_events } true; 1415753#L1690-2 [2021-11-13 18:21:11,990 INFO L793 eck$LassoCheckResult]: Loop: 1415753#L1690-2 assume !false; 1415749#L1691 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet21#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1415745#L1096 assume !false; 1415743#L933 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1415669#L860 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1415659#L922 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1415652#L923 eval_#t~ret9#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1; 1415642#L937 assume !(0 != eval_~tmp~0#1); 1415643#L1111 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1467661#L785-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1467660#L1121-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1467659#L1121-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1467639#L1126-3 assume !(0 == ~T2_E~0); 1467623#L1131-3 assume !(0 == ~T3_E~0); 1467621#L1136-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1467608#L1141-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1467604#L1146-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1467588#L1151-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1192266#L1156-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1192267#L1161-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1191644#L1166-3 assume !(0 == ~T10_E~0); 1191645#L1171-3 assume !(0 == ~T11_E~0); 1191691#L1176-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1191028#L1181-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1191029#L1186-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1191787#L1191-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1191788#L1196-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1192038#L1201-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1192039#L1206-3 assume !(0 == ~E_6~0); 1192437#L1211-3 assume !(0 == ~E_7~0); 1467232#L1216-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1191368#L1221-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1191369#L1226-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1190997#L1231-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1190998#L1236-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1191229#L556-39 assume !(1 == ~m_pc~0); 1192219#L556-41 is_master_triggered_~__retres1~0#1 := 0; 1191755#L567-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1191099#L568-13 activate_threads_#t~ret22#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1191100#L1391-39 assume !(0 != activate_threads_~tmp~1#1); 1191280#L1391-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1191704#L575-39 assume !(1 == ~t1_pc~0); 1191706#L575-41 is_transmit1_triggered_~__retres1~1#1 := 0; 1192046#L586-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1191867#L587-13 activate_threads_#t~ret23#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1191868#L1399-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1191678#L1399-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1191679#L594-39 assume !(1 == ~t2_pc~0); 1191939#L594-41 is_transmit2_triggered_~__retres1~2#1 := 0; 1191680#L605-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1191681#L606-13 activate_threads_#t~ret24#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1192228#L1407-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1191161#L1407-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1191162#L613-39 assume 1 == ~t3_pc~0; 1192198#L614-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1190652#L624-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1190653#L625-13 activate_threads_#t~ret25#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1191418#L1415-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1190749#L1415-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1190750#L632-39 assume !(1 == ~t4_pc~0); 1192464#L632-41 is_transmit4_triggered_~__retres1~4#1 := 0; 1466980#L643-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1466978#L644-13 activate_threads_#t~ret26#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1466976#L1423-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1466973#L1423-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1421126#L651-39 assume !(1 == ~t5_pc~0); 1421124#L651-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1421122#L662-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1421120#L663-13 activate_threads_#t~ret27#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1421119#L1431-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1421117#L1431-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1421112#L670-39 assume !(1 == ~t6_pc~0); 1421110#L670-41 is_transmit6_triggered_~__retres1~6#1 := 0; 1421106#L681-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1421104#L682-13 activate_threads_#t~ret28#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1421102#L1439-39 assume !(0 != activate_threads_~tmp___5~0#1); 1421099#L1439-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1416041#L689-39 assume !(1 == ~t7_pc~0); 1416039#L689-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1416037#L700-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1416035#L701-13 activate_threads_#t~ret29#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1416033#L1447-39 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1416031#L1447-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1416029#L708-39 assume 1 == ~t8_pc~0; 1416027#L709-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1416024#L719-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1416022#L720-13 activate_threads_#t~ret30#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1416021#L1455-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1416020#L1455-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1416019#L727-39 assume !(1 == ~t9_pc~0); 1411402#L727-41 is_transmit9_triggered_~__retres1~9#1 := 0; 1416017#L738-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1416015#L739-13 activate_threads_#t~ret31#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1416013#L1463-39 assume !(0 != activate_threads_~tmp___8~0#1); 1416011#L1463-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1416009#L746-39 assume !(1 == ~t10_pc~0); 1416007#L746-41 is_transmit10_triggered_~__retres1~10#1 := 0; 1416004#L757-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1416001#L758-13 activate_threads_#t~ret32#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1415999#L1471-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1415997#L1471-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1415995#L765-39 assume !(1 == ~t11_pc~0); 1243920#L765-41 is_transmit11_triggered_~__retres1~11#1 := 0; 1415992#L776-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1415991#L777-13 activate_threads_#t~ret33#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1415989#L1479-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1415987#L1479-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1415985#L1249-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1415983#L1249-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1415981#L1254-3 assume !(1 == ~T2_E~0); 1415978#L1259-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1415976#L1264-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1415974#L1269-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1415972#L1274-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1415970#L1279-3 assume !(1 == ~T7_E~0); 1415968#L1284-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1415965#L1289-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1415963#L1294-3 assume !(1 == ~T10_E~0); 1415961#L1299-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1415959#L1304-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1415957#L1309-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1415956#L1314-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1415952#L1319-3 assume !(1 == ~E_3~0); 1415950#L1324-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1415948#L1329-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1415944#L1334-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1415941#L1339-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1415940#L1344-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1415939#L1349-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1415938#L1354-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1415937#L1359-3 assume !(1 == ~E_11~0); 1415936#L1364-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1415926#L860-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1415923#L922-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1415922#L923-1 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1415786#L1709 assume !(0 == start_simulation_~tmp~3#1); 1415784#L1709-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1415775#L860-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1415764#L922-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1415762#L923-2 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 1415760#L1664 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1415758#L1671 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1415757#L1672 start_simulation_#t~ret36#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1415755#L1722 assume !(0 != start_simulation_~tmp___0~1#1); 1415753#L1690-2 [2021-11-13 18:21:11,991 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:21:11,991 INFO L85 PathProgramCache]: Analyzing trace with hash -492429635, now seen corresponding path program 1 times [2021-11-13 18:21:11,992 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:21:11,992 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [549068147] [2021-11-13 18:21:11,992 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:21:11,992 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:21:12,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:21:12,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:21:12,038 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:21:12,038 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [549068147] [2021-11-13 18:21:12,039 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [549068147] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:21:12,039 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:21:12,039 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 18:21:12,039 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [601751807] [2021-11-13 18:21:12,039 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:21:12,040 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 18:21:12,040 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 18:21:12,040 INFO L85 PathProgramCache]: Analyzing trace with hash 2106442822, now seen corresponding path program 1 times [2021-11-13 18:21:12,040 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 18:21:12,041 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1389341198] [2021-11-13 18:21:12,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 18:21:12,041 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 18:21:12,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 18:21:12,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 18:21:12,075 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 18:21:12,075 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1389341198] [2021-11-13 18:21:12,075 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1389341198] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 18:21:12,076 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 18:21:12,076 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 18:21:12,076 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1670296752] [2021-11-13 18:21:12,076 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 18:21:12,076 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 18:21:12,077 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 18:21:12,077 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 18:21:12,077 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 18:21:12,077 INFO L87 Difference]: Start difference. First operand 277155 states and 392435 transitions. cyclomatic complexity: 115288 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 18:21:13,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 18:21:13,709 INFO L93 Difference]: Finished difference Result 277155 states and 391665 transitions. [2021-11-13 18:21:13,710 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 18:21:13,710 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 277155 states and 391665 transitions. [2021-11-13 18:21:14,813 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 276608 [2021-11-13 18:21:16,299 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 277155 states to 277155 states and 391665 transitions. [2021-11-13 18:21:16,299 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 277155 [2021-11-13 18:21:16,386 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 277155 [2021-11-13 18:21:16,386 INFO L73 IsDeterministic]: Start isDeterministic. Operand 277155 states and 391665 transitions. [2021-11-13 18:21:16,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 18:21:16,498 INFO L681 BuchiCegarLoop]: Abstraction has 277155 states and 391665 transitions. [2021-11-13 18:21:16,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 277155 states and 391665 transitions. [2021-11-13 18:21:19,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 277155 to 277155.