./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.11.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 63182f13 Calling Ultimate with: /usr/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfaaa571-b59a-47b7-8d6b-5b3c512cf598/bin/uautomizer-YU5uOKAj3y/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfaaa571-b59a-47b7-8d6b-5b3c512cf598/bin/uautomizer-YU5uOKAj3y/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfaaa571-b59a-47b7-8d6b-5b3c512cf598/bin/uautomizer-YU5uOKAj3y/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfaaa571-b59a-47b7-8d6b-5b3c512cf598/bin/uautomizer-YU5uOKAj3y/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.11.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfaaa571-b59a-47b7-8d6b-5b3c512cf598/bin/uautomizer-YU5uOKAj3y/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfaaa571-b59a-47b7-8d6b-5b3c512cf598/bin/uautomizer-YU5uOKAj3y --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c5f603027c62ff37561a520351662dbe2fd253b52e04e36028cb9a624978ef8e --- Real Ultimate output --- This is Ultimate 0.2.1-dev-63182f1 [2021-11-13 17:45:45,889 INFO L177 SettingsManager]: Resetting all preferences to default values... [2021-11-13 17:45:45,891 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2021-11-13 17:45:45,942 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2021-11-13 17:45:45,943 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2021-11-13 17:45:45,947 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2021-11-13 17:45:45,951 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2021-11-13 17:45:45,955 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2021-11-13 17:45:45,958 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2021-11-13 17:45:45,966 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2021-11-13 17:45:45,967 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2021-11-13 17:45:45,969 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2021-11-13 17:45:45,969 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2021-11-13 17:45:45,972 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2021-11-13 17:45:45,977 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2021-11-13 17:45:45,980 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2021-11-13 17:45:45,981 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2021-11-13 17:45:45,982 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2021-11-13 17:45:45,988 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2021-11-13 17:45:45,998 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2021-11-13 17:45:46,000 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2021-11-13 17:45:46,002 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2021-11-13 17:45:46,003 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2021-11-13 17:45:46,004 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2021-11-13 17:45:46,007 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2021-11-13 17:45:46,008 INFO L184 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2021-11-13 17:45:46,008 INFO L181 SettingsManager]: Resetting TreeAutomizer preferences to default values [2021-11-13 17:45:46,009 INFO L181 SettingsManager]: Resetting IcfgToChc preferences to default values [2021-11-13 17:45:46,010 INFO L181 SettingsManager]: Resetting IcfgTransformer preferences to default values [2021-11-13 17:45:46,011 INFO L184 SettingsManager]: ReqToTest provides no preferences, ignoring... [2021-11-13 17:45:46,011 INFO L181 SettingsManager]: Resetting Boogie Printer preferences to default values [2021-11-13 17:45:46,012 INFO L181 SettingsManager]: Resetting ChcSmtPrinter preferences to default values [2021-11-13 17:45:46,013 INFO L181 SettingsManager]: Resetting ReqPrinter preferences to default values [2021-11-13 17:45:46,014 INFO L181 SettingsManager]: Resetting Witness Printer preferences to default values [2021-11-13 17:45:46,015 INFO L184 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2021-11-13 17:45:46,016 INFO L181 SettingsManager]: Resetting CDTParser preferences to default values [2021-11-13 17:45:46,016 INFO L184 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2021-11-13 17:45:46,017 INFO L184 SettingsManager]: ReqParser provides no preferences, ignoring... [2021-11-13 17:45:46,017 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2021-11-13 17:45:46,018 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2021-11-13 17:45:46,018 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2021-11-13 17:45:46,019 INFO L101 SettingsManager]: Beginning loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfaaa571-b59a-47b7-8d6b-5b3c512cf598/bin/uautomizer-YU5uOKAj3y/config/svcomp-Termination-32bit-Automizer_Default.epf [2021-11-13 17:45:46,047 INFO L113 SettingsManager]: Loading preferences was successful [2021-11-13 17:45:46,047 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2021-11-13 17:45:46,048 INFO L136 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2021-11-13 17:45:46,048 INFO L138 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2021-11-13 17:45:46,049 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2021-11-13 17:45:46,050 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2021-11-13 17:45:46,050 INFO L138 SettingsManager]: * Use SBE=true [2021-11-13 17:45:46,050 INFO L136 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2021-11-13 17:45:46,050 INFO L138 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2021-11-13 17:45:46,051 INFO L138 SettingsManager]: * Use old map elimination=false [2021-11-13 17:45:46,051 INFO L138 SettingsManager]: * Use external solver (rank synthesis)=false [2021-11-13 17:45:46,051 INFO L138 SettingsManager]: * Use only trivial implications for array writes=true [2021-11-13 17:45:46,051 INFO L138 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2021-11-13 17:45:46,052 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2021-11-13 17:45:46,052 INFO L138 SettingsManager]: * sizeof long=4 [2021-11-13 17:45:46,052 INFO L138 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2021-11-13 17:45:46,052 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2021-11-13 17:45:46,052 INFO L138 SettingsManager]: * sizeof POINTER=4 [2021-11-13 17:45:46,053 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2021-11-13 17:45:46,053 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2021-11-13 17:45:46,053 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2021-11-13 17:45:46,053 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2021-11-13 17:45:46,054 INFO L138 SettingsManager]: * sizeof long double=12 [2021-11-13 17:45:46,054 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2021-11-13 17:45:46,054 INFO L138 SettingsManager]: * Assume nondeterminstic values are in range=false [2021-11-13 17:45:46,054 INFO L138 SettingsManager]: * Use constant arrays=true [2021-11-13 17:45:46,055 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2021-11-13 17:45:46,055 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2021-11-13 17:45:46,055 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2021-11-13 17:45:46,055 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2021-11-13 17:45:46,056 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2021-11-13 17:45:46,056 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2021-11-13 17:45:46,057 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2021-11-13 17:45:46,057 INFO L138 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfaaa571-b59a-47b7-8d6b-5b3c512cf598/bin/uautomizer-YU5uOKAj3y/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfaaa571-b59a-47b7-8d6b-5b3c512cf598/bin/uautomizer-YU5uOKAj3y Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c5f603027c62ff37561a520351662dbe2fd253b52e04e36028cb9a624978ef8e [2021-11-13 17:45:46,335 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2021-11-13 17:45:46,366 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2021-11-13 17:45:46,369 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2021-11-13 17:45:46,370 INFO L271 PluginConnector]: Initializing CDTParser... [2021-11-13 17:45:46,372 INFO L275 PluginConnector]: CDTParser initialized [2021-11-13 17:45:46,373 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfaaa571-b59a-47b7-8d6b-5b3c512cf598/bin/uautomizer-YU5uOKAj3y/../../sv-benchmarks/c/systemc/token_ring.11.cil-2.c [2021-11-13 17:45:46,450 INFO L220 CDTParser]: Created temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfaaa571-b59a-47b7-8d6b-5b3c512cf598/bin/uautomizer-YU5uOKAj3y/data/245f8b9a8/1af002e5976b404ebdfd4cff3741e4bb/FLAG3f594a0dc [2021-11-13 17:45:47,001 INFO L306 CDTParser]: Found 1 translation units. [2021-11-13 17:45:47,002 INFO L160 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfaaa571-b59a-47b7-8d6b-5b3c512cf598/sv-benchmarks/c/systemc/token_ring.11.cil-2.c [2021-11-13 17:45:47,019 INFO L349 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfaaa571-b59a-47b7-8d6b-5b3c512cf598/bin/uautomizer-YU5uOKAj3y/data/245f8b9a8/1af002e5976b404ebdfd4cff3741e4bb/FLAG3f594a0dc [2021-11-13 17:45:47,318 INFO L357 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfaaa571-b59a-47b7-8d6b-5b3c512cf598/bin/uautomizer-YU5uOKAj3y/data/245f8b9a8/1af002e5976b404ebdfd4cff3741e4bb [2021-11-13 17:45:47,320 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2021-11-13 17:45:47,322 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2021-11-13 17:45:47,323 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2021-11-13 17:45:47,324 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2021-11-13 17:45:47,335 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2021-11-13 17:45:47,336 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 05:45:47" (1/1) ... [2021-11-13 17:45:47,337 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@24b6edec and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:45:47, skipping insertion in model container [2021-11-13 17:45:47,337 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 13.11 05:45:47" (1/1) ... [2021-11-13 17:45:47,345 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2021-11-13 17:45:47,400 INFO L178 MainTranslator]: Built tables and reachable declarations [2021-11-13 17:45:47,573 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfaaa571-b59a-47b7-8d6b-5b3c512cf598/sv-benchmarks/c/systemc/token_ring.11.cil-2.c[671,684] [2021-11-13 17:45:47,718 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-13 17:45:47,729 INFO L203 MainTranslator]: Completed pre-run [2021-11-13 17:45:47,741 WARN L228 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfaaa571-b59a-47b7-8d6b-5b3c512cf598/sv-benchmarks/c/systemc/token_ring.11.cil-2.c[671,684] [2021-11-13 17:45:47,819 INFO L206 PostProcessor]: Analyzing one entry point: main [2021-11-13 17:45:47,851 INFO L208 MainTranslator]: Completed translation [2021-11-13 17:45:47,852 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:45:47 WrapperNode [2021-11-13 17:45:47,853 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2021-11-13 17:45:47,854 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2021-11-13 17:45:47,855 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2021-11-13 17:45:47,855 INFO L275 PluginConnector]: Boogie Procedure Inliner initialized [2021-11-13 17:45:47,864 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:45:47" (1/1) ... [2021-11-13 17:45:47,898 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:45:47" (1/1) ... [2021-11-13 17:45:48,022 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2021-11-13 17:45:48,023 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2021-11-13 17:45:48,024 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2021-11-13 17:45:48,024 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2021-11-13 17:45:48,033 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:45:47" (1/1) ... [2021-11-13 17:45:48,033 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:45:47" (1/1) ... [2021-11-13 17:45:48,044 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:45:47" (1/1) ... [2021-11-13 17:45:48,045 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:45:47" (1/1) ... [2021-11-13 17:45:48,109 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:45:47" (1/1) ... [2021-11-13 17:45:48,196 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:45:47" (1/1) ... [2021-11-13 17:45:48,202 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:45:47" (1/1) ... [2021-11-13 17:45:48,224 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2021-11-13 17:45:48,225 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2021-11-13 17:45:48,225 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2021-11-13 17:45:48,226 INFO L275 PluginConnector]: RCFGBuilder initialized [2021-11-13 17:45:48,228 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:45:47" (1/1) ... [2021-11-13 17:45:48,237 INFO L168 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2021-11-13 17:45:48,253 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfaaa571-b59a-47b7-8d6b-5b3c512cf598/bin/uautomizer-YU5uOKAj3y/z3 [2021-11-13 17:45:48,272 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfaaa571-b59a-47b7-8d6b-5b3c512cf598/bin/uautomizer-YU5uOKAj3y/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2021-11-13 17:45:48,293 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bfaaa571-b59a-47b7-8d6b-5b3c512cf598/bin/uautomizer-YU5uOKAj3y/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2021-11-13 17:45:48,327 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2021-11-13 17:45:48,327 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2021-11-13 17:45:48,327 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2021-11-13 17:45:48,328 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2021-11-13 17:45:50,510 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2021-11-13 17:45:50,510 INFO L299 CfgBuilder]: Removed 14 assume(true) statements. [2021-11-13 17:45:50,515 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 05:45:50 BoogieIcfgContainer [2021-11-13 17:45:50,515 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2021-11-13 17:45:50,516 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2021-11-13 17:45:50,517 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2021-11-13 17:45:50,520 INFO L275 PluginConnector]: BuchiAutomizer initialized [2021-11-13 17:45:50,521 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-13 17:45:50,521 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 13.11 05:45:47" (1/3) ... [2021-11-13 17:45:50,522 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@74a3843c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 05:45:50, skipping insertion in model container [2021-11-13 17:45:50,522 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-13 17:45:50,523 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 13.11 05:45:47" (2/3) ... [2021-11-13 17:45:50,523 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@74a3843c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 13.11 05:45:50, skipping insertion in model container [2021-11-13 17:45:50,523 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2021-11-13 17:45:50,523 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 13.11 05:45:50" (3/3) ... [2021-11-13 17:45:50,525 INFO L388 chiAutomizerObserver]: Analyzing ICFG token_ring.11.cil-2.c [2021-11-13 17:45:50,582 INFO L359 BuchiCegarLoop]: Interprodecural is true [2021-11-13 17:45:50,582 INFO L360 BuchiCegarLoop]: Hoare is false [2021-11-13 17:45:50,582 INFO L361 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2021-11-13 17:45:50,582 INFO L362 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2021-11-13 17:45:50,583 INFO L363 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2021-11-13 17:45:50,583 INFO L364 BuchiCegarLoop]: Difference is false [2021-11-13 17:45:50,583 INFO L365 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2021-11-13 17:45:50,583 INFO L368 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2021-11-13 17:45:50,635 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1572 states, 1571 states have (on average 1.5022278803309994) internal successors, (2360), 1571 states have internal predecessors, (2360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:50,730 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1417 [2021-11-13 17:45:50,730 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:45:50,731 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:45:50,750 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:50,750 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:50,750 INFO L425 BuchiCegarLoop]: ======== Iteration 1============ [2021-11-13 17:45:50,756 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1572 states, 1571 states have (on average 1.5022278803309994) internal successors, (2360), 1571 states have internal predecessors, (2360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:50,783 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1417 [2021-11-13 17:45:50,783 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:45:50,783 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:45:50,798 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:50,798 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:50,806 INFO L791 eck$LassoCheckResult]: Stem: 395#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 1507#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1131#L1641true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1514#L773true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 114#L780true assume !(1 == ~m_i~0);~m_st~0 := 2; 1152#L780-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1400#L785-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1084#L790-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1398#L795-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 303#L800-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 572#L805-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1095#L810-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1031#L815-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 255#L820-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 727#L825-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 195#L830-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 928#L835-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1453#L1109true assume !(0 == ~M_E~0); 963#L1109-2true assume !(0 == ~T1_E~0); 199#L1114-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 1523#L1119-1true assume !(0 == ~T3_E~0); 1036#L1124-1true assume !(0 == ~T4_E~0); 27#L1129-1true assume !(0 == ~T5_E~0); 350#L1134-1true assume !(0 == ~T6_E~0); 945#L1139-1true assume !(0 == ~T7_E~0); 1021#L1144-1true assume !(0 == ~T8_E~0); 784#L1149-1true assume !(0 == ~T9_E~0); 75#L1154-1true assume 0 == ~T10_E~0;~T10_E~0 := 1; 920#L1159-1true assume !(0 == ~T11_E~0); 769#L1164-1true assume !(0 == ~E_M~0); 282#L1169-1true assume !(0 == ~E_1~0); 224#L1174-1true assume !(0 == ~E_2~0); 155#L1179-1true assume !(0 == ~E_3~0); 116#L1184-1true assume !(0 == ~E_4~0); 134#L1189-1true assume !(0 == ~E_5~0); 180#L1194-1true assume 0 == ~E_6~0;~E_6~0 := 1; 791#L1199-1true assume !(0 == ~E_7~0); 969#L1204-1true assume !(0 == ~E_8~0); 723#L1209-1true assume !(0 == ~E_9~0); 1177#L1214-1true assume !(0 == ~E_10~0); 1526#L1219-1true assume !(0 == ~E_11~0); 1470#L1224-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 293#L544true assume 1 == ~m_pc~0; 1029#L545true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1188#L555true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 798#L556true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 96#L1379true assume !(0 != activate_threads_~tmp~1#1); 1393#L1379-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 557#L563true assume !(1 == ~t1_pc~0); 1184#L563-2true is_transmit1_triggered_~__retres1~1#1 := 0; 32#L574true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1107#L575true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 665#L1387true assume !(0 != activate_threads_~tmp___0~0#1); 30#L1387-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 405#L582true assume 1 == ~t2_pc~0; 886#L583true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 675#L593true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 783#L594true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 843#L1395true assume !(0 != activate_threads_~tmp___1~0#1); 46#L1395-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 757#L601true assume !(1 == ~t3_pc~0); 463#L601-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1016#L612true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1219#L613true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 706#L1403true assume !(0 != activate_threads_~tmp___2~0#1); 1410#L1403-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 655#L620true assume 1 == ~t4_pc~0; 37#L621true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 364#L631true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 329#L632true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 569#L1411true assume !(0 != activate_threads_~tmp___3~0#1); 759#L1411-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 740#L639true assume 1 == ~t5_pc~0; 630#L640true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 183#L650true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 590#L651true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 584#L1419true assume !(0 != activate_threads_~tmp___4~0#1); 849#L1419-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 529#L658true assume !(1 == ~t6_pc~0); 291#L658-2true is_transmit6_triggered_~__retres1~6#1 := 0; 697#L669true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1136#L670true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1477#L1427true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 710#L1427-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 205#L677true assume 1 == ~t7_pc~0; 1245#L678true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 889#L688true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1341#L689true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1071#L1435true assume !(0 != activate_threads_~tmp___6~0#1); 1230#L1435-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1304#L696true assume !(1 == ~t8_pc~0); 324#L696-2true is_transmit8_triggered_~__retres1~8#1 := 0; 1150#L707true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1196#L708true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1347#L1443true assume !(0 != activate_threads_~tmp___7~0#1); 1521#L1443-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 618#L715true assume 1 == ~t9_pc~0; 1222#L716true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 381#L726true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 323#L727true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 605#L1451true assume !(0 != activate_threads_~tmp___8~0#1); 1391#L1451-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 887#L734true assume !(1 == ~t10_pc~0); 1038#L734-2true is_transmit10_triggered_~__retres1~10#1 := 0; 268#L745true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 277#L746true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 813#L1459true assume !(0 != activate_threads_~tmp___9~0#1); 1257#L1459-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 311#L753true assume 1 == ~t11_pc~0; 716#L754true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1570#L764true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 377#L765true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 475#L1467true assume !(0 != activate_threads_~tmp___10~0#1); 777#L1467-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 514#L1237true assume !(1 == ~M_E~0); 1299#L1237-2true assume !(1 == ~T1_E~0); 1420#L1242-1true assume !(1 == ~T2_E~0); 361#L1247-1true assume !(1 == ~T3_E~0); 1067#L1252-1true assume !(1 == ~T4_E~0); 235#L1257-1true assume !(1 == ~T5_E~0); 908#L1262-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1054#L1267-1true assume !(1 == ~T7_E~0); 1055#L1272-1true assume !(1 == ~T8_E~0); 411#L1277-1true assume !(1 == ~T9_E~0); 823#L1282-1true assume !(1 == ~T10_E~0); 751#L1287-1true assume !(1 == ~T11_E~0); 792#L1292-1true assume !(1 == ~E_M~0); 709#L1297-1true assume !(1 == ~E_1~0); 307#L1302-1true assume 1 == ~E_2~0;~E_2~0 := 2; 1040#L1307-1true assume !(1 == ~E_3~0); 1357#L1312-1true assume !(1 == ~E_4~0); 438#L1317-1true assume !(1 == ~E_5~0); 613#L1322-1true assume !(1 == ~E_6~0); 275#L1327-1true assume !(1 == ~E_7~0); 664#L1332-1true assume !(1 == ~E_8~0); 1336#L1337-1true assume !(1 == ~E_9~0); 609#L1342-1true assume 1 == ~E_10~0;~E_10~0 := 2; 1234#L1347-1true assume !(1 == ~E_11~0); 1039#L1352-1true assume { :end_inline_reset_delta_events } true; 1564#L1678-2true [2021-11-13 17:45:50,810 INFO L793 eck$LassoCheckResult]: Loop: 1564#L1678-2true assume !false; 656#L1679true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 817#L1084true assume !true; 171#L1099true assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 105#L773-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1423#L1109-3true assume 0 == ~M_E~0;~M_E~0 := 1; 38#L1109-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 1215#L1114-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 711#L1119-3true assume !(0 == ~T3_E~0); 1559#L1124-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 736#L1129-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 954#L1134-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1115#L1139-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1027#L1144-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 298#L1149-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1551#L1154-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 443#L1159-3true assume !(0 == ~T11_E~0); 1538#L1164-3true assume 0 == ~E_M~0;~E_M~0 := 1; 652#L1169-3true assume 0 == ~E_1~0;~E_1~0 := 1; 986#L1174-3true assume 0 == ~E_2~0;~E_2~0 := 1; 699#L1179-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1306#L1184-3true assume 0 == ~E_4~0;~E_4~0 := 1; 870#L1189-3true assume 0 == ~E_5~0;~E_5~0 := 1; 551#L1194-3true assume 0 == ~E_6~0;~E_6~0 := 1; 168#L1199-3true assume !(0 == ~E_7~0); 794#L1204-3true assume 0 == ~E_8~0;~E_8~0 := 1; 288#L1209-3true assume 0 == ~E_9~0;~E_9~0 := 1; 15#L1214-3true assume 0 == ~E_10~0;~E_10~0 := 1; 602#L1219-3true assume 0 == ~E_11~0;~E_11~0 := 1; 386#L1224-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 644#L544-39true assume !(1 == ~m_pc~0); 5#L544-41true is_master_triggered_~__retres1~0#1 := 0; 738#L555-13true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 124#L556-13true activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 209#L1379-39true assume !(0 != activate_threads_~tmp~1#1); 848#L1379-41true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1317#L563-39true assume !(1 == ~t1_pc~0); 73#L563-41true is_transmit1_triggered_~__retres1~1#1 := 0; 1539#L574-13true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 625#L575-13true activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1434#L1387-39true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1446#L1387-41true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1003#L582-39true assume 1 == ~t2_pc~0; 243#L583-13true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 761#L593-13true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 667#L594-13true activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 971#L1395-39true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 120#L1395-41true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20#L601-39true assume 1 == ~t3_pc~0; 1236#L602-13true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 807#L612-13true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 985#L613-13true activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1492#L1403-39true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 856#L1403-41true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 527#L620-39true assume 1 == ~t4_pc~0; 695#L621-13true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 940#L631-13true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1500#L632-13true activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 821#L1411-39true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1546#L1411-41true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1543#L639-39true assume 1 == ~t5_pc~0; 978#L640-13true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 365#L650-13true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 127#L651-13true activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33#L1419-39true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1380#L1419-41true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 555#L658-39true assume 1 == ~t6_pc~0; 540#L659-13true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1065#L669-13true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10#L670-13true activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 720#L1427-39true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 692#L1427-41true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1238#L677-39true assume 1 == ~t7_pc~0; 659#L678-13true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 115#L688-13true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 992#L689-13true activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 145#L1435-39true assume !(0 != activate_threads_~tmp___6~0#1); 1369#L1435-41true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 477#L696-39true assume !(1 == ~t8_pc~0); 781#L696-41true is_transmit8_triggered_~__retres1~8#1 := 0; 375#L707-13true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1495#L708-13true activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 578#L1443-39true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 547#L1443-41true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 461#L715-39true assume !(1 == ~t9_pc~0); 1058#L715-41true is_transmit9_triggered_~__retres1~9#1 := 0; 815#L726-13true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1569#L727-13true activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1568#L1451-39true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 742#L1451-41true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1141#L734-39true assume !(1 == ~t10_pc~0); 281#L734-41true is_transmit10_triggered_~__retres1~10#1 := 0; 478#L745-13true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 746#L746-13true activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 91#L1459-39true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1460#L1459-41true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1091#L753-39true assume !(1 == ~t11_pc~0); 56#L753-41true is_transmit11_triggered_~__retres1~11#1 := 0; 1019#L764-13true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1147#L765-13true activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 455#L1467-39true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 750#L1467-41true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 525#L1237-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1086#L1237-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 773#L1242-3true assume !(1 == ~T2_E~0); 1511#L1247-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1053#L1252-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 689#L1257-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 1022#L1262-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1098#L1267-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1528#L1272-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 1334#L1277-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 130#L1282-3true assume !(1 == ~T10_E~0); 666#L1287-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 82#L1292-3true assume 1 == ~E_M~0;~E_M~0 := 2; 1489#L1297-3true assume 1 == ~E_1~0;~E_1~0 := 2; 900#L1302-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1227#L1307-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1509#L1312-3true assume 1 == ~E_4~0;~E_4~0 := 2; 1503#L1317-3true assume 1 == ~E_5~0;~E_5~0 := 2; 795#L1322-3true assume !(1 == ~E_6~0); 1556#L1327-3true assume 1 == ~E_7~0;~E_7~0 := 2; 112#L1332-3true assume 1 == ~E_8~0;~E_8~0 := 2; 99#L1337-3true assume 1 == ~E_9~0;~E_9~0 := 2; 504#L1342-3true assume 1 == ~E_10~0;~E_10~0 := 2; 943#L1347-3true assume 1 == ~E_11~0;~E_11~0 := 2; 604#L1352-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 891#L848-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 214#L910-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 698#L911-1true start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 741#L1697true assume !(0 == start_simulation_~tmp~3#1); 520#L1697-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1309#L848-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 857#L910-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 619#L911-2true stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1119#L1652true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 574#L1659true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 306#L1660true start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 888#L1710true assume !(0 != start_simulation_~tmp___0~1#1); 1564#L1678-2true [2021-11-13 17:45:50,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:50,816 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 1 times [2021-11-13 17:45:50,826 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:50,830 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [604713972] [2021-11-13 17:45:50,830 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:50,831 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:50,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:51,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:51,110 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:51,110 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [604713972] [2021-11-13 17:45:51,111 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [604713972] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:51,111 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:51,111 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:51,113 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [457943632] [2021-11-13 17:45:51,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:51,118 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:45:51,119 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:51,119 INFO L85 PathProgramCache]: Analyzing trace with hash -356606326, now seen corresponding path program 1 times [2021-11-13 17:45:51,120 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:51,120 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2097617340] [2021-11-13 17:45:51,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:51,120 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:51,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:51,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:51,227 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:51,227 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2097617340] [2021-11-13 17:45:51,227 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2097617340] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:51,228 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:51,228 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 17:45:51,228 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2074835802] [2021-11-13 17:45:51,228 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:51,230 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:45:51,231 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:45:51,280 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2021-11-13 17:45:51,282 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2021-11-13 17:45:51,288 INFO L87 Difference]: Start difference. First operand has 1572 states, 1571 states have (on average 1.5022278803309994) internal successors, (2360), 1571 states have internal predecessors, (2360), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 69.5) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:51,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:45:51,361 INFO L93 Difference]: Finished difference Result 1571 states and 2330 transitions. [2021-11-13 17:45:51,362 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2021-11-13 17:45:51,367 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1571 states and 2330 transitions. [2021-11-13 17:45:51,385 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:51,405 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1571 states to 1566 states and 2325 transitions. [2021-11-13 17:45:51,406 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-11-13 17:45:51,409 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-11-13 17:45:51,410 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2325 transitions. [2021-11-13 17:45:51,417 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:45:51,418 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2325 transitions. [2021-11-13 17:45:51,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2325 transitions. [2021-11-13 17:45:51,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-11-13 17:45:51,515 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4846743295019158) internal successors, (2325), 1565 states have internal predecessors, (2325), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:51,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2325 transitions. [2021-11-13 17:45:51,525 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2325 transitions. [2021-11-13 17:45:51,525 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2325 transitions. [2021-11-13 17:45:51,525 INFO L425 BuchiCegarLoop]: ======== Iteration 2============ [2021-11-13 17:45:51,526 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2325 transitions. [2021-11-13 17:45:51,538 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:51,539 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:45:51,539 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:45:51,543 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:51,543 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:51,544 INFO L791 eck$LassoCheckResult]: Stem: 3887#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 3888#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 4616#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4617#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3390#L780 assume !(1 == ~m_i~0);~m_st~0 := 2; 3391#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4626#L785-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 4591#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4592#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3739#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3740#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4146#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4564#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3651#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3652#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 3537#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 3538#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4490#L1109 assume !(0 == ~M_E~0); 4512#L1109-2 assume !(0 == ~T1_E~0); 3544#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3545#L1119-1 assume !(0 == ~T3_E~0); 4568#L1124-1 assume !(0 == ~T4_E~0); 3205#L1129-1 assume !(0 == ~T5_E~0); 3206#L1134-1 assume !(0 == ~T6_E~0); 3819#L1139-1 assume !(0 == ~T7_E~0); 4496#L1144-1 assume !(0 == ~T8_E~0); 4368#L1149-1 assume !(0 == ~T9_E~0); 3312#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3313#L1159-1 assume !(0 == ~T11_E~0); 4354#L1164-1 assume !(0 == ~E_M~0); 3705#L1169-1 assume !(0 == ~E_1~0); 3594#L1174-1 assume !(0 == ~E_2~0); 3467#L1179-1 assume !(0 == ~E_3~0); 3394#L1184-1 assume !(0 == ~E_4~0); 3395#L1189-1 assume !(0 == ~E_5~0); 3426#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 3513#L1199-1 assume !(0 == ~E_7~0); 4376#L1204-1 assume !(0 == ~E_8~0); 4312#L1209-1 assume !(0 == ~E_9~0); 4313#L1214-1 assume !(0 == ~E_10~0); 4638#L1219-1 assume !(0 == ~E_11~0); 4711#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3722#L544 assume 1 == ~m_pc~0; 3723#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 4555#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4383#L556 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3356#L1379 assume !(0 != activate_threads_~tmp~1#1); 3357#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4129#L563 assume !(1 == ~t1_pc~0); 3929#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3215#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3216#L575 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4252#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 3211#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3212#L582 assume 1 == ~t2_pc~0; 3907#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4262#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4263#L594 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4367#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 3244#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3245#L601 assume !(1 == ~t3_pc~0); 3923#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3922#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4556#L613 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4298#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 4299#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4242#L620 assume 1 == ~t4_pc~0; 3225#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3226#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3787#L632 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3788#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 4143#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4330#L639 assume 1 == ~t5_pc~0; 4213#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3517#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3518#L651 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4164#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 4165#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4094#L658 assume !(1 == ~t6_pc~0); 3719#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3720#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4288#L670 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4618#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4302#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3557#L677 assume 1 == ~t7_pc~0; 3558#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3460#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4461#L689 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4585#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 4586#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4657#L696 assume !(1 == ~t8_pc~0); 3777#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3778#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4625#L708 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4646#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 4692#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4196#L715 assume 1 == ~t9_pc~0; 4197#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3867#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3775#L727 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3776#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 4185#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4457#L734 assume !(1 == ~t10_pc~0); 4458#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3677#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3678#L746 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3696#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 4401#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3753#L753 assume 1 == ~t11_pc~0; 3754#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 4307#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3862#L765 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3863#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 4012#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4069#L1237 assume !(1 == ~M_E~0); 4070#L1237-2 assume !(1 == ~T1_E~0); 4682#L1242-1 assume !(1 == ~T2_E~0); 3833#L1247-1 assume !(1 == ~T3_E~0); 3834#L1252-1 assume !(1 == ~T4_E~0); 3617#L1257-1 assume !(1 == ~T5_E~0); 3618#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4473#L1267-1 assume !(1 == ~T7_E~0); 4578#L1272-1 assume !(1 == ~T8_E~0); 3916#L1277-1 assume !(1 == ~T9_E~0); 3917#L1282-1 assume !(1 == ~T10_E~0); 4339#L1287-1 assume !(1 == ~T11_E~0); 4340#L1292-1 assume !(1 == ~E_M~0); 4301#L1297-1 assume !(1 == ~E_1~0); 3748#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 3749#L1307-1 assume !(1 == ~E_3~0); 4571#L1312-1 assume !(1 == ~E_4~0); 3959#L1317-1 assume !(1 == ~E_5~0); 3960#L1322-1 assume !(1 == ~E_6~0); 3692#L1327-1 assume !(1 == ~E_7~0); 3693#L1332-1 assume !(1 == ~E_8~0); 4251#L1337-1 assume !(1 == ~E_9~0); 4188#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 4189#L1347-1 assume !(1 == ~E_11~0); 4570#L1352-1 assume { :end_inline_reset_delta_events } true; 4460#L1678-2 [2021-11-13 17:45:51,545 INFO L793 eck$LassoCheckResult]: Loop: 4460#L1678-2 assume !false; 4243#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4244#L1084 assume !false; 4027#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4028#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3331#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4345#L911 eval_#t~ret8#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret8#1;havoc eval_#t~ret8#1; 3257#L925 assume !(0 != eval_~tmp~0#1); 3259#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3373#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3374#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3228#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3229#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4303#L1119-3 assume !(0 == ~T3_E~0); 4304#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4325#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4326#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4504#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4562#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3732#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3733#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3968#L1159-3 assume !(0 == ~T11_E~0); 3969#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4239#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4240#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4290#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4291#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4446#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4123#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3490#L1199-3 assume !(0 == ~E_7~0); 3491#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3714#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3176#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3177#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3875#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3876#L544-39 assume !(1 == ~m_pc~0); 3157#L544-41 is_master_triggered_~__retres1~0#1 := 0; 3158#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3408#L556-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3409#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 3565#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4433#L563-39 assume 1 == ~t1_pc~0; 4439#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3308#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4207#L575-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4208#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4705#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4548#L582-39 assume !(1 == ~t2_pc~0); 3632#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 3633#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4253#L594-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4254#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3401#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3188#L601-39 assume 1 == ~t3_pc~0; 3189#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3239#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4397#L613-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4533#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4437#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4089#L620-39 assume !(1 == ~t4_pc~0); 4090#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 4287#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4495#L632-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4410#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4411#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4716#L639-39 assume 1 == ~t5_pc~0; 4523#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3837#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3414#L651-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3217#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3218#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4126#L658-39 assume 1 == ~t6_pc~0; 4108#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4109#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3167#L670-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3168#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4283#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4284#L677-39 assume 1 == ~t7_pc~0; 4246#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3392#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3393#L689-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3448#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 3449#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4014#L696-39 assume 1 == ~t8_pc~0; 3979#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3859#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3860#L708-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4155#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4119#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3994#L715-39 assume 1 == ~t9_pc~0; 3193#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3194#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4403#L727-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4717#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4332#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4333#L734-39 assume 1 == ~t10_pc~0; 4258#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3704#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4015#L746-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3346#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3347#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4595#L753-39 assume !(1 == ~t11_pc~0); 3266#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 3267#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4559#L765-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3984#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3985#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4086#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4087#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4357#L1242-3 assume !(1 == ~T2_E~0); 4358#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4577#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4277#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4278#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4560#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4601#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4689#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3418#L1282-3 assume !(1 == ~T10_E~0); 3419#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3328#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3329#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4466#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4467#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4655#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4713#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4379#L1322-3 assume !(1 == ~E_6~0); 4380#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3387#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3362#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3363#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4055#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4183#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4184#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3310#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 3575#L911-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 4289#L1697 assume !(0 == start_simulation_~tmp~3#1); 4076#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 4077#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 3434#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 4199#L911-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 4200#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4149#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3746#L1660 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 3747#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 4460#L1678-2 [2021-11-13 17:45:51,546 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:51,546 INFO L85 PathProgramCache]: Analyzing trace with hash 430082112, now seen corresponding path program 2 times [2021-11-13 17:45:51,547 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:51,547 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1882051203] [2021-11-13 17:45:51,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:51,548 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:51,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:51,652 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:51,655 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:51,656 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1882051203] [2021-11-13 17:45:51,656 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1882051203] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:51,656 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:51,657 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:51,658 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [698929599] [2021-11-13 17:45:51,659 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:51,660 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:45:51,662 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:51,664 INFO L85 PathProgramCache]: Analyzing trace with hash 1065978444, now seen corresponding path program 1 times [2021-11-13 17:45:51,664 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:51,664 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [178843685] [2021-11-13 17:45:51,665 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:51,665 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:51,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:51,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:51,847 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:51,847 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [178843685] [2021-11-13 17:45:51,847 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [178843685] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:51,848 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:51,848 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:51,848 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [79718662] [2021-11-13 17:45:51,848 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:51,849 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:45:51,849 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:45:51,853 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 17:45:51,853 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 17:45:51,854 INFO L87 Difference]: Start difference. First operand 1566 states and 2325 transitions. cyclomatic complexity: 760 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:51,928 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:45:51,928 INFO L93 Difference]: Finished difference Result 1566 states and 2324 transitions. [2021-11-13 17:45:51,929 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 17:45:51,930 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2324 transitions. [2021-11-13 17:45:51,948 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:51,964 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2324 transitions. [2021-11-13 17:45:51,964 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-11-13 17:45:51,967 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-11-13 17:45:51,967 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2324 transitions. [2021-11-13 17:45:51,970 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:45:51,970 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2324 transitions. [2021-11-13 17:45:51,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2324 transitions. [2021-11-13 17:45:52,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-11-13 17:45:52,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4840357598978289) internal successors, (2324), 1565 states have internal predecessors, (2324), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:52,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2324 transitions. [2021-11-13 17:45:52,087 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2324 transitions. [2021-11-13 17:45:52,087 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2324 transitions. [2021-11-13 17:45:52,088 INFO L425 BuchiCegarLoop]: ======== Iteration 3============ [2021-11-13 17:45:52,088 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2324 transitions. [2021-11-13 17:45:52,099 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:52,099 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:45:52,100 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:45:52,102 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:52,103 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:52,105 INFO L791 eck$LassoCheckResult]: Stem: 7026#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 7027#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 7755#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7756#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6529#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 6530#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7765#L785-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 7730#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 7731#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6878#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6879#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7285#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7703#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6790#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6791#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 6676#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 6677#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7629#L1109 assume !(0 == ~M_E~0); 7651#L1109-2 assume !(0 == ~T1_E~0); 6683#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6684#L1119-1 assume !(0 == ~T3_E~0); 7707#L1124-1 assume !(0 == ~T4_E~0); 6344#L1129-1 assume !(0 == ~T5_E~0); 6345#L1134-1 assume !(0 == ~T6_E~0); 6958#L1139-1 assume !(0 == ~T7_E~0); 7635#L1144-1 assume !(0 == ~T8_E~0); 7507#L1149-1 assume !(0 == ~T9_E~0); 6451#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6452#L1159-1 assume !(0 == ~T11_E~0); 7493#L1164-1 assume !(0 == ~E_M~0); 6844#L1169-1 assume !(0 == ~E_1~0); 6733#L1174-1 assume !(0 == ~E_2~0); 6606#L1179-1 assume !(0 == ~E_3~0); 6533#L1184-1 assume !(0 == ~E_4~0); 6534#L1189-1 assume !(0 == ~E_5~0); 6565#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 6652#L1199-1 assume !(0 == ~E_7~0); 7515#L1204-1 assume !(0 == ~E_8~0); 7451#L1209-1 assume !(0 == ~E_9~0); 7452#L1214-1 assume !(0 == ~E_10~0); 7777#L1219-1 assume !(0 == ~E_11~0); 7850#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6861#L544 assume 1 == ~m_pc~0; 6862#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 7694#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7522#L556 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6495#L1379 assume !(0 != activate_threads_~tmp~1#1); 6496#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7268#L563 assume !(1 == ~t1_pc~0); 7068#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6354#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6355#L575 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7391#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 6350#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6351#L582 assume 1 == ~t2_pc~0; 7046#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7401#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7402#L594 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7506#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 6383#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6384#L601 assume !(1 == ~t3_pc~0); 7062#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7061#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7695#L613 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7437#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 7438#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7381#L620 assume 1 == ~t4_pc~0; 6364#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6365#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6926#L632 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6927#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 7282#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7469#L639 assume 1 == ~t5_pc~0; 7352#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6656#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6657#L651 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7303#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 7304#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7233#L658 assume !(1 == ~t6_pc~0); 6858#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6859#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7427#L670 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7757#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7441#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6696#L677 assume 1 == ~t7_pc~0; 6697#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6599#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7600#L689 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7724#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 7725#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7796#L696 assume !(1 == ~t8_pc~0); 6916#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6917#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7764#L708 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7785#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 7831#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7335#L715 assume 1 == ~t9_pc~0; 7336#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7006#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6914#L727 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 6915#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 7324#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7596#L734 assume !(1 == ~t10_pc~0); 7597#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6816#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6817#L746 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 6835#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 7540#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 6892#L753 assume 1 == ~t11_pc~0; 6893#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 7446#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7001#L765 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7002#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 7151#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7208#L1237 assume !(1 == ~M_E~0); 7209#L1237-2 assume !(1 == ~T1_E~0); 7821#L1242-1 assume !(1 == ~T2_E~0); 6972#L1247-1 assume !(1 == ~T3_E~0); 6973#L1252-1 assume !(1 == ~T4_E~0); 6756#L1257-1 assume !(1 == ~T5_E~0); 6757#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7612#L1267-1 assume !(1 == ~T7_E~0); 7717#L1272-1 assume !(1 == ~T8_E~0); 7055#L1277-1 assume !(1 == ~T9_E~0); 7056#L1282-1 assume !(1 == ~T10_E~0); 7478#L1287-1 assume !(1 == ~T11_E~0); 7479#L1292-1 assume !(1 == ~E_M~0); 7440#L1297-1 assume !(1 == ~E_1~0); 6887#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6888#L1307-1 assume !(1 == ~E_3~0); 7710#L1312-1 assume !(1 == ~E_4~0); 7098#L1317-1 assume !(1 == ~E_5~0); 7099#L1322-1 assume !(1 == ~E_6~0); 6831#L1327-1 assume !(1 == ~E_7~0); 6832#L1332-1 assume !(1 == ~E_8~0); 7390#L1337-1 assume !(1 == ~E_9~0); 7327#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 7328#L1347-1 assume !(1 == ~E_11~0); 7709#L1352-1 assume { :end_inline_reset_delta_events } true; 7599#L1678-2 [2021-11-13 17:45:52,106 INFO L793 eck$LassoCheckResult]: Loop: 7599#L1678-2 assume !false; 7382#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7383#L1084 assume !false; 7166#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7167#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6470#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7484#L911 eval_#t~ret8#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret8#1;havoc eval_#t~ret8#1; 6396#L925 assume !(0 != eval_~tmp~0#1); 6398#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6512#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6513#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6367#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6368#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7442#L1119-3 assume !(0 == ~T3_E~0); 7443#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7464#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7465#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7643#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7701#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 6871#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6872#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7107#L1159-3 assume !(0 == ~T11_E~0); 7108#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7378#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7379#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7429#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7430#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7585#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7262#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6629#L1199-3 assume !(0 == ~E_7~0); 6630#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6853#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6315#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6316#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7014#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7015#L544-39 assume !(1 == ~m_pc~0); 6296#L544-41 is_master_triggered_~__retres1~0#1 := 0; 6297#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6547#L556-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6548#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 6704#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7572#L563-39 assume 1 == ~t1_pc~0; 7578#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6447#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7346#L575-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7347#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7844#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7687#L582-39 assume 1 == ~t2_pc~0; 6770#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6772#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7392#L594-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7393#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6540#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6327#L601-39 assume 1 == ~t3_pc~0; 6328#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6378#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7536#L613-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7672#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7576#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7228#L620-39 assume !(1 == ~t4_pc~0); 7229#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 7426#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7634#L632-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7549#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7550#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7855#L639-39 assume 1 == ~t5_pc~0; 7662#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6976#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6553#L651-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6356#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6357#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7265#L658-39 assume !(1 == ~t6_pc~0); 7249#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 7248#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6306#L670-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 6307#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7422#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7423#L677-39 assume 1 == ~t7_pc~0; 7385#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6531#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6532#L689-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6587#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 6588#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7153#L696-39 assume 1 == ~t8_pc~0; 7118#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 6998#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6999#L708-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7294#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7258#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7133#L715-39 assume 1 == ~t9_pc~0; 6332#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6333#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7542#L727-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7856#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7471#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7472#L734-39 assume 1 == ~t10_pc~0; 7397#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 6843#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7154#L746-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 6485#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6486#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7734#L753-39 assume !(1 == ~t11_pc~0); 6405#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 6406#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7698#L765-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7123#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7124#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7225#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7226#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7496#L1242-3 assume !(1 == ~T2_E~0); 7497#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7716#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7416#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7417#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7699#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7740#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7828#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6557#L1282-3 assume !(1 == ~T10_E~0); 6558#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 6467#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6468#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7605#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7606#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7794#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7852#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7518#L1322-3 assume !(1 == ~E_6~0); 7519#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6526#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6501#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6502#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7194#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 7322#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7323#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6449#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 6714#L911-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 7428#L1697 assume !(0 == start_simulation_~tmp~3#1); 7215#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 7216#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 6573#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 7338#L911-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 7339#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7288#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6885#L1660 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 6886#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 7599#L1678-2 [2021-11-13 17:45:52,109 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:52,110 INFO L85 PathProgramCache]: Analyzing trace with hash -968871490, now seen corresponding path program 1 times [2021-11-13 17:45:52,110 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:52,110 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1864813623] [2021-11-13 17:45:52,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:52,111 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:52,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:52,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:52,214 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:52,214 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1864813623] [2021-11-13 17:45:52,214 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1864813623] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:52,214 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:52,214 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:52,215 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1200896118] [2021-11-13 17:45:52,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:52,215 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:45:52,215 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:52,216 INFO L85 PathProgramCache]: Analyzing trace with hash 764411212, now seen corresponding path program 1 times [2021-11-13 17:45:52,216 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:52,216 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [534011518] [2021-11-13 17:45:52,216 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:52,216 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:52,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:52,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:52,296 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:52,297 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [534011518] [2021-11-13 17:45:52,298 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [534011518] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:52,298 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:52,298 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:52,298 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1597771823] [2021-11-13 17:45:52,299 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:52,300 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:45:52,300 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:45:52,300 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 17:45:52,301 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 17:45:52,301 INFO L87 Difference]: Start difference. First operand 1566 states and 2324 transitions. cyclomatic complexity: 759 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:52,343 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:45:52,344 INFO L93 Difference]: Finished difference Result 1566 states and 2323 transitions. [2021-11-13 17:45:52,344 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 17:45:52,346 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2323 transitions. [2021-11-13 17:45:52,362 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:52,377 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2323 transitions. [2021-11-13 17:45:52,377 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-11-13 17:45:52,380 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-11-13 17:45:52,380 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2323 transitions. [2021-11-13 17:45:52,383 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:45:52,383 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2323 transitions. [2021-11-13 17:45:52,386 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2323 transitions. [2021-11-13 17:45:52,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-11-13 17:45:52,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.483397190293742) internal successors, (2323), 1565 states have internal predecessors, (2323), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:52,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2323 transitions. [2021-11-13 17:45:52,421 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2323 transitions. [2021-11-13 17:45:52,421 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2323 transitions. [2021-11-13 17:45:52,421 INFO L425 BuchiCegarLoop]: ======== Iteration 4============ [2021-11-13 17:45:52,421 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2323 transitions. [2021-11-13 17:45:52,432 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:52,432 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:45:52,432 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:45:52,435 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:52,435 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:52,436 INFO L791 eck$LassoCheckResult]: Stem: 10165#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 10166#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 10894#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10895#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9668#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 9669#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10904#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10869#L790-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 10870#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 10017#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 10018#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10424#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10842#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9929#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9930#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9815#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9816#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10770#L1109 assume !(0 == ~M_E~0); 10790#L1109-2 assume !(0 == ~T1_E~0); 9822#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9823#L1119-1 assume !(0 == ~T3_E~0); 10846#L1124-1 assume !(0 == ~T4_E~0); 9485#L1129-1 assume !(0 == ~T5_E~0); 9486#L1134-1 assume !(0 == ~T6_E~0); 10097#L1139-1 assume !(0 == ~T7_E~0); 10774#L1144-1 assume !(0 == ~T8_E~0); 10646#L1149-1 assume !(0 == ~T9_E~0); 9592#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9593#L1159-1 assume !(0 == ~T11_E~0); 10632#L1164-1 assume !(0 == ~E_M~0); 9983#L1169-1 assume !(0 == ~E_1~0); 9872#L1174-1 assume !(0 == ~E_2~0); 9748#L1179-1 assume !(0 == ~E_3~0); 9672#L1184-1 assume !(0 == ~E_4~0); 9673#L1189-1 assume !(0 == ~E_5~0); 9704#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 9793#L1199-1 assume !(0 == ~E_7~0); 10654#L1204-1 assume !(0 == ~E_8~0); 10591#L1209-1 assume !(0 == ~E_9~0); 10592#L1214-1 assume !(0 == ~E_10~0); 10916#L1219-1 assume !(0 == ~E_11~0); 10989#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10002#L544 assume 1 == ~m_pc~0; 10003#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 10833#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10663#L556 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9634#L1379 assume !(0 != activate_threads_~tmp~1#1); 9635#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10410#L563 assume !(1 == ~t1_pc~0); 10207#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9493#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9494#L575 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10530#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 9489#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9490#L582 assume 1 == ~t2_pc~0; 10185#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 10540#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10541#L594 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10645#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 9522#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9523#L601 assume !(1 == ~t3_pc~0); 10201#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10200#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10834#L613 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10576#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 10577#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10520#L620 assume 1 == ~t4_pc~0; 9503#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9504#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10065#L632 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10066#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 10421#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10609#L639 assume 1 == ~t5_pc~0; 10494#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9795#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9796#L651 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10442#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 10443#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10374#L658 assume !(1 == ~t6_pc~0); 9997#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9998#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10567#L670 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 10896#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10580#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9837#L677 assume 1 == ~t7_pc~0; 9838#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9741#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10739#L689 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10863#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 10864#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10935#L696 assume !(1 == ~t8_pc~0); 10056#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10057#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10903#L708 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10924#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 10970#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10474#L715 assume 1 == ~t9_pc~0; 10475#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10145#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10053#L727 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 10054#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 10463#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10736#L734 assume !(1 == ~t10_pc~0); 10737#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 9955#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9956#L746 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9976#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 10679#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10031#L753 assume 1 == ~t11_pc~0; 10032#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 10585#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10140#L765 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 10141#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 10292#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10349#L1237 assume !(1 == ~M_E~0); 10350#L1237-2 assume !(1 == ~T1_E~0); 10961#L1242-1 assume !(1 == ~T2_E~0); 10111#L1247-1 assume !(1 == ~T3_E~0); 10112#L1252-1 assume !(1 == ~T4_E~0); 9895#L1257-1 assume !(1 == ~T5_E~0); 9896#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10752#L1267-1 assume !(1 == ~T7_E~0); 10856#L1272-1 assume !(1 == ~T8_E~0); 10194#L1277-1 assume !(1 == ~T9_E~0); 10195#L1282-1 assume !(1 == ~T10_E~0); 10617#L1287-1 assume !(1 == ~T11_E~0); 10618#L1292-1 assume !(1 == ~E_M~0); 10579#L1297-1 assume !(1 == ~E_1~0); 10026#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 10027#L1307-1 assume !(1 == ~E_3~0); 10849#L1312-1 assume !(1 == ~E_4~0); 10237#L1317-1 assume !(1 == ~E_5~0); 10238#L1322-1 assume !(1 == ~E_6~0); 9970#L1327-1 assume !(1 == ~E_7~0); 9971#L1332-1 assume !(1 == ~E_8~0); 10529#L1337-1 assume !(1 == ~E_9~0); 10466#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 10467#L1347-1 assume !(1 == ~E_11~0); 10848#L1352-1 assume { :end_inline_reset_delta_events } true; 10735#L1678-2 [2021-11-13 17:45:52,436 INFO L793 eck$LassoCheckResult]: Loop: 10735#L1678-2 assume !false; 10522#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10523#L1084 assume !false; 10306#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10307#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9609#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10624#L911 eval_#t~ret8#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret8#1;havoc eval_#t~ret8#1; 9535#L925 assume !(0 != eval_~tmp~0#1); 9537#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9651#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9652#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9506#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9507#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10581#L1119-3 assume !(0 == ~T3_E~0); 10582#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10603#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10604#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10782#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10840#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 10010#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10011#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10248#L1159-3 assume !(0 == ~T11_E~0); 10249#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10517#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10518#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10568#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10569#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10724#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10401#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9768#L1199-3 assume !(0 == ~E_7~0); 9769#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9992#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9454#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9455#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10153#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10154#L544-39 assume !(1 == ~m_pc~0); 9435#L544-41 is_master_triggered_~__retres1~0#1 := 0; 9436#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9684#L556-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9685#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 9843#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10711#L563-39 assume !(1 == ~t1_pc~0); 9585#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 9586#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10485#L575-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10486#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10983#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10826#L582-39 assume 1 == ~t2_pc~0; 9909#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9911#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10531#L594-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10532#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9679#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9466#L601-39 assume 1 == ~t3_pc~0; 9467#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9517#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10675#L613-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10811#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10715#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10367#L620-39 assume !(1 == ~t4_pc~0); 10368#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 10565#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10773#L632-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10688#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10689#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10994#L639-39 assume 1 == ~t5_pc~0; 10801#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10115#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9692#L651-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9495#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9496#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10404#L658-39 assume 1 == ~t6_pc~0; 10386#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10387#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9445#L670-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9446#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10561#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10562#L677-39 assume !(1 == ~t7_pc~0); 10192#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 9670#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9671#L689-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9726#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 9727#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10291#L696-39 assume 1 == ~t8_pc~0; 10257#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 10137#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10138#L708-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 10433#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 10397#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10272#L715-39 assume !(1 == ~t9_pc~0); 9473#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 9472#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10681#L727-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 10995#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10610#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10611#L734-39 assume 1 == ~t10_pc~0; 10536#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 9982#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10293#L746-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9624#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9625#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 10873#L753-39 assume !(1 == ~t11_pc~0); 9544#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 9545#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10837#L765-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 10262#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 10263#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10364#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10365#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10635#L1242-3 assume !(1 == ~T2_E~0); 10636#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10855#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10555#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10556#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10838#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10879#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10967#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9696#L1282-3 assume !(1 == ~T10_E~0); 9697#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9606#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9607#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10744#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10745#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10933#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10991#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10657#L1322-3 assume !(1 == ~E_6~0); 10658#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9665#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9640#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9641#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10333#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 10461#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10462#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9588#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 9853#L911-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 10566#L1697 assume !(0 == start_simulation_~tmp~3#1); 10354#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 10355#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 9712#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 10477#L911-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 10478#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10427#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10024#L1660 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 10025#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 10735#L1678-2 [2021-11-13 17:45:52,437 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:52,438 INFO L85 PathProgramCache]: Analyzing trace with hash -1332337988, now seen corresponding path program 1 times [2021-11-13 17:45:52,439 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:52,439 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [660696993] [2021-11-13 17:45:52,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:52,440 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:52,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:52,496 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:52,496 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:52,496 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [660696993] [2021-11-13 17:45:52,497 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [660696993] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:52,497 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:52,498 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:52,498 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1099606281] [2021-11-13 17:45:52,498 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:52,499 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:45:52,499 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:52,503 INFO L85 PathProgramCache]: Analyzing trace with hash 1977169166, now seen corresponding path program 1 times [2021-11-13 17:45:52,503 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:52,507 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1107206513] [2021-11-13 17:45:52,507 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:52,508 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:52,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:52,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:52,589 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:52,590 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1107206513] [2021-11-13 17:45:52,597 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1107206513] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:52,598 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:52,598 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:52,598 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [620058864] [2021-11-13 17:45:52,599 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:52,599 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:45:52,599 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:45:52,601 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 17:45:52,601 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 17:45:52,602 INFO L87 Difference]: Start difference. First operand 1566 states and 2323 transitions. cyclomatic complexity: 758 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:52,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:45:52,689 INFO L93 Difference]: Finished difference Result 1566 states and 2322 transitions. [2021-11-13 17:45:52,689 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 17:45:52,690 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2322 transitions. [2021-11-13 17:45:52,704 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:52,718 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2322 transitions. [2021-11-13 17:45:52,718 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-11-13 17:45:52,720 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-11-13 17:45:52,720 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2322 transitions. [2021-11-13 17:45:52,724 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:45:52,725 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2322 transitions. [2021-11-13 17:45:52,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2322 transitions. [2021-11-13 17:45:52,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-11-13 17:45:52,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4827586206896552) internal successors, (2322), 1565 states have internal predecessors, (2322), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:52,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2322 transitions. [2021-11-13 17:45:52,762 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2322 transitions. [2021-11-13 17:45:52,763 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2322 transitions. [2021-11-13 17:45:52,763 INFO L425 BuchiCegarLoop]: ======== Iteration 5============ [2021-11-13 17:45:52,763 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2322 transitions. [2021-11-13 17:45:52,773 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:52,773 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:45:52,773 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:45:52,778 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:52,778 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:52,779 INFO L791 eck$LassoCheckResult]: Stem: 13304#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 13305#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 14033#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14034#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12807#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 12808#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14043#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14008#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14009#L795-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13156#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13157#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13563#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 13981#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13068#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13069#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 12954#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 12955#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13907#L1109 assume !(0 == ~M_E~0); 13929#L1109-2 assume !(0 == ~T1_E~0); 12961#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12962#L1119-1 assume !(0 == ~T3_E~0); 13985#L1124-1 assume !(0 == ~T4_E~0); 12624#L1129-1 assume !(0 == ~T5_E~0); 12625#L1134-1 assume !(0 == ~T6_E~0); 13236#L1139-1 assume !(0 == ~T7_E~0); 13913#L1144-1 assume !(0 == ~T8_E~0); 13785#L1149-1 assume !(0 == ~T9_E~0); 12729#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12730#L1159-1 assume !(0 == ~T11_E~0); 13771#L1164-1 assume !(0 == ~E_M~0); 13122#L1169-1 assume !(0 == ~E_1~0); 13011#L1174-1 assume !(0 == ~E_2~0); 12884#L1179-1 assume !(0 == ~E_3~0); 12811#L1184-1 assume !(0 == ~E_4~0); 12812#L1189-1 assume !(0 == ~E_5~0); 12843#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 12930#L1199-1 assume !(0 == ~E_7~0); 13793#L1204-1 assume !(0 == ~E_8~0); 13729#L1209-1 assume !(0 == ~E_9~0); 13730#L1214-1 assume !(0 == ~E_10~0); 14055#L1219-1 assume !(0 == ~E_11~0); 14128#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13139#L544 assume 1 == ~m_pc~0; 13140#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13972#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13800#L556 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12773#L1379 assume !(0 != activate_threads_~tmp~1#1); 12774#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13546#L563 assume !(1 == ~t1_pc~0); 13346#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12632#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12633#L575 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13669#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 12628#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12629#L582 assume 1 == ~t2_pc~0; 13324#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13679#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13680#L594 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13784#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 12661#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12662#L601 assume !(1 == ~t3_pc~0); 13340#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13339#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13973#L613 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13715#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 13716#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13659#L620 assume 1 == ~t4_pc~0; 12642#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12643#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13204#L632 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13205#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 13560#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13748#L639 assume 1 == ~t5_pc~0; 13631#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12934#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12935#L651 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13581#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 13582#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13511#L658 assume !(1 == ~t6_pc~0); 13136#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 13137#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13706#L670 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 14035#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13719#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12974#L677 assume 1 == ~t7_pc~0; 12975#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12877#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13878#L689 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14002#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 14003#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14074#L696 assume !(1 == ~t8_pc~0); 13194#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 13195#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14042#L708 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 14063#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 14109#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13613#L715 assume 1 == ~t9_pc~0; 13614#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13284#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13192#L727 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13193#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 13602#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13875#L734 assume !(1 == ~t10_pc~0); 13876#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 13094#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13095#L746 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13113#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 13818#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13170#L753 assume 1 == ~t11_pc~0; 13171#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13724#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13279#L765 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13280#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 13429#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13486#L1237 assume !(1 == ~M_E~0); 13487#L1237-2 assume !(1 == ~T1_E~0); 14099#L1242-1 assume !(1 == ~T2_E~0); 13250#L1247-1 assume !(1 == ~T3_E~0); 13251#L1252-1 assume !(1 == ~T4_E~0); 13034#L1257-1 assume !(1 == ~T5_E~0); 13035#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13890#L1267-1 assume !(1 == ~T7_E~0); 13995#L1272-1 assume !(1 == ~T8_E~0); 13333#L1277-1 assume !(1 == ~T9_E~0); 13334#L1282-1 assume !(1 == ~T10_E~0); 13756#L1287-1 assume !(1 == ~T11_E~0); 13757#L1292-1 assume !(1 == ~E_M~0); 13718#L1297-1 assume !(1 == ~E_1~0); 13165#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 13166#L1307-1 assume !(1 == ~E_3~0); 13988#L1312-1 assume !(1 == ~E_4~0); 13376#L1317-1 assume !(1 == ~E_5~0); 13377#L1322-1 assume !(1 == ~E_6~0); 13109#L1327-1 assume !(1 == ~E_7~0); 13110#L1332-1 assume !(1 == ~E_8~0); 13668#L1337-1 assume !(1 == ~E_9~0); 13605#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 13606#L1347-1 assume !(1 == ~E_11~0); 13987#L1352-1 assume { :end_inline_reset_delta_events } true; 13874#L1678-2 [2021-11-13 17:45:52,779 INFO L793 eck$LassoCheckResult]: Loop: 13874#L1678-2 assume !false; 13660#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13661#L1084 assume !false; 13444#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13445#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12748#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13762#L911 eval_#t~ret8#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret8#1;havoc eval_#t~ret8#1; 12674#L925 assume !(0 != eval_~tmp~0#1); 12676#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12790#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12791#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12645#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12646#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13720#L1119-3 assume !(0 == ~T3_E~0); 13721#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13742#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13743#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13921#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13979#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13149#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13150#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 13385#L1159-3 assume !(0 == ~T11_E~0); 13386#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13656#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13657#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13707#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13708#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13863#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13540#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12907#L1199-3 assume !(0 == ~E_7~0); 12908#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13133#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12593#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 12594#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 13292#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13293#L544-39 assume 1 == ~m_pc~0; 13648#L545-13 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 12575#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12825#L556-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12826#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 12982#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13850#L563-39 assume 1 == ~t1_pc~0; 13856#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12728#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13624#L575-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13625#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14122#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13965#L582-39 assume 1 == ~t2_pc~0; 13048#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13050#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13670#L594-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13671#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12818#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12605#L601-39 assume 1 == ~t3_pc~0; 12606#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12656#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13814#L613-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13950#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13854#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13506#L620-39 assume !(1 == ~t4_pc~0); 13507#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 13704#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13912#L632-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13827#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13828#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14133#L639-39 assume 1 == ~t5_pc~0; 13940#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13254#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12831#L651-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12634#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 12635#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13543#L658-39 assume 1 == ~t6_pc~0; 13525#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13526#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12584#L670-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12585#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13700#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13701#L677-39 assume !(1 == ~t7_pc~0); 13331#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 12809#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12810#L689-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12865#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 12866#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13431#L696-39 assume 1 == ~t8_pc~0; 13396#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13276#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13277#L708-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13572#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13536#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13409#L715-39 assume 1 == ~t9_pc~0; 12608#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12609#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13820#L727-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 14134#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13749#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13750#L734-39 assume 1 == ~t10_pc~0; 13675#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13120#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13432#L746-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12763#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 12764#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 14011#L753-39 assume !(1 == ~t11_pc~0); 12683#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 12684#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13976#L765-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13401#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13402#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13499#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13500#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13774#L1242-3 assume !(1 == ~T2_E~0); 13775#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13994#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13694#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13695#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13977#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14018#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14106#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12834#L1282-3 assume !(1 == ~T10_E~0); 12835#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12745#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12746#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13881#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13882#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14072#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14130#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13796#L1322-3 assume !(1 == ~E_6~0); 13797#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12804#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12779#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12780#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 13472#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13600#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13601#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12722#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 12992#L911-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 13705#L1697 assume !(0 == start_simulation_~tmp~3#1); 13493#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 13494#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 12851#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 13616#L911-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 13617#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13566#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13161#L1660 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 13162#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 13874#L1678-2 [2021-11-13 17:45:52,780 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:52,780 INFO L85 PathProgramCache]: Analyzing trace with hash -1621157378, now seen corresponding path program 1 times [2021-11-13 17:45:52,780 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:52,781 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1418487117] [2021-11-13 17:45:52,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:52,781 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:52,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:52,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:52,829 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:52,829 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1418487117] [2021-11-13 17:45:52,830 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1418487117] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:52,830 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:52,830 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:52,830 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [691576572] [2021-11-13 17:45:52,831 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:52,831 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:45:52,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:52,832 INFO L85 PathProgramCache]: Analyzing trace with hash 1734525003, now seen corresponding path program 1 times [2021-11-13 17:45:52,832 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:52,832 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [221853684] [2021-11-13 17:45:52,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:52,833 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:52,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:52,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:52,889 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:52,890 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [221853684] [2021-11-13 17:45:52,890 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [221853684] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:52,890 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:52,890 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:52,890 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1246784358] [2021-11-13 17:45:52,891 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:52,891 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:45:52,891 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:45:52,892 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 17:45:52,892 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 17:45:52,892 INFO L87 Difference]: Start difference. First operand 1566 states and 2322 transitions. cyclomatic complexity: 757 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:52,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:45:52,933 INFO L93 Difference]: Finished difference Result 1566 states and 2321 transitions. [2021-11-13 17:45:52,934 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 17:45:52,936 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2321 transitions. [2021-11-13 17:45:52,951 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:52,965 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2321 transitions. [2021-11-13 17:45:52,966 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-11-13 17:45:52,967 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-11-13 17:45:52,968 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2321 transitions. [2021-11-13 17:45:52,971 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:45:52,971 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2321 transitions. [2021-11-13 17:45:52,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2321 transitions. [2021-11-13 17:45:52,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-11-13 17:45:52,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4821200510855683) internal successors, (2321), 1565 states have internal predecessors, (2321), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:53,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2321 transitions. [2021-11-13 17:45:53,006 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2321 transitions. [2021-11-13 17:45:53,007 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2321 transitions. [2021-11-13 17:45:53,007 INFO L425 BuchiCegarLoop]: ======== Iteration 6============ [2021-11-13 17:45:53,007 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2321 transitions. [2021-11-13 17:45:53,017 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:53,018 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:45:53,018 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:45:53,020 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:53,021 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:53,021 INFO L791 eck$LassoCheckResult]: Stem: 16443#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 16444#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 17172#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17173#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15946#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 15947#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17182#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17147#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17148#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16295#L800-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 16296#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 16702#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17120#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16207#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16208#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 16093#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 16094#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17046#L1109 assume !(0 == ~M_E~0); 17068#L1109-2 assume !(0 == ~T1_E~0); 16100#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16101#L1119-1 assume !(0 == ~T3_E~0); 17124#L1124-1 assume !(0 == ~T4_E~0); 15761#L1129-1 assume !(0 == ~T5_E~0); 15762#L1134-1 assume !(0 == ~T6_E~0); 16375#L1139-1 assume !(0 == ~T7_E~0); 17052#L1144-1 assume !(0 == ~T8_E~0); 16924#L1149-1 assume !(0 == ~T9_E~0); 15868#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 15869#L1159-1 assume !(0 == ~T11_E~0); 16910#L1164-1 assume !(0 == ~E_M~0); 16261#L1169-1 assume !(0 == ~E_1~0); 16150#L1174-1 assume !(0 == ~E_2~0); 16023#L1179-1 assume !(0 == ~E_3~0); 15950#L1184-1 assume !(0 == ~E_4~0); 15951#L1189-1 assume !(0 == ~E_5~0); 15982#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 16069#L1199-1 assume !(0 == ~E_7~0); 16932#L1204-1 assume !(0 == ~E_8~0); 16868#L1209-1 assume !(0 == ~E_9~0); 16869#L1214-1 assume !(0 == ~E_10~0); 17194#L1219-1 assume !(0 == ~E_11~0); 17267#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16278#L544 assume 1 == ~m_pc~0; 16279#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17111#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16939#L556 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15912#L1379 assume !(0 != activate_threads_~tmp~1#1); 15913#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16685#L563 assume !(1 == ~t1_pc~0); 16485#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 15771#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15772#L575 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16808#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 15767#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15768#L582 assume 1 == ~t2_pc~0; 16463#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16818#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16819#L594 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16923#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 15800#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15801#L601 assume !(1 == ~t3_pc~0); 16479#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16478#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17112#L613 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16854#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 16855#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16798#L620 assume 1 == ~t4_pc~0; 15781#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15782#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16343#L632 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16344#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 16699#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16886#L639 assume 1 == ~t5_pc~0; 16769#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16073#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16074#L651 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16720#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 16721#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16650#L658 assume !(1 == ~t6_pc~0); 16275#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 16276#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16844#L670 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17174#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16858#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16113#L677 assume 1 == ~t7_pc~0; 16114#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 16016#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17017#L689 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17141#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 17142#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17213#L696 assume !(1 == ~t8_pc~0); 16333#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 16334#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17181#L708 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17202#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 17248#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16752#L715 assume 1 == ~t9_pc~0; 16753#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16423#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16331#L727 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 16332#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 16741#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17013#L734 assume !(1 == ~t10_pc~0); 17014#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16233#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16234#L746 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16252#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 16957#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 16309#L753 assume 1 == ~t11_pc~0; 16310#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 16863#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16418#L765 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16419#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 16568#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16625#L1237 assume !(1 == ~M_E~0); 16626#L1237-2 assume !(1 == ~T1_E~0); 17238#L1242-1 assume !(1 == ~T2_E~0); 16389#L1247-1 assume !(1 == ~T3_E~0); 16390#L1252-1 assume !(1 == ~T4_E~0); 16173#L1257-1 assume !(1 == ~T5_E~0); 16174#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17029#L1267-1 assume !(1 == ~T7_E~0); 17134#L1272-1 assume !(1 == ~T8_E~0); 16472#L1277-1 assume !(1 == ~T9_E~0); 16473#L1282-1 assume !(1 == ~T10_E~0); 16895#L1287-1 assume !(1 == ~T11_E~0); 16896#L1292-1 assume !(1 == ~E_M~0); 16857#L1297-1 assume !(1 == ~E_1~0); 16304#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 16305#L1307-1 assume !(1 == ~E_3~0); 17127#L1312-1 assume !(1 == ~E_4~0); 16515#L1317-1 assume !(1 == ~E_5~0); 16516#L1322-1 assume !(1 == ~E_6~0); 16248#L1327-1 assume !(1 == ~E_7~0); 16249#L1332-1 assume !(1 == ~E_8~0); 16807#L1337-1 assume !(1 == ~E_9~0); 16744#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 16745#L1347-1 assume !(1 == ~E_11~0); 17126#L1352-1 assume { :end_inline_reset_delta_events } true; 17016#L1678-2 [2021-11-13 17:45:53,022 INFO L793 eck$LassoCheckResult]: Loop: 17016#L1678-2 assume !false; 16799#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16800#L1084 assume !false; 16583#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16584#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15887#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16901#L911 eval_#t~ret8#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret8#1;havoc eval_#t~ret8#1; 15813#L925 assume !(0 != eval_~tmp~0#1); 15815#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15929#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15930#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15784#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15785#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16859#L1119-3 assume !(0 == ~T3_E~0); 16860#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16881#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16882#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17060#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17118#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16288#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16289#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16524#L1159-3 assume !(0 == ~T11_E~0); 16525#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 16795#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16796#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16846#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16847#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17002#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 16679#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16046#L1199-3 assume !(0 == ~E_7~0); 16047#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16270#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15732#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 15733#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 16431#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16432#L544-39 assume !(1 == ~m_pc~0); 15713#L544-41 is_master_triggered_~__retres1~0#1 := 0; 15714#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15964#L556-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15965#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 16121#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16989#L563-39 assume 1 == ~t1_pc~0; 16995#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15864#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16763#L575-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16764#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17261#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17104#L582-39 assume 1 == ~t2_pc~0; 16187#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16189#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16809#L594-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16810#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 15957#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15744#L601-39 assume 1 == ~t3_pc~0; 15745#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15795#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16953#L613-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17089#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16993#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16645#L620-39 assume !(1 == ~t4_pc~0); 16646#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 16843#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17051#L632-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16966#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16967#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17272#L639-39 assume 1 == ~t5_pc~0; 17079#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 16393#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15970#L651-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 15773#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15774#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16682#L658-39 assume 1 == ~t6_pc~0; 16664#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16665#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15723#L670-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 15724#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 16839#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16840#L677-39 assume 1 == ~t7_pc~0; 16802#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15948#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15949#L689-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 16004#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 16005#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16570#L696-39 assume 1 == ~t8_pc~0; 16535#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16415#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16416#L708-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16711#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16675#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16550#L715-39 assume 1 == ~t9_pc~0; 15749#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15750#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16959#L727-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17273#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 16888#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16889#L734-39 assume !(1 == ~t10_pc~0); 16259#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 16260#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16571#L746-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 15902#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 15903#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17151#L753-39 assume !(1 == ~t11_pc~0); 15822#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 15823#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 17115#L765-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16540#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16541#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16642#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16643#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16913#L1242-3 assume !(1 == ~T2_E~0); 16914#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17133#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16833#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16834#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17116#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17157#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17245#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 15974#L1282-3 assume !(1 == ~T10_E~0); 15975#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 15884#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15885#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17022#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17023#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17211#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17269#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16935#L1322-3 assume !(1 == ~E_6~0); 16936#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15943#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15918#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15919#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 16611#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 16739#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16740#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15866#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16131#L911-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 16845#L1697 assume !(0 == start_simulation_~tmp~3#1); 16632#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 16633#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 15990#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 16755#L911-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 16756#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16705#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16302#L1660 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 16303#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 17016#L1678-2 [2021-11-13 17:45:53,023 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:53,023 INFO L85 PathProgramCache]: Analyzing trace with hash -1076284804, now seen corresponding path program 1 times [2021-11-13 17:45:53,023 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:53,023 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1356279969] [2021-11-13 17:45:53,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:53,024 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:53,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:53,067 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:53,067 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:53,067 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1356279969] [2021-11-13 17:45:53,067 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1356279969] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:53,068 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:53,068 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:53,068 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1926099640] [2021-11-13 17:45:53,068 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:53,069 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:45:53,069 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:53,070 INFO L85 PathProgramCache]: Analyzing trace with hash 100626508, now seen corresponding path program 1 times [2021-11-13 17:45:53,070 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:53,075 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1134580762] [2021-11-13 17:45:53,077 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:53,077 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:53,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:53,145 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:53,145 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:53,145 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1134580762] [2021-11-13 17:45:53,146 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1134580762] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:53,146 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:53,146 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:53,148 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1420616351] [2021-11-13 17:45:53,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:53,149 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:45:53,149 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:45:53,150 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 17:45:53,150 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 17:45:53,150 INFO L87 Difference]: Start difference. First operand 1566 states and 2321 transitions. cyclomatic complexity: 756 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:53,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:45:53,205 INFO L93 Difference]: Finished difference Result 1566 states and 2320 transitions. [2021-11-13 17:45:53,206 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 17:45:53,206 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2320 transitions. [2021-11-13 17:45:53,216 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:53,230 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2320 transitions. [2021-11-13 17:45:53,230 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-11-13 17:45:53,232 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-11-13 17:45:53,232 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2320 transitions. [2021-11-13 17:45:53,235 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:45:53,235 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2320 transitions. [2021-11-13 17:45:53,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2320 transitions. [2021-11-13 17:45:53,260 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-11-13 17:45:53,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4814814814814814) internal successors, (2320), 1565 states have internal predecessors, (2320), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:53,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2320 transitions. [2021-11-13 17:45:53,273 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2320 transitions. [2021-11-13 17:45:53,273 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2320 transitions. [2021-11-13 17:45:53,274 INFO L425 BuchiCegarLoop]: ======== Iteration 7============ [2021-11-13 17:45:53,274 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2320 transitions. [2021-11-13 17:45:53,281 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:53,281 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:45:53,281 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:45:53,284 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:53,284 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:53,284 INFO L791 eck$LassoCheckResult]: Stem: 19582#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 19583#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 20311#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20312#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19085#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 19086#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20321#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20286#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20287#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19434#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19435#L805-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 19841#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 20259#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19346#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19347#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 19232#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 19233#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20185#L1109 assume !(0 == ~M_E~0); 20207#L1109-2 assume !(0 == ~T1_E~0); 19239#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19240#L1119-1 assume !(0 == ~T3_E~0); 20263#L1124-1 assume !(0 == ~T4_E~0); 18900#L1129-1 assume !(0 == ~T5_E~0); 18901#L1134-1 assume !(0 == ~T6_E~0); 19514#L1139-1 assume !(0 == ~T7_E~0); 20191#L1144-1 assume !(0 == ~T8_E~0); 20063#L1149-1 assume !(0 == ~T9_E~0); 19007#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19008#L1159-1 assume !(0 == ~T11_E~0); 20049#L1164-1 assume !(0 == ~E_M~0); 19400#L1169-1 assume !(0 == ~E_1~0); 19289#L1174-1 assume !(0 == ~E_2~0); 19162#L1179-1 assume !(0 == ~E_3~0); 19089#L1184-1 assume !(0 == ~E_4~0); 19090#L1189-1 assume !(0 == ~E_5~0); 19121#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 19208#L1199-1 assume !(0 == ~E_7~0); 20071#L1204-1 assume !(0 == ~E_8~0); 20007#L1209-1 assume !(0 == ~E_9~0); 20008#L1214-1 assume !(0 == ~E_10~0); 20333#L1219-1 assume !(0 == ~E_11~0); 20406#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19417#L544 assume 1 == ~m_pc~0; 19418#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 20250#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20078#L556 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19051#L1379 assume !(0 != activate_threads_~tmp~1#1); 19052#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19824#L563 assume !(1 == ~t1_pc~0); 19624#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 18910#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18911#L575 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19947#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 18906#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18907#L582 assume 1 == ~t2_pc~0; 19602#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19957#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19958#L594 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 20062#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 18939#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18940#L601 assume !(1 == ~t3_pc~0); 19618#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 19617#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20251#L613 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19993#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 19994#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19937#L620 assume 1 == ~t4_pc~0; 18920#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18921#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19482#L632 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19483#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 19838#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20025#L639 assume 1 == ~t5_pc~0; 19908#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19212#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19213#L651 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 19859#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 19860#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19789#L658 assume !(1 == ~t6_pc~0); 19414#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 19415#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19983#L670 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20313#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19997#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19252#L677 assume 1 == ~t7_pc~0; 19253#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19155#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20156#L689 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 20280#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 20281#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20352#L696 assume !(1 == ~t8_pc~0); 19472#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 19473#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20320#L708 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20341#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 20387#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19891#L715 assume 1 == ~t9_pc~0; 19892#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 19562#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19470#L727 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 19471#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 19880#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20152#L734 assume !(1 == ~t10_pc~0); 20153#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 19372#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19373#L746 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19391#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 20096#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 19448#L753 assume 1 == ~t11_pc~0; 19449#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 20002#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 19557#L765 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19558#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 19707#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19764#L1237 assume !(1 == ~M_E~0); 19765#L1237-2 assume !(1 == ~T1_E~0); 20377#L1242-1 assume !(1 == ~T2_E~0); 19528#L1247-1 assume !(1 == ~T3_E~0); 19529#L1252-1 assume !(1 == ~T4_E~0); 19312#L1257-1 assume !(1 == ~T5_E~0); 19313#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20168#L1267-1 assume !(1 == ~T7_E~0); 20273#L1272-1 assume !(1 == ~T8_E~0); 19611#L1277-1 assume !(1 == ~T9_E~0); 19612#L1282-1 assume !(1 == ~T10_E~0); 20034#L1287-1 assume !(1 == ~T11_E~0); 20035#L1292-1 assume !(1 == ~E_M~0); 19996#L1297-1 assume !(1 == ~E_1~0); 19443#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 19444#L1307-1 assume !(1 == ~E_3~0); 20266#L1312-1 assume !(1 == ~E_4~0); 19654#L1317-1 assume !(1 == ~E_5~0); 19655#L1322-1 assume !(1 == ~E_6~0); 19387#L1327-1 assume !(1 == ~E_7~0); 19388#L1332-1 assume !(1 == ~E_8~0); 19946#L1337-1 assume !(1 == ~E_9~0); 19883#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 19884#L1347-1 assume !(1 == ~E_11~0); 20265#L1352-1 assume { :end_inline_reset_delta_events } true; 20155#L1678-2 [2021-11-13 17:45:53,285 INFO L793 eck$LassoCheckResult]: Loop: 20155#L1678-2 assume !false; 19938#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19939#L1084 assume !false; 19722#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19723#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19026#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 20040#L911 eval_#t~ret8#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret8#1;havoc eval_#t~ret8#1; 18952#L925 assume !(0 != eval_~tmp~0#1); 18954#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19068#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19069#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18923#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18924#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19998#L1119-3 assume !(0 == ~T3_E~0); 19999#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20020#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 20021#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20199#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20257#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19427#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19428#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19663#L1159-3 assume !(0 == ~T11_E~0); 19664#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19934#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19935#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19985#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19986#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 20141#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19818#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19185#L1199-3 assume !(0 == ~E_7~0); 19186#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19409#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 18871#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 18872#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 19570#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19571#L544-39 assume !(1 == ~m_pc~0); 18852#L544-41 is_master_triggered_~__retres1~0#1 := 0; 18853#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19103#L556-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19104#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 19260#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20128#L563-39 assume 1 == ~t1_pc~0; 20134#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19003#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19902#L575-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19903#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20400#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20243#L582-39 assume 1 == ~t2_pc~0; 19326#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19328#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19948#L594-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19949#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19096#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18883#L601-39 assume 1 == ~t3_pc~0; 18884#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18934#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20092#L613-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20228#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20132#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19784#L620-39 assume !(1 == ~t4_pc~0); 19785#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 19982#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20190#L632-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 20105#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20106#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20411#L639-39 assume 1 == ~t5_pc~0; 20218#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19532#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19109#L651-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18912#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18913#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19821#L658-39 assume 1 == ~t6_pc~0; 19803#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19804#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18862#L670-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 18863#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19978#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19979#L677-39 assume 1 == ~t7_pc~0; 19941#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 19087#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19088#L689-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 19143#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 19144#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19709#L696-39 assume 1 == ~t8_pc~0; 19674#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19554#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19555#L708-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 19850#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19814#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19689#L715-39 assume 1 == ~t9_pc~0; 18888#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18889#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20098#L727-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 20412#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 20027#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20028#L734-39 assume 1 == ~t10_pc~0; 19953#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 19399#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19710#L746-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 19041#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 19042#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 20290#L753-39 assume !(1 == ~t11_pc~0); 18961#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 18962#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20254#L765-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 19679#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 19680#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19781#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19782#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20052#L1242-3 assume !(1 == ~T2_E~0); 20053#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20272#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19972#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19973#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20255#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20296#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 20384#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19113#L1282-3 assume !(1 == ~T10_E~0); 19114#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 19023#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 19024#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20161#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 20162#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20350#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20408#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20074#L1322-3 assume !(1 == ~E_6~0); 20075#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19082#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19057#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 19058#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 19750#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 19878#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19879#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19005#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19270#L911-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 19984#L1697 assume !(0 == start_simulation_~tmp~3#1); 19771#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 19772#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 19129#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 19894#L911-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 19895#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 19844#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 19441#L1660 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 19442#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 20155#L1678-2 [2021-11-13 17:45:53,286 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:53,286 INFO L85 PathProgramCache]: Analyzing trace with hash -1751444930, now seen corresponding path program 1 times [2021-11-13 17:45:53,286 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:53,287 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1116830887] [2021-11-13 17:45:53,287 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:53,287 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:53,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:53,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:53,321 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:53,321 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1116830887] [2021-11-13 17:45:53,321 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1116830887] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:53,321 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:53,322 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:53,322 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2080482346] [2021-11-13 17:45:53,322 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:53,323 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:45:53,323 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:53,323 INFO L85 PathProgramCache]: Analyzing trace with hash -1367576821, now seen corresponding path program 1 times [2021-11-13 17:45:53,324 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:53,324 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1837272961] [2021-11-13 17:45:53,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:53,324 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:53,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:53,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:53,368 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:53,368 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1837272961] [2021-11-13 17:45:53,368 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1837272961] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:53,368 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:53,368 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:53,368 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1806685795] [2021-11-13 17:45:53,369 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:53,369 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:45:53,369 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:45:53,369 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 17:45:53,370 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 17:45:53,370 INFO L87 Difference]: Start difference. First operand 1566 states and 2320 transitions. cyclomatic complexity: 755 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:53,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:45:53,408 INFO L93 Difference]: Finished difference Result 1566 states and 2319 transitions. [2021-11-13 17:45:53,408 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 17:45:53,410 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2319 transitions. [2021-11-13 17:45:53,421 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:53,435 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2319 transitions. [2021-11-13 17:45:53,435 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-11-13 17:45:53,437 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-11-13 17:45:53,437 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2319 transitions. [2021-11-13 17:45:53,439 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:45:53,440 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2319 transitions. [2021-11-13 17:45:53,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2319 transitions. [2021-11-13 17:45:53,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-11-13 17:45:53,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4808429118773947) internal successors, (2319), 1565 states have internal predecessors, (2319), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:53,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2319 transitions. [2021-11-13 17:45:53,476 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2319 transitions. [2021-11-13 17:45:53,476 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2319 transitions. [2021-11-13 17:45:53,476 INFO L425 BuchiCegarLoop]: ======== Iteration 8============ [2021-11-13 17:45:53,476 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2319 transitions. [2021-11-13 17:45:53,483 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:53,483 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:45:53,483 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:45:53,485 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:53,485 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:53,486 INFO L791 eck$LassoCheckResult]: Stem: 22721#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 22722#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 23450#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 23451#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22224#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 22225#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 23460#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23425#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23426#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22573#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22574#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22980#L810-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 23398#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 22485#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 22486#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 22371#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 22372#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23326#L1109 assume !(0 == ~M_E~0); 23347#L1109-2 assume !(0 == ~T1_E~0); 22378#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22379#L1119-1 assume !(0 == ~T3_E~0); 23402#L1124-1 assume !(0 == ~T4_E~0); 22041#L1129-1 assume !(0 == ~T5_E~0); 22042#L1134-1 assume !(0 == ~T6_E~0); 22653#L1139-1 assume !(0 == ~T7_E~0); 23330#L1144-1 assume !(0 == ~T8_E~0); 23202#L1149-1 assume !(0 == ~T9_E~0); 22148#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22149#L1159-1 assume !(0 == ~T11_E~0); 23188#L1164-1 assume !(0 == ~E_M~0); 22539#L1169-1 assume !(0 == ~E_1~0); 22428#L1174-1 assume !(0 == ~E_2~0); 22304#L1179-1 assume !(0 == ~E_3~0); 22228#L1184-1 assume !(0 == ~E_4~0); 22229#L1189-1 assume !(0 == ~E_5~0); 22260#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 22349#L1199-1 assume !(0 == ~E_7~0); 23210#L1204-1 assume !(0 == ~E_8~0); 23147#L1209-1 assume !(0 == ~E_9~0); 23148#L1214-1 assume !(0 == ~E_10~0); 23472#L1219-1 assume !(0 == ~E_11~0); 23545#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22558#L544 assume 1 == ~m_pc~0; 22559#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 23389#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 23219#L556 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22192#L1379 assume !(0 != activate_threads_~tmp~1#1); 22193#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22966#L563 assume !(1 == ~t1_pc~0); 22763#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22049#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22050#L575 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23086#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 22045#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22046#L582 assume 1 == ~t2_pc~0; 22741#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 23097#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23098#L594 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23201#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 22078#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22079#L601 assume !(1 == ~t3_pc~0); 22757#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22756#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23390#L613 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23132#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 23133#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 23076#L620 assume 1 == ~t4_pc~0; 22059#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22060#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22621#L632 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 22622#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 22977#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23164#L639 assume 1 == ~t5_pc~0; 23047#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22351#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22352#L651 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22998#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 22999#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22928#L658 assume !(1 == ~t6_pc~0); 22553#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 22554#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23122#L670 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 23452#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23136#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22391#L677 assume 1 == ~t7_pc~0; 22392#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22294#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 23295#L689 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 23419#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 23420#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23491#L696 assume !(1 == ~t8_pc~0); 22611#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 22612#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 23459#L708 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 23480#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 23526#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 23030#L715 assume 1 == ~t9_pc~0; 23031#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22701#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22609#L727 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 22610#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 23019#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23291#L734 assume !(1 == ~t10_pc~0); 23292#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 22511#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22512#L746 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 22530#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 23235#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22587#L753 assume 1 == ~t11_pc~0; 22588#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 23141#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22696#L765 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 22697#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 22846#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22903#L1237 assume !(1 == ~M_E~0); 22904#L1237-2 assume !(1 == ~T1_E~0); 23516#L1242-1 assume !(1 == ~T2_E~0); 22667#L1247-1 assume !(1 == ~T3_E~0); 22668#L1252-1 assume !(1 == ~T4_E~0); 22451#L1257-1 assume !(1 == ~T5_E~0); 22452#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23307#L1267-1 assume !(1 == ~T7_E~0); 23412#L1272-1 assume !(1 == ~T8_E~0); 22750#L1277-1 assume !(1 == ~T9_E~0); 22751#L1282-1 assume !(1 == ~T10_E~0); 23173#L1287-1 assume !(1 == ~T11_E~0); 23174#L1292-1 assume !(1 == ~E_M~0); 23135#L1297-1 assume !(1 == ~E_1~0); 22582#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 22583#L1307-1 assume !(1 == ~E_3~0); 23405#L1312-1 assume !(1 == ~E_4~0); 22793#L1317-1 assume !(1 == ~E_5~0); 22794#L1322-1 assume !(1 == ~E_6~0); 22526#L1327-1 assume !(1 == ~E_7~0); 22527#L1332-1 assume !(1 == ~E_8~0); 23085#L1337-1 assume !(1 == ~E_9~0); 23022#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 23023#L1347-1 assume !(1 == ~E_11~0); 23404#L1352-1 assume { :end_inline_reset_delta_events } true; 23294#L1678-2 [2021-11-13 17:45:53,486 INFO L793 eck$LassoCheckResult]: Loop: 23294#L1678-2 assume !false; 23077#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 23078#L1084 assume !false; 22861#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22862#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22165#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 23179#L911 eval_#t~ret8#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret8#1;havoc eval_#t~ret8#1; 22091#L925 assume !(0 != eval_~tmp~0#1); 22093#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22207#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 22208#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22062#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22063#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23137#L1119-3 assume !(0 == ~T3_E~0); 23138#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23159#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23160#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23338#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23396#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 22566#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22567#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 22802#L1159-3 assume !(0 == ~T11_E~0); 22803#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 23073#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23074#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23124#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23125#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23280#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22957#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22324#L1199-3 assume !(0 == ~E_7~0); 22325#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 22548#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 22010#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 22011#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22709#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22710#L544-39 assume !(1 == ~m_pc~0); 21991#L544-41 is_master_triggered_~__retres1~0#1 := 0; 21992#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22242#L556-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22243#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 22399#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23267#L563-39 assume 1 == ~t1_pc~0; 23273#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 22142#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23041#L575-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23042#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23539#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23382#L582-39 assume 1 == ~t2_pc~0; 22465#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22467#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23087#L594-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 23088#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22235#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22022#L601-39 assume 1 == ~t3_pc~0; 22023#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22073#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23231#L613-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 23367#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 23271#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22923#L620-39 assume !(1 == ~t4_pc~0); 22924#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 23121#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23329#L632-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23244#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 23245#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23550#L639-39 assume 1 == ~t5_pc~0; 23357#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22671#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22248#L651-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 22051#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22052#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22960#L658-39 assume !(1 == ~t6_pc~0); 22944#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 22943#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22001#L670-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 22002#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23117#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 23118#L677-39 assume 1 == ~t7_pc~0; 23080#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22226#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22227#L689-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22282#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 22283#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22848#L696-39 assume 1 == ~t8_pc~0; 22813#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 22693#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22694#L708-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 22989#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22953#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22828#L715-39 assume 1 == ~t9_pc~0; 22027#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 22028#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23237#L727-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 23551#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 23166#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23167#L734-39 assume 1 == ~t10_pc~0; 23092#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 22538#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 22849#L746-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 22180#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 22181#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 23429#L753-39 assume !(1 == ~t11_pc~0); 22100#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 22101#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 23393#L765-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 22818#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 22819#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22920#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22921#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23191#L1242-3 assume !(1 == ~T2_E~0); 23192#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23411#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23111#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23112#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23394#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 23435#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 23523#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22252#L1282-3 assume !(1 == ~T10_E~0); 22253#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 22162#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22163#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 23300#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23301#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23489#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23547#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23213#L1322-3 assume !(1 == ~E_6~0); 23214#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22221#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 22196#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 22197#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 22889#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 23017#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 23018#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22144#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 22409#L911-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 23123#L1697 assume !(0 == start_simulation_~tmp~3#1); 22910#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 22911#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 22268#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 23033#L911-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 23034#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22983#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22580#L1660 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 22581#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 23294#L1678-2 [2021-11-13 17:45:53,487 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:53,487 INFO L85 PathProgramCache]: Analyzing trace with hash -803392964, now seen corresponding path program 1 times [2021-11-13 17:45:53,487 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:53,488 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [859108798] [2021-11-13 17:45:53,488 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:53,488 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:53,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:53,533 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:53,533 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:53,533 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [859108798] [2021-11-13 17:45:53,534 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [859108798] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:53,535 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:53,535 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:53,535 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1731593920] [2021-11-13 17:45:53,536 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:53,536 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:45:53,536 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:53,537 INFO L85 PathProgramCache]: Analyzing trace with hash 764411212, now seen corresponding path program 2 times [2021-11-13 17:45:53,537 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:53,537 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1690913400] [2021-11-13 17:45:53,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:53,537 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:53,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:53,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:53,620 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:53,621 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1690913400] [2021-11-13 17:45:53,621 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1690913400] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:53,621 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:53,621 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:53,622 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1275102212] [2021-11-13 17:45:53,622 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:53,622 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:45:53,623 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:45:53,623 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 17:45:53,623 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 17:45:53,623 INFO L87 Difference]: Start difference. First operand 1566 states and 2319 transitions. cyclomatic complexity: 754 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:53,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:45:53,666 INFO L93 Difference]: Finished difference Result 1566 states and 2318 transitions. [2021-11-13 17:45:53,666 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 17:45:53,669 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2318 transitions. [2021-11-13 17:45:53,680 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:53,695 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2318 transitions. [2021-11-13 17:45:53,695 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-11-13 17:45:53,700 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-11-13 17:45:53,700 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2318 transitions. [2021-11-13 17:45:53,702 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:45:53,703 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2318 transitions. [2021-11-13 17:45:53,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2318 transitions. [2021-11-13 17:45:53,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-11-13 17:45:53,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4802043422733078) internal successors, (2318), 1565 states have internal predecessors, (2318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:53,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2318 transitions. [2021-11-13 17:45:53,754 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2318 transitions. [2021-11-13 17:45:53,754 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2318 transitions. [2021-11-13 17:45:53,754 INFO L425 BuchiCegarLoop]: ======== Iteration 9============ [2021-11-13 17:45:53,754 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2318 transitions. [2021-11-13 17:45:53,761 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:53,762 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:45:53,762 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:45:53,765 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:53,765 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:53,765 INFO L791 eck$LassoCheckResult]: Stem: 25860#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 25861#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 26589#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 26590#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25363#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 25364#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26599#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26564#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26565#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25712#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25713#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26119#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 26537#L815-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25624#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25625#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25510#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25511#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26463#L1109 assume !(0 == ~M_E~0); 26485#L1109-2 assume !(0 == ~T1_E~0); 25517#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25518#L1119-1 assume !(0 == ~T3_E~0); 26541#L1124-1 assume !(0 == ~T4_E~0); 25180#L1129-1 assume !(0 == ~T5_E~0); 25181#L1134-1 assume !(0 == ~T6_E~0); 25792#L1139-1 assume !(0 == ~T7_E~0); 26469#L1144-1 assume !(0 == ~T8_E~0); 26341#L1149-1 assume !(0 == ~T9_E~0); 25287#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25288#L1159-1 assume !(0 == ~T11_E~0); 26327#L1164-1 assume !(0 == ~E_M~0); 25678#L1169-1 assume !(0 == ~E_1~0); 25567#L1174-1 assume !(0 == ~E_2~0); 25440#L1179-1 assume !(0 == ~E_3~0); 25367#L1184-1 assume !(0 == ~E_4~0); 25368#L1189-1 assume !(0 == ~E_5~0); 25399#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 25486#L1199-1 assume !(0 == ~E_7~0); 26349#L1204-1 assume !(0 == ~E_8~0); 26285#L1209-1 assume !(0 == ~E_9~0); 26286#L1214-1 assume !(0 == ~E_10~0); 26611#L1219-1 assume !(0 == ~E_11~0); 26684#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25695#L544 assume 1 == ~m_pc~0; 25696#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 26528#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 26356#L556 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25329#L1379 assume !(0 != activate_threads_~tmp~1#1); 25330#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26102#L563 assume !(1 == ~t1_pc~0); 25902#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25188#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25189#L575 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26225#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 25184#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25185#L582 assume 1 == ~t2_pc~0; 25880#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 26235#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26236#L594 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26340#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 25217#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25218#L601 assume !(1 == ~t3_pc~0); 25896#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25895#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26529#L613 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26271#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 26272#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26215#L620 assume 1 == ~t4_pc~0; 25198#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25199#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25760#L632 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25761#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 26116#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26304#L639 assume 1 == ~t5_pc~0; 26187#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25490#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25491#L651 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 26137#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 26138#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26067#L658 assume !(1 == ~t6_pc~0); 25692#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25693#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 26262#L670 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 26591#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26275#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25530#L677 assume 1 == ~t7_pc~0; 25531#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25433#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 26434#L689 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26558#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 26559#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26630#L696 assume !(1 == ~t8_pc~0); 25751#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 25752#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 26598#L708 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26619#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 26665#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 26169#L715 assume 1 == ~t9_pc~0; 26170#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25840#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 25748#L727 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25749#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 26158#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26431#L734 assume !(1 == ~t10_pc~0); 26432#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 25650#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25651#L746 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25669#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 26374#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25726#L753 assume 1 == ~t11_pc~0; 25727#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 26280#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 25835#L765 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25836#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 25987#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26042#L1237 assume !(1 == ~M_E~0); 26043#L1237-2 assume !(1 == ~T1_E~0); 26656#L1242-1 assume !(1 == ~T2_E~0); 25806#L1247-1 assume !(1 == ~T3_E~0); 25807#L1252-1 assume !(1 == ~T4_E~0); 25590#L1257-1 assume !(1 == ~T5_E~0); 25591#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26446#L1267-1 assume !(1 == ~T7_E~0); 26551#L1272-1 assume !(1 == ~T8_E~0); 25889#L1277-1 assume !(1 == ~T9_E~0); 25890#L1282-1 assume !(1 == ~T10_E~0); 26312#L1287-1 assume !(1 == ~T11_E~0); 26313#L1292-1 assume !(1 == ~E_M~0); 26274#L1297-1 assume !(1 == ~E_1~0); 25721#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 25722#L1307-1 assume !(1 == ~E_3~0); 26544#L1312-1 assume !(1 == ~E_4~0); 25932#L1317-1 assume !(1 == ~E_5~0); 25933#L1322-1 assume !(1 == ~E_6~0); 25665#L1327-1 assume !(1 == ~E_7~0); 25666#L1332-1 assume !(1 == ~E_8~0); 26224#L1337-1 assume !(1 == ~E_9~0); 26161#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 26162#L1347-1 assume !(1 == ~E_11~0); 26543#L1352-1 assume { :end_inline_reset_delta_events } true; 26430#L1678-2 [2021-11-13 17:45:53,766 INFO L793 eck$LassoCheckResult]: Loop: 26430#L1678-2 assume !false; 26216#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 26217#L1084 assume !false; 26001#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26002#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25304#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 26319#L911 eval_#t~ret8#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret8#1;havoc eval_#t~ret8#1; 25230#L925 assume !(0 != eval_~tmp~0#1); 25232#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25346#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25347#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25201#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25202#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26276#L1119-3 assume !(0 == ~T3_E~0); 26277#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26298#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26299#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 26477#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 26535#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25705#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 25706#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 25942#L1159-3 assume !(0 == ~T11_E~0); 25943#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 26212#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26213#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 26263#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 26264#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26419#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26096#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25466#L1199-3 assume !(0 == ~E_7~0); 25467#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25691#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25152#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25153#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 25848#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25849#L544-39 assume !(1 == ~m_pc~0); 25130#L544-41 is_master_triggered_~__retres1~0#1 := 0; 25131#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25381#L556-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25382#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 25538#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 26406#L563-39 assume !(1 == ~t1_pc~0); 25283#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 25284#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 26180#L575-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 26181#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 26678#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26521#L582-39 assume 1 == ~t2_pc~0; 25604#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 25606#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 26226#L594-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26227#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25376#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25161#L601-39 assume 1 == ~t3_pc~0; 25162#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25212#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26370#L613-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26506#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26410#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26064#L620-39 assume !(1 == ~t4_pc~0); 26065#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 26260#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 26468#L632-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 26383#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26384#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 26689#L639-39 assume 1 == ~t5_pc~0; 26496#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25810#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25387#L651-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25190#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25191#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26099#L658-39 assume 1 == ~t6_pc~0; 26081#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 26082#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25138#L670-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25139#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 26256#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26257#L677-39 assume 1 == ~t7_pc~0; 26219#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 25365#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25366#L689-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25421#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 25422#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25986#L696-39 assume 1 == ~t8_pc~0; 25952#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 25832#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25833#L708-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 26128#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 26092#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25967#L715-39 assume 1 == ~t9_pc~0; 25164#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 25165#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26376#L727-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 26690#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 26305#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 26306#L734-39 assume 1 == ~t10_pc~0; 26231#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 25677#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25988#L746-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25319#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25320#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26568#L753-39 assume !(1 == ~t11_pc~0); 25239#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 25240#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26532#L765-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 25957#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 25958#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26055#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 26056#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26330#L1242-3 assume !(1 == ~T2_E~0); 26331#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26550#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26250#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 26251#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 26533#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26574#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 26662#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 25390#L1282-3 assume !(1 == ~T10_E~0); 25391#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25301#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25302#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26438#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 26439#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26628#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 26686#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 26352#L1322-3 assume !(1 == ~E_6~0); 26353#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 25360#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 25335#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25336#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 26028#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 26156#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26157#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25278#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 25548#L911-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 26261#L1697 assume !(0 == start_simulation_~tmp~3#1); 26049#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 26050#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 25407#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 26172#L911-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 26173#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26122#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25717#L1660 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 25718#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 26430#L1678-2 [2021-11-13 17:45:53,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:53,767 INFO L85 PathProgramCache]: Analyzing trace with hash -218621314, now seen corresponding path program 1 times [2021-11-13 17:45:53,767 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:53,767 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1402020543] [2021-11-13 17:45:53,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:53,768 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:53,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:53,804 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:53,804 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:53,805 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1402020543] [2021-11-13 17:45:53,805 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1402020543] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:53,805 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:53,805 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:53,805 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2012819178] [2021-11-13 17:45:53,806 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:53,806 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:45:53,807 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:53,807 INFO L85 PathProgramCache]: Analyzing trace with hash 947803532, now seen corresponding path program 1 times [2021-11-13 17:45:53,807 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:53,807 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1173201593] [2021-11-13 17:45:53,807 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:53,808 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:53,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:53,853 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:53,854 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:53,854 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1173201593] [2021-11-13 17:45:53,854 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1173201593] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:53,854 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:53,854 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:53,855 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2105823222] [2021-11-13 17:45:53,855 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:53,855 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:45:53,855 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:45:53,856 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 17:45:53,856 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 17:45:53,857 INFO L87 Difference]: Start difference. First operand 1566 states and 2318 transitions. cyclomatic complexity: 753 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:53,902 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:45:53,902 INFO L93 Difference]: Finished difference Result 1566 states and 2317 transitions. [2021-11-13 17:45:53,903 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 17:45:53,904 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2317 transitions. [2021-11-13 17:45:53,915 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:53,929 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2317 transitions. [2021-11-13 17:45:53,929 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-11-13 17:45:53,931 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-11-13 17:45:53,931 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2317 transitions. [2021-11-13 17:45:53,934 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:45:53,934 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2317 transitions. [2021-11-13 17:45:53,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2317 transitions. [2021-11-13 17:45:53,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-11-13 17:45:53,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4795657726692208) internal successors, (2317), 1565 states have internal predecessors, (2317), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:53,974 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2317 transitions. [2021-11-13 17:45:53,975 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2317 transitions. [2021-11-13 17:45:53,975 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2317 transitions. [2021-11-13 17:45:53,975 INFO L425 BuchiCegarLoop]: ======== Iteration 10============ [2021-11-13 17:45:53,975 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2317 transitions. [2021-11-13 17:45:53,983 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:53,983 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:45:53,983 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:45:53,986 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:53,986 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:53,987 INFO L791 eck$LassoCheckResult]: Stem: 28999#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 29000#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 29728#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29729#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28502#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 28503#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29738#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29703#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29704#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 28851#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28852#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29258#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29676#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 28763#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28764#L825-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 28649#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 28650#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29602#L1109 assume !(0 == ~M_E~0); 29624#L1109-2 assume !(0 == ~T1_E~0); 28656#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28657#L1119-1 assume !(0 == ~T3_E~0); 29680#L1124-1 assume !(0 == ~T4_E~0); 28317#L1129-1 assume !(0 == ~T5_E~0); 28318#L1134-1 assume !(0 == ~T6_E~0); 28931#L1139-1 assume !(0 == ~T7_E~0); 29608#L1144-1 assume !(0 == ~T8_E~0); 29480#L1149-1 assume !(0 == ~T9_E~0); 28424#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28425#L1159-1 assume !(0 == ~T11_E~0); 29466#L1164-1 assume !(0 == ~E_M~0); 28817#L1169-1 assume !(0 == ~E_1~0); 28706#L1174-1 assume !(0 == ~E_2~0); 28579#L1179-1 assume !(0 == ~E_3~0); 28506#L1184-1 assume !(0 == ~E_4~0); 28507#L1189-1 assume !(0 == ~E_5~0); 28538#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 28625#L1199-1 assume !(0 == ~E_7~0); 29488#L1204-1 assume !(0 == ~E_8~0); 29424#L1209-1 assume !(0 == ~E_9~0); 29425#L1214-1 assume !(0 == ~E_10~0); 29750#L1219-1 assume !(0 == ~E_11~0); 29823#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28834#L544 assume 1 == ~m_pc~0; 28835#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29667#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29495#L556 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28468#L1379 assume !(0 != activate_threads_~tmp~1#1); 28469#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29241#L563 assume !(1 == ~t1_pc~0); 29041#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 28327#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 28328#L575 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29364#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 28323#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 28324#L582 assume 1 == ~t2_pc~0; 29019#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29374#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29375#L594 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29479#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 28356#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28357#L601 assume !(1 == ~t3_pc~0); 29035#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29034#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29668#L613 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29410#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 29411#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29354#L620 assume 1 == ~t4_pc~0; 28337#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 28338#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28899#L632 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28900#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 29255#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29442#L639 assume 1 == ~t5_pc~0; 29325#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28629#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28630#L651 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29276#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 29277#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29206#L658 assume !(1 == ~t6_pc~0); 28831#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 28832#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29400#L670 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29730#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29414#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28669#L677 assume 1 == ~t7_pc~0; 28670#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28572#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29573#L689 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29697#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 29698#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29769#L696 assume !(1 == ~t8_pc~0); 28889#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 28890#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29737#L708 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29758#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 29804#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29308#L715 assume 1 == ~t9_pc~0; 29309#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28979#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28887#L727 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 28888#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 29297#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29569#L734 assume !(1 == ~t10_pc~0); 29570#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28789#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28790#L746 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28808#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 29513#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 28865#L753 assume 1 == ~t11_pc~0; 28866#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29419#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28974#L765 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28975#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 29124#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29181#L1237 assume !(1 == ~M_E~0); 29182#L1237-2 assume !(1 == ~T1_E~0); 29794#L1242-1 assume !(1 == ~T2_E~0); 28945#L1247-1 assume !(1 == ~T3_E~0); 28946#L1252-1 assume !(1 == ~T4_E~0); 28729#L1257-1 assume !(1 == ~T5_E~0); 28730#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29585#L1267-1 assume !(1 == ~T7_E~0); 29690#L1272-1 assume !(1 == ~T8_E~0); 29028#L1277-1 assume !(1 == ~T9_E~0); 29029#L1282-1 assume !(1 == ~T10_E~0); 29451#L1287-1 assume !(1 == ~T11_E~0); 29452#L1292-1 assume !(1 == ~E_M~0); 29413#L1297-1 assume !(1 == ~E_1~0); 28860#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 28861#L1307-1 assume !(1 == ~E_3~0); 29683#L1312-1 assume !(1 == ~E_4~0); 29071#L1317-1 assume !(1 == ~E_5~0); 29072#L1322-1 assume !(1 == ~E_6~0); 28804#L1327-1 assume !(1 == ~E_7~0); 28805#L1332-1 assume !(1 == ~E_8~0); 29363#L1337-1 assume !(1 == ~E_9~0); 29300#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 29301#L1347-1 assume !(1 == ~E_11~0); 29682#L1352-1 assume { :end_inline_reset_delta_events } true; 29572#L1678-2 [2021-11-13 17:45:53,988 INFO L793 eck$LassoCheckResult]: Loop: 29572#L1678-2 assume !false; 29355#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29356#L1084 assume !false; 29139#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29140#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28443#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29457#L911 eval_#t~ret8#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret8#1;havoc eval_#t~ret8#1; 28369#L925 assume !(0 != eval_~tmp~0#1); 28371#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28485#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28486#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28340#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28341#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29415#L1119-3 assume !(0 == ~T3_E~0); 29416#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29437#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29438#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29616#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29674#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28844#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28845#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 29080#L1159-3 assume !(0 == ~T11_E~0); 29081#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29351#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29352#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29402#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29403#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29558#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29235#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 28602#L1199-3 assume !(0 == ~E_7~0); 28603#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28826#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 28288#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 28289#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 28987#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 28988#L544-39 assume !(1 == ~m_pc~0); 28269#L544-41 is_master_triggered_~__retres1~0#1 := 0; 28270#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 28520#L556-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28521#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 28677#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29545#L563-39 assume !(1 == ~t1_pc~0); 28419#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 28420#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29319#L575-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29320#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29817#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29660#L582-39 assume 1 == ~t2_pc~0; 28743#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28745#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29365#L594-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29366#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 28513#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28300#L601-39 assume 1 == ~t3_pc~0; 28301#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 28351#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29509#L613-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 29645#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29549#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29201#L620-39 assume !(1 == ~t4_pc~0); 29202#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 29399#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29607#L632-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29522#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29523#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29828#L639-39 assume 1 == ~t5_pc~0; 29635#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28949#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28526#L651-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28329#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 28330#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29238#L658-39 assume 1 == ~t6_pc~0; 29220#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29221#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28279#L670-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28280#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29395#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29396#L677-39 assume !(1 == ~t7_pc~0); 29026#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 28504#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28505#L689-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 28560#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 28561#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29126#L696-39 assume 1 == ~t8_pc~0; 29091#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28971#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28972#L708-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29267#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 29231#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29106#L715-39 assume 1 == ~t9_pc~0; 28305#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28306#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 29515#L727-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29829#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 29444#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29445#L734-39 assume 1 == ~t10_pc~0; 29370#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28816#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 29127#L746-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28458#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28459#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29707#L753-39 assume !(1 == ~t11_pc~0); 28378#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 28379#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 29671#L765-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 29096#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 29097#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29198#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29199#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29469#L1242-3 assume !(1 == ~T2_E~0); 29470#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29689#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29389#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 29390#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 29672#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 29713#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 29801#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28530#L1282-3 assume !(1 == ~T10_E~0); 28531#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28440#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 28441#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29578#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29579#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 29767#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29825#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 29491#L1322-3 assume !(1 == ~E_6~0); 29492#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28499#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28474#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28475#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 29167#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29295#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29296#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28422#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 28687#L911-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 29401#L1697 assume !(0 == start_simulation_~tmp~3#1); 29188#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 29189#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 28546#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 29311#L911-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 29312#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29261#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28858#L1660 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 28859#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 29572#L1678-2 [2021-11-13 17:45:53,989 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:53,989 INFO L85 PathProgramCache]: Analyzing trace with hash 215884284, now seen corresponding path program 1 times [2021-11-13 17:45:53,989 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:53,989 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [192908662] [2021-11-13 17:45:53,989 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:53,990 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:54,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:54,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:54,027 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:54,027 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [192908662] [2021-11-13 17:45:54,027 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [192908662] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:54,027 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:54,027 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:54,028 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [697787284] [2021-11-13 17:45:54,028 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:54,029 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:45:54,030 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:54,030 INFO L85 PathProgramCache]: Analyzing trace with hash -1209669491, now seen corresponding path program 1 times [2021-11-13 17:45:54,030 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:54,030 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [521191412] [2021-11-13 17:45:54,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:54,031 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:54,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:54,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:54,086 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:54,086 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [521191412] [2021-11-13 17:45:54,086 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [521191412] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:54,087 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:54,087 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:54,087 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [246376917] [2021-11-13 17:45:54,087 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:54,088 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:45:54,088 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:45:54,088 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 17:45:54,088 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 17:45:54,089 INFO L87 Difference]: Start difference. First operand 1566 states and 2317 transitions. cyclomatic complexity: 752 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:54,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:45:54,136 INFO L93 Difference]: Finished difference Result 1566 states and 2316 transitions. [2021-11-13 17:45:54,136 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 17:45:54,137 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2316 transitions. [2021-11-13 17:45:54,147 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:54,160 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2316 transitions. [2021-11-13 17:45:54,160 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-11-13 17:45:54,162 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-11-13 17:45:54,163 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2316 transitions. [2021-11-13 17:45:54,165 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:45:54,165 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2316 transitions. [2021-11-13 17:45:54,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2316 transitions. [2021-11-13 17:45:54,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-11-13 17:45:54,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4789272030651341) internal successors, (2316), 1565 states have internal predecessors, (2316), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:54,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2316 transitions. [2021-11-13 17:45:54,203 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2316 transitions. [2021-11-13 17:45:54,203 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2316 transitions. [2021-11-13 17:45:54,203 INFO L425 BuchiCegarLoop]: ======== Iteration 11============ [2021-11-13 17:45:54,204 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2316 transitions. [2021-11-13 17:45:54,211 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:54,211 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:45:54,212 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:45:54,215 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:54,215 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:54,215 INFO L791 eck$LassoCheckResult]: Stem: 32138#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 32139#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 32867#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 32868#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 31641#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 31642#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32877#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32842#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32843#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 31990#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 31991#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 32397#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 32815#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 31902#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 31903#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 31788#L830-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 31789#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32741#L1109 assume !(0 == ~M_E~0); 32763#L1109-2 assume !(0 == ~T1_E~0); 31795#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31796#L1119-1 assume !(0 == ~T3_E~0); 32819#L1124-1 assume !(0 == ~T4_E~0); 31456#L1129-1 assume !(0 == ~T5_E~0); 31457#L1134-1 assume !(0 == ~T6_E~0); 32070#L1139-1 assume !(0 == ~T7_E~0); 32747#L1144-1 assume !(0 == ~T8_E~0); 32619#L1149-1 assume !(0 == ~T9_E~0); 31563#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 31564#L1159-1 assume !(0 == ~T11_E~0); 32605#L1164-1 assume !(0 == ~E_M~0); 31956#L1169-1 assume !(0 == ~E_1~0); 31845#L1174-1 assume !(0 == ~E_2~0); 31718#L1179-1 assume !(0 == ~E_3~0); 31645#L1184-1 assume !(0 == ~E_4~0); 31646#L1189-1 assume !(0 == ~E_5~0); 31677#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 31764#L1199-1 assume !(0 == ~E_7~0); 32627#L1204-1 assume !(0 == ~E_8~0); 32563#L1209-1 assume !(0 == ~E_9~0); 32564#L1214-1 assume !(0 == ~E_10~0); 32889#L1219-1 assume !(0 == ~E_11~0); 32962#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 31973#L544 assume 1 == ~m_pc~0; 31974#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 32806#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 32634#L556 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31607#L1379 assume !(0 != activate_threads_~tmp~1#1); 31608#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32380#L563 assume !(1 == ~t1_pc~0); 32180#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 31466#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 31467#L575 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32503#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 31462#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 31463#L582 assume 1 == ~t2_pc~0; 32158#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32513#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32514#L594 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32618#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 31495#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31496#L601 assume !(1 == ~t3_pc~0); 32174#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 32173#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32807#L613 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32549#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 32550#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32493#L620 assume 1 == ~t4_pc~0; 31476#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 31477#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32038#L632 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32039#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 32394#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32581#L639 assume 1 == ~t5_pc~0; 32464#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 31768#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31769#L651 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32415#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 32416#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32345#L658 assume !(1 == ~t6_pc~0); 31970#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 31971#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32539#L670 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32869#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32553#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 31808#L677 assume 1 == ~t7_pc~0; 31809#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31711#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 32712#L689 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 32836#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 32837#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32908#L696 assume !(1 == ~t8_pc~0); 32028#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 32029#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32876#L708 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32897#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 32943#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32447#L715 assume 1 == ~t9_pc~0; 32448#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32118#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32026#L727 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32027#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 32436#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32708#L734 assume !(1 == ~t10_pc~0); 32709#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 31928#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 31929#L746 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31947#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 32652#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32004#L753 assume 1 == ~t11_pc~0; 32005#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 32558#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32113#L765 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32114#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 32263#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32320#L1237 assume !(1 == ~M_E~0); 32321#L1237-2 assume !(1 == ~T1_E~0); 32933#L1242-1 assume !(1 == ~T2_E~0); 32084#L1247-1 assume !(1 == ~T3_E~0); 32085#L1252-1 assume !(1 == ~T4_E~0); 31868#L1257-1 assume !(1 == ~T5_E~0); 31869#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32724#L1267-1 assume !(1 == ~T7_E~0); 32829#L1272-1 assume !(1 == ~T8_E~0); 32167#L1277-1 assume !(1 == ~T9_E~0); 32168#L1282-1 assume !(1 == ~T10_E~0); 32590#L1287-1 assume !(1 == ~T11_E~0); 32591#L1292-1 assume !(1 == ~E_M~0); 32552#L1297-1 assume !(1 == ~E_1~0); 31999#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 32000#L1307-1 assume !(1 == ~E_3~0); 32822#L1312-1 assume !(1 == ~E_4~0); 32210#L1317-1 assume !(1 == ~E_5~0); 32211#L1322-1 assume !(1 == ~E_6~0); 31943#L1327-1 assume !(1 == ~E_7~0); 31944#L1332-1 assume !(1 == ~E_8~0); 32502#L1337-1 assume !(1 == ~E_9~0); 32439#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 32440#L1347-1 assume !(1 == ~E_11~0); 32821#L1352-1 assume { :end_inline_reset_delta_events } true; 32711#L1678-2 [2021-11-13 17:45:54,216 INFO L793 eck$LassoCheckResult]: Loop: 32711#L1678-2 assume !false; 32494#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 32495#L1084 assume !false; 32278#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32279#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31582#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32596#L911 eval_#t~ret8#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret8#1;havoc eval_#t~ret8#1; 31508#L925 assume !(0 != eval_~tmp~0#1); 31510#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 31624#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 31625#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 31479#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31480#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 32554#L1119-3 assume !(0 == ~T3_E~0); 32555#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32576#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32577#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 32755#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32813#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 31983#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 31984#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 32219#L1159-3 assume !(0 == ~T11_E~0); 32220#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32490#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32491#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 32541#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32542#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32697#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32374#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31741#L1199-3 assume !(0 == ~E_7~0); 31742#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 31965#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 31427#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 31428#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 32126#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 32127#L544-39 assume !(1 == ~m_pc~0); 31408#L544-41 is_master_triggered_~__retres1~0#1 := 0; 31409#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 31659#L556-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 31660#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 31816#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 32684#L563-39 assume 1 == ~t1_pc~0; 32690#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 31559#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32458#L575-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 32459#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 32956#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 32799#L582-39 assume 1 == ~t2_pc~0; 31882#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 31884#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32504#L594-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 32505#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 31652#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 31439#L601-39 assume 1 == ~t3_pc~0; 31440#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 31490#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32648#L613-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32784#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32688#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32340#L620-39 assume !(1 == ~t4_pc~0); 32341#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 32538#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32746#L632-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 32661#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32662#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32967#L639-39 assume 1 == ~t5_pc~0; 32774#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32088#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 31665#L651-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 31468#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 31469#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32377#L658-39 assume 1 == ~t6_pc~0; 32359#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32360#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 31418#L670-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 31419#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32534#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 32535#L677-39 assume 1 == ~t7_pc~0; 32497#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 31643#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 31644#L689-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 31699#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 31700#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32265#L696-39 assume 1 == ~t8_pc~0; 32230#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32110#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32111#L708-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 32406#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32370#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32245#L715-39 assume 1 == ~t9_pc~0; 31444#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 31445#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32654#L727-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 32968#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 32583#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32584#L734-39 assume !(1 == ~t10_pc~0); 31954#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 31955#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 32266#L746-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 31597#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 31598#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 32846#L753-39 assume !(1 == ~t11_pc~0); 31517#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 31518#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32810#L765-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32235#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 32236#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32337#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32338#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32608#L1242-3 assume !(1 == ~T2_E~0); 32609#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 32828#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32528#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32529#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32811#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 32852#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 32940#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 31669#L1282-3 assume !(1 == ~T10_E~0); 31670#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 31579#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 31580#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32717#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32718#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 32906#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32964#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32630#L1322-3 assume !(1 == ~E_6~0); 32631#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 31638#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 31613#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 31614#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 32306#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 32434#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32435#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31561#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 31826#L911-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 32540#L1697 assume !(0 == start_simulation_~tmp~3#1); 32327#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 32328#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 31685#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 32450#L911-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 32451#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 32400#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31997#L1660 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 31998#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 32711#L1678-2 [2021-11-13 17:45:54,217 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:54,217 INFO L85 PathProgramCache]: Analyzing trace with hash 922480890, now seen corresponding path program 1 times [2021-11-13 17:45:54,218 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:54,218 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [891798808] [2021-11-13 17:45:54,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:54,218 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:54,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:54,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:54,269 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:54,269 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [891798808] [2021-11-13 17:45:54,269 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [891798808] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:54,269 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:54,270 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:54,270 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1671859499] [2021-11-13 17:45:54,270 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:54,270 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:45:54,271 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:54,271 INFO L85 PathProgramCache]: Analyzing trace with hash 100626508, now seen corresponding path program 2 times [2021-11-13 17:45:54,271 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:54,272 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [511073548] [2021-11-13 17:45:54,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:54,272 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:54,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:54,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:54,321 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:54,322 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [511073548] [2021-11-13 17:45:54,322 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [511073548] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:54,322 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:54,322 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:54,322 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [341033190] [2021-11-13 17:45:54,323 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:54,323 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:45:54,323 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:45:54,324 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 17:45:54,324 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 17:45:54,325 INFO L87 Difference]: Start difference. First operand 1566 states and 2316 transitions. cyclomatic complexity: 751 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:54,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:45:54,362 INFO L93 Difference]: Finished difference Result 1566 states and 2315 transitions. [2021-11-13 17:45:54,362 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 17:45:54,363 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2315 transitions. [2021-11-13 17:45:54,372 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:54,384 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2315 transitions. [2021-11-13 17:45:54,384 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-11-13 17:45:54,386 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-11-13 17:45:54,387 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2315 transitions. [2021-11-13 17:45:54,389 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:45:54,390 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2315 transitions. [2021-11-13 17:45:54,393 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2315 transitions. [2021-11-13 17:45:54,421 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-11-13 17:45:54,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4782886334610472) internal successors, (2315), 1565 states have internal predecessors, (2315), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:54,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2315 transitions. [2021-11-13 17:45:54,431 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2315 transitions. [2021-11-13 17:45:54,431 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2315 transitions. [2021-11-13 17:45:54,431 INFO L425 BuchiCegarLoop]: ======== Iteration 12============ [2021-11-13 17:45:54,432 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2315 transitions. [2021-11-13 17:45:54,438 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:54,439 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:45:54,439 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:45:54,441 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:54,442 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:54,442 INFO L791 eck$LassoCheckResult]: Stem: 35277#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 35278#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 36006#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 36007#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34780#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 34781#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 36016#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35981#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35982#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35129#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35130#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35536#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35954#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35041#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35042#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 34927#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 34928#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35880#L1109 assume !(0 == ~M_E~0); 35902#L1109-2 assume !(0 == ~T1_E~0); 34934#L1114-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 34935#L1119-1 assume !(0 == ~T3_E~0); 35958#L1124-1 assume !(0 == ~T4_E~0); 34595#L1129-1 assume !(0 == ~T5_E~0); 34596#L1134-1 assume !(0 == ~T6_E~0); 35209#L1139-1 assume !(0 == ~T7_E~0); 35886#L1144-1 assume !(0 == ~T8_E~0); 35758#L1149-1 assume !(0 == ~T9_E~0); 34702#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 34703#L1159-1 assume !(0 == ~T11_E~0); 35744#L1164-1 assume !(0 == ~E_M~0); 35095#L1169-1 assume !(0 == ~E_1~0); 34984#L1174-1 assume !(0 == ~E_2~0); 34857#L1179-1 assume !(0 == ~E_3~0); 34784#L1184-1 assume !(0 == ~E_4~0); 34785#L1189-1 assume !(0 == ~E_5~0); 34816#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 34903#L1199-1 assume !(0 == ~E_7~0); 35766#L1204-1 assume !(0 == ~E_8~0); 35702#L1209-1 assume !(0 == ~E_9~0); 35703#L1214-1 assume !(0 == ~E_10~0); 36028#L1219-1 assume !(0 == ~E_11~0); 36101#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35112#L544 assume 1 == ~m_pc~0; 35113#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 35945#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35773#L556 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34746#L1379 assume !(0 != activate_threads_~tmp~1#1); 34747#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35519#L563 assume !(1 == ~t1_pc~0); 35319#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34605#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34606#L575 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35642#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 34601#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34602#L582 assume 1 == ~t2_pc~0; 35297#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35652#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35653#L594 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35757#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 34634#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34635#L601 assume !(1 == ~t3_pc~0); 35313#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 35312#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35946#L613 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35688#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 35689#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35632#L620 assume 1 == ~t4_pc~0; 34615#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 34616#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35177#L632 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35178#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 35533#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 35720#L639 assume 1 == ~t5_pc~0; 35603#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34907#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34908#L651 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35554#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 35555#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35484#L658 assume !(1 == ~t6_pc~0); 35109#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 35110#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 35678#L670 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 36008#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35692#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34947#L677 assume 1 == ~t7_pc~0; 34948#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34850#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35851#L689 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 35975#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 35976#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36047#L696 assume !(1 == ~t8_pc~0); 35167#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 35168#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36015#L708 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 36036#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 36082#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35586#L715 assume 1 == ~t9_pc~0; 35587#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35257#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35165#L727 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 35166#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 35575#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35847#L734 assume !(1 == ~t10_pc~0); 35848#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 35067#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35068#L746 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 35086#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 35791#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35143#L753 assume 1 == ~t11_pc~0; 35144#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 35697#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35252#L765 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 35253#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 35402#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35459#L1237 assume !(1 == ~M_E~0); 35460#L1237-2 assume !(1 == ~T1_E~0); 36072#L1242-1 assume !(1 == ~T2_E~0); 35223#L1247-1 assume !(1 == ~T3_E~0); 35224#L1252-1 assume !(1 == ~T4_E~0); 35007#L1257-1 assume !(1 == ~T5_E~0); 35008#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35863#L1267-1 assume !(1 == ~T7_E~0); 35968#L1272-1 assume !(1 == ~T8_E~0); 35306#L1277-1 assume !(1 == ~T9_E~0); 35307#L1282-1 assume !(1 == ~T10_E~0); 35729#L1287-1 assume !(1 == ~T11_E~0); 35730#L1292-1 assume !(1 == ~E_M~0); 35691#L1297-1 assume !(1 == ~E_1~0); 35138#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 35139#L1307-1 assume !(1 == ~E_3~0); 35961#L1312-1 assume !(1 == ~E_4~0); 35349#L1317-1 assume !(1 == ~E_5~0); 35350#L1322-1 assume !(1 == ~E_6~0); 35082#L1327-1 assume !(1 == ~E_7~0); 35083#L1332-1 assume !(1 == ~E_8~0); 35641#L1337-1 assume !(1 == ~E_9~0); 35578#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 35579#L1347-1 assume !(1 == ~E_11~0); 35960#L1352-1 assume { :end_inline_reset_delta_events } true; 35850#L1678-2 [2021-11-13 17:45:54,443 INFO L793 eck$LassoCheckResult]: Loop: 35850#L1678-2 assume !false; 35633#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35634#L1084 assume !false; 35417#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35418#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34721#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35735#L911 eval_#t~ret8#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret8#1;havoc eval_#t~ret8#1; 34647#L925 assume !(0 != eval_~tmp~0#1); 34649#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 34763#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 34764#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 34618#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 34619#L1114-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35693#L1119-3 assume !(0 == ~T3_E~0); 35694#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35715#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 35716#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 35894#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35952#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 35122#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 35123#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 35358#L1159-3 assume !(0 == ~T11_E~0); 35359#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 35629#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35630#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35680#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35681#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35836#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 35513#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34880#L1199-3 assume !(0 == ~E_7~0); 34881#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35104#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 34566#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 34567#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 35265#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 35266#L544-39 assume !(1 == ~m_pc~0); 34547#L544-41 is_master_triggered_~__retres1~0#1 := 0; 34548#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34798#L556-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34799#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 34955#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35823#L563-39 assume 1 == ~t1_pc~0; 35829#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 34698#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 35597#L575-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 35598#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36095#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 35938#L582-39 assume 1 == ~t2_pc~0; 35021#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 35023#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 35643#L594-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35644#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34791#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34578#L601-39 assume 1 == ~t3_pc~0; 34579#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34629#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 35787#L613-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35923#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 35827#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35479#L620-39 assume !(1 == ~t4_pc~0); 35480#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 35677#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 35885#L632-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35800#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 35801#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36106#L639-39 assume 1 == ~t5_pc~0; 35913#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 35227#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34804#L651-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34607#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 34608#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35516#L658-39 assume 1 == ~t6_pc~0; 35498#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 35499#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34557#L670-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 34558#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 35673#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35674#L677-39 assume 1 == ~t7_pc~0; 35636#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34782#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34783#L689-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34838#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 34839#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 35404#L696-39 assume 1 == ~t8_pc~0; 35369#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 35249#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35250#L708-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 35545#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35509#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35384#L715-39 assume 1 == ~t9_pc~0; 34583#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 34584#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35793#L727-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 36107#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 35722#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35723#L734-39 assume 1 == ~t10_pc~0; 35648#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35094#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35405#L746-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 34736#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34737#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 35985#L753-39 assume !(1 == ~t11_pc~0); 34656#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 34657#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 35949#L765-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 35374#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 35375#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35476#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35477#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35747#L1242-3 assume !(1 == ~T2_E~0); 35748#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 35967#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35667#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35668#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35950#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 35991#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 36079#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34808#L1282-3 assume !(1 == ~T10_E~0); 34809#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34718#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 34719#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35856#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35857#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36045#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36103#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35769#L1322-3 assume !(1 == ~E_6~0); 35770#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 34777#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 34752#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 34753#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35445#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 35573#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35574#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34700#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 34965#L911-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 35679#L1697 assume !(0 == start_simulation_~tmp~3#1); 35466#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 35467#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 34824#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 35589#L911-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 35590#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35539#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35136#L1660 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 35137#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 35850#L1678-2 [2021-11-13 17:45:54,444 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:54,444 INFO L85 PathProgramCache]: Analyzing trace with hash -24556996, now seen corresponding path program 1 times [2021-11-13 17:45:54,444 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:54,444 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [393167980] [2021-11-13 17:45:54,444 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:54,445 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:54,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:54,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:54,486 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:54,486 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [393167980] [2021-11-13 17:45:54,487 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [393167980] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:54,489 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:54,489 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 17:45:54,491 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1061310801] [2021-11-13 17:45:54,491 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:54,492 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:45:54,492 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:54,493 INFO L85 PathProgramCache]: Analyzing trace with hash -1367576821, now seen corresponding path program 2 times [2021-11-13 17:45:54,493 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:54,493 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [281028096] [2021-11-13 17:45:54,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:54,493 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:54,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:54,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:54,534 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:54,534 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [281028096] [2021-11-13 17:45:54,534 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [281028096] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:54,534 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:54,535 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:54,535 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1125900588] [2021-11-13 17:45:54,535 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:54,535 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:45:54,536 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:45:54,536 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 17:45:54,536 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 17:45:54,536 INFO L87 Difference]: Start difference. First operand 1566 states and 2315 transitions. cyclomatic complexity: 750 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:54,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:45:54,604 INFO L93 Difference]: Finished difference Result 1566 states and 2310 transitions. [2021-11-13 17:45:54,604 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 17:45:54,605 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2310 transitions. [2021-11-13 17:45:54,615 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:54,635 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2310 transitions. [2021-11-13 17:45:54,635 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-11-13 17:45:54,637 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-11-13 17:45:54,637 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2310 transitions. [2021-11-13 17:45:54,639 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:45:54,640 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2310 transitions. [2021-11-13 17:45:54,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2310 transitions. [2021-11-13 17:45:54,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-11-13 17:45:54,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.475095785440613) internal successors, (2310), 1565 states have internal predecessors, (2310), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:54,706 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2310 transitions. [2021-11-13 17:45:54,707 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2310 transitions. [2021-11-13 17:45:54,707 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2310 transitions. [2021-11-13 17:45:54,707 INFO L425 BuchiCegarLoop]: ======== Iteration 13============ [2021-11-13 17:45:54,707 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2310 transitions. [2021-11-13 17:45:54,714 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:54,714 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:45:54,714 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:45:54,717 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:54,717 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:54,718 INFO L791 eck$LassoCheckResult]: Stem: 38416#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 38417#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 39145#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39146#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 37919#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 37920#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39155#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39120#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39121#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38268#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38269#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 38675#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 39093#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 38180#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38181#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 38066#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 38067#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39019#L1109 assume !(0 == ~M_E~0); 39041#L1109-2 assume !(0 == ~T1_E~0); 38073#L1114-1 assume !(0 == ~T2_E~0); 38074#L1119-1 assume !(0 == ~T3_E~0); 39097#L1124-1 assume !(0 == ~T4_E~0); 37736#L1129-1 assume !(0 == ~T5_E~0); 37737#L1134-1 assume !(0 == ~T6_E~0); 38348#L1139-1 assume !(0 == ~T7_E~0); 39025#L1144-1 assume !(0 == ~T8_E~0); 38897#L1149-1 assume !(0 == ~T9_E~0); 37843#L1154-1 assume 0 == ~T10_E~0;~T10_E~0 := 1; 37844#L1159-1 assume !(0 == ~T11_E~0); 38883#L1164-1 assume !(0 == ~E_M~0); 38234#L1169-1 assume !(0 == ~E_1~0); 38123#L1174-1 assume !(0 == ~E_2~0); 37996#L1179-1 assume !(0 == ~E_3~0); 37923#L1184-1 assume !(0 == ~E_4~0); 37924#L1189-1 assume !(0 == ~E_5~0); 37955#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 38042#L1199-1 assume !(0 == ~E_7~0); 38905#L1204-1 assume !(0 == ~E_8~0); 38841#L1209-1 assume !(0 == ~E_9~0); 38842#L1214-1 assume !(0 == ~E_10~0); 39167#L1219-1 assume !(0 == ~E_11~0); 39240#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38251#L544 assume 1 == ~m_pc~0; 38252#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 39084#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38912#L556 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37885#L1379 assume !(0 != activate_threads_~tmp~1#1); 37886#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38661#L563 assume !(1 == ~t1_pc~0); 38458#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 37744#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37745#L575 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38781#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 37740#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37741#L582 assume 1 == ~t2_pc~0; 38436#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38791#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38792#L594 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38896#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 37773#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37774#L601 assume !(1 == ~t3_pc~0); 38452#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 38451#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39085#L613 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38827#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 38828#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38771#L620 assume 1 == ~t4_pc~0; 37754#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37755#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38316#L632 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38317#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 38672#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38860#L639 assume 1 == ~t5_pc~0; 38743#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38046#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38047#L651 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 38693#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 38694#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38623#L658 assume !(1 == ~t6_pc~0); 38248#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 38249#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38818#L670 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 39147#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38831#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38088#L677 assume 1 == ~t7_pc~0; 38089#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37992#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38990#L689 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 39114#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 39115#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 39186#L696 assume !(1 == ~t8_pc~0); 38307#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 38308#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39154#L708 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 39175#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 39221#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38725#L715 assume 1 == ~t9_pc~0; 38726#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 38396#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38304#L727 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38305#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 38714#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38987#L734 assume !(1 == ~t10_pc~0); 38988#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 38206#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38207#L746 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38225#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 38930#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38282#L753 assume 1 == ~t11_pc~0; 38283#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 38836#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38391#L765 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38392#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 38543#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38600#L1237 assume !(1 == ~M_E~0); 38601#L1237-2 assume !(1 == ~T1_E~0); 39212#L1242-1 assume !(1 == ~T2_E~0); 38362#L1247-1 assume !(1 == ~T3_E~0); 38363#L1252-1 assume !(1 == ~T4_E~0); 38146#L1257-1 assume !(1 == ~T5_E~0); 38147#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 39002#L1267-1 assume !(1 == ~T7_E~0); 39107#L1272-1 assume !(1 == ~T8_E~0); 38445#L1277-1 assume !(1 == ~T9_E~0); 38446#L1282-1 assume !(1 == ~T10_E~0); 38868#L1287-1 assume !(1 == ~T11_E~0); 38869#L1292-1 assume !(1 == ~E_M~0); 38830#L1297-1 assume !(1 == ~E_1~0); 38277#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 38278#L1307-1 assume !(1 == ~E_3~0); 39100#L1312-1 assume !(1 == ~E_4~0); 38488#L1317-1 assume !(1 == ~E_5~0); 38489#L1322-1 assume !(1 == ~E_6~0); 38221#L1327-1 assume !(1 == ~E_7~0); 38222#L1332-1 assume !(1 == ~E_8~0); 38780#L1337-1 assume !(1 == ~E_9~0); 38717#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 38718#L1347-1 assume !(1 == ~E_11~0); 39099#L1352-1 assume { :end_inline_reset_delta_events } true; 38986#L1678-2 [2021-11-13 17:45:54,718 INFO L793 eck$LassoCheckResult]: Loop: 38986#L1678-2 assume !false; 38772#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38773#L1084 assume !false; 38557#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 38558#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 37860#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 38875#L911 eval_#t~ret8#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret8#1;havoc eval_#t~ret8#1; 37786#L925 assume !(0 != eval_~tmp~0#1); 37788#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37902#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37903#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37757#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37758#L1114-3 assume !(0 == ~T2_E~0); 38832#L1119-3 assume !(0 == ~T3_E~0); 38833#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38854#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 38855#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 39033#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 39091#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 38261#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38262#L1154-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 38498#L1159-3 assume !(0 == ~T11_E~0); 38499#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 38768#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 38769#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38819#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38820#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38975#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38652#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 38022#L1199-3 assume !(0 == ~E_7~0); 38023#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 38247#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 37710#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37711#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38404#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38405#L544-39 assume !(1 == ~m_pc~0); 37686#L544-41 is_master_triggered_~__retres1~0#1 := 0; 37687#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37937#L556-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37938#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 38094#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38962#L563-39 assume 1 == ~t1_pc~0; 38968#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37840#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38736#L575-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38737#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39234#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39077#L582-39 assume 1 == ~t2_pc~0; 38160#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 38162#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38782#L594-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38783#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 37930#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37714#L601-39 assume 1 == ~t3_pc~0; 37715#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37765#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38926#L613-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 39062#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38966#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38617#L620-39 assume !(1 == ~t4_pc~0); 38618#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 38816#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39024#L632-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38939#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38940#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39245#L639-39 assume 1 == ~t5_pc~0; 39052#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38366#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 37943#L651-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37746#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 37747#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38655#L658-39 assume 1 == ~t6_pc~0; 38637#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38638#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37696#L670-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37697#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38812#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38813#L677-39 assume 1 == ~t7_pc~0; 38775#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 37921#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37922#L689-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37977#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 37978#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38542#L696-39 assume 1 == ~t8_pc~0; 38508#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 38388#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38389#L708-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38684#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 38648#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38523#L715-39 assume 1 == ~t9_pc~0; 37722#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 37723#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38932#L727-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 39246#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38861#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38862#L734-39 assume 1 == ~t10_pc~0; 38787#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 38233#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38544#L746-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37875#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37876#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 39124#L753-39 assume !(1 == ~t11_pc~0); 37795#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 37796#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 39088#L765-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38513#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 38514#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38611#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 38612#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 38886#L1242-3 assume !(1 == ~T2_E~0); 38887#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 39106#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 38806#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 38807#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 39089#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 39130#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 39218#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 37947#L1282-3 assume !(1 == ~T10_E~0); 37948#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37857#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37858#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38995#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 38996#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 39184#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39242#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 38908#L1322-3 assume !(1 == ~E_6~0); 38909#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37916#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37891#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 37892#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 38584#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 38712#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 38713#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 37834#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 38104#L911-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 38817#L1697 assume !(0 == start_simulation_~tmp~3#1); 38605#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 38606#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 37963#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 38728#L911-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 38729#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38678#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38275#L1660 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 38276#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 38986#L1678-2 [2021-11-13 17:45:54,719 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:54,719 INFO L85 PathProgramCache]: Analyzing trace with hash -1117192198, now seen corresponding path program 1 times [2021-11-13 17:45:54,720 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:54,720 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [294391984] [2021-11-13 17:45:54,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:54,720 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:54,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:54,771 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:54,771 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:54,771 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [294391984] [2021-11-13 17:45:54,772 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [294391984] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:54,772 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:54,772 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 17:45:54,772 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [488263580] [2021-11-13 17:45:54,772 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:54,773 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:45:54,774 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:54,774 INFO L85 PathProgramCache]: Analyzing trace with hash -1078757431, now seen corresponding path program 1 times [2021-11-13 17:45:54,774 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:54,774 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [573889665] [2021-11-13 17:45:54,775 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:54,775 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:54,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:54,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:54,813 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:54,813 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [573889665] [2021-11-13 17:45:54,813 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [573889665] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:54,813 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:54,813 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:54,814 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1493699828] [2021-11-13 17:45:54,814 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:54,814 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:45:54,815 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:45:54,815 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 17:45:54,815 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 17:45:54,816 INFO L87 Difference]: Start difference. First operand 1566 states and 2310 transitions. cyclomatic complexity: 745 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:54,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:45:54,855 INFO L93 Difference]: Finished difference Result 1566 states and 2305 transitions. [2021-11-13 17:45:54,855 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 17:45:54,856 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1566 states and 2305 transitions. [2021-11-13 17:45:54,865 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:54,874 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1566 states to 1566 states and 2305 transitions. [2021-11-13 17:45:54,874 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1566 [2021-11-13 17:45:54,876 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1566 [2021-11-13 17:45:54,876 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1566 states and 2305 transitions. [2021-11-13 17:45:54,878 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:45:54,879 INFO L681 BuchiCegarLoop]: Abstraction has 1566 states and 2305 transitions. [2021-11-13 17:45:54,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1566 states and 2305 transitions. [2021-11-13 17:45:54,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1566 to 1566. [2021-11-13 17:45:54,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1566 states, 1566 states have (on average 1.4719029374201789) internal successors, (2305), 1565 states have internal predecessors, (2305), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:54,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1566 states to 1566 states and 2305 transitions. [2021-11-13 17:45:54,927 INFO L704 BuchiCegarLoop]: Abstraction has 1566 states and 2305 transitions. [2021-11-13 17:45:54,928 INFO L587 BuchiCegarLoop]: Abstraction has 1566 states and 2305 transitions. [2021-11-13 17:45:54,928 INFO L425 BuchiCegarLoop]: ======== Iteration 14============ [2021-11-13 17:45:54,928 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1566 states and 2305 transitions. [2021-11-13 17:45:54,935 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1415 [2021-11-13 17:45:54,935 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:45:54,935 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:45:54,938 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:54,938 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:54,938 INFO L791 eck$LassoCheckResult]: Stem: 41555#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 41556#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 42284#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42285#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41058#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 41059#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42294#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42259#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42260#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41407#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41408#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41814#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 42232#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41319#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41320#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41205#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 41206#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42158#L1109 assume !(0 == ~M_E~0); 42180#L1109-2 assume !(0 == ~T1_E~0); 41212#L1114-1 assume !(0 == ~T2_E~0); 41213#L1119-1 assume !(0 == ~T3_E~0); 42236#L1124-1 assume !(0 == ~T4_E~0); 40873#L1129-1 assume !(0 == ~T5_E~0); 40874#L1134-1 assume !(0 == ~T6_E~0); 41487#L1139-1 assume !(0 == ~T7_E~0); 42164#L1144-1 assume !(0 == ~T8_E~0); 42036#L1149-1 assume !(0 == ~T9_E~0); 40980#L1154-1 assume !(0 == ~T10_E~0); 40981#L1159-1 assume !(0 == ~T11_E~0); 42022#L1164-1 assume !(0 == ~E_M~0); 41373#L1169-1 assume !(0 == ~E_1~0); 41262#L1174-1 assume !(0 == ~E_2~0); 41135#L1179-1 assume !(0 == ~E_3~0); 41062#L1184-1 assume !(0 == ~E_4~0); 41063#L1189-1 assume !(0 == ~E_5~0); 41094#L1194-1 assume 0 == ~E_6~0;~E_6~0 := 1; 41181#L1199-1 assume !(0 == ~E_7~0); 42044#L1204-1 assume !(0 == ~E_8~0); 41980#L1209-1 assume !(0 == ~E_9~0); 41981#L1214-1 assume !(0 == ~E_10~0); 42306#L1219-1 assume !(0 == ~E_11~0); 42379#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41390#L544 assume 1 == ~m_pc~0; 41391#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 42223#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42051#L556 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41024#L1379 assume !(0 != activate_threads_~tmp~1#1); 41025#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41797#L563 assume !(1 == ~t1_pc~0); 41597#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40883#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40884#L575 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41920#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 40879#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40880#L582 assume 1 == ~t2_pc~0; 41575#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41930#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41931#L594 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42035#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 40912#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40913#L601 assume !(1 == ~t3_pc~0); 41591#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41590#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42224#L613 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 41966#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 41967#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41910#L620 assume 1 == ~t4_pc~0; 40893#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40894#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41455#L632 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41456#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 41811#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41998#L639 assume 1 == ~t5_pc~0; 41881#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 41185#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41186#L651 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41832#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 41833#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41762#L658 assume !(1 == ~t6_pc~0); 41387#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41388#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41956#L670 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42286#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41970#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41225#L677 assume 1 == ~t7_pc~0; 41226#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41128#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42129#L689 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42253#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 42254#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42325#L696 assume !(1 == ~t8_pc~0); 41445#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 41446#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 42293#L708 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 42314#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 42360#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41864#L715 assume 1 == ~t9_pc~0; 41865#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41535#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 41443#L727 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41444#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 41853#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42125#L734 assume !(1 == ~t10_pc~0); 42126#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 41345#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41346#L746 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41364#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 42069#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 41421#L753 assume 1 == ~t11_pc~0; 41422#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 41975#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41530#L765 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41531#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 41680#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41737#L1237 assume !(1 == ~M_E~0); 41738#L1237-2 assume !(1 == ~T1_E~0); 42350#L1242-1 assume !(1 == ~T2_E~0); 41501#L1247-1 assume !(1 == ~T3_E~0); 41502#L1252-1 assume !(1 == ~T4_E~0); 41285#L1257-1 assume !(1 == ~T5_E~0); 41286#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42141#L1267-1 assume !(1 == ~T7_E~0); 42246#L1272-1 assume !(1 == ~T8_E~0); 41584#L1277-1 assume !(1 == ~T9_E~0); 41585#L1282-1 assume !(1 == ~T10_E~0); 42007#L1287-1 assume !(1 == ~T11_E~0); 42008#L1292-1 assume !(1 == ~E_M~0); 41969#L1297-1 assume !(1 == ~E_1~0); 41416#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 41417#L1307-1 assume !(1 == ~E_3~0); 42239#L1312-1 assume !(1 == ~E_4~0); 41627#L1317-1 assume !(1 == ~E_5~0); 41628#L1322-1 assume !(1 == ~E_6~0); 41360#L1327-1 assume !(1 == ~E_7~0); 41361#L1332-1 assume !(1 == ~E_8~0); 41919#L1337-1 assume !(1 == ~E_9~0); 41856#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 41857#L1347-1 assume !(1 == ~E_11~0); 42238#L1352-1 assume { :end_inline_reset_delta_events } true; 42128#L1678-2 [2021-11-13 17:45:54,939 INFO L793 eck$LassoCheckResult]: Loop: 42128#L1678-2 assume !false; 41911#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41912#L1084 assume !false; 41695#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41696#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40999#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 42013#L911 eval_#t~ret8#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret8#1;havoc eval_#t~ret8#1; 40925#L925 assume !(0 != eval_~tmp~0#1); 40927#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41041#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41042#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40896#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40897#L1114-3 assume !(0 == ~T2_E~0); 41971#L1119-3 assume !(0 == ~T3_E~0); 41972#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41993#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41994#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 42172#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42230#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41400#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 41401#L1154-3 assume !(0 == ~T10_E~0); 41636#L1159-3 assume !(0 == ~T11_E~0); 41637#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 41907#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41908#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41958#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 41959#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42114#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 41791#L1194-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41158#L1199-3 assume !(0 == ~E_7~0); 41159#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41382#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 40844#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 40845#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 41543#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41544#L544-39 assume !(1 == ~m_pc~0); 40825#L544-41 is_master_triggered_~__retres1~0#1 := 0; 40826#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41076#L556-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41077#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 41233#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42101#L563-39 assume 1 == ~t1_pc~0; 42107#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 40976#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41875#L575-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41876#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 42373#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42216#L582-39 assume 1 == ~t2_pc~0; 41299#L583-13 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41301#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41921#L594-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 41922#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 41069#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40856#L601-39 assume 1 == ~t3_pc~0; 40857#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 40907#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42065#L613-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42201#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42105#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41757#L620-39 assume !(1 == ~t4_pc~0); 41758#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 41955#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42163#L632-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42078#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42079#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42384#L639-39 assume !(1 == ~t5_pc~0); 42192#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 41505#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 41082#L651-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40885#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40886#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41794#L658-39 assume 1 == ~t6_pc~0; 41776#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41777#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 40835#L670-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 40836#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 41951#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41952#L677-39 assume 1 == ~t7_pc~0; 41914#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 41060#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41061#L689-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 41116#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 41117#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 41682#L696-39 assume !(1 == ~t8_pc~0); 41648#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 41527#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41528#L708-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41823#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41787#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41662#L715-39 assume 1 == ~t9_pc~0; 40861#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40862#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42071#L727-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42385#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 42000#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42001#L734-39 assume 1 == ~t10_pc~0; 41926#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41372#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 41683#L746-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41014#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41015#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42263#L753-39 assume !(1 == ~t11_pc~0); 40934#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 40935#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42227#L765-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 41652#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41653#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41754#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 41755#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 42025#L1242-3 assume !(1 == ~T2_E~0); 42026#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42245#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41945#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41946#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 42228#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42269#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 42357#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 41086#L1282-3 assume !(1 == ~T10_E~0); 41087#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 40996#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 40997#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 42134#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 42135#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42323#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 42381#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 42047#L1322-3 assume !(1 == ~E_6~0); 42048#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41055#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41030#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 41031#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 41723#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41851#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41852#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 40978#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 41243#L911-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 41957#L1697 assume !(0 == start_simulation_~tmp~3#1); 41744#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 41745#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 41102#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 41867#L911-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 41868#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 41817#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 41414#L1660 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 41415#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 42128#L1678-2 [2021-11-13 17:45:54,940 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:54,941 INFO L85 PathProgramCache]: Analyzing trace with hash -645835848, now seen corresponding path program 1 times [2021-11-13 17:45:54,941 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:54,941 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [452088519] [2021-11-13 17:45:54,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:54,942 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:54,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:54,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:54,995 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:54,995 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [452088519] [2021-11-13 17:45:54,995 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [452088519] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:54,995 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:54,996 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:54,996 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [234003155] [2021-11-13 17:45:54,996 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:54,998 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:45:54,998 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:54,999 INFO L85 PathProgramCache]: Analyzing trace with hash -40214583, now seen corresponding path program 1 times [2021-11-13 17:45:54,999 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:54,999 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2016430529] [2021-11-13 17:45:54,999 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:55,000 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:55,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:55,046 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:55,046 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:55,046 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2016430529] [2021-11-13 17:45:55,047 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2016430529] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:55,047 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:55,047 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:55,047 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1867482308] [2021-11-13 17:45:55,047 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:55,048 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:45:55,048 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:45:55,048 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 17:45:55,049 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 17:45:55,049 INFO L87 Difference]: Start difference. First operand 1566 states and 2305 transitions. cyclomatic complexity: 740 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:55,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:45:55,266 INFO L93 Difference]: Finished difference Result 2912 states and 4281 transitions. [2021-11-13 17:45:55,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 17:45:55,267 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2912 states and 4281 transitions. [2021-11-13 17:45:55,284 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2744 [2021-11-13 17:45:55,300 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2912 states to 2912 states and 4281 transitions. [2021-11-13 17:45:55,300 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2912 [2021-11-13 17:45:55,303 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2912 [2021-11-13 17:45:55,304 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2912 states and 4281 transitions. [2021-11-13 17:45:55,308 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:45:55,308 INFO L681 BuchiCegarLoop]: Abstraction has 2912 states and 4281 transitions. [2021-11-13 17:45:55,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2912 states and 4281 transitions. [2021-11-13 17:45:55,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2912 to 2911. [2021-11-13 17:45:55,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2911 states, 2911 states have (on average 1.470285125386465) internal successors, (4280), 2910 states have internal predecessors, (4280), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:55,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2911 states to 2911 states and 4280 transitions. [2021-11-13 17:45:55,373 INFO L704 BuchiCegarLoop]: Abstraction has 2911 states and 4280 transitions. [2021-11-13 17:45:55,373 INFO L587 BuchiCegarLoop]: Abstraction has 2911 states and 4280 transitions. [2021-11-13 17:45:55,373 INFO L425 BuchiCegarLoop]: ======== Iteration 15============ [2021-11-13 17:45:55,374 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2911 states and 4280 transitions. [2021-11-13 17:45:55,387 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2744 [2021-11-13 17:45:55,387 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:45:55,387 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:45:55,390 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:55,390 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:55,391 INFO L791 eck$LassoCheckResult]: Stem: 46044#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 46045#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 46792#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46793#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45546#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 45547#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 46803#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 46766#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 46767#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45896#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 45897#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 46303#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 46737#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45808#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 45809#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 45693#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45694#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 46661#L1109 assume !(0 == ~M_E~0); 46683#L1109-2 assume !(0 == ~T1_E~0); 45700#L1114-1 assume !(0 == ~T2_E~0); 45701#L1119-1 assume !(0 == ~T3_E~0); 46741#L1124-1 assume !(0 == ~T4_E~0); 45363#L1129-1 assume !(0 == ~T5_E~0); 45364#L1134-1 assume !(0 == ~T6_E~0); 45976#L1139-1 assume !(0 == ~T7_E~0); 46667#L1144-1 assume !(0 == ~T8_E~0); 46530#L1149-1 assume !(0 == ~T9_E~0); 45468#L1154-1 assume !(0 == ~T10_E~0); 45469#L1159-1 assume !(0 == ~T11_E~0); 46516#L1164-1 assume !(0 == ~E_M~0); 45862#L1169-1 assume !(0 == ~E_1~0); 45751#L1174-1 assume !(0 == ~E_2~0); 45623#L1179-1 assume !(0 == ~E_3~0); 45550#L1184-1 assume !(0 == ~E_4~0); 45551#L1189-1 assume !(0 == ~E_5~0); 45582#L1194-1 assume !(0 == ~E_6~0); 45669#L1199-1 assume !(0 == ~E_7~0); 46538#L1204-1 assume !(0 == ~E_8~0); 46473#L1209-1 assume !(0 == ~E_9~0); 46474#L1214-1 assume !(0 == ~E_10~0); 46818#L1219-1 assume !(0 == ~E_11~0); 46919#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 45879#L544 assume 1 == ~m_pc~0; 45880#L545 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 46727#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46546#L556 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45512#L1379 assume !(0 != activate_threads_~tmp~1#1); 45513#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46286#L563 assume !(1 == ~t1_pc~0); 46086#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 45371#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45372#L575 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46413#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 45367#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45368#L582 assume 1 == ~t2_pc~0; 46064#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 46423#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46424#L594 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46529#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 45400#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45401#L601 assume !(1 == ~t3_pc~0); 46080#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46079#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46728#L613 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46459#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 46460#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46403#L620 assume 1 == ~t4_pc~0; 45381#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 45382#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45944#L632 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45945#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 46300#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46492#L639 assume 1 == ~t5_pc~0; 46372#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 45673#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 45674#L651 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46321#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 46322#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46251#L658 assume !(1 == ~t6_pc~0); 45876#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 45877#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46449#L670 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46794#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46463#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45713#L677 assume 1 == ~t7_pc~0; 45714#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 45616#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 46632#L689 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46760#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 46761#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46844#L696 assume !(1 == ~t8_pc~0); 45934#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 45935#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 46802#L708 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46828#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 46892#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 46353#L715 assume 1 == ~t9_pc~0; 46354#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 46024#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45932#L727 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45933#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 46342#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46629#L734 assume !(1 == ~t10_pc~0); 46630#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 45834#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 45835#L746 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 45853#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 46565#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 45910#L753 assume 1 == ~t11_pc~0; 45911#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46468#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46019#L765 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46020#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 46169#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46226#L1237 assume !(1 == ~M_E~0); 46227#L1237-2 assume !(1 == ~T1_E~0); 46874#L1242-1 assume !(1 == ~T2_E~0); 45990#L1247-1 assume !(1 == ~T3_E~0); 45991#L1252-1 assume !(1 == ~T4_E~0); 45774#L1257-1 assume !(1 == ~T5_E~0); 45775#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46644#L1267-1 assume !(1 == ~T7_E~0); 46752#L1272-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46073#L1277-1 assume !(1 == ~T9_E~0); 46074#L1282-1 assume !(1 == ~T10_E~0); 46501#L1287-1 assume !(1 == ~T11_E~0); 46502#L1292-1 assume !(1 == ~E_M~0); 46462#L1297-1 assume !(1 == ~E_1~0); 45905#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 45906#L1307-1 assume !(1 == ~E_3~0); 46744#L1312-1 assume !(1 == ~E_4~0); 46116#L1317-1 assume !(1 == ~E_5~0); 46117#L1322-1 assume !(1 == ~E_6~0); 45849#L1327-1 assume !(1 == ~E_7~0); 45850#L1332-1 assume !(1 == ~E_8~0); 46412#L1337-1 assume !(1 == ~E_9~0); 46345#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 46346#L1347-1 assume !(1 == ~E_11~0); 46971#L1352-1 assume { :end_inline_reset_delta_events } true; 46964#L1678-2 [2021-11-13 17:45:55,391 INFO L793 eck$LassoCheckResult]: Loop: 46964#L1678-2 assume !false; 46957#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 46954#L1084 assume !false; 46953#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 46839#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 45487#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 46507#L911 eval_#t~ret8#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret8#1;havoc eval_#t~ret8#1; 45413#L925 assume !(0 != eval_~tmp~0#1); 45415#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45529#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45530#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 45384#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 45385#L1114-3 assume !(0 == ~T2_E~0); 46934#L1119-3 assume !(0 == ~T3_E~0); 46933#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 46932#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 46931#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46930#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 46929#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45889#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 45890#L1154-3 assume !(0 == ~T10_E~0); 46125#L1159-3 assume !(0 == ~T11_E~0); 46126#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 46400#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 46401#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 46451#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46452#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 46617#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46280#L1194-3 assume !(0 == ~E_6~0); 45646#L1199-3 assume !(0 == ~E_7~0); 45647#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45871#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 45332#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 45333#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 46032#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46033#L544-39 assume !(1 == ~m_pc~0); 45313#L544-41 is_master_triggered_~__retres1~0#1 := 0; 45314#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47816#L556-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 47815#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 47814#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47813#L563-39 assume 1 == ~t1_pc~0; 47811#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47788#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47787#L575-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 47785#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47783#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47781#L582-39 assume !(1 == ~t2_pc~0); 47777#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 47774#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47772#L594-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 47770#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47768#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47766#L601-39 assume 1 == ~t3_pc~0; 47763#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47760#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47758#L613-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 47756#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47754#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47752#L620-39 assume !(1 == ~t4_pc~0); 47749#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 47746#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47298#L632-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 47295#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 47293#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47291#L639-39 assume 1 == ~t5_pc~0; 47288#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47286#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47284#L651-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 47281#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 47279#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 47277#L658-39 assume !(1 == ~t6_pc~0); 47272#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 47270#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 47268#L670-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 47266#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 47263#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 47261#L677-39 assume 1 == ~t7_pc~0; 47258#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 47256#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 47254#L689-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 47252#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 47249#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 47247#L696-39 assume 1 == ~t8_pc~0; 47244#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 47242#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 47240#L708-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 47238#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 47235#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 47233#L715-39 assume 1 == ~t9_pc~0; 47217#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 47215#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 47213#L727-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 47210#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 47208#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 47206#L734-39 assume !(1 == ~t10_pc~0); 47200#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 47197#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 47195#L746-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 47193#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 47191#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 47189#L753-39 assume !(1 == ~t11_pc~0); 47185#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 47183#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 47181#L765-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 47179#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 47177#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47175#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 47172#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 47170#L1242-3 assume !(1 == ~T2_E~0); 47168#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47166#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47164#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47162#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 47159#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 47157#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 46924#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 47154#L1282-3 assume !(1 == ~T10_E~0); 47152#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 47150#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 47147#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47145#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 47143#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 47141#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47139#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47137#L1322-3 assume !(1 == ~E_6~0); 46543#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 47133#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 47131#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 47129#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 47127#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 47125#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 47076#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 47072#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 47069#L911-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 47024#L1697 assume !(0 == start_simulation_~tmp~3#1); 47022#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 47015#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 47005#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 47003#L911-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 47001#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 47000#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46979#L1660 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 46970#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 46964#L1678-2 [2021-11-13 17:45:55,392 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:55,392 INFO L85 PathProgramCache]: Analyzing trace with hash -1963161228, now seen corresponding path program 1 times [2021-11-13 17:45:55,392 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:55,393 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1236526406] [2021-11-13 17:45:55,393 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:55,393 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:55,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:55,430 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:55,431 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:55,431 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1236526406] [2021-11-13 17:45:55,431 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1236526406] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:55,431 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:55,432 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 17:45:55,432 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1681265308] [2021-11-13 17:45:55,432 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:55,432 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:45:55,433 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:55,433 INFO L85 PathProgramCache]: Analyzing trace with hash 1274416648, now seen corresponding path program 1 times [2021-11-13 17:45:55,433 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:55,433 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1856553827] [2021-11-13 17:45:55,434 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:55,434 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:55,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:55,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:55,480 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:55,480 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1856553827] [2021-11-13 17:45:55,480 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1856553827] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:55,481 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:55,481 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-13 17:45:55,482 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [799402760] [2021-11-13 17:45:55,482 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:55,482 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:45:55,482 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:45:55,483 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 17:45:55,483 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 17:45:55,483 INFO L87 Difference]: Start difference. First operand 2911 states and 4280 transitions. cyclomatic complexity: 1371 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:55,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:45:55,610 INFO L93 Difference]: Finished difference Result 5621 states and 8205 transitions. [2021-11-13 17:45:55,610 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 17:45:55,611 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5621 states and 8205 transitions. [2021-11-13 17:45:55,644 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5453 [2021-11-13 17:45:55,679 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5621 states to 5621 states and 8205 transitions. [2021-11-13 17:45:55,679 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5621 [2021-11-13 17:45:55,686 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5621 [2021-11-13 17:45:55,686 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5621 states and 8205 transitions. [2021-11-13 17:45:55,695 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:45:55,695 INFO L681 BuchiCegarLoop]: Abstraction has 5621 states and 8205 transitions. [2021-11-13 17:45:55,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5621 states and 8205 transitions. [2021-11-13 17:45:55,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5621 to 5455. [2021-11-13 17:45:55,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5455 states, 5455 states have (on average 1.4612282309807516) internal successors, (7971), 5454 states have internal predecessors, (7971), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:55,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5455 states to 5455 states and 7971 transitions. [2021-11-13 17:45:55,867 INFO L704 BuchiCegarLoop]: Abstraction has 5455 states and 7971 transitions. [2021-11-13 17:45:55,867 INFO L587 BuchiCegarLoop]: Abstraction has 5455 states and 7971 transitions. [2021-11-13 17:45:55,868 INFO L425 BuchiCegarLoop]: ======== Iteration 16============ [2021-11-13 17:45:55,868 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5455 states and 7971 transitions. [2021-11-13 17:45:55,895 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5287 [2021-11-13 17:45:55,896 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:45:55,896 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:45:55,899 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:55,899 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:55,900 INFO L791 eck$LassoCheckResult]: Stem: 54594#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 54595#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 55396#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 55397#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54088#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 54089#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55406#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55363#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55364#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54443#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54444#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 54864#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 55325#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 54353#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54354#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 54237#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 54238#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55243#L1109 assume !(0 == ~M_E~0); 55267#L1109-2 assume !(0 == ~T1_E~0); 54244#L1114-1 assume !(0 == ~T2_E~0); 54245#L1119-1 assume !(0 == ~T3_E~0); 55329#L1124-1 assume !(0 == ~T4_E~0); 53904#L1129-1 assume !(0 == ~T5_E~0); 53905#L1134-1 assume !(0 == ~T6_E~0); 54525#L1139-1 assume !(0 == ~T7_E~0); 55248#L1144-1 assume !(0 == ~T8_E~0); 55110#L1149-1 assume !(0 == ~T9_E~0); 54011#L1154-1 assume !(0 == ~T10_E~0); 54012#L1159-1 assume !(0 == ~T11_E~0); 55096#L1164-1 assume !(0 == ~E_M~0); 54407#L1169-1 assume !(0 == ~E_1~0); 54296#L1174-1 assume !(0 == ~E_2~0); 54169#L1179-1 assume !(0 == ~E_3~0); 54092#L1184-1 assume !(0 == ~E_4~0); 54093#L1189-1 assume !(0 == ~E_5~0); 54124#L1194-1 assume !(0 == ~E_6~0); 54215#L1199-1 assume !(0 == ~E_7~0); 55118#L1204-1 assume !(0 == ~E_8~0); 55048#L1209-1 assume !(0 == ~E_9~0); 55049#L1214-1 assume !(0 == ~E_10~0); 55420#L1219-1 assume !(0 == ~E_11~0); 55535#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54427#L544 assume !(1 == ~m_pc~0); 54428#L544-2 is_master_triggered_~__retres1~0#1 := 0; 55311#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 55128#L556 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54055#L1379 assume !(0 != activate_threads_~tmp~1#1); 54056#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54849#L563 assume !(1 == ~t1_pc~0); 54636#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53912#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53913#L575 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54983#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 53908#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53909#L582 assume 1 == ~t2_pc~0; 54614#L583 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 54995#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54996#L594 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 55109#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 53941#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53942#L601 assume !(1 == ~t3_pc~0); 54630#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54629#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 55314#L613 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 55031#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 55032#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54972#L620 assume 1 == ~t4_pc~0; 53924#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53925#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 54492#L632 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54493#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 54860#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 55069#L639 assume 1 == ~t5_pc~0; 54944#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 54217#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54218#L651 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54882#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 54883#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54813#L658 assume !(1 == ~t6_pc~0); 54422#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 54423#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 55022#L670 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 55398#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 55037#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54259#L677 assume 1 == ~t7_pc~0; 54260#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 54161#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 55210#L689 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 55356#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 55357#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 55447#L696 assume !(1 == ~t8_pc~0); 54483#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 54484#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 55405#L708 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 55430#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 55494#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54922#L715 assume 1 == ~t9_pc~0; 54923#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 54573#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54480#L727 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54481#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 54905#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 55207#L734 assume !(1 == ~t10_pc~0); 55208#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 54379#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54380#L746 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54400#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 55144#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54459#L753 assume 1 == ~t11_pc~0; 54460#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 55042#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54568#L765 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54569#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 54728#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54785#L1237 assume !(1 == ~M_E~0); 54786#L1237-2 assume !(1 == ~T1_E~0); 55484#L1242-1 assume !(1 == ~T2_E~0); 54539#L1247-1 assume !(1 == ~T3_E~0); 54540#L1252-1 assume !(1 == ~T4_E~0); 54319#L1257-1 assume !(1 == ~T5_E~0); 54320#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 55224#L1267-1 assume !(1 == ~T7_E~0); 55345#L1272-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 54623#L1277-1 assume !(1 == ~T9_E~0); 54624#L1282-1 assume !(1 == ~T10_E~0); 55079#L1287-1 assume !(1 == ~T11_E~0); 55080#L1292-1 assume !(1 == ~E_M~0); 55035#L1297-1 assume !(1 == ~E_1~0); 55036#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 55333#L1307-1 assume !(1 == ~E_3~0); 55334#L1312-1 assume !(1 == ~E_4~0); 54667#L1317-1 assume !(1 == ~E_5~0); 54668#L1322-1 assume !(1 == ~E_6~0); 54396#L1327-1 assume !(1 == ~E_7~0); 54397#L1332-1 assume !(1 == ~E_8~0); 54982#L1337-1 assume !(1 == ~E_9~0); 54911#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 54912#L1347-1 assume !(1 == ~E_11~0); 55331#L1352-1 assume { :end_inline_reset_delta_events } true; 55332#L1678-2 [2021-11-13 17:45:55,900 INFO L793 eck$LassoCheckResult]: Loop: 55332#L1678-2 assume !false; 55681#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 56614#L1084 assume !false; 56613#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 55589#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 55587#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 55575#L911 eval_#t~ret8#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret8#1;havoc eval_#t~ret8#1; 55576#L925 assume !(0 != eval_~tmp~0#1); 56600#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 56598#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 56596#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 56594#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 56592#L1114-3 assume !(0 == ~T2_E~0); 56590#L1119-3 assume !(0 == ~T3_E~0); 56588#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 56586#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 56584#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 56582#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 56578#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 56579#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 57625#L1154-3 assume !(0 == ~T10_E~0); 57624#L1159-3 assume !(0 == ~T11_E~0); 57623#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 57622#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 57621#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 57620#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 57619#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 57618#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 57617#L1194-3 assume !(0 == ~E_6~0); 57616#L1199-3 assume !(0 == ~E_7~0); 57615#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 57614#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 57613#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 57612#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 57611#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57610#L544-39 assume !(1 == ~m_pc~0); 57609#L544-41 is_master_triggered_~__retres1~0#1 := 0; 57608#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 57607#L556-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 57606#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 57605#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 57604#L563-39 assume 1 == ~t1_pc~0; 57602#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 57601#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57600#L575-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 57599#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 57598#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57597#L582-39 assume !(1 == ~t2_pc~0); 57595#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 57594#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 57593#L594-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 57592#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 57591#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 57590#L601-39 assume 1 == ~t3_pc~0; 57588#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 57587#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57586#L613-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 57585#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 57584#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57583#L620-39 assume !(1 == ~t4_pc~0); 57581#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 57580#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57579#L632-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 57578#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 57577#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 57576#L639-39 assume 1 == ~t5_pc~0; 57574#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 57573#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 57572#L651-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 57571#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 57570#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 57569#L658-39 assume 1 == ~t6_pc~0; 57568#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 57566#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 57565#L670-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 57564#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 57563#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 57562#L677-39 assume 1 == ~t7_pc~0; 57560#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 57559#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 57558#L689-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 57557#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 57556#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56321#L696-39 assume 1 == ~t8_pc~0; 56322#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 57427#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 57426#L708-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 57425#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 57424#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 57423#L715-39 assume 1 == ~t9_pc~0; 57421#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 57420#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 57419#L727-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 57418#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 57417#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 57416#L734-39 assume 1 == ~t10_pc~0; 57414#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 57413#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 57412#L746-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 57411#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 57410#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 57409#L753-39 assume 1 == ~t11_pc~0; 57408#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 57406#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 57405#L765-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 57404#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 57403#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57402#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 57401#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 57400#L1242-3 assume !(1 == ~T2_E~0); 57399#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57398#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 57397#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 57396#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 57395#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 56149#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 56150#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 56142#L1282-3 assume !(1 == ~T10_E~0); 56143#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 56113#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 56110#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 56107#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 56108#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 56101#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 56102#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 56095#L1322-3 assume !(1 == ~E_6~0); 56096#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 56086#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 56087#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 56069#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 56070#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 56061#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 56062#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 55785#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 55786#L911-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 55727#L1697 assume !(0 == start_simulation_~tmp~3#1); 55728#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 55708#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 55697#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 55694#L911-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 55691#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 55689#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 55686#L1660 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 55683#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 55332#L1678-2 [2021-11-13 17:45:55,901 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:55,901 INFO L85 PathProgramCache]: Analyzing trace with hash 470394037, now seen corresponding path program 1 times [2021-11-13 17:45:55,901 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:55,901 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2142484419] [2021-11-13 17:45:55,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:55,902 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:55,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:55,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:55,944 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:55,944 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2142484419] [2021-11-13 17:45:55,946 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2142484419] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:55,946 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:55,946 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:55,946 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1610880586] [2021-11-13 17:45:55,947 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:55,947 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:45:55,947 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:55,948 INFO L85 PathProgramCache]: Analyzing trace with hash 70662277, now seen corresponding path program 1 times [2021-11-13 17:45:55,948 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:55,948 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [841066582] [2021-11-13 17:45:55,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:55,948 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:55,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:55,990 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:55,991 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:55,991 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [841066582] [2021-11-13 17:45:55,991 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [841066582] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:55,991 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:55,992 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:55,992 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2109609582] [2021-11-13 17:45:55,992 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:55,993 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:45:55,993 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:45:55,993 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 17:45:55,993 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 17:45:55,994 INFO L87 Difference]: Start difference. First operand 5455 states and 7971 transitions. cyclomatic complexity: 2520 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:56,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:45:56,346 INFO L93 Difference]: Finished difference Result 13139 states and 19046 transitions. [2021-11-13 17:45:56,347 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 17:45:56,347 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13139 states and 19046 transitions. [2021-11-13 17:45:56,412 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 12790 [2021-11-13 17:45:56,469 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13139 states to 13139 states and 19046 transitions. [2021-11-13 17:45:56,469 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13139 [2021-11-13 17:45:56,483 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13139 [2021-11-13 17:45:56,484 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13139 states and 19046 transitions. [2021-11-13 17:45:56,499 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:45:56,499 INFO L681 BuchiCegarLoop]: Abstraction has 13139 states and 19046 transitions. [2021-11-13 17:45:56,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13139 states and 19046 transitions. [2021-11-13 17:45:56,668 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13139 to 10341. [2021-11-13 17:45:56,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10341 states, 10341 states have (on average 1.4543080939947781) internal successors, (15039), 10340 states have internal predecessors, (15039), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:56,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10341 states to 10341 states and 15039 transitions. [2021-11-13 17:45:56,849 INFO L704 BuchiCegarLoop]: Abstraction has 10341 states and 15039 transitions. [2021-11-13 17:45:56,849 INFO L587 BuchiCegarLoop]: Abstraction has 10341 states and 15039 transitions. [2021-11-13 17:45:56,849 INFO L425 BuchiCegarLoop]: ======== Iteration 17============ [2021-11-13 17:45:56,850 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10341 states and 15039 transitions. [2021-11-13 17:45:56,974 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 10172 [2021-11-13 17:45:56,974 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:45:56,975 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:45:56,978 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:56,978 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:56,979 INFO L791 eck$LassoCheckResult]: Stem: 73194#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 73195#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 74007#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 74008#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 72691#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 72692#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 74020#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 73973#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 73974#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 73043#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 73044#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 73463#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 73940#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 72955#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 72956#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 72839#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 72840#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 73839#L1109 assume !(0 == ~M_E~0); 73868#L1109-2 assume !(0 == ~T1_E~0); 72846#L1114-1 assume !(0 == ~T2_E~0); 72847#L1119-1 assume !(0 == ~T3_E~0); 73944#L1124-1 assume !(0 == ~T4_E~0); 72508#L1129-1 assume !(0 == ~T5_E~0); 72509#L1134-1 assume !(0 == ~T6_E~0); 73127#L1139-1 assume !(0 == ~T7_E~0); 73845#L1144-1 assume !(0 == ~T8_E~0); 73702#L1149-1 assume !(0 == ~T9_E~0); 72615#L1154-1 assume !(0 == ~T10_E~0); 72616#L1159-1 assume !(0 == ~T11_E~0); 73688#L1164-1 assume !(0 == ~E_M~0); 73009#L1169-1 assume !(0 == ~E_1~0); 72896#L1174-1 assume !(0 == ~E_2~0); 72770#L1179-1 assume !(0 == ~E_3~0); 72695#L1184-1 assume !(0 == ~E_4~0); 72696#L1189-1 assume !(0 == ~E_5~0); 72727#L1194-1 assume !(0 == ~E_6~0); 72817#L1199-1 assume !(0 == ~E_7~0); 73710#L1204-1 assume !(0 == ~E_8~0); 73642#L1209-1 assume !(0 == ~E_9~0); 73643#L1214-1 assume !(0 == ~E_10~0); 74032#L1219-1 assume !(0 == ~E_11~0); 74148#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 73029#L544 assume !(1 == ~m_pc~0); 73030#L544-2 is_master_triggered_~__retres1~0#1 := 0; 73929#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 73721#L556 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 72658#L1379 assume !(0 != activate_threads_~tmp~1#1); 72659#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 73448#L563 assume !(1 == ~t1_pc~0); 73235#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 72516#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 72517#L575 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 73578#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 72512#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 72513#L582 assume !(1 == ~t2_pc~0); 73214#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 73589#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 73590#L594 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 73701#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 72545#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 72546#L601 assume !(1 == ~t3_pc~0); 73229#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 73228#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 73932#L613 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 73624#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 73625#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 73567#L620 assume 1 == ~t4_pc~0; 72528#L621 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 72529#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 73092#L632 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 73093#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 73460#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 73661#L639 assume 1 == ~t5_pc~0; 73540#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 72819#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 72820#L651 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 73482#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 73483#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 73410#L658 assume !(1 == ~t6_pc~0); 73024#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 73025#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 73615#L670 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 74009#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 73630#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 72861#L677 assume 1 == ~t7_pc~0; 72862#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 72764#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 73803#L689 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 73967#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 73968#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 74060#L696 assume !(1 == ~t8_pc~0); 73083#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 73084#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 74019#L708 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 74042#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 74116#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 73518#L715 assume 1 == ~t9_pc~0; 73519#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 73174#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 73080#L727 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 73081#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 73503#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 73800#L734 assume !(1 == ~t10_pc~0); 73801#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 72981#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 72982#L746 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 73002#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 73738#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 73058#L753 assume 1 == ~t11_pc~0; 73059#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 73635#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 73169#L765 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 73170#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 73325#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 73382#L1237 assume !(1 == ~M_E~0); 73383#L1237-2 assume !(1 == ~T1_E~0); 74098#L1242-1 assume !(1 == ~T2_E~0); 73141#L1247-1 assume !(1 == ~T3_E~0); 73142#L1252-1 assume !(1 == ~T4_E~0); 72919#L1257-1 assume !(1 == ~T5_E~0); 72920#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 73819#L1267-1 assume !(1 == ~T7_E~0); 73958#L1272-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 73959#L1277-1 assume !(1 == ~T9_E~0); 73749#L1282-1 assume !(1 == ~T10_E~0); 73750#L1287-1 assume !(1 == ~T11_E~0); 73711#L1292-1 assume !(1 == ~E_M~0); 73712#L1297-1 assume !(1 == ~E_1~0); 73052#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 73053#L1307-1 assume !(1 == ~E_3~0); 74120#L1312-1 assume !(1 == ~E_4~0); 74121#L1317-1 assume !(1 == ~E_5~0); 73513#L1322-1 assume !(1 == ~E_6~0); 73514#L1327-1 assume !(1 == ~E_7~0); 73576#L1332-1 assume !(1 == ~E_8~0); 73577#L1337-1 assume !(1 == ~E_9~0); 73508#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 73509#L1347-1 assume !(1 == ~E_11~0); 73946#L1352-1 assume { :end_inline_reset_delta_events } true; 73799#L1678-2 [2021-11-13 17:45:56,979 INFO L793 eck$LassoCheckResult]: Loop: 73799#L1678-2 assume !false; 73568#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 73569#L1084 assume !false; 73338#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 73339#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 81642#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 81641#L911 eval_#t~ret8#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret8#1;havoc eval_#t~ret8#1; 81639#L925 assume !(0 != eval_~tmp~0#1); 72800#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 72674#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 72675#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 72526#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 72527#L1114-3 assume !(0 == ~T2_E~0); 81635#L1119-3 assume !(0 == ~T3_E~0); 81634#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 81633#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 81632#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 81631#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 81630#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 73036#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 73037#L1154-3 assume !(0 == ~T10_E~0); 73277#L1159-3 assume !(0 == ~T11_E~0); 73278#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 73564#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 73565#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 73616#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 73617#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 82625#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 82624#L1194-3 assume !(0 == ~E_6~0); 82623#L1199-3 assume !(0 == ~E_7~0); 82622#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 82621#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 82620#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 82619#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 82618#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82617#L544-39 assume !(1 == ~m_pc~0); 82616#L544-41 is_master_triggered_~__retres1~0#1 := 0; 82615#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82614#L556-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 82613#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 82612#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82611#L563-39 assume 1 == ~t1_pc~0; 82609#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 82608#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82607#L575-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 82606#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 82605#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82604#L582-39 assume !(1 == ~t2_pc~0); 81268#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 82603#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82510#L594-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 82509#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 82508#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82507#L601-39 assume 1 == ~t3_pc~0; 82505#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 82504#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82503#L613-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 82502#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 82501#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82500#L620-39 assume 1 == ~t4_pc~0; 82499#L621-13 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 82497#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82496#L632-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 82495#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 82494#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82493#L639-39 assume 1 == ~t5_pc~0; 82491#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 82490#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82489#L651-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 82488#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 82487#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 82486#L658-39 assume 1 == ~t6_pc~0; 82485#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 73963#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 72466#L670-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 72467#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 73609#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 73610#L677-39 assume !(1 == ~t7_pc~0); 73219#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 72693#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 72694#L689-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 72749#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 72750#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 73321#L696-39 assume !(1 == ~t8_pc~0); 73289#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 73166#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 73167#L708-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 73473#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 73433#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 73301#L715-39 assume 1 == ~t9_pc~0; 72492#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 72493#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 73740#L727-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 74167#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 73662#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 73663#L734-39 assume !(1 == ~t10_pc~0); 74013#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 82447#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 82445#L746-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 82443#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 82441#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 82438#L753-39 assume !(1 == ~t11_pc~0); 82435#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 82434#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 82433#L765-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 82432#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 82431#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82430#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 73976#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 73977#L1242-3 assume !(1 == ~T2_E~0); 82401#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 82400#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 73603#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 73604#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 73935#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 82394#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 74162#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 82393#L1282-3 assume !(1 == ~T10_E~0); 82392#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 82391#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 74153#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 73806#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 73807#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 74057#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 74155#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 73715#L1322-3 assume !(1 == ~E_6~0); 73716#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 72688#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 72662#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 72663#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 73366#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 82284#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 82100#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 82085#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 82079#L911-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 82070#L1697 assume !(0 == start_simulation_~tmp~3#1); 82069#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 81721#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 81712#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 81711#L911-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 81710#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 81709#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 73050#L1660 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 73051#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 73799#L1678-2 [2021-11-13 17:45:56,980 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:56,985 INFO L85 PathProgramCache]: Analyzing trace with hash -746792586, now seen corresponding path program 1 times [2021-11-13 17:45:56,986 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:56,986 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [836470822] [2021-11-13 17:45:56,986 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:56,986 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:56,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:57,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:57,027 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:57,028 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [836470822] [2021-11-13 17:45:57,028 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [836470822] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:57,028 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:57,028 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 17:45:57,029 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1137115685] [2021-11-13 17:45:57,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:57,029 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:45:57,030 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:57,030 INFO L85 PathProgramCache]: Analyzing trace with hash -769325624, now seen corresponding path program 1 times [2021-11-13 17:45:57,030 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:57,030 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1587124546] [2021-11-13 17:45:57,031 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:57,031 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:57,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:57,067 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:57,068 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:57,068 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1587124546] [2021-11-13 17:45:57,068 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1587124546] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:57,068 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:57,068 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:57,069 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [33507074] [2021-11-13 17:45:57,069 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:57,069 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:45:57,070 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:45:57,070 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 17:45:57,070 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 17:45:57,070 INFO L87 Difference]: Start difference. First operand 10341 states and 15039 transitions. cyclomatic complexity: 4702 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:57,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:45:57,268 INFO L93 Difference]: Finished difference Result 19736 states and 28576 transitions. [2021-11-13 17:45:57,269 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 17:45:57,269 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19736 states and 28576 transitions. [2021-11-13 17:45:57,377 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19548 [2021-11-13 17:45:57,461 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19736 states to 19736 states and 28576 transitions. [2021-11-13 17:45:57,461 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19736 [2021-11-13 17:45:57,484 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19736 [2021-11-13 17:45:57,484 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19736 states and 28576 transitions. [2021-11-13 17:45:57,507 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:45:57,507 INFO L681 BuchiCegarLoop]: Abstraction has 19736 states and 28576 transitions. [2021-11-13 17:45:57,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19736 states and 28576 transitions. [2021-11-13 17:45:57,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19736 to 19720. [2021-11-13 17:45:57,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19720 states, 19720 states have (on average 1.4482758620689655) internal successors, (28560), 19719 states have internal predecessors, (28560), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:58,050 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19720 states to 19720 states and 28560 transitions. [2021-11-13 17:45:58,051 INFO L704 BuchiCegarLoop]: Abstraction has 19720 states and 28560 transitions. [2021-11-13 17:45:58,051 INFO L587 BuchiCegarLoop]: Abstraction has 19720 states and 28560 transitions. [2021-11-13 17:45:58,051 INFO L425 BuchiCegarLoop]: ======== Iteration 18============ [2021-11-13 17:45:58,051 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19720 states and 28560 transitions. [2021-11-13 17:45:58,112 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19532 [2021-11-13 17:45:58,112 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:45:58,113 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:45:58,115 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:58,116 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:45:58,116 INFO L791 eck$LassoCheckResult]: Stem: 103273#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 103274#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 104087#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 104088#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 102770#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 102771#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 104100#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 104059#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 104060#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 103122#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 103123#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 103538#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 104022#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 103034#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 103035#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 102917#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 102918#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 103922#L1109 assume !(0 == ~M_E~0); 103953#L1109-2 assume !(0 == ~T1_E~0); 102924#L1114-1 assume !(0 == ~T2_E~0); 102925#L1119-1 assume !(0 == ~T3_E~0); 104026#L1124-1 assume !(0 == ~T4_E~0); 102591#L1129-1 assume !(0 == ~T5_E~0); 102592#L1134-1 assume !(0 == ~T6_E~0); 103203#L1139-1 assume !(0 == ~T7_E~0); 103930#L1144-1 assume !(0 == ~T8_E~0); 103785#L1149-1 assume !(0 == ~T9_E~0); 102695#L1154-1 assume !(0 == ~T10_E~0); 102696#L1159-1 assume !(0 == ~T11_E~0); 103771#L1164-1 assume !(0 == ~E_M~0); 103088#L1169-1 assume !(0 == ~E_1~0); 102975#L1174-1 assume !(0 == ~E_2~0); 102848#L1179-1 assume !(0 == ~E_3~0); 102774#L1184-1 assume !(0 == ~E_4~0); 102775#L1189-1 assume !(0 == ~E_5~0); 102807#L1194-1 assume !(0 == ~E_6~0); 102893#L1199-1 assume !(0 == ~E_7~0); 103793#L1204-1 assume !(0 == ~E_8~0); 103722#L1209-1 assume !(0 == ~E_9~0); 103723#L1214-1 assume !(0 == ~E_10~0); 104115#L1219-1 assume !(0 == ~E_11~0); 104224#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103106#L544 assume !(1 == ~m_pc~0); 103107#L544-2 is_master_triggered_~__retres1~0#1 := 0; 104011#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103802#L556 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 102736#L1379 assume !(0 != activate_threads_~tmp~1#1); 102737#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 103522#L563 assume !(1 == ~t1_pc~0); 103315#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 102599#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 102600#L575 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 103654#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 102595#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 102596#L582 assume !(1 == ~t2_pc~0); 103293#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 103664#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 103665#L594 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 103784#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 102625#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102626#L601 assume !(1 == ~t3_pc~0); 103308#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 103307#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 104012#L613 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 103704#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 103705#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 103643#L620 assume !(1 == ~t4_pc~0); 103644#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 103221#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 103167#L632 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 103168#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 103535#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 103744#L639 assume 1 == ~t5_pc~0; 103612#L640 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 102897#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 102898#L651 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 103556#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 103557#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 103484#L658 assume !(1 == ~t6_pc~0); 103103#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 103104#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 103695#L670 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 104089#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 103711#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 102937#L677 assume 1 == ~t7_pc~0; 102938#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 102841#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 103892#L689 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 104047#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 104048#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 104138#L696 assume !(1 == ~t8_pc~0); 103159#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 103160#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 104099#L708 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 104124#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 104191#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 103593#L715 assume 1 == ~t9_pc~0; 103594#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 103253#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 103156#L727 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 103157#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 103579#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 103889#L734 assume !(1 == ~t10_pc~0); 103890#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 103060#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 103061#L746 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 103079#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 103820#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 103135#L753 assume 1 == ~t11_pc~0; 103136#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 103716#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 103248#L765 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 103249#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 103401#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 103460#L1237 assume !(1 == ~M_E~0); 103461#L1237-2 assume !(1 == ~T1_E~0); 104176#L1242-1 assume !(1 == ~T2_E~0); 103217#L1247-1 assume !(1 == ~T3_E~0); 103218#L1252-1 assume !(1 == ~T4_E~0); 102998#L1257-1 assume !(1 == ~T5_E~0); 102999#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 103904#L1267-1 assume !(1 == ~T7_E~0); 104039#L1272-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 103301#L1277-1 assume !(1 == ~T9_E~0); 103302#L1282-1 assume !(1 == ~T10_E~0); 103755#L1287-1 assume !(1 == ~T11_E~0); 103756#L1292-1 assume !(1 == ~E_M~0); 103710#L1297-1 assume !(1 == ~E_1~0); 103130#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 103131#L1307-1 assume !(1 == ~E_3~0); 104029#L1312-1 assume !(1 == ~E_4~0); 103346#L1317-1 assume !(1 == ~E_5~0); 103347#L1322-1 assume !(1 == ~E_6~0); 103075#L1327-1 assume !(1 == ~E_7~0); 103076#L1332-1 assume !(1 == ~E_8~0); 103653#L1337-1 assume !(1 == ~E_9~0); 103585#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 103586#L1347-1 assume !(1 == ~E_11~0); 104028#L1352-1 assume { :end_inline_reset_delta_events } true; 103888#L1678-2 [2021-11-13 17:45:58,117 INFO L793 eck$LassoCheckResult]: Loop: 103888#L1678-2 assume !false; 103645#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 103646#L1084 assume !false; 103416#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 103417#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 102712#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 103762#L911 eval_#t~ret8#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret8#1;havoc eval_#t~ret8#1; 102638#L925 assume !(0 != eval_~tmp~0#1); 102640#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 121876#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 121875#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 121873#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 121871#L1114-3 assume !(0 == ~T2_E~0); 121869#L1119-3 assume !(0 == ~T3_E~0); 121867#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 121865#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 121863#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 121861#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 121855#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 103115#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 103116#L1154-3 assume !(0 == ~T10_E~0); 122182#L1159-3 assume !(0 == ~T11_E~0); 122180#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 122178#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 122176#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 121940#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 104182#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 104183#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 121841#L1194-3 assume !(0 == ~E_6~0); 121840#L1199-3 assume !(0 == ~E_7~0); 121839#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 121838#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 102564#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 102565#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 103261#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 103262#L544-39 assume !(1 == ~m_pc~0); 102539#L544-41 is_master_triggered_~__retres1~0#1 := 0; 102540#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 103741#L556-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 118709#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 118708#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 118707#L563-39 assume 1 == ~t1_pc~0; 118705#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 118704#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 118703#L575-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 118702#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 118700#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 118698#L582-39 assume !(1 == ~t2_pc~0); 112769#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 118695#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 118692#L594-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 118690#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 118688#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 102573#L601-39 assume !(1 == ~t3_pc~0); 102575#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 102620#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 103815#L613-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 103975#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 104229#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 119009#L620-39 assume !(1 == ~t4_pc~0); 119008#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 119007#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 119006#L632-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 119005#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 119004#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 119003#L639-39 assume 1 == ~t5_pc~0; 119001#L640-13 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 119000#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 118999#L651-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 118998#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 118997#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 118996#L658-39 assume 1 == ~t6_pc~0; 118995#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 118993#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 118992#L670-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 118991#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 118990#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 118989#L677-39 assume 1 == ~t7_pc~0; 118987#L678-13 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 118986#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 118985#L689-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 118984#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 118983#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 118982#L696-39 assume !(1 == ~t8_pc~0); 118981#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 118979#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 118978#L708-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 118977#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 118976#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 118975#L715-39 assume 1 == ~t9_pc~0; 118973#L716-13 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 118972#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 118971#L727-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 118970#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 118969#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 118968#L734-39 assume !(1 == ~t10_pc~0); 118967#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 118965#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 118964#L746-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 118963#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 118962#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 118961#L753-39 assume 1 == ~t11_pc~0; 118960#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 118958#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 104096#L765-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 103372#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 103373#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 103470#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 103471#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 103774#L1242-3 assume !(1 == ~T2_E~0); 103775#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 104038#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 103679#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 103680#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 104017#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 104070#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 104188#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 102799#L1282-3 assume !(1 == ~T10_E~0); 102800#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 102709#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 102710#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 103895#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 103896#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 104135#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 104231#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 103796#L1322-3 assume !(1 == ~E_6~0); 103797#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 102767#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 102742#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 102743#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 103444#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 103577#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 103578#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 102686#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 102955#L911-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 103694#L1697 assume !(0 == start_simulation_~tmp~3#1); 103465#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 103466#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 102815#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 103596#L911-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 103597#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 103541#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 103126#L1660 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 103127#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 103888#L1678-2 [2021-11-13 17:45:58,117 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:58,117 INFO L85 PathProgramCache]: Analyzing trace with hash 1385195447, now seen corresponding path program 1 times [2021-11-13 17:45:58,118 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:58,118 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1289824173] [2021-11-13 17:45:58,118 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:58,118 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:58,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:58,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:58,170 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:58,170 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1289824173] [2021-11-13 17:45:58,170 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1289824173] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:58,170 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:58,170 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:58,170 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1369095449] [2021-11-13 17:45:58,171 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:58,171 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:45:58,171 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:45:58,172 INFO L85 PathProgramCache]: Analyzing trace with hash 1406550408, now seen corresponding path program 1 times [2021-11-13 17:45:58,172 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:45:58,172 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1104380804] [2021-11-13 17:45:58,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:45:58,172 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:45:58,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:45:58,338 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:45:58,338 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:45:58,338 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1104380804] [2021-11-13 17:45:58,338 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1104380804] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:45:58,339 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:45:58,339 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:45:58,339 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [97312053] [2021-11-13 17:45:58,339 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:45:58,340 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:45:58,340 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:45:58,341 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 17:45:58,341 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 17:45:58,341 INFO L87 Difference]: Start difference. First operand 19720 states and 28560 transitions. cyclomatic complexity: 8848 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:45:58,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:45:58,927 INFO L93 Difference]: Finished difference Result 48371 states and 69533 transitions. [2021-11-13 17:45:58,927 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 17:45:58,928 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48371 states and 69533 transitions. [2021-11-13 17:45:59,154 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 47440 [2021-11-13 17:45:59,345 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48371 states to 48371 states and 69533 transitions. [2021-11-13 17:45:59,346 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48371 [2021-11-13 17:45:59,499 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48371 [2021-11-13 17:45:59,500 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48371 states and 69533 transitions. [2021-11-13 17:45:59,541 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:45:59,541 INFO L681 BuchiCegarLoop]: Abstraction has 48371 states and 69533 transitions. [2021-11-13 17:45:59,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48371 states and 69533 transitions. [2021-11-13 17:46:00,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48371 to 38367. [2021-11-13 17:46:00,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38367 states, 38367 states have (on average 1.441577397242422) internal successors, (55309), 38366 states have internal predecessors, (55309), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:46:00,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38367 states to 38367 states and 55309 transitions. [2021-11-13 17:46:00,242 INFO L704 BuchiCegarLoop]: Abstraction has 38367 states and 55309 transitions. [2021-11-13 17:46:00,242 INFO L587 BuchiCegarLoop]: Abstraction has 38367 states and 55309 transitions. [2021-11-13 17:46:00,242 INFO L425 BuchiCegarLoop]: ======== Iteration 19============ [2021-11-13 17:46:00,242 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38367 states and 55309 transitions. [2021-11-13 17:46:00,362 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 38156 [2021-11-13 17:46:00,363 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:46:00,363 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:46:00,367 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:46:00,367 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:46:00,367 INFO L791 eck$LassoCheckResult]: Stem: 171378#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 171379#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 172204#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 172205#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 170873#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 170874#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 172216#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 172175#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 172176#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 171223#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 171224#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 171649#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 172134#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 171136#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 171137#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 171019#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 171020#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 172034#L1109 assume !(0 == ~M_E~0); 172063#L1109-2 assume !(0 == ~T1_E~0); 171026#L1114-1 assume !(0 == ~T2_E~0); 171027#L1119-1 assume !(0 == ~T3_E~0); 172138#L1124-1 assume !(0 == ~T4_E~0); 170693#L1129-1 assume !(0 == ~T5_E~0); 170694#L1134-1 assume !(0 == ~T6_E~0); 171307#L1139-1 assume !(0 == ~T7_E~0); 172042#L1144-1 assume !(0 == ~T8_E~0); 171893#L1149-1 assume !(0 == ~T9_E~0); 170797#L1154-1 assume !(0 == ~T10_E~0); 170798#L1159-1 assume !(0 == ~T11_E~0); 171878#L1164-1 assume !(0 == ~E_M~0); 171189#L1169-1 assume !(0 == ~E_1~0); 171076#L1174-1 assume !(0 == ~E_2~0); 170952#L1179-1 assume !(0 == ~E_3~0); 170877#L1184-1 assume !(0 == ~E_4~0); 170878#L1189-1 assume !(0 == ~E_5~0); 170909#L1194-1 assume !(0 == ~E_6~0); 170997#L1199-1 assume !(0 == ~E_7~0); 171903#L1204-1 assume !(0 == ~E_8~0); 171831#L1209-1 assume !(0 == ~E_9~0); 171832#L1214-1 assume !(0 == ~E_10~0); 172233#L1219-1 assume !(0 == ~E_11~0); 172366#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 171208#L544 assume !(1 == ~m_pc~0); 171209#L544-2 is_master_triggered_~__retres1~0#1 := 0; 172124#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 171915#L556 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 170840#L1379 assume !(0 != activate_threads_~tmp~1#1); 170841#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 171635#L563 assume !(1 == ~t1_pc~0); 171419#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 170701#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 170702#L575 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 171764#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 170697#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 170698#L582 assume !(1 == ~t2_pc~0); 171398#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 171775#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 171776#L594 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 171892#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 170727#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 170728#L601 assume !(1 == ~t3_pc~0); 171413#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 171412#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 172127#L613 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 171813#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 171814#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 171752#L620 assume !(1 == ~t4_pc~0); 171753#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 171325#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 171273#L632 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 171274#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 171646#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 171851#L639 assume !(1 == ~t5_pc~0); 171852#L639-2 is_transmit5_triggered_~__retres1~5#1 := 0; 170999#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 171000#L651 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 171667#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 171668#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 171597#L658 assume !(1 == ~t6_pc~0); 171203#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 171204#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 171804#L670 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 172206#L1427 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 171818#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 171041#L677 assume 1 == ~t7_pc~0; 171042#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 170946#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 172001#L689 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 172166#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 172167#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 172258#L696 assume !(1 == ~t8_pc~0); 171263#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 171264#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 172215#L708 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 172243#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 172324#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 171704#L715 assume 1 == ~t9_pc~0; 171705#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 171356#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 171260#L727 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 171261#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 171688#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 171998#L734 assume !(1 == ~t10_pc~0); 171999#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 171162#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 171163#L746 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 171183#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 171932#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 171239#L753 assume 1 == ~t11_pc~0; 171240#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 171824#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 171350#L765 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 171351#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 171509#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 171570#L1237 assume !(1 == ~M_E~0); 171571#L1237-2 assume !(1 == ~T1_E~0); 172309#L1242-1 assume !(1 == ~T2_E~0); 171321#L1247-1 assume !(1 == ~T3_E~0); 171322#L1252-1 assume !(1 == ~T4_E~0); 171099#L1257-1 assume !(1 == ~T5_E~0); 171100#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 172017#L1267-1 assume !(1 == ~T7_E~0); 172156#L1272-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 172157#L1277-1 assume !(1 == ~T9_E~0); 171943#L1282-1 assume !(1 == ~T10_E~0); 171944#L1287-1 assume !(1 == ~T11_E~0); 171904#L1292-1 assume !(1 == ~E_M~0); 171905#L1297-1 assume !(1 == ~E_1~0); 171232#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 171233#L1307-1 assume !(1 == ~E_3~0); 172329#L1312-1 assume !(1 == ~E_4~0); 172330#L1317-1 assume !(1 == ~E_5~0); 171699#L1322-1 assume !(1 == ~E_6~0); 171700#L1327-1 assume !(1 == ~E_7~0); 171762#L1332-1 assume !(1 == ~E_8~0); 171763#L1337-1 assume !(1 == ~E_9~0); 171694#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 171695#L1347-1 assume !(1 == ~E_11~0); 172140#L1352-1 assume { :end_inline_reset_delta_events } true; 172141#L1678-2 [2021-11-13 17:46:00,368 INFO L793 eck$LassoCheckResult]: Loop: 172141#L1678-2 assume !false; 207401#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 207397#L1084 assume !false; 207395#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 207382#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 207378#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 207376#L911 eval_#t~ret8#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret8#1;havoc eval_#t~ret8#1; 207372#L925 assume !(0 != eval_~tmp~0#1); 207373#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 208964#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 208963#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 208962#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 208927#L1114-3 assume !(0 == ~T2_E~0); 208926#L1119-3 assume !(0 == ~T3_E~0); 208924#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 208922#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 208920#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 208917#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 208916#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 208914#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 208912#L1154-3 assume !(0 == ~T10_E~0); 208910#L1159-3 assume !(0 == ~T11_E~0); 208908#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 208907#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 208906#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 208905#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 208904#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 208903#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 208902#L1194-3 assume !(0 == ~E_6~0); 208832#L1199-3 assume !(0 == ~E_7~0); 171908#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 171202#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 170667#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 170668#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 171364#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 171365#L544-39 assume !(1 == ~m_pc~0); 170640#L544-41 is_master_triggered_~__retres1~0#1 := 0; 170641#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 170889#L556-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 170890#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 171047#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 171970#L563-39 assume !(1 == ~t1_pc~0); 170787#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 170788#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 171715#L575-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 171716#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 172357#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 172106#L582-39 assume !(1 == ~t2_pc~0); 172107#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 171873#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 171765#L594-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 171766#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 170884#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 170671#L601-39 assume 1 == ~t3_pc~0; 170672#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 170719#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 171927#L613-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 172088#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 171975#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 171590#L620-39 assume !(1 == ~t4_pc~0); 171591#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 208564#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 208563#L632-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 208562#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 208561#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 208560#L639-39 assume !(1 == ~t5_pc~0); 179711#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 208559#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 208558#L651-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 208557#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 208556#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 208555#L658-39 assume 1 == ~t6_pc~0; 208554#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 208552#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 208551#L670-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 208550#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 208549#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 208548#L677-39 assume !(1 == ~t7_pc~0); 208547#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 208545#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 208544#L689-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 208543#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 208542#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 208541#L696-39 assume 1 == ~t8_pc~0; 208539#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 208538#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 208537#L708-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 208536#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 208535#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 208534#L715-39 assume !(1 == ~t9_pc~0); 208533#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 208531#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 208530#L727-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 208529#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 208528#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 208527#L734-39 assume !(1 == ~t10_pc~0); 208526#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 208524#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 208523#L746-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 208522#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 208521#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 208520#L753-39 assume 1 == ~t11_pc~0; 208519#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 208517#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 208516#L765-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 208515#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 208514#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 208513#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 208512#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 208511#L1242-3 assume !(1 == ~T2_E~0); 208510#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 208508#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 208507#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 208506#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 208503#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 208079#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 176302#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 208078#L1282-3 assume !(1 == ~T10_E~0); 208077#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 208075#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 208073#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 208071#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 208069#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 208067#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 208065#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 208063#L1322-3 assume !(1 == ~E_6~0); 176279#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 208060#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 208058#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 208056#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 208054#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 208052#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 172003#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 170793#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 171057#L911-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 171803#L1697 assume !(0 == start_simulation_~tmp~3#1); 171849#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 208197#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 208188#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 208187#L911-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 207412#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 207407#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 207406#L1660 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 207405#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 172141#L1678-2 [2021-11-13 17:46:00,369 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:46:00,369 INFO L85 PathProgramCache]: Analyzing trace with hash -772277576, now seen corresponding path program 1 times [2021-11-13 17:46:00,369 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:46:00,369 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1544506245] [2021-11-13 17:46:00,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:46:00,370 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:46:00,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:46:00,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:46:00,423 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:46:00,423 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1544506245] [2021-11-13 17:46:00,423 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1544506245] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:46:00,424 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:46:00,424 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-13 17:46:00,424 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1128183141] [2021-11-13 17:46:00,424 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:46:00,425 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:46:00,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:46:00,425 INFO L85 PathProgramCache]: Analyzing trace with hash -348382902, now seen corresponding path program 1 times [2021-11-13 17:46:00,426 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:46:00,426 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [69091547] [2021-11-13 17:46:00,426 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:46:00,574 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:46:00,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:46:00,658 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:46:00,658 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:46:00,659 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [69091547] [2021-11-13 17:46:00,659 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [69091547] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:46:00,659 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:46:00,659 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:46:00,659 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1833331094] [2021-11-13 17:46:00,659 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:46:00,661 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:46:00,661 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:46:00,661 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2021-11-13 17:46:00,662 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2021-11-13 17:46:00,662 INFO L87 Difference]: Start difference. First operand 38367 states and 55309 transitions. cyclomatic complexity: 16950 Second operand has 5 states, 5 states have (on average 27.8) internal successors, (139), 5 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:46:01,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:46:01,455 INFO L93 Difference]: Finished difference Result 96464 states and 139644 transitions. [2021-11-13 17:46:01,455 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2021-11-13 17:46:01,456 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 96464 states and 139644 transitions. [2021-11-13 17:46:01,980 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 96000 [2021-11-13 17:46:02,422 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 96464 states to 96464 states and 139644 transitions. [2021-11-13 17:46:02,422 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 96464 [2021-11-13 17:46:02,469 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 96464 [2021-11-13 17:46:02,469 INFO L73 IsDeterministic]: Start isDeterministic. Operand 96464 states and 139644 transitions. [2021-11-13 17:46:02,587 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:46:02,587 INFO L681 BuchiCegarLoop]: Abstraction has 96464 states and 139644 transitions. [2021-11-13 17:46:02,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96464 states and 139644 transitions. [2021-11-13 17:46:03,421 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96464 to 39498. [2021-11-13 17:46:03,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39498 states, 39498 states have (on average 1.4289331105372425) internal successors, (56440), 39497 states have internal predecessors, (56440), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:46:03,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39498 states to 39498 states and 56440 transitions. [2021-11-13 17:46:03,570 INFO L704 BuchiCegarLoop]: Abstraction has 39498 states and 56440 transitions. [2021-11-13 17:46:03,571 INFO L587 BuchiCegarLoop]: Abstraction has 39498 states and 56440 transitions. [2021-11-13 17:46:03,571 INFO L425 BuchiCegarLoop]: ======== Iteration 20============ [2021-11-13 17:46:03,571 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39498 states and 56440 transitions. [2021-11-13 17:46:03,711 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 39284 [2021-11-13 17:46:03,711 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:46:03,711 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:46:03,715 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:46:03,715 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:46:03,716 INFO L791 eck$LassoCheckResult]: Stem: 306222#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 306223#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 307066#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 307067#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 305715#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 305716#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 307082#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 307038#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 307039#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 306068#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 306069#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 306500#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 306993#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 305980#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 305981#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 305863#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 305864#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 306891#L1109 assume !(0 == ~M_E~0); 306920#L1109-2 assume !(0 == ~T1_E~0); 305870#L1114-1 assume !(0 == ~T2_E~0); 305871#L1119-1 assume !(0 == ~T3_E~0); 306998#L1124-1 assume !(0 == ~T4_E~0); 305536#L1129-1 assume !(0 == ~T5_E~0); 305537#L1134-1 assume !(0 == ~T6_E~0); 306150#L1139-1 assume !(0 == ~T7_E~0); 306900#L1144-1 assume !(0 == ~T8_E~0); 306747#L1149-1 assume !(0 == ~T9_E~0); 305640#L1154-1 assume !(0 == ~T10_E~0); 305641#L1159-1 assume !(0 == ~T11_E~0); 306733#L1164-1 assume !(0 == ~E_M~0); 306034#L1169-1 assume !(0 == ~E_1~0); 305922#L1174-1 assume !(0 == ~E_2~0); 305794#L1179-1 assume !(0 == ~E_3~0); 305719#L1184-1 assume !(0 == ~E_4~0); 305720#L1189-1 assume !(0 == ~E_5~0); 305751#L1194-1 assume !(0 == ~E_6~0); 305840#L1199-1 assume !(0 == ~E_7~0); 306755#L1204-1 assume !(0 == ~E_8~0); 306686#L1209-1 assume !(0 == ~E_9~0); 306687#L1214-1 assume !(0 == ~E_10~0); 307099#L1219-1 assume !(0 == ~E_11~0); 307243#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 306054#L544 assume !(1 == ~m_pc~0); 306055#L544-2 is_master_triggered_~__retres1~0#1 := 0; 306983#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 306765#L556 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 305681#L1379 assume !(0 != activate_threads_~tmp~1#1); 305682#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 306483#L563 assume !(1 == ~t1_pc~0); 306263#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 305544#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 305545#L575 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 306618#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 305540#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 305541#L582 assume !(1 == ~t2_pc~0); 306242#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 306628#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 306629#L594 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 306746#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 305570#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 305571#L601 assume !(1 == ~t3_pc~0); 306257#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 306256#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 306984#L613 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 306668#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 306669#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 306607#L620 assume !(1 == ~t4_pc~0); 306608#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 306170#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 306115#L632 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 306116#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 306497#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 306707#L639 assume !(1 == ~t5_pc~0); 306708#L639-2 is_transmit5_triggered_~__retres1~5#1 := 0; 305842#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 305843#L651 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 306519#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 306520#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 306437#L658 assume !(1 == ~t6_pc~0); 306048#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 306049#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 306660#L670 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 307245#L1427 assume !(0 != activate_threads_~tmp___5~0#1); 306672#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 305885#L677 assume 1 == ~t7_pc~0; 305886#L678 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 305788#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 306857#L689 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 307028#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 307029#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 307130#L696 assume !(1 == ~t8_pc~0); 306107#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 306108#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 307081#L708 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 307112#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 307190#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 306556#L715 assume 1 == ~t9_pc~0; 306557#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 306200#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 306104#L727 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 306105#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 306543#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 306854#L734 assume !(1 == ~t10_pc~0); 306855#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 306007#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 306008#L746 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 306028#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 306780#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 306082#L753 assume 1 == ~t11_pc~0; 306083#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 306680#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 306195#L765 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 306196#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 306352#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 306413#L1237 assume !(1 == ~M_E~0); 306414#L1237-2 assume !(1 == ~T1_E~0); 307174#L1242-1 assume !(1 == ~T2_E~0); 306166#L1247-1 assume !(1 == ~T3_E~0); 306167#L1252-1 assume !(1 == ~T4_E~0); 305945#L1257-1 assume !(1 == ~T5_E~0); 305946#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 306871#L1267-1 assume !(1 == ~T7_E~0); 307014#L1272-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 307015#L1277-1 assume !(1 == ~T9_E~0); 335615#L1282-1 assume !(1 == ~T10_E~0); 335614#L1287-1 assume !(1 == ~T11_E~0); 335613#L1292-1 assume !(1 == ~E_M~0); 335612#L1297-1 assume !(1 == ~E_1~0); 335611#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 335610#L1307-1 assume !(1 == ~E_3~0); 335609#L1312-1 assume !(1 == ~E_4~0); 335608#L1317-1 assume !(1 == ~E_5~0); 335607#L1322-1 assume !(1 == ~E_6~0); 306024#L1327-1 assume !(1 == ~E_7~0); 306025#L1332-1 assume !(1 == ~E_8~0); 306617#L1337-1 assume !(1 == ~E_9~0); 306547#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 306548#L1347-1 assume !(1 == ~E_11~0); 307000#L1352-1 assume { :end_inline_reset_delta_events } true; 306853#L1678-2 [2021-11-13 17:46:03,717 INFO L793 eck$LassoCheckResult]: Loop: 306853#L1678-2 assume !false; 306609#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 306610#L1084 assume !false; 306366#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 306367#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 305657#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 306724#L911 eval_#t~ret8#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret8#1;havoc eval_#t~ret8#1; 305583#L925 assume !(0 != eval_~tmp~0#1); 305585#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 344970#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 344968#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 344966#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 344964#L1114-3 assume !(0 == ~T2_E~0); 344962#L1119-3 assume !(0 == ~T3_E~0); 344961#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 344960#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 344959#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 344958#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 344957#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 344956#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 344954#L1154-3 assume !(0 == ~T10_E~0); 344953#L1159-3 assume !(0 == ~T11_E~0); 344951#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 344949#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 344940#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 344939#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 344935#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 344931#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 344924#L1194-3 assume !(0 == ~E_6~0); 344874#L1199-3 assume !(0 == ~E_7~0); 344872#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 344777#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 344776#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 344760#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 306209#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 306210#L544-39 assume !(1 == ~m_pc~0); 305484#L544-41 is_master_triggered_~__retres1~0#1 := 0; 305485#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 305731#L556-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 305732#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 305891#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 306820#L563-39 assume !(1 == ~t1_pc~0); 305633#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 305634#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 306567#L575-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 306568#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 343572#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 306968#L582-39 assume !(1 == ~t2_pc~0); 306969#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 306728#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 306619#L594-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 306620#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 305726#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 305518#L601-39 assume !(1 == ~t3_pc~0); 305520#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 305565#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 306776#L613-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 306945#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 306826#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 306433#L620-39 assume !(1 == ~t4_pc~0); 306434#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 306896#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 306897#L632-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 306789#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 306790#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 307264#L639-39 assume !(1 == ~t5_pc~0); 307168#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 306171#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 305739#L651-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 305546#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 305547#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 306477#L658-39 assume !(1 == ~t6_pc~0); 306453#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 344646#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 344645#L670-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 344142#L1427-39 assume !(0 != activate_threads_~tmp___5~0#1); 344139#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 344137#L677-39 assume !(1 == ~t7_pc~0); 344135#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 344132#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 344131#L689-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 344128#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 344126#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 344124#L696-39 assume !(1 == ~t8_pc~0); 344121#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 306192#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 306193#L708-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 306509#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 306465#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 306331#L715-39 assume !(1 == ~t9_pc~0); 305525#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 305524#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 306782#L727-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 307268#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 306709#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 306710#L734-39 assume 1 == ~t10_pc~0; 306624#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 306032#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 306353#L746-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 305671#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 305672#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 307041#L753-39 assume !(1 == ~t11_pc~0); 305589#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 305590#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 306987#L765-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 306321#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 306322#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 306428#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 306429#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 306736#L1242-3 assume !(1 == ~T2_E~0); 306737#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 307011#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 306645#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 306646#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 306988#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 307048#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 307186#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 305743#L1282-3 assume !(1 == ~T10_E~0); 305744#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 305654#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 305655#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 306863#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 306864#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 307127#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 307251#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 306759#L1322-3 assume !(1 == ~E_6~0); 306760#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 305712#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 305687#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 305688#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 306393#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 306541#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 306542#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 305631#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 305901#L911-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 306659#L1697 assume !(0 == start_simulation_~tmp~3#1); 306421#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 306422#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 305759#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 306559#L911-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 306560#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 306503#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 306075#L1660 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 306076#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 306853#L1678-2 [2021-11-13 17:46:03,717 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:46:03,718 INFO L85 PathProgramCache]: Analyzing trace with hash 488639674, now seen corresponding path program 1 times [2021-11-13 17:46:03,718 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:46:03,718 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1320320830] [2021-11-13 17:46:03,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:46:03,719 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:46:03,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:46:03,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:46:03,765 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:46:03,766 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1320320830] [2021-11-13 17:46:03,766 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1320320830] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:46:03,766 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:46:03,766 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:46:03,766 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [160767322] [2021-11-13 17:46:03,767 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:46:03,767 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:46:03,767 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:46:03,768 INFO L85 PathProgramCache]: Analyzing trace with hash 1588990735, now seen corresponding path program 1 times [2021-11-13 17:46:03,768 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:46:03,768 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [761862478] [2021-11-13 17:46:03,768 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:46:03,768 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:46:03,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:46:03,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:46:03,814 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:46:03,815 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [761862478] [2021-11-13 17:46:03,815 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [761862478] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:46:03,815 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:46:03,815 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-13 17:46:03,816 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [499156411] [2021-11-13 17:46:03,816 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:46:03,816 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:46:03,816 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:46:03,817 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 17:46:03,817 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 17:46:03,817 INFO L87 Difference]: Start difference. First operand 39498 states and 56440 transitions. cyclomatic complexity: 16950 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:46:04,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:46:04,546 INFO L93 Difference]: Finished difference Result 95397 states and 135457 transitions. [2021-11-13 17:46:04,547 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 17:46:04,547 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 95397 states and 135457 transitions. [2021-11-13 17:46:05,272 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 93656 [2021-11-13 17:46:05,526 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 95397 states to 95397 states and 135457 transitions. [2021-11-13 17:46:05,528 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 95397 [2021-11-13 17:46:05,582 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 95397 [2021-11-13 17:46:05,583 INFO L73 IsDeterministic]: Start isDeterministic. Operand 95397 states and 135457 transitions. [2021-11-13 17:46:05,626 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:46:05,626 INFO L681 BuchiCegarLoop]: Abstraction has 95397 states and 135457 transitions. [2021-11-13 17:46:05,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95397 states and 135457 transitions. [2021-11-13 17:46:06,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95397 to 75605. [2021-11-13 17:46:06,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 75605 states, 75605 states have (on average 1.4239402155942067) internal successors, (107657), 75604 states have internal predecessors, (107657), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:46:06,720 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75605 states to 75605 states and 107657 transitions. [2021-11-13 17:46:06,720 INFO L704 BuchiCegarLoop]: Abstraction has 75605 states and 107657 transitions. [2021-11-13 17:46:06,721 INFO L587 BuchiCegarLoop]: Abstraction has 75605 states and 107657 transitions. [2021-11-13 17:46:06,721 INFO L425 BuchiCegarLoop]: ======== Iteration 21============ [2021-11-13 17:46:06,721 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 75605 states and 107657 transitions. [2021-11-13 17:46:07,297 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 75344 [2021-11-13 17:46:07,297 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:46:07,297 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:46:07,322 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:46:07,322 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:46:07,322 INFO L791 eck$LassoCheckResult]: Stem: 441129#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 441130#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 441979#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 441980#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 440625#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 440626#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 441993#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 441949#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 441950#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 440976#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 440977#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 441405#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 441910#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 440887#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 440888#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 440773#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 440774#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 441809#L1109 assume !(0 == ~M_E~0); 441836#L1109-2 assume !(0 == ~T1_E~0); 440780#L1114-1 assume !(0 == ~T2_E~0); 440781#L1119-1 assume !(0 == ~T3_E~0); 441915#L1124-1 assume !(0 == ~T4_E~0); 440443#L1129-1 assume !(0 == ~T5_E~0); 440444#L1134-1 assume !(0 == ~T6_E~0); 441058#L1139-1 assume !(0 == ~T7_E~0); 441815#L1144-1 assume !(0 == ~T8_E~0); 441658#L1149-1 assume !(0 == ~T9_E~0); 440547#L1154-1 assume !(0 == ~T10_E~0); 440548#L1159-1 assume !(0 == ~T11_E~0); 441644#L1164-1 assume !(0 == ~E_M~0); 440940#L1169-1 assume !(0 == ~E_1~0); 440827#L1174-1 assume !(0 == ~E_2~0); 440705#L1179-1 assume !(0 == ~E_3~0); 440629#L1184-1 assume !(0 == ~E_4~0); 440630#L1189-1 assume !(0 == ~E_5~0); 440661#L1194-1 assume !(0 == ~E_6~0); 440751#L1199-1 assume !(0 == ~E_7~0); 441666#L1204-1 assume !(0 == ~E_8~0); 441596#L1209-1 assume !(0 == ~E_9~0); 441597#L1214-1 assume !(0 == ~E_10~0); 442009#L1219-1 assume !(0 == ~E_11~0); 442145#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 440960#L544 assume !(1 == ~m_pc~0); 440961#L544-2 is_master_triggered_~__retres1~0#1 := 0; 441900#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 441678#L556 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 440592#L1379 assume !(0 != activate_threads_~tmp~1#1); 440593#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 441390#L563 assume !(1 == ~t1_pc~0); 441173#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 440451#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 440452#L575 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 441528#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 440447#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 440448#L582 assume !(1 == ~t2_pc~0); 441149#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 441538#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 441539#L594 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 441657#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 440477#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 440478#L601 assume !(1 == ~t3_pc~0); 441166#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 441165#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 441903#L613 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 441575#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 441576#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 441512#L620 assume !(1 == ~t4_pc~0); 441513#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 441077#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 441022#L632 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 441023#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 441402#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 441616#L639 assume !(1 == ~t5_pc~0); 441617#L639-2 is_transmit5_triggered_~__retres1~5#1 := 0; 440753#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 440754#L651 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 441423#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 441424#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 441347#L658 assume !(1 == ~t6_pc~0); 440955#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 440956#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 442175#L670 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 442146#L1427 assume !(0 != activate_threads_~tmp___5~0#1); 441580#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 440795#L677 assume !(1 == ~t7_pc~0); 440697#L677-2 is_transmit7_triggered_~__retres1~7#1 := 0; 440698#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 441776#L689 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 441941#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 441942#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 442035#L696 assume !(1 == ~t8_pc~0); 441013#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 441014#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 441992#L708 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 442017#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 442102#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 441465#L715 assume 1 == ~t9_pc~0; 441466#L716 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 441109#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 441010#L727 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 441011#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 441448#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 441773#L734 assume !(1 == ~t10_pc~0); 441774#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 440913#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 440914#L746 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 440934#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 441695#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 440989#L753 assume 1 == ~t11_pc~0; 440990#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 441587#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 441103#L765 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 441104#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 441260#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 441322#L1237 assume !(1 == ~M_E~0); 441323#L1237-2 assume !(1 == ~T1_E~0); 442080#L1242-1 assume !(1 == ~T2_E~0); 441073#L1247-1 assume !(1 == ~T3_E~0); 441074#L1252-1 assume !(1 == ~T4_E~0); 440851#L1257-1 assume !(1 == ~T5_E~0); 440852#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 441789#L1267-1 assume !(1 == ~T7_E~0); 441930#L1272-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 441931#L1277-1 assume !(1 == ~T9_E~0); 441707#L1282-1 assume !(1 == ~T10_E~0); 441708#L1287-1 assume !(1 == ~T11_E~0); 441667#L1292-1 assume !(1 == ~E_M~0); 441668#L1297-1 assume !(1 == ~E_1~0); 440984#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 440985#L1307-1 assume !(1 == ~E_3~0); 442106#L1312-1 assume !(1 == ~E_4~0); 442107#L1317-1 assume !(1 == ~E_5~0); 441460#L1322-1 assume !(1 == ~E_6~0); 441461#L1327-1 assume !(1 == ~E_7~0); 441526#L1332-1 assume !(1 == ~E_8~0); 441527#L1337-1 assume !(1 == ~E_9~0); 441455#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 441456#L1347-1 assume !(1 == ~E_11~0); 441917#L1352-1 assume { :end_inline_reset_delta_events } true; 441918#L1678-2 [2021-11-13 17:46:07,322 INFO L793 eck$LassoCheckResult]: Loop: 441918#L1678-2 assume !false; 511848#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 511844#L1084 assume !false; 510690#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 491066#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 491063#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 491062#L911 eval_#t~ret8#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret8#1;havoc eval_#t~ret8#1; 491060#L925 assume !(0 != eval_~tmp~0#1); 491061#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 515932#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 515931#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 515930#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 442027#L1114-3 assume !(0 == ~T2_E~0); 441581#L1119-3 assume !(0 == ~T3_E~0); 441582#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 441610#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 441611#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 441828#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 441908#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 440969#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 440970#L1154-3 assume !(0 == ~T10_E~0); 441215#L1159-3 assume !(0 == ~T11_E~0); 441216#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 441509#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 441510#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 441568#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 441569#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 441759#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 441380#L1194-3 assume !(0 == ~E_6~0); 440726#L1199-3 assume !(0 == ~E_7~0); 440727#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 441671#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 440413#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 440414#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 441117#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 441118#L544-39 assume !(1 == ~m_pc~0); 440391#L544-41 is_master_triggered_~__retres1~0#1 := 0; 440392#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 440643#L556-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 440644#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 440800#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 441739#L563-39 assume 1 == ~t1_pc~0; 441750#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 440544#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 441478#L575-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 441479#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 442136#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 441884#L582-39 assume !(1 == ~t2_pc~0); 441885#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 441637#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 441529#L594-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 441530#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 440636#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 440425#L601-39 assume 1 == ~t3_pc~0; 440426#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 440472#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 441690#L613-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 441863#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 441746#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 441343#L620-39 assume !(1 == ~t4_pc~0); 441344#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 441812#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 441813#L632-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 441705#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 441706#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 442170#L639-39 assume !(1 == ~t5_pc~0); 513660#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 513622#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 513615#L651-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 513607#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 513599#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 513596#L658-39 assume !(1 == ~t6_pc~0); 513594#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 513610#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 513602#L670-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 513583#L1427-39 assume !(0 != activate_threads_~tmp___5~0#1); 513580#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 513578#L677-39 assume !(1 == ~t7_pc~0); 471414#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 513575#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 513566#L689-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 513563#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 513561#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 513559#L696-39 assume !(1 == ~t8_pc~0); 513554#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 513551#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 513549#L708-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 513547#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 513545#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 513534#L715-39 assume !(1 == ~t9_pc~0); 513527#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 513524#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 513522#L727-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 513520#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 513505#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 513495#L734-39 assume !(1 == ~t10_pc~0); 513486#L734-41 is_transmit10_triggered_~__retres1~10#1 := 0; 513446#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 513443#L746-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 513441#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 513439#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 513437#L753-39 assume 1 == ~t11_pc~0; 513435#L754-13 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 513432#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 513429#L765-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 513427#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 513425#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 513423#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 513421#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 513419#L1242-3 assume !(1 == ~T2_E~0); 513417#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 513415#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 513413#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 513411#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 513409#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 513407#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 510023#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 513404#L1282-3 assume !(1 == ~T10_E~0); 513403#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 513401#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 513399#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 513397#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 513395#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 513388#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 513380#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 513374#L1322-3 assume !(1 == ~E_6~0); 509954#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 513346#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 513344#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 513342#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 513324#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 513321#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 513271#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 513267#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 513265#L911-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 513262#L1697 assume !(0 == start_simulation_~tmp~3#1); 513257#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 513205#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 513195#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 513193#L911-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 513191#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 513189#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 513182#L1660 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 513178#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 441918#L1678-2 [2021-11-13 17:46:07,323 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:46:07,323 INFO L85 PathProgramCache]: Analyzing trace with hash -619488965, now seen corresponding path program 1 times [2021-11-13 17:46:07,323 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:46:07,323 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [577516083] [2021-11-13 17:46:07,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:46:07,324 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:46:07,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:46:07,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:46:07,372 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:46:07,373 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [577516083] [2021-11-13 17:46:07,373 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [577516083] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:46:07,373 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:46:07,373 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:46:07,373 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2029568491] [2021-11-13 17:46:07,373 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:46:07,374 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:46:07,375 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:46:07,375 INFO L85 PathProgramCache]: Analyzing trace with hash 4130765, now seen corresponding path program 1 times [2021-11-13 17:46:07,375 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:46:07,375 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [864073666] [2021-11-13 17:46:07,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:46:07,376 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:46:07,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:46:07,419 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:46:07,420 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:46:07,420 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [864073666] [2021-11-13 17:46:07,420 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [864073666] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:46:07,420 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:46:07,420 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-13 17:46:07,421 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [562038931] [2021-11-13 17:46:07,421 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:46:07,421 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:46:07,422 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:46:07,422 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 17:46:07,422 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 17:46:07,423 INFO L87 Difference]: Start difference. First operand 75605 states and 107657 transitions. cyclomatic complexity: 32060 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:46:08,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:46:08,316 INFO L93 Difference]: Finished difference Result 181768 states and 257250 transitions. [2021-11-13 17:46:08,318 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 17:46:08,318 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 181768 states and 257250 transitions. [2021-11-13 17:46:09,584 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 178468 [2021-11-13 17:46:10,081 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 181768 states to 181768 states and 257250 transitions. [2021-11-13 17:46:10,082 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 181768 [2021-11-13 17:46:10,174 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 181768 [2021-11-13 17:46:10,174 INFO L73 IsDeterministic]: Start isDeterministic. Operand 181768 states and 257250 transitions. [2021-11-13 17:46:10,271 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:46:10,271 INFO L681 BuchiCegarLoop]: Abstraction has 181768 states and 257250 transitions. [2021-11-13 17:46:10,392 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181768 states and 257250 transitions. [2021-11-13 17:46:12,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181768 to 144660. [2021-11-13 17:46:12,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 144660 states, 144660 states have (on average 1.4193142541130928) internal successors, (205318), 144659 states have internal predecessors, (205318), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:46:12,761 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144660 states to 144660 states and 205318 transitions. [2021-11-13 17:46:12,761 INFO L704 BuchiCegarLoop]: Abstraction has 144660 states and 205318 transitions. [2021-11-13 17:46:12,761 INFO L587 BuchiCegarLoop]: Abstraction has 144660 states and 205318 transitions. [2021-11-13 17:46:12,761 INFO L425 BuchiCegarLoop]: ======== Iteration 22============ [2021-11-13 17:46:12,761 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 144660 states and 205318 transitions. [2021-11-13 17:46:13,138 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 144304 [2021-11-13 17:46:13,138 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:46:13,138 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:46:13,143 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:46:13,144 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:46:13,144 INFO L791 eck$LassoCheckResult]: Stem: 698517#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 698518#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 699364#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 699365#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 698009#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 698010#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 699378#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 699330#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 699331#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 698361#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 698362#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 698797#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 699290#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 698271#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 698272#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 698159#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 698160#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 699197#L1109 assume !(0 == ~M_E~0); 699222#L1109-2 assume !(0 == ~T1_E~0); 698168#L1114-1 assume !(0 == ~T2_E~0); 698169#L1119-1 assume !(0 == ~T3_E~0); 699295#L1124-1 assume !(0 == ~T4_E~0); 697829#L1129-1 assume !(0 == ~T5_E~0); 697830#L1134-1 assume !(0 == ~T6_E~0); 698446#L1139-1 assume !(0 == ~T7_E~0); 699204#L1144-1 assume !(0 == ~T8_E~0); 699050#L1149-1 assume !(0 == ~T9_E~0); 697933#L1154-1 assume !(0 == ~T10_E~0); 697934#L1159-1 assume !(0 == ~T11_E~0); 699036#L1164-1 assume !(0 == ~E_M~0); 698325#L1169-1 assume !(0 == ~E_1~0); 698216#L1174-1 assume !(0 == ~E_2~0); 698090#L1179-1 assume !(0 == ~E_3~0); 698013#L1184-1 assume !(0 == ~E_4~0); 698014#L1189-1 assume !(0 == ~E_5~0); 698046#L1194-1 assume !(0 == ~E_6~0); 698135#L1199-1 assume !(0 == ~E_7~0); 699060#L1204-1 assume !(0 == ~E_8~0); 698991#L1209-1 assume !(0 == ~E_9~0); 698992#L1214-1 assume !(0 == ~E_10~0); 699396#L1219-1 assume !(0 == ~E_11~0); 699534#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 698345#L544 assume !(1 == ~m_pc~0); 698346#L544-2 is_master_triggered_~__retres1~0#1 := 0; 699280#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 699072#L556 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 697976#L1379 assume !(0 != activate_threads_~tmp~1#1); 697977#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 698782#L563 assume !(1 == ~t1_pc~0); 698561#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 697837#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 697838#L575 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 698921#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 697833#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 697834#L582 assume !(1 == ~t2_pc~0); 698537#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 698932#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 698933#L594 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 699049#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 697863#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 697864#L601 assume !(1 == ~t3_pc~0); 698555#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 698554#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 699283#L613 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 698969#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 698970#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 698905#L620 assume !(1 == ~t4_pc~0); 698906#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 698467#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 698410#L632 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 698411#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 698794#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 699010#L639 assume !(1 == ~t5_pc~0); 699011#L639-2 is_transmit5_triggered_~__retres1~5#1 := 0; 698137#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 698138#L651 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 698816#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 698817#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 698741#L658 assume !(1 == ~t6_pc~0); 698340#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 698341#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 699574#L670 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 699538#L1427 assume !(0 != activate_threads_~tmp___5~0#1); 698974#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 698183#L677 assume !(1 == ~t7_pc~0); 698082#L677-2 is_transmit7_triggered_~__retres1~7#1 := 0; 698083#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 699161#L689 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 699321#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 699322#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 699421#L696 assume !(1 == ~t8_pc~0); 698401#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 698402#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 699377#L708 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 699406#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 699485#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 698857#L715 assume !(1 == ~t9_pc~0); 698858#L715-2 is_transmit9_triggered_~__retres1~9#1 := 0; 698497#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 698396#L727 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 698397#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 698842#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 699158#L734 assume !(1 == ~t10_pc~0); 699159#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 698298#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 698299#L746 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 698319#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 699088#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 698374#L753 assume 1 == ~t11_pc~0; 698375#L754 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 698984#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 698492#L765 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 698493#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 698651#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 698714#L1237 assume !(1 == ~M_E~0); 698715#L1237-2 assume !(1 == ~T1_E~0); 699470#L1242-1 assume !(1 == ~T2_E~0); 698463#L1247-1 assume !(1 == ~T3_E~0); 698464#L1252-1 assume !(1 == ~T4_E~0); 698239#L1257-1 assume !(1 == ~T5_E~0); 698240#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 699177#L1267-1 assume !(1 == ~T7_E~0); 699311#L1272-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 698548#L1277-1 assume !(1 == ~T9_E~0); 698549#L1282-1 assume !(1 == ~T10_E~0); 699021#L1287-1 assume !(1 == ~T11_E~0); 699022#L1292-1 assume !(1 == ~E_M~0); 698972#L1297-1 assume !(1 == ~E_1~0); 698973#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 699299#L1307-1 assume !(1 == ~E_3~0); 699300#L1312-1 assume !(1 == ~E_4~0); 698593#L1317-1 assume !(1 == ~E_5~0); 698594#L1322-1 assume !(1 == ~E_6~0); 698315#L1327-1 assume !(1 == ~E_7~0); 698316#L1332-1 assume !(1 == ~E_8~0); 699480#L1337-1 assume !(1 == ~E_9~0); 699481#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 699425#L1347-1 assume !(1 == ~E_11~0); 699426#L1352-1 assume { :end_inline_reset_delta_events } true; 800674#L1678-2 [2021-11-13 17:46:13,145 INFO L793 eck$LassoCheckResult]: Loop: 800674#L1678-2 assume !false; 800670#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 800667#L1084 assume !false; 800666#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 800556#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 800546#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 800538#L911 eval_#t~ret8#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret8#1;havoc eval_#t~ret8#1; 800532#L925 assume !(0 != eval_~tmp~0#1); 800533#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 801250#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 801248#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 801246#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 801244#L1114-3 assume !(0 == ~T2_E~0); 801242#L1119-3 assume !(0 == ~T3_E~0); 801240#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 801238#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 801236#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 801234#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 801232#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 801230#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 801228#L1154-3 assume !(0 == ~T10_E~0); 801226#L1159-3 assume !(0 == ~T11_E~0); 801224#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 801222#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 801220#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 801218#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 801216#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 801214#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 801212#L1194-3 assume !(0 == ~E_6~0); 801210#L1199-3 assume !(0 == ~E_7~0); 801208#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 801206#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 801204#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 801202#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 801200#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 801198#L544-39 assume !(1 == ~m_pc~0); 801196#L544-41 is_master_triggered_~__retres1~0#1 := 0; 801194#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 801192#L556-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 801190#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 801188#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 801186#L563-39 assume 1 == ~t1_pc~0; 801183#L564-13 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 801181#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 801178#L575-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 801176#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 801174#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 801172#L582-39 assume !(1 == ~t2_pc~0); 800747#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 801169#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 801168#L594-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 801166#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 801164#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 801162#L601-39 assume !(1 == ~t3_pc~0); 801160#L601-41 is_transmit3_triggered_~__retres1~3#1 := 0; 801157#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 801154#L613-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 801152#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 801150#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 801148#L620-39 assume !(1 == ~t4_pc~0); 801146#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 801144#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 801142#L632-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 801140#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 801138#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 801136#L639-39 assume !(1 == ~t5_pc~0); 800093#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 801133#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 801132#L651-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 801130#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 801128#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 801126#L658-39 assume 1 == ~t6_pc~0; 801124#L659-13 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 801125#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 801788#L670-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 801113#L1427-39 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 801111#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 801108#L677-39 assume !(1 == ~t7_pc~0); 792060#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 801105#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 801104#L689-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 801102#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 801100#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 801098#L696-39 assume !(1 == ~t8_pc~0); 801096#L696-41 is_transmit8_triggered_~__retres1~8#1 := 0; 801093#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 801090#L708-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 801088#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 801086#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 801084#L715-39 assume !(1 == ~t9_pc~0); 758400#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 801081#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 801080#L727-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 801078#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 801076#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 801074#L734-39 assume 1 == ~t10_pc~0; 801071#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 801069#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 801066#L746-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 801064#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 801062#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 801060#L753-39 assume !(1 == ~t11_pc~0); 801057#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 801055#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 801052#L765-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 801050#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 801048#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 801046#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 801044#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 801042#L1242-3 assume !(1 == ~T2_E~0); 801040#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 801038#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 801036#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 801034#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 801032#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 801030#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 801028#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 801026#L1282-3 assume !(1 == ~T10_E~0); 801024#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 801022#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 801020#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 801018#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 801016#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 801014#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 801012#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 801007#L1322-3 assume !(1 == ~E_6~0); 801005#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 801004#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 801003#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 801002#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 801001#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 801000#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 800990#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 800987#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 800986#L911-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 800791#L1697 assume !(0 == start_simulation_~tmp~3#1); 800789#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 800696#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 800686#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 800684#L911-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 800681#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 800679#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 800677#L1660 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 800676#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 800674#L1678-2 [2021-11-13 17:46:13,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:46:13,146 INFO L85 PathProgramCache]: Analyzing trace with hash 1279041340, now seen corresponding path program 1 times [2021-11-13 17:46:13,146 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:46:13,146 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [649306712] [2021-11-13 17:46:13,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:46:13,147 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:46:13,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:46:13,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:46:13,201 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:46:13,202 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [649306712] [2021-11-13 17:46:13,203 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [649306712] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:46:13,203 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:46:13,203 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:46:13,203 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1579663928] [2021-11-13 17:46:13,205 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:46:13,205 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:46:13,206 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:46:13,206 INFO L85 PathProgramCache]: Analyzing trace with hash 1929215819, now seen corresponding path program 1 times [2021-11-13 17:46:13,206 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:46:13,206 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1075638711] [2021-11-13 17:46:13,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:46:13,207 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:46:13,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:46:13,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:46:13,271 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:46:13,271 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1075638711] [2021-11-13 17:46:13,271 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1075638711] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:46:13,272 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:46:13,272 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2021-11-13 17:46:13,272 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [963415334] [2021-11-13 17:46:13,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:46:13,273 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:46:13,273 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:46:13,273 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2021-11-13 17:46:13,273 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2021-11-13 17:46:13,274 INFO L87 Difference]: Start difference. First operand 144660 states and 205318 transitions. cyclomatic complexity: 60666 Second operand has 4 states, 4 states have (on average 34.75) internal successors, (139), 3 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:46:15,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:46:15,254 INFO L93 Difference]: Finished difference Result 345811 states and 487907 transitions. [2021-11-13 17:46:15,254 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2021-11-13 17:46:15,254 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 345811 states and 487907 transitions. [2021-11-13 17:46:17,457 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 339408 [2021-11-13 17:46:18,929 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 345811 states to 345811 states and 487907 transitions. [2021-11-13 17:46:18,930 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 345811 [2021-11-13 17:46:19,037 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 345811 [2021-11-13 17:46:19,037 INFO L73 IsDeterministic]: Start isDeterministic. Operand 345811 states and 487907 transitions. [2021-11-13 17:46:19,134 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:46:19,135 INFO L681 BuchiCegarLoop]: Abstraction has 345811 states and 487907 transitions. [2021-11-13 17:46:19,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 345811 states and 487907 transitions. [2021-11-13 17:46:22,006 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 345811 to 276515. [2021-11-13 17:46:22,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 276515 states, 276515 states have (on average 1.4150516246858218) internal successors, (391283), 276514 states have internal predecessors, (391283), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:46:22,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 276515 states to 276515 states and 391283 transitions. [2021-11-13 17:46:22,837 INFO L704 BuchiCegarLoop]: Abstraction has 276515 states and 391283 transitions. [2021-11-13 17:46:22,837 INFO L587 BuchiCegarLoop]: Abstraction has 276515 states and 391283 transitions. [2021-11-13 17:46:22,837 INFO L425 BuchiCegarLoop]: ======== Iteration 23============ [2021-11-13 17:46:22,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 276515 states and 391283 transitions. [2021-11-13 17:46:24,499 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 275968 [2021-11-13 17:46:24,499 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2021-11-13 17:46:24,499 INFO L119 BuchiIsEmpty]: Starting construction of run [2021-11-13 17:46:24,505 INFO L842 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:46:24,505 INFO L843 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2021-11-13 17:46:24,506 INFO L791 eck$LassoCheckResult]: Stem: 1188997#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;#NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];assume 0 < #StackHeapBarrier;call #t~string4.base, #t~string4.offset := #Ultimate.allocOnStack(2);call write~init~int(48, #t~string4.base, #t~string4.offset, 1);call write~init~int(0, #t~string4.base, 1 + #t~string4.offset, 1);call #t~string5.base, #t~string5.offset := #Ultimate.allocOnStack(22);call #t~string6.base, #t~string6.offset := #Ultimate.allocOnStack(12);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~token~0 := 0;~local~0 := 0; 1188998#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~13#1;havoc main_~__retres1~13#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1; 1189896#L1641 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret34#1, start_simulation_#t~ret35#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1189897#L773 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1188489#L780 assume 1 == ~m_i~0;~m_st~0 := 0; 1188490#L780-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1189913#L785-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1189857#L790-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1189858#L795-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1188843#L800-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1188844#L805-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1189288#L810-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1189815#L815-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1188755#L820-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1188756#L825-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1188640#L830-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1188641#L835-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1189719#L1109 assume !(0 == ~M_E~0); 1189746#L1109-2 assume !(0 == ~T1_E~0); 1188649#L1114-1 assume !(0 == ~T2_E~0); 1188650#L1119-1 assume !(0 == ~T3_E~0); 1189820#L1124-1 assume !(0 == ~T4_E~0); 1188309#L1129-1 assume !(0 == ~T5_E~0); 1188310#L1134-1 assume !(0 == ~T6_E~0); 1188926#L1139-1 assume !(0 == ~T7_E~0); 1189731#L1144-1 assume !(0 == ~T8_E~0); 1189542#L1149-1 assume !(0 == ~T9_E~0); 1188413#L1154-1 assume !(0 == ~T10_E~0); 1188414#L1159-1 assume !(0 == ~T11_E~0); 1189528#L1164-1 assume !(0 == ~E_M~0); 1188808#L1169-1 assume !(0 == ~E_1~0); 1188696#L1174-1 assume !(0 == ~E_2~0); 1188567#L1179-1 assume !(0 == ~E_3~0); 1188493#L1184-1 assume !(0 == ~E_4~0); 1188494#L1189-1 assume !(0 == ~E_5~0); 1188525#L1194-1 assume !(0 == ~E_6~0); 1188613#L1199-1 assume !(0 == ~E_7~0); 1189551#L1204-1 assume !(0 == ~E_8~0); 1189477#L1209-1 assume !(0 == ~E_9~0); 1189478#L1214-1 assume !(0 == ~E_10~0); 1189935#L1219-1 assume !(0 == ~E_11~0); 1190105#L1224-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1188827#L544 assume !(1 == ~m_pc~0); 1188828#L544-2 is_master_triggered_~__retres1~0#1 := 0; 1189804#L555 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1189563#L556 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1188454#L1379 assume !(0 != activate_threads_~tmp~1#1); 1188455#L1379-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1189272#L563 assume !(1 == ~t1_pc~0); 1189040#L563-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1188317#L574 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1188318#L575 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1189407#L1387 assume !(0 != activate_threads_~tmp___0~0#1); 1188313#L1387-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1188314#L582 assume !(1 == ~t2_pc~0); 1189016#L582-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1189418#L593 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1189419#L594 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1189541#L1395 assume !(0 != activate_threads_~tmp___1~0#1); 1188343#L1395-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1188344#L601 assume !(1 == ~t3_pc~0); 1189034#L601-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1189033#L612 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1189805#L613 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1189457#L1403 assume !(0 != activate_threads_~tmp___2~0#1); 1189458#L1403-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1189391#L620 assume !(1 == ~t4_pc~0); 1189392#L620-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1188947#L631 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1188893#L632 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1188894#L1411 assume !(0 != activate_threads_~tmp___3~0#1); 1189285#L1411-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1189499#L639 assume !(1 == ~t5_pc~0); 1189500#L639-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1188617#L650 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1188618#L651 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1189307#L1419 assume !(0 != activate_threads_~tmp___4~0#1); 1189308#L1419-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1189227#L658 assume !(1 == ~t6_pc~0); 1188822#L658-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1188823#L669 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1190145#L670 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1190108#L1427 assume !(0 != activate_threads_~tmp___5~0#1); 1189462#L1427-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1188664#L677 assume !(1 == ~t7_pc~0); 1188561#L677-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1188562#L688 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1189667#L689 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1189847#L1435 assume !(0 != activate_threads_~tmp___6~0#1); 1189848#L1435-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1189963#L696 assume !(1 == ~t8_pc~0); 1188883#L696-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1188884#L707 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1189912#L708 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1189945#L1443 assume !(0 != activate_threads_~tmp___7~0#1); 1190051#L1443-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1189345#L715 assume !(1 == ~t9_pc~0); 1189346#L715-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1188977#L726 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1188878#L727 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1188879#L1451 assume !(0 != activate_threads_~tmp___8~0#1); 1189331#L1451-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1189664#L734 assume !(1 == ~t10_pc~0); 1189665#L734-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1188781#L745 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1188782#L746 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1188800#L1459 assume !(0 != activate_threads_~tmp___9~0#1); 1189579#L1459-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1188857#L753 assume !(1 == ~t11_pc~0); 1188858#L753-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1189844#L764 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1188972#L765 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1188973#L1467 assume !(0 != activate_threads_~tmp___10~0#1); 1189137#L1467-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1189200#L1237 assume !(1 == ~M_E~0); 1189201#L1237-2 assume !(1 == ~T1_E~0); 1190025#L1242-1 assume !(1 == ~T2_E~0); 1188943#L1247-1 assume !(1 == ~T3_E~0); 1188944#L1252-1 assume !(1 == ~T4_E~0); 1188718#L1257-1 assume !(1 == ~T5_E~0); 1188719#L1262-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1189688#L1267-1 assume !(1 == ~T7_E~0); 1189834#L1272-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1189835#L1277-1 assume !(1 == ~T9_E~0); 1189591#L1282-1 assume !(1 == ~T10_E~0); 1189592#L1287-1 assume !(1 == ~T11_E~0); 1189552#L1292-1 assume !(1 == ~E_M~0); 1189553#L1297-1 assume !(1 == ~E_1~0); 1188852#L1302-1 assume 1 == ~E_2~0;~E_2~0 := 2; 1188853#L1307-1 assume !(1 == ~E_3~0); 1190056#L1312-1 assume !(1 == ~E_4~0); 1190057#L1317-1 assume !(1 == ~E_5~0); 1189340#L1322-1 assume !(1 == ~E_6~0); 1189341#L1327-1 assume !(1 == ~E_7~0); 1189405#L1332-1 assume !(1 == ~E_8~0); 1189406#L1337-1 assume !(1 == ~E_9~0); 1189335#L1342-1 assume 1 == ~E_10~0;~E_10~0 := 2; 1189336#L1347-1 assume !(1 == ~E_11~0); 1189822#L1352-1 assume { :end_inline_reset_delta_events } true; 1189663#L1678-2 [2021-11-13 17:46:24,507 INFO L793 eck$LassoCheckResult]: Loop: 1189663#L1678-2 assume !false; 1189394#L1679 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret8#1, eval_#t~nondet9#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet20#1, eval_~tmp_ndt_12~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1189395#L1084 assume !false; 1189152#L921 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1189153#L848 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1188430#L910 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1189517#L911 eval_#t~ret8#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret8#1;havoc eval_#t~ret8#1; 1188356#L925 assume !(0 != eval_~tmp~0#1); 1188358#L1099 assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1461139#L773-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1461136#L1109-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1461133#L1109-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1461130#L1114-3 assume !(0 == ~T2_E~0); 1461126#L1119-3 assume !(0 == ~T3_E~0); 1461122#L1124-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1461119#L1129-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1461116#L1134-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1461113#L1139-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1461110#L1144-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1461107#L1149-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1461104#L1154-3 assume !(0 == ~T10_E~0); 1461101#L1159-3 assume !(0 == ~T11_E~0); 1461098#L1164-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1461095#L1169-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1461092#L1174-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1461091#L1179-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1461090#L1184-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1461089#L1189-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1461088#L1194-3 assume !(0 == ~E_6~0); 1461087#L1199-3 assume !(0 == ~E_7~0); 1461086#L1204-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1461085#L1209-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1461084#L1214-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1461083#L1219-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1461082#L1224-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1461081#L544-39 assume !(1 == ~m_pc~0); 1461080#L544-41 is_master_triggered_~__retres1~0#1 := 0; 1461079#L555-13 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1461078#L556-13 activate_threads_#t~ret21#1 := is_master_triggered_#res#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1461077#L1379-39 assume !(0 != activate_threads_~tmp~1#1); 1461076#L1379-41 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1461075#L563-39 assume !(1 == ~t1_pc~0); 1461074#L563-41 is_transmit1_triggered_~__retres1~1#1 := 0; 1461072#L574-13 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1461071#L575-13 activate_threads_#t~ret22#1 := is_transmit1_triggered_#res#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1461070#L1387-39 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1461069#L1387-41 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1189793#L582-39 assume !(1 == ~t2_pc~0); 1189794#L582-41 is_transmit2_triggered_~__retres1~2#1 := 0; 1189520#L593-13 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1189408#L594-13 activate_threads_#t~ret23#1 := is_transmit2_triggered_#res#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1189409#L1395-39 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1188500#L1395-41 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1188291#L601-39 assume 1 == ~t3_pc~0; 1188292#L602-13 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1188335#L612-13 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1189574#L613-13 activate_threads_#t~ret24#1 := is_transmit3_triggered_#res#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1189773#L1403-39 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1189634#L1403-41 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1189220#L620-39 assume !(1 == ~t4_pc~0); 1189221#L620-41 is_transmit4_triggered_~__retres1~4#1 := 0; 1189726#L631-13 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1189727#L632-13 activate_threads_#t~ret25#1 := is_transmit4_triggered_#res#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1189589#L1411-39 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1189590#L1411-41 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1190128#L639-39 assume !(1 == ~t5_pc~0); 1190015#L639-41 is_transmit5_triggered_~__retres1~5#1 := 0; 1188948#L650-13 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1188513#L651-13 activate_threads_#t~ret26#1 := is_transmit5_triggered_#res#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1188319#L1419-39 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1188320#L1419-41 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1189265#L658-39 assume !(1 == ~t6_pc~0); 1189243#L658-41 is_transmit6_triggered_~__retres1~6#1 := 0; 1189842#L669-13 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1188270#L670-13 activate_threads_#t~ret27#1 := is_transmit6_triggered_#res#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1188271#L1427-39 assume !(0 != activate_threads_~tmp___5~0#1); 1189441#L1427-41 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1189442#L677-39 assume !(1 == ~t7_pc~0); 1189024#L677-41 is_transmit7_triggered_~__retres1~7#1 := 0; 1188491#L688-13 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1188492#L689-13 activate_threads_#t~ret28#1 := is_transmit7_triggered_#res#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1188547#L1435-39 assume !(0 != activate_threads_~tmp___6~0#1); 1188548#L1435-41 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1189136#L696-39 assume 1 == ~t8_pc~0; 1189099#L697-13 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1188969#L707-13 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1188970#L708-13 activate_threads_#t~ret29#1 := is_transmit8_triggered_#res#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1189297#L1443-39 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1189298#L1443-41 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1189113#L715-39 assume !(1 == ~t9_pc~0); 1189114#L715-41 is_transmit9_triggered_~__retres1~9#1 := 0; 1189581#L726-13 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1189582#L727-13 activate_threads_#t~ret30#1 := is_transmit9_triggered_#res#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1190142#L1451-39 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1189501#L1451-41 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1189502#L734-39 assume 1 == ~t10_pc~0; 1189414#L735-13 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1188807#L745-13 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1189138#L746-13 activate_threads_#t~ret31#1 := is_transmit10_triggered_#res#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1188444#L1459-39 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1188445#L1459-41 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1189869#L753-39 assume !(1 == ~t11_pc~0); 1188365#L753-41 is_transmit11_triggered_~__retres1~11#1 := 0; 1188366#L764-13 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1189809#L765-13 activate_threads_#t~ret32#1 := is_transmit11_triggered_#res#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1189103#L1467-39 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1189104#L1467-41 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1189218#L1237-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1189219#L1237-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1189531#L1242-3 assume !(1 == ~T2_E~0); 1189532#L1247-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1189833#L1252-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1189435#L1257-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1189436#L1262-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1189810#L1267-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1189876#L1272-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1190044#L1277-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1188516#L1282-3 assume !(1 == ~T10_E~0); 1188517#L1287-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1188427#L1292-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1188428#L1297-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1189680#L1302-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1189681#L1307-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1189960#L1312-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1190117#L1317-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1189556#L1322-3 assume !(1 == ~E_6~0); 1189557#L1327-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1188486#L1332-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1188460#L1337-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1188461#L1342-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1189181#L1347-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1189329#L1352-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1189330#L848-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1188406#L910-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1188678#L911-1 start_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret34#1;havoc start_simulation_#t~ret34#1; 1189448#L1697 assume !(0 == start_simulation_~tmp~3#1); 1189208#L1697-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret33#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~12#1;havoc exists_runnable_thread_~__retres1~12#1; 1189209#L848-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~12#1 := 1; 1188533#L910-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~12#1; 1189347#L911-2 stop_simulation_#t~ret33#1 := exists_runnable_thread_#res#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret33#1;havoc stop_simulation_#t~ret33#1; 1189348#L1652 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1189291#L1659 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1188850#L1660 start_simulation_#t~ret35#1 := stop_simulation_#res#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1188851#L1710 assume !(0 != start_simulation_~tmp___0~1#1); 1189663#L1678-2 [2021-11-13 17:46:24,507 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:46:24,508 INFO L85 PathProgramCache]: Analyzing trace with hash -492429635, now seen corresponding path program 1 times [2021-11-13 17:46:24,508 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:46:24,508 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [225864182] [2021-11-13 17:46:24,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:46:24,509 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:46:24,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:46:24,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:46:24,558 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:46:24,558 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [225864182] [2021-11-13 17:46:24,559 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [225864182] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:46:24,559 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:46:24,559 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2021-11-13 17:46:24,559 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1259955974] [2021-11-13 17:46:24,559 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:46:24,560 INFO L796 eck$LassoCheckResult]: stem already infeasible [2021-11-13 17:46:24,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2021-11-13 17:46:24,561 INFO L85 PathProgramCache]: Analyzing trace with hash 1721305933, now seen corresponding path program 1 times [2021-11-13 17:46:24,561 INFO L121 FreeRefinementEngine]: Executing refinement strategy CAMEL [2021-11-13 17:46:24,561 INFO L332 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [534008613] [2021-11-13 17:46:24,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2021-11-13 17:46:24,561 INFO L126 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2021-11-13 17:46:24,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2021-11-13 17:46:24,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2021-11-13 17:46:24,600 INFO L139 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2021-11-13 17:46:24,600 INFO L332 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [534008613] [2021-11-13 17:46:24,601 INFO L160 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [534008613] provided 1 perfect and 0 imperfect interpolant sequences [2021-11-13 17:46:24,601 INFO L186 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2021-11-13 17:46:24,601 INFO L199 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2021-11-13 17:46:24,601 INFO L115 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2060527594] [2021-11-13 17:46:24,601 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2021-11-13 17:46:24,602 INFO L808 eck$LassoCheckResult]: loop already infeasible [2021-11-13 17:46:24,602 INFO L103 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2021-11-13 17:46:24,602 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2021-11-13 17:46:24,603 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2021-11-13 17:46:24,603 INFO L87 Difference]: Start difference. First operand 276515 states and 391283 transitions. cyclomatic complexity: 114776 Second operand has 3 states, 3 states have (on average 46.333333333333336) internal successors, (139), 2 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:46:25,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2021-11-13 17:46:25,606 INFO L93 Difference]: Finished difference Result 276515 states and 390513 transitions. [2021-11-13 17:46:25,607 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2021-11-13 17:46:25,607 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 276515 states and 390513 transitions. [2021-11-13 17:46:27,782 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 275968 [2021-11-13 17:46:28,569 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 276515 states to 276515 states and 390513 transitions. [2021-11-13 17:46:28,570 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 276515 [2021-11-13 17:46:28,731 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 276515 [2021-11-13 17:46:28,731 INFO L73 IsDeterministic]: Start isDeterministic. Operand 276515 states and 390513 transitions. [2021-11-13 17:46:29,663 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2021-11-13 17:46:29,664 INFO L681 BuchiCegarLoop]: Abstraction has 276515 states and 390513 transitions. [2021-11-13 17:46:29,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 276515 states and 390513 transitions. [2021-11-13 17:46:32,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 276515 to 276515. [2021-11-13 17:46:32,283 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 276515 states, 276515 states have (on average 1.4122669656257345) internal successors, (390513), 276514 states have internal predecessors, (390513), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2021-11-13 17:46:34,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 276515 states to 276515 states and 390513 transitions. [2021-11-13 17:46:34,075 INFO L704 BuchiCegarLoop]: Abstraction has 276515 states and 390513 transitions. [2021-11-13 17:46:34,075 INFO L587 BuchiCegarLoop]: Abstraction has 276515 states and 390513 transitions. [2021-11-13 17:46:34,076 INFO L425 BuchiCegarLoop]: ======== Iteration 24============ [2021-11-13 17:46:34,076 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 276515 states and 390513 transitions.